A GaN-based LED epitaxial wafer and its epitaxial growth method

Abstract

This invention provides a GaN-based LED epitaxial wafer and an epitaxial growth method. By controlling the change in the In content of the extended and retarded sublayers in the extended and retarded layers, which first increases and then decreases, a potential well depth can be generated between the active layer, the retarded layer, and the extended layer. The potential well of the retarded layer closer to the active layer is relatively deeper, which can effectively slow down the migration rate of electrons to the active layer, improve the electron confinement ability of the active layer, and improve the non-radiative recombination of electrons injected into the p-type nitride layer, ultimately achieving the goal of improving luminous efficiency.

Description

Technical Field

[0001] This invention relates to the field of LED technology, and in particular to a GaN-based LED epitaxial wafer and an epitaxial growth method. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor electronic component that emits light. Due to its small size, high brightness, and low power consumption, it has attracted increasing attention from researchers.

[0003] A typical GaN-based LED epitaxial structure includes an N-type nitride layer, an active layer, and a P-type nitride layer. The active layer is a periodic structure composed of alternating AlGaN quantum barrier layers and InGaN quantum well layers. The N-type nitride layer is doped with Si to generate enough electrons. These electrons are generated to recombine with holes in the active layer to emit light. However, in addition to being confined to the active layer, a significant portion of the electrons will overflow into the P-type nitride layer and recombine with holes therein, resulting in a decrease in luminous efficiency.

[0004] In addition, the AlGaN quantum barrier layer and InGaN quantum well layer in the active layer will generate dislocation defects due to their different lattice constants. Furthermore, due to the relatively low temperature growth characteristics of the InGaN quantum well layer with a higher In content, the dislocation defects in the active layer will increase further, leading to the proliferation of leakage channels, which will affect the antistatic capability of the LED and thus further reduce the luminous efficiency. Summary of the Invention

[0005] Based on this, the purpose of this invention is to provide a GaN-based LED epitaxial wafer and an epitaxial growth method, which aims to solve the problem in the prior art that electrons can easily break through the active layer and be injected into the P-type nitride layer.

[0006] According to an embodiment of the present invention, a GaN-based LED epitaxial wafer includes an extended layer and a retardation layer deposited on the extended layer. The extended layer includes a plurality of extended sub-layers stacked sequentially, and the retardation layer includes a plurality of retardation sub-layers stacked sequentially. Both the extended sub-layers and the retardation sub-layers are formed by sequentially stacking InGaN layers and GaN layers. In and Si are doped during the growth of the extended sub-layers and the retardation sub-layers.

[0007] During the growth of the extended sublayer and the retarded sublayer, the In content first increases and then decreases along the epitaxial growth direction, while the Si content first decreases and then increases along the epitaxial growth direction, and the maximum value of the In content corresponds to the minimum value of the Si content.

[0008] Furthermore, the ratio of the diffraction intensity value corresponding to the maximum In content in the extended sublayer to the diffraction intensity value corresponding to the maximum In content in the hysteretic sublayer is less than 1 / 2.

[0009] Furthermore, the ratio of the maximum Si content in the extended sublayer to the maximum Si content in the retarded sublayer is greater than 3.

[0010] Furthermore, the diffraction intensity value corresponding to the maximum In content in the extended sublayer is 5 × 10⁻⁶. 3 c / s ~ 5 × 10 4 c / s.

[0011] Furthermore, the diffraction intensity value corresponding to the maximum In content in the retarded sublayer is 1×10⁻⁶. 4 c / s ~ 1×10 5 c / s.

[0012] Furthermore, the maximum Si content in the extended sublayer is 1×10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 .

[0013] Furthermore, the maximum Si content in the retarded sublayer is 1×10⁻⁶. 17 atoms / cm 3 ~5×10 17 atoms / cm 3 .

[0014] Furthermore, the GaN-based LED epitaxial wafer also includes a substrate, a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, an active layer, a P-type electron blocking layer, and a P-type gallium nitride layer;

[0015] Specifically, the buffer layer, the undoped gallium nitride layer, the N-type gallium nitride layer, the extended layer, the retardation layer, the active layer, the P-type electron blocking layer, and the P-type gallium nitride layer are sequentially deposited on the substrate along the epitaxial growth direction.

[0016] Furthermore, the In doping concentration of the retardation layer is lower than that of the In doping concentration of the active layer.

[0017] According to an embodiment of the present invention, an epitaxial growth method for GaN-based LED epitaxial wafers is used to prepare the aforementioned GaN-based LED epitaxial wafers. The epitaxial growth method includes:

[0018] An extended layer and a retardation layer are epitaxially grown sequentially. The extended layer includes several extended sub-layers stacked sequentially, and the retardation layer includes several retardation sub-layers stacked sequentially. Both the extended sub-layers and the retardation sub-layers are formed by stacking InGaN layers and GaN layers sequentially. In and Si are doped during the growth of the extended sub-layers and the retardation sub-layers.

[0019] In the process of growing the extended sublayer and the retarded sublayer, the In content is controlled to first increase and then decrease along the epitaxial growth direction, and the Si content is controlled to first decrease and then increase along the epitaxial growth direction, and the maximum value of the In content corresponds to the minimum value of the Si content.

[0020] Compared with existing technologies, by controlling the change of the In content of the extended and retarded sublayers in the extended and retarded layers from first increasing to then decreasing, a potential well depth can be generated between the active layer, the retarded layer, and the extended layer. The potential well of the retarded layer closer to the active layer is relatively deeper, which can effectively slow down the migration rate of electrons to the active layer, improve the electron confinement ability of the active layer, improve the non-radiative recombination of electrons injected into the p-type nitride layer, and ultimately achieve the goal of improving luminescence efficiency. Attached Figure Description

[0021] Figure 1 This invention provides a schematic diagram of the structure of a GaN-based LED epitaxial wafer.

[0022] Figure 2 A schematic diagram showing the diffraction intensity and Si content changes during the epitaxial growth of the extended layer and the retardation layer provided by this invention.

[0023] Figure 3 The flowchart illustrates an epitaxial growth method for LED epitaxial wafers provided by this invention. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] refer to Figure 1 The present invention discloses a GaN-based LED epitaxial wafer, comprising a substrate 1 and a buffer layer 2, an undoped gallium nitride layer 3, an N-type gallium nitride layer 4, an extension layer 5, a retardation layer 6, an active layer 7, a P-type electron blocking layer 8, and a P-type gallium nitride layer 9 sequentially disposed on the substrate 1.

[0028] The buffer layer 2 can be any one or a combination of AlN buffer layer 2, AlGaN buffer layer 2, and GaN buffer layer 2, and the thickness of the buffer layer 2 is 10nm to 20nm. For example, the thickness of the buffer layer 2 is 11nm, 13nm, 14nm, 17nm, or 19nm, etc., but not limited to these. The thickness of the undoped gallium nitride layer 3 is 1μm to 1.5μm. For example, the thickness of the undoped gallium nitride layer 3 is 1.1μm, 1.2μm, 1.3μm, or 1.4μm, but not limited to these. The thickness of the N-type gallium nitride layer 4 is 1μm to 2μm. For example, the thickness of the N-type gallium nitride layer 4 is 1.1μm, 1.3μm, 1.4μm, 1.6μm, or... The thickness is 1.9 μm, but not limited to this; the extended layer 5 includes several extended sub-layers stacked sequentially, the extended sub-layers being composed of InGaN layers and GaN layers stacked sequentially. It is understood that the extended layer 5 is a periodic structure of InGaN layers and GaN layers stacked sequentially, with a growth cycle number ≥ 2, meaning at least two InGaN layers and two GaN layers exist. The thickness of the extended layer 5 is 15 nm to 45 nm. For example, the thickness of the extended layer 5 is 16 nm, 20 nm, 25 nm, 35 nm, or 40 nm, but not limited to this; the retardation layer 6 includes several retardation sub-layers stacked sequentially, the retardation sub-layers being composed of InGaN layers and GaN layers stacked sequentially. It is understood that the retardation layer 6 is an InGaN layer stacked sequentially. The structure consists of a periodic structure with N-layers and GaN layers stacked sequentially, having a growth cycle number ≥ 4, meaning at least four InGaN layers and four GaN layers are present. The retardation layer 6 has a thickness of 20nm–60nm. For example, the extension layer 5 has a thickness of 16nm, 20nm, 25nm, 35nm, or 40nm, but is not limited to these. The active layer 7 is formed by periodically alternating quantum barrier layers and quantum well layers, with a growth cycle number ≥ 8. Specifically, the quantum barrier layer can be a GaN layer, and the quantum well layer can be an InGaN layer. The thickness of the quantum barrier layer is 8nm–12nm. For example, the thickness of the quantum barrier layer is 8.2nm, 9nm, 9.5nm, 10nm, or 11nm, but is not limited to these. In this context, the thickness of the quantum well layer is 2nm to 4nm. For example, the thickness of the quantum well layer is 2.2nm, 2.8nm, 3nm, 3.2nm, or 3.6nm, but is not limited thereto. The P-type electron blocking layer 8 is an AlInGaN layer, and the thickness of the P-type electron blocking layer 8 is 10nm to 30nm. For example, the thickness of the P-type electron blocking layer 8 is 11nm, 15nm, 21nm, 26nm, or 29nm, but is not limited thereto. The P-type gallium nitride layer 9 is a Mg-doped GaN layer, and the thickness of the P-type gallium nitride layer 9 is 5nm to 15nm. For example, the thickness of the P-type gallium nitride layer 9 is 6nm, 8nm, 10nm, 13nm, or 14nm, but is not limited thereto.

[0029] Specifically, both In and Si are doped during the growth of the extended and retarded sublayers. It should be noted that during the growth of the extended and retarded sublayers, the In content first increases and then decreases along the epitaxial growth direction, while the Si content first decreases and then increases along the epitaxial growth direction. The maximum value of the In content corresponds to the minimum value of the Si content. It should also be noted that the ratio of the diffraction intensity value corresponding to the maximum In content in the extended sublayer to the diffraction intensity value corresponding to the maximum In content in the retarded sublayer is less than 1 / 2, and the ratio of the maximum Si content in the extended sublayer to the maximum Si content in the retarded sublayer is greater than 3.

[0030] More specifically, the diffraction intensity value corresponding to the maximum In content in the extended sublayer is 5 × 10⁻⁶. 3 c / s ~ 5 × 10 4 c / s, the diffraction intensity corresponding to the maximum In content in the lag sublayer is 1×10 4 c / s ~ 1×10 5 Regarding c / s, it should be noted that if the diffraction intensity of In in the extended sublayer and retarded sublayer is too high, it indicates that the In composition of the extended layer 5 and retarded layer 6 is too high, which easily leads to V-type defects, thus affecting crystal quality, leakage current, and impacting device reliability and luminous efficiency. Conversely, if the diffraction intensity of In in the extended sublayer and retarded sublayer is too low, it indicates that the In composition of the extended layer 5 and retarded layer 6 is too low, which cannot generate a sufficiently deep potential well to slow down the migration rate of electrons to the active layer 7. This easily leads to electrons migrating to the P-type layer and recombinating with holes, reducing the efficiency of the device. The low luminous efficiency is addressed by gradually increasing the In content from the extended layer 5, retardation layer 6, to the active layer 7. This alleviates the lattice mismatch between the N-type nitride layer and the active layer 7, improves the crystal quality of the active layer 7, enhances device reliability, and increases luminous efficiency. Furthermore, the gradually increasing potential well depth effectively slows down the electron migration rate to the active layer 7, improves the electron confinement capability of the active layer 7, and reduces non-radiative recombination of electrons injected into the P-type nitride layer, thereby improving luminous efficiency. Additionally, the maximum Si content in the extended sublayer is 1 × 10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 The maximum Si content in the lag sublayer is 1×10 17 atoms / cm 3 ~5×10 17 atoms / cm 3It should be noted that excessively high Si content in the extended and retarded sublayers indicates an overly high Si composition in the extended layer 5 and retarded layer 6, which reduces the crystal quality of the grown epitaxial layer and makes it prone to leakage current, thus affecting device reliability and luminous efficiency. Conversely, excessively low Si content in the extended and retarded sublayers indicates an underlying Si composition in the extended layer 5 and retarded layer 6, resulting in a poor ability to guide current diffusion. When the active layer 7 is subjected to current surges, it is not conducive to current diffusion and is easily broken down by current. Understandably, by controlling the maximum Si content in the extended sublayer to be greater than the maximum Si content in the retarded sublayer, the relatively highly Si-doped extended layer 5 can effectively guide current diffusion when the LED is subjected to current surges, preventing the active layer 7, which has a relatively high defect density and many leakage channels, from being broken down by current surges. This improves the LED's anti-static capability and enhances device reliability.

[0031] Additionally, for easier understanding, please refer to Figure 2 This diagram illustrates the diffraction intensity and Si content changes of the In content during the epitaxial growth of the extended layer 5 and the retardation layer 6 provided by the present invention. Curve X1 represents the diffraction intensity profile of the In content in the extended layer 5, curve Y1 represents the concentration profile of the Si content in the extended layer 5, curve X2 represents the diffraction intensity profile of the In content in the retardation layer 6, and curve Y2 represents the concentration profile of the Si content in the retardation layer 6. Figure 2 The direction from right to left in the diagram represents the epitaxial growth direction, with the rightmost position being the starting point. Understandably, the extension layer 5 is grown epitaxially first, followed by the growth of the retardation layer 6 on top of the extension layer 5. Figure 2 As can be seen, extended layer 5 is composed of three extended sublayers stacked sequentially. During the growth of the extended sublayers, the diffraction intensity of the In content first increases and then decreases along the epitaxial growth direction. For the entire epitaxial growth of extended layer 5, the diffraction intensity of the In content periodically increases and decreases along the epitaxial growth direction, ultimately resulting in a diffraction intensity line shape resembling a sine wave. Simultaneously, during the growth of the extended sublayers, the Si content first decreases and then increases along the epitaxial growth direction. For the entire epitaxial growth of extended layer 5, the Si content periodically decreases and increases along the epitaxial growth direction, ultimately resulting in a continuous broken line shape for the Si content. It should be noted that the maximum value of the In content corresponds to the minimum value of the Si content; that is, the peak in the diffraction intensity line shape of the In content corresponds to the trough in the Si content line shape, and the trough in the diffraction intensity line shape of the In content corresponds to the peak in the Si content line shape. Figure 2When the extended layer 5 is epitaxially grown, the three peaks in the diffraction intensity line of the In content correspond to the three troughs in the Si content line. Similarly, when the retardation layer 6 is epitaxially grown, the six peaks in the diffraction intensity line of the In content correspond to the six troughs in the Si content line. That is, the retardation layer 6 is composed of six extended sublayers stacked sequentially.

[0032] It should be noted that, Figure 2 In the diagram, the diffraction intensity profile curves of the In content in extended layer 5 and retarded layer 6 are the profile curves corresponding to the diffraction peaks of In in extended layer 5 and retarded layer 6 as measured by the instrument. The right vertical axis represents the relative intensity corresponding to the diffraction peak, in c / s (counts / s), which indicates the number of photons received in one second. It can be understood that when measuring the composition using an instrument, a beam of photons is emitted to the epitaxial layer, and the instrument receives the photons reflected back from the epitaxial layer, thus obtaining the diffraction peaks of materials such as Al, Ga, In, and N in the epitaxial layer. Figure 2 The left vertical axis represents the doping concentration, in units of atoms / cm. 3 This is used to describe the Si content of the extended layer 5 and the retardation layer 6.

[0033] Accordingly, refer to Figure 3 This application also discloses an epitaxial growth method for GaN-based LED epitaxial wafers, which is used to prepare the aforementioned GaN-based LED epitaxial wafers, specifically including the following steps:

[0034] S100: Provides substrate 1;

[0035] Preferably, the selected substrate 1 can be any one of sapphire substrate, silicon substrate, silicon carbide substrate, and gallium nitride substrate. In one embodiment of the present invention, the substrate 1 is placed in MOCVD and annealed at 1000℃~1200℃, 200torr~600torr, and hydrogen atmosphere for 5min~8min to remove impurities such as particles and oxides on the surface of the substrate 1.

[0036] S200: A buffer layer 2, an undoped gallium nitride layer 3, an N-type gallium nitride layer 4, an extension layer 5, a retardation layer 6, an active layer 7, a P-type electron blocking layer 8, and a P-type gallium nitride layer 9 are epitaxially grown sequentially on a substrate 1.

[0037] Specifically, S200 includes:

[0038] S210: Grow a buffer layer 2 on substrate 1;

[0039] Specifically, the buffer layer 2 can be any one or a combination of AlN buffer layer 2, AlGaN buffer layer 2, and GaN buffer layer 2. In one embodiment of the present invention, the buffer layer 2 can be a GaN buffer layer 2, which is grown in MOCVD. The specific growth process is as follows: the temperature of the MOCVD reaction chamber is controlled at 780℃~830℃, the pressure is controlled at 100 torr~200 torr, NH3 is introduced as N (nitrogen) source, and TMGa is introduced as Ga (gallium) source, so that GaN buffer layer 2 is grown, and the thickness of the deposited GaN buffer layer 2 is controlled to be 10nm~20nm.

[0040] S220: An undoped gallium nitride layer 3 is grown on the buffer layer 2;

[0041] Specifically, an undoped gallium nitride layer 3 is grown in MOCVD. The temperature of the MOCVD reaction chamber is controlled at 1080℃~1180℃, the pressure is controlled at 150 torr~250 torr, NH3 is used as the N (nitrogen) source, and TMGa is used as the Ga (gallium) source, so as to grow an undoped gallium nitride layer 3, and the thickness of the deposited undoped gallium nitride layer 3 is controlled to be 1μm~1.5μm.

[0042] S230: An N-type gallium nitride layer 4 is grown on the undoped gallium nitride layer 3;

[0043] Specifically, an N-type gallium nitride layer 4 is grown in MOCVD. The MOCVD reaction chamber temperature is lowered to 1060℃~1150℃, the pressure is controlled at 150 torr~250 torr, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and SiH4 is introduced as the N-type dopant. Simultaneously, the Si (silicon) doping concentration can be 5×E18 atoms / cm². 3 ~5×E19atoms / cm 3 The thickness of the deposited N-type gallium nitride layer 4 is controlled to be 1 μm to 2 μm.

[0044] S240: An extended layer 5 is grown on the N-type gallium nitride layer 4;

[0045] Specifically, in MOCVD, an extended layer 5 is grown. The MOCVD reaction chamber temperature is controlled at 820℃~900℃, and the pressure is controlled at 150 torr~250 torr. The N (nitrogen) source can be NH3, with a flow rate of 45L~85L. The Ga (gallium) source can be TEGa, the In (indium) source can be TMI, with a flow rate of 1100sccm~1600sccm, and the Si (silicon) source can be SiH4. This results in an extended layer 5 with a periodic structure of alternating InGaN and GaN layers. The number of growth cycles of the extended layer 5 is at least greater than 2, meaning that the extended layer 5 consists of at least two extended sublayers. To make the In intensity profile curves appear as curves X1 and X2, the flow of TMI needs to be periodically controlled. Specifically, the In flux variation curve is not equal to the profile curve corresponding to the In diffraction peak. This is because after In has been fluxed to grow an epitaxial layer for a period of time, even if the flux is stopped, an In source will remain in the cavity to act on the growth, and the In in the epitaxial layer will diffuse, resulting in the detection of the diffraction peak corresponding to In in the epitaxial layer that has not been fluxed. It should be noted that the reaction source and its flow rate required for the growth of the extended layer 5 are controlled by MFC (digital flow controller) and PC (digital pressure controller). Understandably, during the growth of the extended layer 5, the flux of NH3, TEGa, TMIn, and SiH4 at different time periods can be preset and controlled within the growth program in MOCVD to complete the growth of the extended layer 5 and control the thickness of the extended layer 5 to be 15nm to 45nm.

[0046] S250: A retardation layer 6 is grown on the extended layer 5;

[0047] Specifically, in MOCVD, a retardation layer 6 is grown. The MOCVD reaction chamber temperature is controlled at 780℃~880℃, and the pressure is controlled at 150 torr~250 torr. The N (nitrogen) source can be NH3, with a flow rate of 45L~85L; the Ga (gallium) source can be TEGa; the In (indium) source can be TMI, with a flow rate of 1500sccm~2000sccm; and the Si (silicon) source can be SiH4. This results in the retardation layer 6 being a periodically grown alternating InGaN and GaN layer. The structure of the retardation layer 6 has a growth cycle of at least 4, meaning that the retardation layer 6 consists of at least four retardation sublayers. It should be noted that the reaction source and its flow rate required for the growth of the retardation layer 6 are controlled by MFC (Digital Flow Controller) and PC (Digital Pressure Controller). Understandably, during the growth of the retardation layer 6, the amount of NH3, TEGa, TMI, and SiH4 introduced at different time periods can be preset and controlled within the growth program in MOCVD to complete the growth of the retardation layer 6 and control the thickness of the retardation layer 6 to be 20nm to 60nm.

[0048] Specifically, the ratio of the maximum In content in the extended sublayer to the maximum In content in the retarded sublayer is less than 1 / 2, i.e., the relative intensity ratio is less than 1 / 2, and the ratio of the maximum Si content in the extended sublayer to the maximum Si content in the retarded sublayer is greater than 3, i.e., the doping concentration ratio is greater than 3.

[0049] S260: An active layer 7 is grown on the retardation layer 6;

[0050] Specifically, an active layer 7 is grown in MOCVD, wherein the active layer 7 is formed by periodically alternating growth of a quantum barrier layer and a quantum well layer, and the number of growth cycles is ≥8. In one embodiment of the present invention, the number of cycles can be 10, that is, the active layer 7 is obtained by alternating growth of a quantum well layer and a quantum barrier layer 10 times;

[0051] Furthermore, the temperature of the MOCVD reaction chamber during the growth of the quantum well layer is controlled at 760℃~800℃, and the pressure is controlled at 150 torr~250 torr. The N (nitrogen) source can be NH3, the Ga (gallium) source can be TEGa, and the In (indium) source can be TMIn. The thickness of the deposited InGaN quantum well layer is controlled at 2nm~4nm.

[0052] Furthermore, the temperature of the MOCVD reaction chamber during the growth of the quantum barrier layer is controlled at 860℃~900℃, and the pressure is controlled at 150 torr~250 torr. The N (nitrogen) source can be NH3, the Ga (gallium) source can be TEGa, and the thickness of the deposited GaN quantum barrier layer is controlled at 8nm~12nm.

[0053] S270: A P-type electron blocking layer 8 is grown on the active layer 7;

[0054] Specifically, a P-type electron blocking layer 8 is grown in MOCVD. The P-type electron blocking layer 8 can be an AlInGaN electron blocking layer. The specific growth process is as follows: the temperature of the MOCVD reaction chamber is controlled at 940℃~1000℃, the pressure is controlled at 150 torr~250 torr, NH3 is used as the N (nitrogen) source, TEGa is used as the Ga (gallium) source, TMAl is used as the Al source, and TMIn is used as the In source. The thickness of the deposited P-type AlInGaN electron blocking layer is controlled to be 10nm~30nm.

[0055] S280: A P-type gallium nitride layer 9 is grown on the P-type electron blocking layer 8;

[0056] Specifically, the growth process of the p-type gallium nitride layer 9 in MOCVD is as follows: the MOCVD reaction chamber temperature is controlled at 930℃~1000℃, the pressure is controlled at 150 torr~250 torr, NH3 is used as the N (nitrogen) source, TEGa is used as the Ga (gallium) source, and CP2Mg is used as the p-type dopant. The thickness of the deposited p-type gallium nitride layer 9 is controlled to be 5nm~15nm, wherein the Mg doping concentration can be 5×E18~5×E20 atoms / cm 3 .

[0057] The present invention will be further described below with reference to specific embodiments:

[0058] Example 1

[0059] This embodiment provides a GaN-based LED epitaxial wafer. Please refer to [link / reference]. Figure 1 It includes a substrate 1 and a buffer layer 2, an undoped gallium nitride layer 3, an N-type gallium nitride layer 4, an extension layer 5, a retardation layer 6, an active layer 7, a P-type electron blocking layer 8, and a P-type gallium nitride layer 9 sequentially disposed on the substrate 1.

[0060] In this design, substrate 1 is a sapphire substrate, buffer layer 2 is a GaN buffer layer with a thickness of 18 nm, undoped gallium nitride layer 3 has a thickness of 1.2 μm, and N-type gallium nitride layer 4 is doped with Si with a doping concentration of 5.5E18 atoms / cm². 3 The thickness of the N-type gallium nitride layer 4 is 1.5 μm. The extended layer 5 is formed by alternating InGaN and GaN layers for three cycles, i.e., there are three extended sub-layers. Each extended sub-layer consists of an InGaN layer and a GaN layer deposited on top of the InGaN layer. The thickness of the extended layer 5 is 30 nm. Specifically, the diffraction intensity corresponding to the maximum In content in the extended layer 5 is 1 × 10⁻⁶. 4 The minimum c / s value corresponds to a diffraction intensity of 5 × 10⁻⁶. 3 c / s, with a maximum Si content of 2×10 18 atoms / cm 3 The minimum value is 1.75 × 10 18 atoms / cm 3 It should be noted that in each extended sublayer, the diffraction intensity value of In increases from a minimum of 5 × 10⁻⁶. 3 c / s gradually increases to a maximum value of 1×10 4 c / s, then gradually decreases to a minimum of 5 × 10 3 c / s, while the Si content shows the opposite trend, increasing from a maximum of 2 × 10 18 atoms / cm 3 It gradually decreased to the minimum value of 1.75 × 10. 18 atoms / cm3 Then it gradually rises to the maximum value of 2×10 18 atoms / cm 3 The retardation layer 6 is formed by alternating InGaN and GaN layers for six cycles. Similarly, the retardation layer 6 has six retardation sublayers, each consisting of an InGaN layer and a GaN layer deposited on top of that InGaN layer. The thickness of the retardation layer 6 is 40 nm, and the diffraction intensity corresponding to the maximum In content in the retardation layer 6 is 4 × 10⁻⁶. 4 The minimum value of c / s corresponds to a diffraction intensity of 8 × 10⁻⁶. 3 c / s, with a maximum Si content of 4×10 17 atoms / cm 3 The minimum Si content is 3 × 10⁻⁶. 17 atoms / cm 3 It should be noted that in each hysteresis sublayer, the diffraction intensity value of In increases from the minimum value of 8 × 10⁻⁶ in extended layer 5. 3 c / s gradually increases to a maximum value of 1×10 4 c / s, then gradually decreases to a minimum of 8 × 10 3 c / s, while the Si content, conversely, increases from a maximum of 2 × 10 in extended layer 5. 18 atoms / cm 3 Gradually decreasing to the minimum value of 3×10 17 atoms / cm 3 Then it gradually rises to the maximum value of 4×10 of the lag sublayer. 17 atoms / cm 3 .

[0061] Furthermore, the active layer 7 is formed by periodically alternating InGaN quantum barrier layers and GaN quantum well layers, with a growth cycle number of 10. The thickness of the active layer 7 is 120 nm. The p-type electron blocking layer 8 is an AlInGaN electron blocking layer with a thickness of 20 nm. The p-type gallium nitride layer 9 is doped with Mg at a doping concentration of 5E19 atoms / cm². 3 The thickness of the p-type gallium nitride layer 9 is 10 nm.

[0062] The epitaxial growth method for GaN-based LED epitaxial wafers in this embodiment includes the following steps:

[0063] (1) Provide substrate 1; load substrate 1 into MOCVD and anneal it at 1150℃, 450 torr, and hydrogen atmosphere for 6 min.

[0064] (2) Grow a buffer layer 2 on substrate 1;

[0065] Specifically, GaN buffer layer 2 is grown by MOCVD at a growth temperature of 800℃ and a growth pressure of 150 torr. NH3 is introduced into the MOCVD reaction chamber as the N (nitrogen) source, H2 and N2 are used as carrier gases, and TMGa is introduced as the Ga (gallium) source.

[0066] (3) An undoped gallium nitride layer 3 is grown on the buffer layer 2;

[0067] Specifically, an undoped gallium nitride layer 3 was grown using MOCVD at a growth temperature of 1100℃ and a growth pressure of 200 torr. NH3 was introduced into the MOCVD reaction chamber as the N (nitrogen) source, H2 and N2 were used as carrier gases, and TMGa was introduced as the Ga (ga) source.

[0068] (4) An N-type gallium nitride layer 4 is grown on the undoped gallium nitride layer 3;

[0069] Specifically, an N-type gallium nitride layer 4 was grown using MOCVD, with a growth temperature of 1100℃ and a growth pressure of 200 torr. NH3 was introduced into the MOCVD reaction chamber as the N (nitrogen) source, SiH4 was introduced as the N-type dopant, H2 and N2 were used as carrier gases, and TMGa was introduced as the Ga (ga) source.

[0070] (5) An extended layer 5 is grown on the N-type gallium nitride layer 4;

[0071] Specifically, InGaN and GaN layers are periodically grown in MOCVD to obtain extended layer 5. The growth temperature is 850℃ and the growth pressure is 200 torr. NH3 is introduced as the N (nitrogen) source, SiH4 is introduced as the Si (silicon) source, H2 or N2 is used as the carrier gas, TMGa is introduced as the Ga (gallium) source, and TMIn is introduced as the In (indium) source. It should be noted that the flow rate of NH3 as the N (nitrogen) source is 55L, and the flow rate of TMIn as the In (indium) source can be 1200sccm.

[0072] (6) Grow a lag layer 6 on the extended layer 5;

[0073] Specifically, InGaN and GaN layers are periodically grown in MOCVD to obtain retardation layer 6. The growth temperature is 800℃ and the growth pressure is 200 torr. NH3 is introduced as the N (nitrogen) source, SiH4 is introduced as the Si (silicon) source, H2 or N2 is used as the carrier gas, TMGa is introduced as the Ga (gallium) source, and TMIn is introduced as the In (indium) source. It should be noted that the flow rate of NH3 as the N (nitrogen) source is 55L, and the flow rate of TMIn as the In (indium) source can be 1600sccm.

[0074] (7) An active layer 7 is grown on the sluggish layer 6;

[0075] Specifically, InGaN and GaN layers are periodically grown in MOCVD to obtain active layer 7, wherein the InGaN layer is a quantum well layer and the GaN layer is a quantum barrier layer. The thickness of the quantum well layer is 3 nm, the growth temperature is 780 °C, and the growth pressure is 200 torr. The thickness of the quantum barrier layer is 9 nm, the growth temperature is 880 °C, and the growth pressure is 200 torr. NH3 is introduced into the MOCVD reaction chamber as the N (nitrogen) source, H2 or N2 is used as the carrier gas, TMGa is introduced as the Ga (gallium) source, and TMIn is introduced as the In (indium) source.

[0076] (8) A P-type electron blocking layer 8 is grown on the active layer 7;

[0077] Specifically, an AlInGaN electron blocking layer was grown using MOCVD at a growth temperature of 960℃ and a growth pressure of 220 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N (nitrogen) source, H2 and N2 were used as carrier gases, TMGa was introduced as the Ga (gallium) source, TMIn was introduced as the In (indium) source, and TMAl was introduced as the Al source.

[0078] (9) A P-type gallium nitride layer 9 is grown on the P-type electron blocking layer 8;

[0079] Specifically, a P-type gallium nitride layer 9 was grown using MOCVD at a growth temperature of 950℃ and a growth pressure of 220 torr. During growth, NH3 was introduced into the MOCVD reaction chamber as the N (nitrogen) source, CP2Mg was introduced as the P-type dopant, H2 and N2 were used as carrier gases, and TMGa was introduced as the Ga (ga) source.

[0080] Example 2

[0081] This embodiment also provides a GaN-based LED epitaxial wafer. The difference from Embodiment 1 is that, in the extended layer 5, the diffraction intensity value corresponding to the maximum In content is 5 × 10⁻⁶. 3 c / s, in lag layer 6, the diffraction intensity value corresponding to the maximum In content is 2×10 4 c / s.

[0082] Example 3

[0083] This embodiment also provides a GaN-based LED epitaxial wafer. The difference from Embodiment 1 is that, in the extended layer 5, the diffraction intensity value corresponding to the maximum In content is 2.5 × 10⁻⁶. 4 c / s, in lag layer 6, the diffraction intensity value corresponding to the maximum In content is 1×10 5 c / s.

[0084] Example 4

[0085] This embodiment also provides a GaN-based LED epitaxial wafer, the difference from Embodiment 1 being that the maximum Si content in the extended layer 5 is 1×10⁻⁶. 18 atoms / cm 3 In the retardation layer 6, the maximum Si content is 2 × 10⁻⁶. 17 atoms / cm 3 .

[0086] Example 5

[0087] This embodiment also provides a GaN-based LED epitaxial wafer, the difference from Embodiment 1 being that the maximum Si content in the extended layer 5 is 2.5 × 10⁻⁶. 18 atoms / cm 3 In the retardation layer 6, the maximum Si content is 3 × 10⁻⁶. 17 atoms / cm 3 .

[0088] Comparative Example 1

[0089] This comparative example provides a GaN-based LED epitaxial wafer. The difference from Example 1 is that the Si and In contents remain constant during the growth of the extended layer 5 and the retardation layer 6. Specifically, in the extended layer 5, the diffraction intensity value of In is 1 × 10⁻⁶. 4 c / s, Si content is 2×10 18 atoms / cm 3 In the retardation layer 6, the diffraction intensity value of In is 4 × 10⁻⁶. 4 c / s, Si content is 4×10 17 atoms / cm 3 .

[0090] Comparative Example 2

[0091] This comparative example provides a GaN-based LED epitaxial wafer, which differs from Example 1 in that the maximum Si content in the extended layer 5 is 1.2 × 10⁻⁶. 18 atoms / cm 3 In the retardation layer 6, the diffraction intensity corresponding to the maximum In content is 2 × 10⁻⁶. 4 c / s.

[0092] The GaN-based LEDs obtained in Examples 1-5 and Comparative Examples 1-2 were tested. Specifically, the antistatic performance and brightness of the GaN-based LEDs were tested. The antistatic performance test was conducted using an electrostatic meter under the HBM (Human Body Discharge Model) model to test the antistatic performance of the base chip. The percentage of the chip that could withstand a reverse 6000V static electricity was tested. The brightness test was conducted by measuring the luminous intensity of the chip when a current of 120mA was applied.

[0093] The specific results are as follows:

[0094]

[0095] As can be seen from the table, the LEDs prepared by the method in the embodiments of the present invention can effectively improve antistatic performance and brightness. The highest antistatic performance can reach 98.5%, and the highest brightness can reach 184.6mW.

[0096] In summary, the GaN-based LED epitaxial wafer and epitaxial growth method in the embodiments of the present invention, by controlling the change of the In content of the extended and retarded sublayers in the extended and retarded layers first increasing and then decreasing, can generate a potential well depth between the active layer, the retarded layer, and the extended layer. Moreover, the potential well of the retarded layer closer to the active layer is relatively deeper, which can effectively slow down the migration rate of electrons to the active layer, improve the electron confinement ability of the active layer, and improve the non-radiative recombination of electrons injected into the p-type nitride layer, ultimately achieving the goal of improving luminous efficiency. In addition, by controlling the change of the Si content of the extended and retarded sublayers in the extended and retarded layers first decreasing and then increasing, and with the Si content of the extended layer being higher than that of the retarded layer, the lateral expansion capability between the retarded layer and the extended layer can be improved, the antistatic capability of the epitaxial layer can be improved, and the reliability of the process can be improved.

[0097] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A GaN-based LED epitaxial wafer, characterized in that, The system includes an extended layer and a retardation layer deposited on the extended layer. The extended layer includes a plurality of extended sub-layers stacked sequentially, and the retardation layer includes a plurality of retardation sub-layers stacked sequentially. Both the extended sub-layers and the retardation sub-layers are formed by stacking InGaN layers and GaN layers sequentially. Both the extended sub-layers and the retardation sub-layers are doped with In and Si during the growth of the extended sub-layers and the retardation sub-layers. During the growth of the extended sublayer and the retarded sublayer, the In content first increases and then decreases along the epitaxial growth direction, while the Si content first decreases and then increases along the epitaxial growth direction, and the maximum value of the In content corresponds to the minimum value of the Si content.

2. The GaN-based LED epitaxial wafer according to claim 1, characterized in that, The ratio of the diffraction intensity value corresponding to the maximum In content in the extended sublayer to the diffraction intensity value corresponding to the maximum In content in the hysteretic sublayer is less than 1 / 2.

3. The GaN-based LED epitaxial wafer according to claim 1, characterized in that, The ratio of the maximum Si content in the extended sublayer to the maximum Si content in the lag sublayer is greater than 3.

4. The GaN-based LED epitaxial wafer according to claim 2, characterized in that, The diffraction intensity value corresponding to the maximum In content in the extended sublayer is 5 × 10⁻⁶. 3 c / s ~ 5 × 10 4 c / s.

5. The GaN-based LED epitaxial wafer according to claim 4, characterized in that, The diffraction intensity value corresponding to the maximum In content in the retarded sublayer is 1×10⁻⁶. 4 c / s ~ 1×10 5 c / s.

6. The GaN-based LED epitaxial wafer according to claim 3, characterized in that, The maximum Si content in the extended sublayer is 1×10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 .

7. The GaN-based LED epitaxial wafer according to claim 6, characterized in that, The maximum Si content in the retarder sublayer is 1×10⁻⁶. 17 atoms / cm 3 ~5×10 17 atoms / cm 3 .

8. The GaN-based LED epitaxial wafer according to claim 1, characterized in that, The GaN-based LED epitaxial wafer also includes a substrate, a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, an active layer, a P-type electron blocking layer, and a P-type gallium nitride layer. Specifically, the buffer layer, the undoped gallium nitride layer, the N-type gallium nitride layer, the extended layer, the retardation layer, the active layer, the P-type electron blocking layer, and the P-type gallium nitride layer are sequentially deposited on the substrate along the epitaxial growth direction.

9. The GaN-based LED epitaxial wafer according to claim 8, characterized in that, The In doping concentration of the retardation layer is lower than that of the In doping concentration of the active layer.

10. A method for epitaxial growth of GaN-based LED epitaxial wafers, characterized in that, The epitaxial growth method for preparing the GaN-based LED epitaxial wafer according to any one of claims 1-9 comprises: An extended layer and a retardation layer are epitaxially grown sequentially. The extended layer includes several extended sub-layers stacked sequentially, and the retardation layer includes several retardation sub-layers stacked sequentially. Both the extended sub-layers and the retardation sub-layers are formed by stacking InGaN layers and GaN layers sequentially. In and Si are doped during the growth of the extended sub-layers and the retardation sub-layers. In the process of growing the extended sublayer and the retarded sublayer, the In content is controlled to first increase and then decrease along the epitaxial growth direction, and the Si content is controlled to first decrease and then increase along the epitaxial growth direction, and the maximum value of the In content corresponds to the minimum value of the Si content.

Images