Shift register, scan driving circuit and display device

Abstract

A shift register (100) is electrically connected with at least one row of sub-pixels. The shift register (100) comprises a first scanning unit (1) and a black insertion circuit (2). The first scanning unit (1) comprises a first input circuit (11) and a first output circuit (12). The first input circuit (11) is configured to transmit a display input signal to a first pull-up node. The first output circuit (12) is configured to, in the case that the first input circuit (11) transmits the display input signal to the first pull-up node, transmit a first clock signal received at a first clock signal terminal to a first scanning signal terminal, and drive the at least one row of sub-pixels to display an image. The black insertion circuit (2) is configured to transmit a black insertion input signal to the first pull-up node. The first output circuit (12) is further configured to, in the case that the black insertion circuit (2) transmits the black insertion input signal to the first pull-up node, transmit the first clock signal to the first scanning signal terminal under the control of a voltage of the first pull-up node, and drive the at least one row of sub-pixels to display a black image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a scan drive circuit, and a display device. Background Technology

[0002] The scan drive circuit is an important component of a display device. It may include multiple cascaded shift registers, each of which can be electrically connected to at least one line in the display device. The scan drive circuit can input scan signals line by line into multiple lines (e.g., gate lines or enable signal lines) in the display device, enabling the display device to display an image.

[0003] Incorporating a scanning drive circuit into a display device can effectively reduce costs and improve yield. Summary of the Invention

[0004] On one hand, a shift register is provided. The shift register is applied to a display device comprising multiple rows of sub-pixels. The shift register is electrically connected to at least one row of sub-pixels. The shift register includes a first scanning unit and a black-insertion circuit. The first scanning unit includes a first input circuit and a first output circuit. The first input circuit is electrically connected to a display input signal terminal and a first pull-up node; the first input circuit is configured to transmit a display input signal received at the display input signal terminal to the first pull-up node in response to the display input signal received at the display input signal terminal. The first output circuit is electrically connected to the first pull-up node, a first clock signal terminal, and a first scan signal terminal; the first output circuit is configured to, when the first input circuit transmits the display input signal to the first pull-up node, under the control of the voltage of the first pull-up node, transmit a first clock signal received at the first clock signal terminal to the first scan signal terminal, driving the at least one row of sub-pixels to display an image. The black pixel insertion circuit is electrically connected to a first control signal terminal, a black pixel insertion cascade signal terminal, a second control signal terminal, a black pixel insertion input signal terminal, a first pull-up node, and a first voltage signal terminal. The black pixel insertion circuit is configured to, under the control of the first control signal transmitted from the first control signal terminal, the black pixel insertion cascade signal transmitted from the black pixel insertion cascade signal terminal, and the second control signal transmitted from the second control signal terminal, transmit the black pixel insertion input signal received at the black pixel insertion input signal terminal to the first pull-up node. The output circuit is further configured to, when the black pixel insertion circuit transmits the black pixel insertion input signal to the first pull-up node, transmit the first clock signal to the first scan signal terminal under the control of the voltage of the first pull-up node, driving the at least one row of sub-pixels to display a black screen.

[0005] In some embodiments, the shift register further includes a second scanning unit. The second scanning unit includes a second input circuit and a second output circuit. The second input circuit is electrically connected to the display input signal terminal and the second pull-up node; the second input circuit is configured to transmit the display input signal to the second pull-up node in response to the display input signal. The second output circuit is electrically connected to the second pull-up node, a second clock signal terminal, and a second scan signal terminal; the second output circuit is configured to, when the second input circuit transmits the display input signal to the second pull-up node, under the control of the voltage of the second pull-up node, transmit the second clock signal received at the second clock signal terminal to the second scan signal terminal, driving the at least one row of sub-pixels to display an image. The black pixel insertion circuit is also electrically connected to the second pull-up node; the black pixel insertion circuit is further configured to transmit the black pixel insertion input signal to the second pull-up node simultaneously with transmitting the black pixel insertion input signal to the first pull-up node. The output circuit is further configured to, when the black insertion circuit transmits the black insertion input signal to the second pull-up node, transmit the second clock signal to the second scan signal terminal under the control of the voltage of the second pull-up node, thereby driving the at least one row of sub-pixels to display a black screen.

[0006] In some embodiments, the black insertion circuit includes: a black insertion control subcircuit, a black insertion input subcircuit, and a first black insertion transmission subcircuit. The black insertion control subcircuit is electrically connected to the first control signal terminal, the black insertion cascade signal terminal, the first voltage signal terminal, and the first black insertion node; the black insertion control subcircuit is configured to transmit the black insertion cascade signal to the first black insertion node under the control of the first control signal. The black insertion input subcircuit is electrically connected to the first black insertion node, the black insertion input signal terminal, and the second black insertion node; the black insertion input subcircuit is configured to transmit the black insertion input signal to the second black insertion node under the control of the voltage of the first black insertion node. The first black insertion transmission subcircuit is electrically connected to the second control signal terminal, the second black insertion node, and the first pull-up node; the first black insertion transmission subcircuit is configured to transmit the black insertion input signal from the second black insertion node to the first pull-up node under the control of the second control signal. If the shift register further includes a second scanning unit, the black insertion circuit further includes: a second black insertion transmission subcircuit. The second black insertion transmission sub-circuit is electrically connected to the second control signal terminal, the second black insertion node, and the second pull-up node; the second black insertion transmission sub-circuit is configured to transmit the black insertion input signal from the second black insertion node to the second pull-up node under the control of the second control signal.

[0007] In some embodiments, the first input circuit includes a first transistor. The control electrode of the first transistor is electrically connected to the display input signal terminal, the first terminal of the first transistor is electrically connected to the display input signal terminal, and the second terminal of the first transistor is electrically connected to the first pull-up node. The first output circuit includes a second transistor and a first capacitor. The control electrode of the second transistor is electrically connected to the first pull-up node, the first terminal of the second transistor is electrically connected to the first clock signal terminal, and the second terminal of the second transistor is electrically connected to the first scan signal terminal. The first terminal of the first capacitor is electrically connected to the first pull-up node, and the second terminal of the first capacitor is electrically connected to the first scan signal terminal. When the shift register further includes a second scan unit, the second input circuit includes a third transistor. The control electrode of the third transistor is electrically connected to the display input signal terminal, the first terminal of the third transistor is electrically connected to the display input signal terminal, and the second terminal of the third transistor is electrically connected to the second pull-up node. The second output circuit includes a fourth transistor and a second capacitor. The control electrode of the fourth transistor is electrically connected to the second pull-up node, the first terminal of the fourth transistor is electrically connected to the second clock signal terminal, and the second terminal of the fourth transistor is electrically connected to the second scan signal terminal. The first terminal of the second capacitor is electrically connected to the second pull-up node, and the second terminal of the second capacitor is electrically connected to the second scan signal terminal. In the case where the black-insertion circuit includes a black-insertion control sub-circuit, a black-insertion input sub-circuit, a first black-insertion transmission sub-circuit, and a second black-insertion transmission sub-circuit, the black-insertion control sub-circuit includes: a fifth transistor and a third capacitor. The control electrode of the fifth transistor is electrically connected to the first control signal terminal, the first electrode of the fifth transistor is electrically connected to the black-insertion cascade signal terminal, and the second electrode of the fifth transistor is electrically connected to the first black-insertion node. The first terminal of the third capacitor is electrically connected to the first black-insertion node, and the second terminal of the third capacitor is electrically connected to the first voltage signal terminal. The black-insertion input sub-circuit includes: a sixth transistor. The control electrode of the sixth transistor is electrically connected to the first black-insertion node, the first electrode of the sixth transistor is electrically connected to the black-insertion input signal terminal, and the second electrode of the sixth transistor is electrically connected to the second black-insertion node. The first black-insertion transmission sub-circuit includes: a seventh transistor. The control electrode of the seventh transistor is electrically connected to the second control signal terminal, the first electrode of the seventh transistor is electrically connected to the second black-insertion node, and the second electrode of the seventh transistor is electrically connected to the first pull-up node. The second black-insertion transmission sub-circuit includes an eighth transistor. The control terminal of the eighth transistor is electrically connected to the second control signal terminal, the first terminal of the eighth transistor is electrically connected to the second black-insertion node, and the second terminal of the eighth transistor is electrically connected to the second pull-up node.

[0008] In some embodiments, the first output circuit is also electrically connected to a third clock signal terminal and a first sensing signal terminal. The first output circuit is further configured to, when the first input circuit transmits the display input signal to the first pull-up node, transmit the third clock signal received at the third clock signal terminal to the first sensing signal terminal under the control of the voltage of the first pull-up node, driving the at least one row of sub-pixels to reset; or, when the black insertion circuit transmits the black insertion input signal to the first pull-up node, transmit the third clock signal to the first sensing signal terminal under the control of the voltage of the first pull-up node, driving the at least one row of sub-pixels to display a black screen. If the shift register further includes a second scanning unit, the second output circuit is also electrically connected to a fourth clock signal terminal and a second sensing signal terminal. The second output circuit is further configured to, when the second input circuit transmits the display input signal to the second pull-up node, transmit the fourth clock signal received at the fourth clock signal terminal to the second sensing signal terminal under the control of the voltage of the second pull-up node, thereby driving the at least one row of sub-pixels to reset; or, when the black insertion circuit transmits the black insertion input signal to the second pull-up node, transmit the fourth clock signal to the second sensing signal terminal under the control of the voltage of the second pull-up node, thereby driving the at least one row of sub-pixels to display a black screen.

[0009] In some embodiments, the first output circuit further includes a ninth transistor and a fourth capacitor. The control electrode of the ninth transistor is electrically connected to the first pull-up node, the first electrode of the ninth transistor is electrically connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the first sensing signal terminal. The first terminal of the fourth capacitor is electrically connected to the first pull-up node, and the second terminal of the fourth capacitor is electrically connected to the first sensing signal terminal. The second output circuit further includes a tenth transistor and a fifth capacitor. The control electrode of the tenth transistor is electrically connected to the second pull-up node, the first electrode of the tenth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the second sensing signal terminal. The first terminal of the fifth capacitor is electrically connected to the second pull-up node, and the second terminal of the fifth capacitor is electrically connected to the second sensing signal terminal.

[0010] In some embodiments, the first output circuit is also electrically connected to a fifth clock signal terminal and a first shift signal terminal. The first output circuit is further configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first shift signal terminal under the control of the voltage of the first pull-up node.

[0011] In some embodiments, the first output circuit further includes an eleventh transistor. The control terminal of the eleventh transistor is electrically connected to the first pull-up node, the first terminal of the eleventh transistor is electrically connected to the fifth clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the first shift signal terminal.

[0012] In some embodiments, where the shift register further includes a second scan unit, the second output circuit is also electrically connected to the sixth clock signal terminal and the second shift signal terminal. The second output circuit is further configured to transmit the sixth clock signal received at the sixth clock signal terminal to the second shift signal terminal under the control of the voltage of the second pull-up node.

[0013] In some embodiments, the second output circuit further includes a twelfth transistor. The control terminal of the twelfth transistor is electrically connected to the second pull-up node, the first terminal of the twelfth transistor is electrically connected to the sixth clock signal terminal, and the second terminal of the twelfth transistor is electrically connected to the second shift signal terminal.

[0014] In some embodiments, the first scanning unit further includes a first reset circuit and a second reset circuit. The first reset circuit is electrically connected to a first reset signal terminal, a first pull-up node, and a first voltage signal terminal; the first reset circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the first pull-up node under the control of a first reset signal transmitted at the first reset signal terminal. When the black insertion circuit includes a black insertion control sub-circuit, the second reset circuit is electrically connected to a second reset signal terminal, the first black insertion node, the first pull-up node, and the first voltage signal terminal; the second reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of the voltage at the first black insertion node and a second reset signal transmitted at the second reset signal terminal. When the shift register further includes a second scanning unit, the second scanning unit further includes a third reset circuit and a fourth reset circuit. The third reset circuit is electrically connected to the first reset signal terminal, the second pull-up node, and the first voltage signal terminal; the third reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the first reset signal. The fourth reset circuit is electrically connected to the second reset signal terminal, the first black plug node, the second pull-up node, and the first voltage signal terminal; the fourth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the first black plug node and the second reset signal.

[0015] In some embodiments, the first reset circuit includes a thirteenth transistor. The control electrode of the thirteenth transistor is electrically connected to the first reset signal terminal, the first electrode of the thirteenth transistor is electrically connected to the first pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first voltage signal terminal. The second reset circuit includes a fourteenth transistor and a fifteenth transistor. The control electrode of the fourteenth transistor is electrically connected to the first black socket node, the first electrode of the fourteenth transistor is electrically connected to the first pull-up node, and the second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor. The control electrode of the fifteenth transistor is electrically connected to the second reset signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the first voltage signal terminal. The third reset circuit includes a sixteenth transistor. The control electrode of the sixteenth transistor is electrically connected to the first reset signal terminal, the first electrode of the sixteenth transistor is electrically connected to the second pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first voltage signal terminal. The fourth reset circuit includes a seventeenth transistor and an eighteenth transistor. The control terminal of the seventeenth transistor is electrically connected to the first black plug node, the first terminal of the seventeenth transistor is electrically connected to the second pull-up node, and the second terminal of the seventeenth transistor is electrically connected to the first terminal of the eighteenth transistor. The control terminal of the eighteenth transistor is electrically connected to the second reset signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the first voltage signal terminal.

[0016] In some embodiments, the first scanning unit further includes: a first control circuit electrically connected to the first pull-up node, the first pull-down node, the first voltage signal terminal, and the second voltage signal terminal; the first control circuit is configured to transmit the second voltage signal to the first pull-down node in response to a second voltage signal received at the second voltage signal terminal, and to transmit the first voltage signal received at the first voltage signal terminal to the first pull-down node under the control of the voltage of the first pull-up node. When the shift register further includes a second scanning unit, the second scanning unit further includes: a second control circuit electrically connected to the second pull-up node, the second pull-down node, the first voltage signal terminal, and the third voltage signal terminal; the second control circuit is configured to transmit the third voltage signal to the second pull-down node in response to a third voltage signal received at the third voltage signal terminal, and to transmit the first voltage signal to the second pull-down node under the control of the voltage of the second pull-up node.

[0017] In some embodiments, the first control circuit includes: a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor. The control electrode of the nineteenth transistor is electrically connected to the second voltage signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the control electrode of the twenty-first transistor and the first electrode of the twenty-first transistor. The first electrode of the twenty-first transistor is electrically connected to the second voltage signal terminal and is electrically connected to the first pull-down node. The control electrode of the twenty-first transistor is electrically connected to the first pull-up node, and the second electrode of the twenty-first transistor is electrically connected to the first voltage signal terminal. The control electrode of the twenty-second transistor is electrically connected to the first pull-up node, the first electrode of the twenty-second transistor is electrically connected to the first pull-down node, and the second electrode of the twenty-second transistor is electrically connected to the first voltage signal terminal. The second control circuit includes: a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, and a twenty-sixth transistor. The control electrode of the twenty-third transistor is electrically connected to the third voltage signal terminal, the first electrode of the twenty-third transistor is electrically connected to the third voltage signal terminal, and the second electrode of the twenty-third transistor is electrically connected to the control electrode of the twenty-fourth transistor and the first electrode of the twenty-fifth transistor. The first terminal of the 24th transistor is electrically connected to the third voltage signal terminal, and the second terminal of the 24th transistor is electrically connected to the second pull-down node. The control terminal of the 25th transistor is electrically connected to the second pull-up node, and the second terminal of the 25th transistor is electrically connected to the first voltage signal terminal. The control terminal of the 26th transistor is electrically connected to the second pull-up node, the first terminal of the 26th transistor is electrically connected to the second pull-down node, and the second terminal of the 26th transistor is electrically connected to the first voltage signal terminal.

[0018] In some embodiments, the first scanning unit further includes a fifth reset circuit, a sixth reset circuit, and a seventh reset circuit. The fifth reset circuit is electrically connected to the first pull-down node, the first pull-up node, and the first voltage signal terminal; the fifth reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the first pull-down node. The sixth reset circuit is electrically connected to the first pull-down node, the first scan signal terminal, and a fourth voltage signal terminal; the sixth reset circuit is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal to the first scan signal terminal under the control of the voltage of the first pull-down node. When the first output circuit is also electrically connected to the third clock signal terminal and the first sensing signal terminal, the sixth reset circuit is also electrically connected to the first sensing signal terminal; the sixth reset circuit is further configured to transmit the fourth voltage signal to the first sensing signal terminal under the control of the voltage of the first pull-down node. When the first output circuit is also electrically connected to the fifth clock signal terminal and the first shift signal terminal, the sixth reset circuit is also electrically connected to the first shift signal terminal and the first voltage signal terminal; the sixth reset circuit is further configured to transmit the first voltage signal to the first shift signal terminal under the control of the voltage of the first pull-down node. When the black insertion circuit includes a black insertion control sub-circuit, the seventh reset circuit is electrically connected to the first black insertion node, the second control signal terminal, the first pull-down node, and the first voltage signal terminal; the seventh reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the voltage of the first black insertion node and the second control signal. The second scanning unit further includes: an eighth reset circuit, a ninth reset circuit, and a tenth reset circuit. The eighth reset circuit is electrically connected to the second pull-down node, the second pull-up node, and the first voltage signal terminal; the eighth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the second pull-down node. The ninth reset circuit is electrically connected to the second pull-down node, the second scan signal terminal, and the fourth voltage signal terminal. The ninth reset circuit is configured to transmit the fourth voltage signal to the second scan signal terminal under the control of the voltage of the second pull-down node. When the second output circuit is also electrically connected to the fourth clock signal terminal and the second sensing signal terminal, the ninth reset circuit is also electrically connected to the second sensing signal terminal. The ninth reset circuit is further configured to transmit the fourth voltage signal to the second sensing signal terminal under the control of the voltage of the second pull-down node.With the second output circuit also electrically connected to the sixth clock signal terminal and the second shift signal terminal, the ninth reset circuit is also electrically connected to the second shift signal terminal and the first voltage signal terminal; the ninth reset circuit is further configured to transmit the first voltage signal to the second shift signal terminal under the control of the voltage of the second pull-down node. The tenth reset circuit is electrically connected to the first black insertion node, the second control signal terminal, the second pull-down node, and the first voltage signal terminal; the tenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the voltage of the first black insertion node and the second control signal.

[0019] In some embodiments, the fifth reset circuit includes a twenty-seventh transistor. The control electrode of the twenty-seventh transistor is electrically connected to the first pull-down node, the first electrode of the twenty-seventh transistor is electrically connected to the first pull-up node, and the second electrode of the twenty-seventh transistor is electrically connected to the first voltage signal terminal. The sixth reset circuit includes a twenty-eighth transistor, a twenty-ninth transistor, and a thirtieth transistor. The control electrode of the twenty-eighth transistor is electrically connected to the first pull-down node, the first electrode of the twenty-eighth transistor is electrically connected to the first scan signal terminal, and the second electrode of the twenty-eighth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the twenty-ninth transistor is electrically connected to the first pull-down node, the first electrode of the twenty-ninth transistor is electrically connected to the first sensing signal terminal, and the second electrode of the twenty-ninth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the thirtieth transistor is electrically connected to the first pull-down node, the first electrode of the thirtieth transistor is electrically connected to the first shift signal terminal, and the second electrode of the thirtieth transistor is electrically connected to the first voltage signal terminal. The seventh reset circuit includes a thirty-first transistor and a thirty-second transistor. The control electrode of the thirty-first transistor is electrically connected to the first black insertion node, the first electrode of the thirty-first transistor is electrically connected to the first pull-down node, and the second electrode of the thirty-first transistor is electrically connected to the first electrode of the thirty-second transistor. The control electrode of the thirty-second transistor is electrically connected to the second control signal terminal, and the second electrode of the thirty-second transistor is electrically connected to the first voltage signal terminal. The eighth reset circuit includes a thirty-third transistor. The control electrode of the thirty-third transistor is electrically connected to the second pull-down node, the first electrode of the thirty-third transistor is electrically connected to the second pull-up node, and the second electrode of the thirty-third transistor is electrically connected to the first voltage signal terminal. The ninth reset circuit includes a thirty-fourth transistor, a thirty-fifth transistor, and a thirty-sixth transistor. The control electrode of the thirty-fourth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-fourth transistor is electrically connected to the second scan signal terminal, and the second electrode of the thirty-fourth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the thirty-fifth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-fifth transistor is electrically connected to the second sensing signal terminal, and the second electrode of the thirty-fifth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the thirty-sixth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-sixth transistor is electrically connected to the second shift signal terminal, and the second electrode of the thirty-sixth transistor is electrically connected to the first voltage signal terminal. The tenth reset circuit includes a thirty-seventh transistor and a thirty-eighth transistor.The control terminal of the thirty-seventh transistor is electrically connected to the first black plug node, the first terminal of the thirty-seventh transistor is electrically connected to the second pull-down node, and the second terminal of the thirty-seventh transistor is electrically connected to the first terminal of the thirty-eighth transistor. The control terminal of the thirty-eighth transistor is electrically connected to the second control signal terminal, and the second terminal of the thirty-eighth transistor is electrically connected to the first voltage signal terminal.

[0020] In some embodiments, the fifth reset circuit is also electrically connected to the second pull-down node; the fifth reset circuit is also configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the second pull-down node. The sixth reset circuit is also electrically connected to the second pull-down node; the sixth reset circuit is also configured to transmit the fourth voltage signal to the first scan signal terminal, the fourth voltage signal to the first sensing signal terminal, and the first voltage signal to the first shift signal terminal under the control of the voltage of the second pull-down node. The eighth reset circuit is also electrically connected to the first pull-down node; the eighth reset circuit is also configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the first pull-down node. The ninth reset circuit is also electrically connected to the first pull-down node; the ninth reset circuit is also configured to transmit the fourth voltage signal to the second scan signal terminal, the fourth voltage signal to the second sensing signal terminal, and the first voltage signal to the second shift signal terminal under the control of the voltage of the first pull-down node.

[0021] In some embodiments, the fifth reset circuit further includes a thirty-ninth transistor. The control electrode of the thirty-ninth transistor is electrically connected to the second pull-down node, the first electrode of the thirty-ninth transistor is electrically connected to the first pull-up node, and the second electrode of the thirty-ninth transistor is electrically connected to the first voltage signal terminal. The sixth reset circuit further includes a fortieth transistor, a forty-first transistor, and a forty-second transistor. The control electrode of the fortieth transistor is electrically connected to the second pull-down node, the first electrode of the fortieth transistor is electrically connected to the first scan signal terminal, and the second electrode of the fortieth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the forty-first transistor is electrically connected to the second pull-down node, the first electrode of the forty-first transistor is electrically connected to the first sensing signal terminal, and the second electrode of the forty-first transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the forty-second transistor is electrically connected to the second pull-down node, the first electrode of the forty-second transistor is electrically connected to the first shift signal terminal, and the second electrode of the forty-second transistor is electrically connected to the first voltage signal terminal. The eighth reset circuit further includes a forty-third transistor. The control electrode of the forty-third transistor is electrically connected to the first pull-down node, the first electrode of the forty-third transistor is electrically connected to the second pull-up node, and the second electrode of the forty-third transistor is electrically connected to the first voltage signal terminal. The ninth reset circuit further includes a forty-fourth transistor, a forty-fifth transistor, and a forty-sixth transistor. The control electrode of the forty-fourth transistor is electrically connected to the first pull-down node, the first electrode of the forty-fourth transistor is electrically connected to the second scan signal terminal, and the second electrode of the forty-fourth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the forty-fifth transistor is electrically connected to the first pull-down node, the first electrode of the forty-fifth transistor is electrically connected to the second sensing signal terminal, and the second electrode of the forty-fifth transistor is electrically connected to the fourth voltage signal terminal. The control electrode of the forty-sixth transistor is electrically connected to the first pull-down node, the first electrode of the forty-sixth transistor is electrically connected to the second shift signal terminal, and the second electrode of the forty-sixth transistor is electrically connected to the first voltage signal terminal.

[0022] In some embodiments, the shift register further includes a blanking circuit. The blanking circuit is electrically connected to a third control signal terminal, a display input signal terminal, a seventh clock signal terminal, a first pull-up node, and a first voltage signal terminal. The blanking circuit is configured to transmit the seventh clock signal to the first pull-up node under the control of the third control signal transmitted at the third control signal terminal, the display input signal, and the seventh clock signal transmitted at the seventh clock signal terminal. If the shift register further includes a second scanning unit, the blanking circuit is also electrically connected to a second pull-up node; the blanking circuit is further configured to transmit the seventh clock signal to the second pull-up node.

[0023] In some embodiments, the blanking circuit includes: a selection control subcircuit, a blanking input subcircuit, a first blanking transmission subcircuit, and a second blanking transmission subcircuit. The selection control subcircuit is electrically connected to the third control signal terminal, the display input signal terminal, the first blanking node, and the first voltage signal terminal; the selection control subcircuit is configured to transmit the display input signal to the first blanking node under the control of the third control signal. The blanking transmission subcircuit is electrically connected to the first blanking node, the seventh clock signal terminal, and the second blanking node; the blanking transmission subcircuit is configured to transmit the seventh clock signal to the second blanking node under the control of the voltage of the first blanking node. The first blanking transmission subcircuit is electrically connected to the seventh clock signal terminal, the second blanking node, and the first pull-up node; the first blanking transmission subcircuit is configured to transmit the seventh clock signal from the second blanking node to the first pull-up node under the control of the seventh clock signal. The second blanking transmission sub-circuit is electrically connected to the seventh clock signal terminal, the second blanking node, and the second pull-up node; the second blanking transmission sub-circuit is configured to transmit the seventh clock signal from the second blanking node to the second pull-up node under the control of the seventh clock signal.

[0024] In some embodiments, the selection control sub-circuit includes a forty-seventh transistor and a sixth capacitor. The control electrode of the forty-seventh transistor is electrically connected to the third control signal terminal, the first electrode of the forty-seventh transistor is electrically connected to the display input signal terminal, and the second electrode of the forty-seventh transistor is electrically connected to the first blanking node. The first terminal of the sixth capacitor is electrically connected to the first blanking node, and the second terminal of the sixth capacitor is electrically connected to the first voltage signal terminal. The blanking input sub-circuit includes a forty-eighth transistor. The control electrode of the forty-eighth transistor is electrically connected to the first blanking node, the first electrode of the forty-eighth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the forty-eighth transistor is electrically connected to the second blanking node. The first blanking transmission sub-circuit includes a forty-ninth transistor. The control electrode of the forty-ninth transistor is electrically connected to the seventh clock signal terminal, the first electrode of the forty-ninth transistor is electrically connected to the second blanking node, and the second electrode of the forty-ninth transistor is electrically connected to the first pull-up node. The second blanking transmission sub-circuit includes a fiftieth transistor. The control terminal of the fiftieth transistor is electrically connected to the seventh clock signal terminal, the first terminal of the fiftieth transistor is electrically connected to the second blanking node, and the second terminal of the fiftieth transistor is electrically connected to the second pull-up node.

[0025] In some embodiments, the first scanning unit further includes an eleventh reset circuit, a twelfth reset circuit, and a thirteenth reset circuit. The eleventh reset circuit is electrically connected to a global reset signal terminal, the first pull-up node, and the first voltage signal terminal; the eleventh reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of the global reset signal transmitted at the global reset signal terminal. The twelfth reset circuit is electrically connected to the display input signal terminal, the first pull-down node, and the first voltage signal terminal; the twelfth reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the display input signal. When the blanking circuit includes a selection control sub-circuit, the thirteenth reset circuit is electrically connected to the first blanking node, the seventh clock signal terminal, the first pull-down node, and the first voltage signal terminal; the thirteenth reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the voltage of the first blanking node and the seventh clock signal. The second scanning unit further includes a fourteenth reset circuit, a fifteenth reset circuit, and a sixteenth reset circuit. The fourteenth reset circuit is electrically connected to the global reset signal terminal, the second pull-up node, and the first voltage signal terminal; the fourteenth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the global reset signal. The fifteenth reset circuit is electrically connected to the display input signal terminal, the second pull-down node, and the first voltage signal terminal; the fifteenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the display input signal. The sixteenth reset circuit is electrically connected to the first blanking node, the seventh clock signal terminal, the second pull-down node, and the first voltage signal terminal; the sixteenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the voltage of the first blanking node and the seventh clock signal.

[0026] In some embodiments, the eleventh reset circuit includes a fifty-first transistor. The control electrode of the fifty-first transistor is electrically connected to the global reset signal terminal, the first electrode of the fifty-first transistor is electrically connected to the first pull-up node, and the second electrode of the fifty-first transistor is electrically connected to the first voltage signal terminal. The twelfth reset circuit includes a fifty-second transistor. The control electrode of the fifty-second transistor is electrically connected to the display input signal terminal, the first electrode of the fifty-second transistor is electrically connected to the first pull-down node, and the second electrode of the fifty-second transistor is electrically connected to the first voltage signal terminal. The thirteenth reset circuit includes a fifty-third transistor and a fifty-fourth transistor. The control electrode of the fifty-third transistor is electrically connected to the first blanking node, the first electrode of the fifty-third transistor is electrically connected to the first pull-down node, and the second electrode of the fifty-third transistor is electrically connected to the first electrode of the fifty-fourth transistor. The control electrode of the fifty-fourth transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the fifty-fourth transistor is electrically connected to the first voltage signal terminal. The fourteenth reset circuit includes a fifty-fifth transistor. The control electrode of the 55th transistor is electrically connected to the global reset signal terminal. The first electrode of the 55th transistor is electrically connected to the second pull-up node, and the second electrode of the 55th transistor is electrically connected to the first voltage signal terminal. The 15th reset circuit includes a 56th transistor. The control electrode of the 56th transistor is electrically connected to the display input signal terminal. The first electrode of the 56th transistor is electrically connected to the second pull-down node, and the second electrode of the 56th transistor is electrically connected to the first voltage signal terminal. The 16th reset circuit includes a 57th transistor and a 58th transistor. The control electrode of the 57th transistor is electrically connected to the first blanking node. The first electrode of the 57th transistor is electrically connected to the second pull-down node, and the second electrode of the 57th transistor is electrically connected to the first electrode of the 58th transistor. The control electrode of the 58th transistor is electrically connected to the seventh clock signal terminal, and the second electrode of the 58th transistor is electrically connected to the first voltage signal terminal.

[0027] In some embodiments, the shift register further includes a first leakage protection circuit. The first leakage protection circuit is electrically connected to the first blanking node, the fifth voltage signal terminal, and the first leakage protection node; the first leakage protection circuit is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal to the first leakage protection node under the control of the voltage of the first blanking node. The selection control sub-circuit is also electrically connected to the first leakage protection node.

[0028] In some embodiments, the first leakage protection circuit includes a fifty-ninth transistor. The control electrode of the fifty-ninth transistor is electrically connected to the first blanking node, the first electrode of the fifty-ninth transistor is electrically connected to the fifth voltage signal terminal, and the second electrode of the fifty-ninth transistor is electrically connected to the first leakage protection node. The selection control sub-circuit further includes a sixtieth transistor. The control electrode of the sixtieth transistor is electrically connected to the third control signal terminal, the first electrode of the sixtieth transistor is electrically connected to the display input signal terminal, and the second electrode of the sixtieth transistor is electrically connected to the first leakage protection node. The first electrode of the forty-seventh transistor of the selection control sub-circuit is electrically connected to the first leakage protection node, and is electrically connected to the display input signal terminal through the sixtieth transistor.

[0029] In some embodiments, the shift register further includes a second leakage protection circuit. The second leakage protection circuit is electrically connected to the first pull-up node, the fifth voltage signal terminal, and the second leakage protection node. The second leakage protection circuit is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal to the second leakage protection node under the control of the voltage of the first pull-up node. The first input circuit is also electrically connected to the second leakage protection node. If the shift register further includes a second scanning unit, the second input circuit is also electrically connected to the second leakage protection node. The black-insertion circuit is also electrically connected to the second leakage protection node. If the first scanning unit further includes a first reset circuit and a second reset circuit, and the second scanning unit further includes a third reset circuit and a fourth reset circuit, the first reset circuit, the second reset circuit, the third reset circuit, and the fourth reset circuit are all electrically connected to the second leakage protection node. If the first scanning unit further includes a fifth reset circuit, and the second scanning unit further includes an eighth reset circuit, the fifth reset circuit and the eighth reset circuit are both electrically connected to the second leakage protection node. If the shift register further includes a blanking circuit, the blanking circuit is also electrically connected to the second leakage protection node. If the first scan unit further includes an eleventh reset circuit and the second scan unit further includes a fourteenth reset circuit, both the eleventh reset circuit and the fourteenth reset circuit are also electrically connected to the second leakage protection node.

[0030] In some embodiments, the second leakage protection circuit includes a sixty-first transistor. The control electrode of the sixty-first transistor is electrically connected to the first pull-up node, the first electrode of the sixty-first transistor is electrically connected to the fifth voltage signal terminal, and the second electrode of the sixty-first transistor is electrically connected to the second leakage protection node. The first input circuit further includes a sixty-second transistor. The control electrode of the sixty-second transistor is electrically connected to the display input signal terminal, the first electrode of the sixty-second transistor is electrically connected to the display input signal terminal, and the second electrode of the sixty-second transistor is electrically connected to the second leakage protection node. The first electrode of the first transistor is electrically connected to the second leakage protection node and is also electrically connected to the display input signal terminal through the sixty-second transistor. The first electrode of the third transistor in the second input circuit is electrically connected to the second leakage protection node and is also electrically connected to the display input signal terminal through the sixty-second transistor. When the black insertion circuit includes a first black insertion transmission sub-circuit, the first black insertion transmission sub-circuit further includes a sixty-third transistor. The control electrode of the sixty-third transistor is electrically connected to the second control signal terminal, the first electrode of the sixty-third transistor is electrically connected to the second black insertion node, and the second electrode of the sixty-third transistor is electrically connected to the second leakage protection node. The first terminal of the seventh transistor in the first black-insertion transmission sub-circuit is electrically connected to the second leakage protection node, and is also electrically connected to the second black-insertion node through the sixty-third transistor. The first terminal of the eighth transistor in the second black-insertion transmission sub-circuit is electrically connected to the second leakage protection node, and is also electrically connected to the second black-insertion node through the sixty-third transistor. The first reset circuit further includes a sixty-fourth transistor. The control terminal of the sixty-fourth transistor is electrically connected to the first reset signal terminal, the first terminal of the sixty-fourth transistor is electrically connected to the second leakage protection node, and the second terminal of the sixty-fourth transistor is electrically connected to the first voltage signal terminal. The second terminal of the thirteenth transistor in the first reset circuit is electrically connected to the second leakage protection node, and is also electrically connected to the first voltage signal terminal through the sixty-fourth transistor. The second reset circuit further includes a sixty-fifth transistor. The control terminal of the sixty-fifth transistor is electrically connected to the second reset signal terminal, the first terminal of the sixty-fifth transistor is electrically connected to the second leakage protection node, and the second terminal of the sixty-fifth transistor is electrically connected to the first voltage signal terminal. The second terminal of the fifteenth transistor in the second reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-fifth transistor.The second terminal of the eighteenth transistor in the fourth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-fifth transistor. The fifth reset circuit further includes a sixty-sixth transistor. The control terminal of the sixty-sixth transistor is electrically connected to the first pull-down node, the first terminal of the sixty-sixth transistor is electrically connected to the second leakage protection node, and the second terminal of the sixty-sixth transistor is electrically connected to the first voltage signal terminal. The second terminal of the twenty-seventh transistor in the fifth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-sixth transistor. The second terminal of the thirty-third transistor in the eighth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-sixth transistor. If the fifth reset circuit is also electrically connected to the second pull-down node, the fifth reset circuit further includes a sixty-seventh transistor. The control terminal of the sixty-seventh transistor is electrically connected to the second pull-down node, the first terminal of the sixty-seventh transistor is electrically connected to the second leakage protection node, and the second terminal of the sixty-seventh transistor is electrically connected to the first voltage signal terminal. The second terminal of the thirty-ninth transistor in the fifth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-seventh transistor. The second terminal of the forty-third transistor in the eighth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-seventh transistor. If the first scanning unit further includes an eleventh reset circuit, the eleventh reset circuit further includes a sixty-eighth transistor. The control terminal of the sixty-eighth transistor is electrically connected to the global reset signal terminal, the first terminal of the sixty-eighth transistor is electrically connected to the second leakage protection node, and the second terminal of the sixty-eighth transistor is electrically connected to the first voltage signal terminal. The second terminal of the fifty-first transistor in the eleventh reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-eighth transistor. The second terminal of the fifty-fifth transistor in the fourteenth reset circuit is electrically connected to the second leakage protection node, and is electrically connected to the first voltage signal terminal through the sixty-eighth transistor. If the blanking circuit includes a first blanking transmission sub-circuit, the first blanking transmission sub-circuit further includes a sixty-ninth transistor. The control terminal of the sixty-ninth transistor is electrically connected to the seventh clock signal terminal, the first terminal of the sixty-ninth transistor is electrically connected to the second blanking node, and the second terminal of the sixty-ninth transistor is electrically connected to the second leakage protection node. The first terminal of the forty-ninth transistor in the first blanking transmitter circuit is electrically connected to the second leakage protection node, and is also electrically connected to the second blanking node through the sixty-ninth transistor.The first terminal of the fiftieth transistor in the second blanking transporter circuit is electrically connected to the second leakage protection node, and is electrically connected to the second blanking node through the sixty-ninth transistor.

[0031] In some embodiments, the shift register further includes a third leakage protection circuit. The third leakage protection circuit is electrically connected to the first black-insertion node, the fifth voltage signal terminal, and the third leakage protection node; the third leakage protection circuit is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal to the third leakage protection node under the control of the voltage of the first black-insertion node. The black-insertion control sub-circuit is also electrically connected to the third leakage protection node.

[0032] In some embodiments, the third leakage protection circuit includes a seventieth transistor. The control electrode of the seventieth transistor is electrically connected to the first black insertion node, the first electrode of the seventieth transistor is electrically connected to the fifth voltage signal terminal, and the second electrode of the seventieth transistor is electrically connected to the third leakage protection node. The black insertion control sub-circuit further includes a seventy-first transistor. The control electrode of the seventy-first transistor is electrically connected to the first control signal terminal, the first electrode of the seventy-first transistor is electrically connected to the black insertion cascade signal terminal, and the second electrode of the seventy-first transistor is electrically connected to the third leakage protection node. The first electrode of the fifth transistor in the black insertion control sub-circuit is electrically connected to the third leakage protection node and is electrically connected to the black insertion cascade signal terminal through the seventy-first transistor.

[0033] On the other hand, a scan driving circuit is provided. The scan driving circuit includes: multiple cascaded shift registers as described in any of the above embodiments.

[0034] In some embodiments, the multi-level shift registers include multiple first shift register groups and multiple second shift register groups; the first shift register groups and second shift register groups are arranged alternately. When the shift registers include a first scan unit and a second scan unit, the first shift register group includes 2N levels of shift registers, and the second shift register group includes 2N levels of shift registers; where N is a positive integer. The scan driving circuit further includes: a first control signal line group, including a first sub-control signal line and a second sub-control signal line; the first sub-control signal line is electrically connected to the first control signal terminal of each shift register in the first shift register group, and the second sub-control signal line is electrically connected to the first control signal terminal of each shift register in the second shift register group; and a first clock signal line group, including 8N first sub-clock signal lines; the 8N first sub-clock signal lines are respectively electrically connected to the first clock signal terminal and the second clock signal terminal of each shift register in the first shift register group, and the first clock signal terminal and the second clock signal terminal of each shift register in the second shift register group. When the first output circuit of the shift register is also electrically connected to the third clock signal terminal and the first sensing signal terminal, and the second output circuit is also electrically connected to the fourth clock signal terminal and the second sensing signal terminal, the scan driving circuit further includes: a second clock signal line group. The second clock signal line group includes 4N second sub-clock signal lines; the 4N second sub-clock signal lines are respectively electrically connected to the third clock signal terminal and the fourth clock signal terminal of each shift register in the first shift register group, and are also respectively electrically connected to the third clock signal terminal and the fourth clock signal terminal of each shift register in the second shift register group. Alternatively, the second clock signal line group includes 8N second sub-clock signal lines; the 8N second sub-clock signal lines are respectively electrically connected to the third clock signal terminal and the fourth clock signal terminal of each shift register in the first shift register group, and the third clock signal terminal and the fourth clock signal terminal of each shift register in the second shift register group. When the first output circuit of the shift register is also electrically connected to the fifth clock signal terminal and the first shift signal terminal, and the second output circuit is also electrically connected to the sixth clock signal terminal and the second shift signal terminal, the scan drive circuit further includes: a third clock signal line group.The third clock signal line group includes 4N third sub-clock signal lines; the 4N third sub-clock signal lines are electrically connected to the fifth and sixth clock signal terminals of each shift register in the first shift register group, and are also electrically connected to the fifth and sixth clock signal terminals of each shift register in the second shift register group; or, 2N of the 4N third sub-clock signal lines are electrically connected to the fifth clock signal terminals of each shift register in the first shift register group, and the other 2N third sub-clock signal lines are electrically connected to the fifth clock signal terminals of each shift register in the second shift register group; or, the third clock signal line group includes 8N third sub-clock signal lines; the 8N third sub-clock signal lines are electrically connected to the fifth and sixth clock signal terminals of each shift register in the first shift register group and the fifth and sixth clock signal terminals of each shift register in the second shift register group.

[0035] In some embodiments, the scan driving circuit further includes a second control signal line group. The second control signal line group includes a third sub-control signal line and a fourth sub-control signal line. The third sub-control signal line is electrically connected to the second control signal terminal of each shift register in the first shift register group; the fourth sub-control signal line is electrically connected to the second control signal terminal of each shift register in the second shift register group.

[0036] In some embodiments, the third sub-control signal line is also electrically connected to the black insertion input signal terminal of each shift register in the first shift register group. The fourth sub-control signal line is also electrically connected to the black insertion input signal terminal of each shift register in the second shift register group.

[0037] In some embodiments, among the multiple shift registers, except for the first at least one shift register, the display input signal terminals of the remaining shift registers are electrically connected to the first shift signal terminal of the preceding shift register; except for the first at least two shift registers, the black slit concatenation signal terminals of the remaining shift registers are electrically connected to the second shift signal terminal of the preceding shift register; or, if the shift register further includes a second leakage protection circuit, except for the first at least two shift registers, the black slit concatenation signal terminals of the remaining shift registers are electrically connected to the second leakage protection node of the preceding shift register.

[0038] In some embodiments, among the multiple shift registers, except for the first at least one shift register, the display input signal terminal of the remaining shift registers is electrically connected to the second shift signal terminal of the preceding shift register; except for the first at least two shift registers, the black cascade signal terminal of the remaining shift registers is electrically connected to the first shift signal terminal of the preceding shift register.

[0039] In some embodiments, in the first shift register group, at least two shift registers share a black insertion circuit. In the second shift register group, at least two shift registers share a black insertion circuit.

[0040] In another aspect, a display device is provided. The display device includes: multiple rows of sub-pixels; and a scan driving circuit as described in any of the above embodiments. wherein a first-stage shift register in the scan driving circuit is electrically connected to at least one row of sub-pixels. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0042] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0043] Figure 2 This is a structural diagram of another display device according to some embodiments of the present disclosure;

[0044] Figure 3 This is a structural diagram of yet another display device according to some embodiments of the present disclosure;

[0045] Figure 4 This is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0046] Figure 5 According to a corresponding one in the related technology Figure 4 The timing diagram of the sub-pixels shown;

[0047] Figure 6 According to some embodiments of this disclosure, one corresponding to Figure 4 The timing diagram of the sub-pixels shown;

[0048] Figure 7 Another corresponding to some embodiments of this disclosure Figure 4 The timing diagram of the sub-pixels shown;

[0049] Figure 8 This is a structural diagram of a shift register according to some embodiments of the present disclosure;

[0050] Figure 9This is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0051] Figure 10 Here is a circuit diagram of a shift register according to some embodiments of this disclosure;

[0052] Figure 11 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0053] Figure 12 This is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0054] Figure 13 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0055] Figure 14 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0056] Figure 15 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0057] Figure 16 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0058] Figure 17 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0059] Figure 18 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0060] Figure 19 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0061] Figure 20 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0062] Figure 21 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0063] Figure 22 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0064] Figure 23 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0065] Figure 24 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0066] Figure 25 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0067] Figure 26 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0068] Figure 27 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0069] Figure 28 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0070] Figure 29 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0071] Figure 30 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0072] Figure 31 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0073] Figure 32 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0074] Figure 33 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0075] Figure 34 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0076] Figure 35 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0077] Figure 36 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0078] Figure 37 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0079] Figure 38 This is a structural diagram of a scanning drive circuit according to some embodiments of the present disclosure;

[0080] Figure 39 This is a structural diagram of another scanning drive circuit according to some embodiments of the present disclosure;

[0081] Figure 40 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0082] Figure 41 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0083] Figure 42 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0084] Figure 43 This is a circuit diagram of a black insertion circuit in a first shift register group or a second shift register group according to some embodiments of the present disclosure;

[0085] Figure 44 This is a circuit diagram of a black-insertion circuit in another first shift register group or second shift register group according to some embodiments of this disclosure;

[0086] Figure 45 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0087] Figure 46 According to some embodiments of this disclosure, one corresponding to Figure 38 The timing control diagram of the scan drive circuit is shown.

[0088] Figure 47 Another corresponding to some embodiments of this disclosure Figure 38 The timing control diagram of the scan drive circuit is shown.

[0089] Figure 48 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0090] Figure 49 According to some embodiments of this disclosure, one corresponding to Figure 39 The timing control diagram of the scan drive circuit is shown.

[0091] Figure 50 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure;

[0092] Figure 51 According to some embodiments of this disclosure, one corresponding to Figure 40 The timing control diagram of the scan drive circuit is shown.

[0093] Figure 52 This is a structural diagram of yet another scanning drive circuit according to some embodiments of the present disclosure. Detailed Implementation

[0094] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0095] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0096] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0097] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0098] In addition, in some embodiments, "electrical connection" can refer to either a direct electrical connection or an indirect electrical connection.

[0099] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0100] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0101] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0102] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0103] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0104] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0105] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0106] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors) or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example.

[0107] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0108] In the circuits provided in the embodiments of this disclosure, nodes such as pull-up nodes and pull-down nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0109] In embodiments of this disclosure, the term "pull-up" refers to charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn on). The term "pull-down" refers to discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn off).

[0110] In the circuits provided in the embodiments of this disclosure, all transistors are N-type transistors, which will be used as an example for explanation.

[0111] Some embodiments of this disclosure provide a shift register 100, a scan drive circuit 1000, and a display device 2000. The shift register 100, the scan drive circuit 1000, and the display device 2000 are described below.

[0112] Some embodiments of this disclosure provide a display device 2000, such as Figure 1As shown. The display device 2000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0113] In some examples, the display device 2000 described above may include a frame, a display panel disposed within the frame, a circuit board, a display driver IC (integrated circuit), and other electronic components.

[0114] The above-mentioned display panel types include various types, and you can choose the settings according to your actual needs.

[0115] For example, the above-mentioned display panel may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, etc., and this disclosure does not specifically limit it.

[0116] The following describes some embodiments of this disclosure using the example of an OLED display panel (i.e., display device 2000 being an OLED display device).

[0117] In some embodiments, such as Figure 2 and Figure 3 As shown, the display device 2000 has a display area A and a border area B disposed next to the display area A. Here, "next to" refers to one side, two sides, three sides, or the perimeter of the display area A, that is, the border area B can be located on one side, two sides, or three sides of the display area A, or the border area B can be disposed around the display area A.

[0118] In some embodiments, such as Figure 2 and Figure 3As shown, the display device 2000 may include: a substrate 200, a plurality of sub-pixels P, and a scan driving circuit 1000. The substrate 200 is used to support the plurality of sub-pixels and the scan driving circuit 1000.

[0119] For example, such as Figure 2 and Figure 3 As shown, the scan drive circuit 1000 can be located in the border area B. Of course, the scan drive circuit 1000 can also be located in other positions, and this disclosure does not limit this.

[0120] Here, the scan driving circuit 1000 can be, for example, a light-emitting control circuit or a gate driving circuit. In this disclosure, the scan driving circuit 1000 is illustrated as a gate driving circuit.

[0121] The substrate 200 mentioned above includes various types, which can be selected and set according to actual needs.

[0122] For example, substrate 200 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0123] For example, the substrate 200 can be a flexible substrate. This flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display device 2000 can be a flexible display panel.

[0124] For example, such as Figure 2 and Figure 3 As shown, the aforementioned multiple sub-pixels P can be located within the display area A. These multiple sub-pixels P can be arranged in multiple rows along a first direction X and in multiple columns along a second direction Y. Each row of sub-pixels P can include multiple sub-pixels P, and each column of sub-pixels P can include multiple sub-pixels P.

[0125] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 89° or 90°, etc.

[0126] In some examples, such as Figure 2 and Figure 3As shown, the display device 2000 may further include: a plurality of gate lines GL and a plurality of data lines DL disposed on one side of the substrate 200 and located in the display area A. The plurality of gate lines GL extend along a first direction X, and the plurality of data lines DL extend along a second direction Y.

[0127] For example, sub-pixels P arranged in a row along the first direction X can be called row sub-pixels P, and sub-pixels P arranged in a column along the second direction Y can be called column sub-pixels P. Row sub-pixels P can be electrically connected to at least one gate line GL, and column sub-pixels P can be electrically connected to one data line DL.

[0128] In some examples, such as Figure 4 As shown, each of the aforementioned multiple sub-pixels P may include a pixel driving circuit P1 and a light-emitting device P2 electrically connected to the pixel driving circuit P1. The light-emitting device may be an OLED.

[0129] For example, a gate line GL can be electrically connected to multiple pixel driving circuits P1 in the same row of sub-pixels P, and a data line DL can be electrically connected to multiple pixel driving circuits P2 in the same column of sub-pixels P.

[0130] The pixel driving circuit P1 described above has various structures, which can be selected and configured according to actual needs. For example, the structure of the pixel driving circuit P1 can include "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C", etc. Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0131] Here, during the use of the display device 2000, the stability of the transistors in the pixel driving circuit P1 and the light-emitting device P2 may decrease (for example, the threshold voltage of the driving transistors may drift), affecting the display effect of the display device 2000. Therefore, it is necessary to compensate for the sub-pixel P.

[0132] There are various ways to compensate for sub-pixel P, and the appropriate method can be selected based on actual needs. For example, a pixel compensation circuit can be incorporated into sub-pixel P to perform internal compensation. Alternatively, the driving transistor or light-emitting device can be sensed by a transistor inside sub-pixel P, and the sensed data can be transmitted to an external sensing circuit. This external sensing circuit can then calculate the required driving voltage value for compensation and provide feedback, thereby achieving external compensation for sub-pixel P.

[0133] This disclosure uses an external compensation method (sensing the driving transistor) and a pixel driving circuit with a "3T1C" structure as an example to illustrate the structure and working process of the sub-pixel P.

[0134] For example, such as Figure 4 As shown, the pixel driving circuit P1 may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

[0135] For example, such as Figure 4 As shown, the control terminal of the switching transistor T1 is electrically connected to the first gate signal terminal G1, the first terminal of the switching transistor T1 is electrically connected to the data signal terminal Data, and the second terminal of the switching transistor T1 is electrically connected to the first node G. The switching transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to a first scan signal received at the first gate signal terminal G1.

[0136] Here, the data signals include, for example, detection data signals and display data signals. The detection data signals are used during the blanking period, and the display data signals are used during the display period. The display period and blanking period can be referred to in the descriptions of some of the following embodiments, and will not be repeated here.

[0137] For example, such as Figure 4 As shown, the control terminal of driving transistor T2 is electrically connected to the first node G, the first terminal of driving transistor T2 is electrically connected to the sixth voltage signal terminal ELVDD, and the second terminal of driving transistor T2 is electrically connected to the second node S. Driving transistor T2 is configured to conduct under the control of the voltage at the first node G, generate a driving signal based on the voltage at the first node G and the sixth voltage signal received at the sixth voltage signal terminal ELVDD, and transmit the driving signal to the second node S.

[0138] For example, such as Figure 4 As shown, the first terminal of the storage capacitor Cst is electrically connected to the first node G, and the second terminal of the storage capacitor Cst is electrically connected to the second node S. The switching transistor T1 charges the storage capacitor Cst simultaneously while charging the first node G.

[0139] For example, such as Figure 4 As shown, the anode of the light-emitting device P2 is electrically connected to the second node S, and the cathode of the light-emitting device P2 is electrically connected to the seventh voltage signal terminal ELVSS. The light-emitting device P2 is configured to emit light under the drive signal.

[0140] For example, such as Figure 4As shown, the control terminal of sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first terminal of sensing transistor T3 is electrically connected to the second node S, and the second terminal of sensing transistor T3 is electrically connected to the sensing signal terminal Sense. Sensing transistor T3 is configured to detect the electrical characteristics of driving transistor T2 in response to a second scan signal received at the second gate signal terminal G2 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of driving transistor T2.

[0141] Here, the sensing signal terminal Sense can provide a reset signal or acquire a sensing signal. The reset signal is used to reset the second node S during the display period, and the acquire sensing signal is used to acquire the threshold voltage and / or carrier mobility of the driving transistor T2 during the blanking period.

[0142] Based on the structure of pixel driving circuit P1, such as Figure 2 As shown, multiple pixel driving circuits P1 in the same row of sub-pixels P can be electrically connected to two gate lines GL (i.e., the first gate line and the second gate line). For example, each first gate signal terminal G1 can be electrically connected to the first gate line and receive the first scan signal transmitted by the first gate line; each second gate signal terminal G2 can be electrically connected to the second gate line and receive the second scan signal transmitted by the second gate line.

[0143] It should be noted that the display phase of a frame may include, for example, a display period and a blanking period performed sequentially.

[0144] The display period in a frame display phase, such as Figure 5 As shown, the working process of sub-pixel P may include, for example, a reset phase t1, a data writing phase t2, and a light emission phase t3.

[0145] During the reset phase t1, the first scan signal is at a high level, the data signal terminal is at a low level (e.g., low level), the second scan signal is at a high level, and the sense signal terminal (Sense) provides a low level for the reset signal. Switching transistor T1 is turned on under the control of the first scan signal, receives the data signal, and transmits the data signal to the first node G to reset the first node G. Sensing transistor T3 is turned on under the control of the second scan signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.

[0146] During the data writing phase t2, the level of the first scan signal is high, and the level of the data signal (i.e., the display data signal) is also high. The switching transistor T1 remains on under the control of the first scan signal, receives the display data signal, transmits it to the first node G, and simultaneously charges the storage capacitor Cst.

[0147] During the light-emitting stage t3, the level of the first scan signal is low, the level of the second scan signal is low, and the level of the sixth voltage signal is high. Switching transistor T1 is turned off under the control of the first scan signal, and sensing transistor T3 is turned off under the control of the second scan signal. Storage capacitor Cst begins to discharge, keeping the voltage at the first node G high. Driving transistor T2 is turned on under the control of the voltage at the first node G, receives the sixth voltage signal, generates a driving signal, and transmits this driving signal to the second node S to drive the light-emitting device P2 to emit light.

[0148] During the blanking period in a frame display phase, the working process of subpixel P may include, for example, a first phase and a second phase.

[0149] In the first stage, both the first and second scan signals are at a high level, and the data signal (i.e., the detection data signal) is also at a high level. Switching transistor T1 is turned on under the control of the first scan signal, receives the detection data signal, and transmits it to the first node G to charge it. Sensing transistor T3 is turned on under the control of the second scan signal, receives a reset signal from the sensing signal terminal Sense, and transmits the reset signal to the second node S.

[0150] In the second stage, the sensing signal terminal Sense is in a floating state. Driven transistor T2 is turned on under the control of the voltage at the first node G, receiving the sixth voltage signal and transmitting it to the second node S to charge it, causing the voltage at the second node S to rise until driven transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of driven transistor T2.

[0151] Since the sensing transistor T3 is in the ON state and the sensing signal terminal Sense is in the Floating state, the driving transistor T2 charges the second node S simultaneously with the sensing signal terminal Sense. By sampling the voltage of the sensing signal terminal Sense (i.e., acquiring the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated based on the relationship between the voltage of the sensing signal terminal Sense and the level of the detected data signal.

[0152] After calculating the threshold voltage Vth of the driving transistor T2, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display stage, thus completing the external compensation of the sub-pixel P.

[0153] In some examples, the scan driving circuit 1000 described above is located on the same side of the substrate 200 as the plurality of sub-pixels P described above. The scan driving circuit 1000 may include multiple cascaded shift registers 100. A first-level shift register 100 may, for example, be electrically connected to at least one row of sub-pixels P (i.e., the plurality of pixel driving circuits P1 in the sub-pixels P).

[0154] It should be noted that during the display phase of one frame, the first scan signal transmitted by the first gate signal terminal G1 and the second scan signal transmitted by the second gate signal terminal G2 are both provided by the scan driving circuit 1000. That is, each shift register 100 in the scan driving circuit 1000 can be electrically connected to the first gate signal terminal G1 through a first gate line, transmitting the first scan signal to the first gate signal terminal G1 through the first gate line, and electrically connected to the second gate signal terminal G2 through a second gate line, transmitting the second scan signal to the second scan signal terminal G2 through the second gate line.

[0155] Of course, such as Figure 3 As shown, multiple pixel driving circuits P1 in the same row of sub-pixels P can also be electrically connected to the same gate line GL. In this case, the first scan signal and the second scan signal are the same. Each shift register 1 in the scan driving circuit 1000 can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 through the corresponding gate line GL, and transmits the scan signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL.

[0156] In related technologies, during the display process of the display device 2000, image ghosting will occur during the dynamic image switching process. That is, when the display device 2000 switches from one frame to another, the viewer will feel the ghosting of the previous frame (also known as dynamic image ghosting), which will affect the image display effect.

[0157] Based on this, such as Figures 39-42 As shown, some embodiments of this disclosure provide a scan driving circuit 1000. The scan driving circuit 1000 includes multiple cascaded shift registers 100. These shift registers 100 are used in the aforementioned display device 2000, and each shift register 100 is electrically connected to at least one row of sub-pixels P.

[0158] Here, the number of rows of sub-pixels P electrically connected to each shift register 100 can be determined according to the structure of the shift register 100.

[0159] In some embodiments, such as Figures 8-10 As shown, the shift register 100 includes a first scanning unit 1 and a black-insertion circuit 2. The first scanning unit 1 includes a first input circuit 11 and a first output circuit 12.

[0160] In some examples, such as Figures 8-10 As shown, the first input circuit 11 is connected to the display input signal terminal Iput and the first pull-up node Q. <1> Electrical connection. The first input circuit 11 is configured to transmit the display input signal to the first pull-up node Q in response to a display input signal received at the display input signal terminal Iput. <1> .

[0161] For example, when the display input signal level is high, the first input circuit 11 can be turned on by the display input signal to receive and transmit the display input signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0162] In some examples, such as Figures 8-10 As shown, the first output circuit 12 and the first pull-up node Q <1> The first clock signal terminal CLKE1 and the first scan signal terminal are electrically connected to Oput1. <n>The first output circuit 12 is configured to transmit the display input signal to the first pull-up node Q via the first input circuit 11. <1> In the case of the first pull-up node Q <1> Under the control of the voltage, the first clock signal received at the first clock signal terminal CLKE1 is transmitted to the first scan signal terminal Oput1. <n>This drives at least one row of sub-pixels P to display the image.

[0163] For example, in the first pull-up node Q <1> When the voltage is high, the first output circuit 12 can pull up at the first pull-up node Q. <1> Under the control of the voltage, it is turned on and transmits the first clock signal received at the first clock signal terminal CLKE1 to the first scan signal terminal Oput1. <n>And the first clock signal is used as the first scan signal, from the first scan signal terminal Oput1 <n>Output.

[0164] In this case, multiple pixel driving circuits P1 in the same row of sub-pixels P can be electrically connected to the same gate line GL. The first scan signal terminal Oput1 of a shift register 100... <n>This gate line GL can then be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 of multiple pixel driving circuits P1 in the corresponding row sub-pixel P. First scan signal terminal Oput1 <n>The first scan signal output can then be transmitted via the gate line GL to the first gate signal terminal G1 and the second gate signal terminal G2 of the multiple pixel driving circuit P1.

[0165] In some examples, such as Figures 8-10 As shown, the black bar insertion circuit 2 is connected to the first control signal terminal BCS1, the black bar insertion cascade signal terminal BCR, the second control signal terminal BCS2, the black bar insertion input signal terminal BI, and the first pull-up node Q. <1> And electrically connected to the first voltage signal terminal V1. The black insertion circuit 2 is configured to, under the control of the first control signal transmitted at the first control signal terminal BCS1, the black insertion cascade signal transmitted at the black insertion cascade signal terminal BCR, and the second control signal transmitted at the second control signal terminal BCS2, transmit the black insertion input signal received at the black insertion input signal terminal BI to the first pull-up node Q. <1> .

[0166] For example, when the level of the first control signal is high, the level of the black insertion cascade signal is high, and the level of the second control signal is high, the black insertion circuit 2 can be turned on under the control of the first control signal, the black insertion cascade signal, and the second control signal, receive the black insertion input signal, and transmit the black insertion input signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0167] Here, the first voltage signal terminal V1 is configured, for example, to transmit a DC low-level signal (e.g., a portion of the clock signal that is lower than or equal to the low level of the clock signal). Exemplarily, this first voltage terminal V1 is grounded.

[0168] For example, the output circuit 12 is also configured to transmit the black insertion input signal to the first pull-up node Q in the black insertion circuit 2. <1> In the case of the first pull-up node Q <1> Under the control of the voltage, the first clock signal is transmitted to the first scan signal terminal Oput1. <n>This drives at least one row of sub-pixels P to display a black screen.

[0169] For example, in the first pull-up node Q <1> When the voltage is high, the first output circuit 12 can pull up at the first pull-up node Q. <1> Under the control of the voltage, it is turned on and transmits the first clock signal received at the first clock signal terminal CLKE1 to the first scan signal terminal Oput1. <n>And the first clock signal is used as the first scan signal, from the first scan signal terminal Oput1 <n>Output.

[0170] It should be noted that, in the embodiments of this disclosure, during the display period of a frame display stage, the first input circuit 11 and the black insertion circuit 2 are turned on at different times.

[0171] like Figure 3 As shown, taking the example of multiple pixel driving circuits P1 in the same row of sub-pixels P, where the first gate signal terminal G1 and the second gate signal terminal G2 are electrically connected to the same gate line GL, the first scan signal terminal Oput1 is shown. <n>The output first scan signal corresponds to the scan signal received by the first gate signal terminal G1 and the second gate signal terminal G2.

[0172] During the display period in a frame display phase, the first pull-up node Q <1> The voltage is first boosted by the first input circuit 11. The first input circuit 11 is turned on and pulls up the first pull-up node Q. <1> After charging, the first output circuit 12 can be connected to the first pull-up node Q. <1> It is turned on under the control of the voltage, and the first clock signal is used as the first scan signal, from the first scan signal terminal Oput1. <n>Output. (e.g., ...) Figure 6 As shown, during the reset phase t1 and the data write phase t2, the first input circuit 11 is turned off, and the first pull-up node Q... <1> The voltage remains high, and the first output circuit 12 is at the first pull-up node Q. <1> The circuit remains in the conducting state under the influence of the voltage. Since the level of the first clock signal is high, the level of the first scan signal output by the first output circuit 12 is also high. During the light-emitting stage t3, the first pull-up node Q... <1> When the voltage is low, the first output circuit 12 is turned off, and the level of the first scan signal is low; the driving transistor T2 is turned on under the control of the voltage of the first node G (the storage capacitor Cst discharges), driving the light-emitting device P2 to emit light. Correspondingly, at least one row of sub-pixels P corresponding to the shift register 100 is used for image display.

[0173] At a certain moment during the light-emitting process of the light-emitting device P2 (i.e. Figure 6 As shown in the diagram, during the alternation of the light-emitting stage t3 and the black insertion writing stage t4, the black insertion circuit 2 is turned on and activates the first pull-up node Q. <1> During charging, the first output circuit 12 can be connected to the first pull-up node Q. <1> It is turned on under the control of the voltage. At this time, the first clock signal can be used as the black insertion signal from the first scan signal terminal Oput1. <n>The signal is output and transmitted to the first gate signal terminal G1 and the second gate signal terminal G2 of the corresponding row pixel driving circuit P1. Since the black insertion signal is at a high level, the switching transistor T1 can be turned on under the control of the black insertion signal, transmitting a low-level or lower-level data signal (also called the black insertion data signal) to the first node G; the sensing transistor T3 can also be turned on under the control of the black insertion signal, transmitting a low-level reset signal to the second node S. At this time, Vgs (that is, the voltage difference between the first node G and the second node S) is less than Vth (that is, the threshold voltage of the driving transistor T2), causing the sub-pixel P to stop emitting light and switch to a black screen. During the black insertion holding phase t5, the sub-pixel P continues to display a black screen.

[0174] Therefore, the shift register 100 provided in some embodiments of this disclosure, by setting the black-insertion circuit 2, can insert a black screen during the process of sub-pixel P emitting light for normal image display, shortening the normal light emission time of sub-pixel P and the normal display time of the display device 2000. This increases MPRT (Motion Picture Response Time) without increasing the refresh rate, improving the phenomenon of motion blur and enhancing the image display effect.

[0175] Furthermore, by controlling the alternation time between the black insertion circuit 2 during the light emission stage t3 and the black insertion writing stage t4, the ratio of the duration of normal light emission to the duration of black screen for sub-pixel P can be controlled. This facilitates the adjustment of MPRT, thereby improving the phenomenon of motion blur in dynamic images and enhancing the image display effect.

[0176] It should be noted that there are various ways to control the light emission process of sub-pixel P to insert a black screen, and the specific settings can be selected according to actual needs. This disclosure does not limit this.

[0177] In some embodiments, such as Figure 13 and Figure 14 As shown, the first output circuit 12 can also be connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2. <n>Electrical connection. The first output circuit 12 is further configured to transmit the display input signal to the first pull-up node Q via the first input circuit 11. <1> In the case of the first pull-up node Q <1> Under the control of the voltage, the third clock signal received at the third clock signal terminal CLKF1 will be transmitted to the first sensing signal terminal Oput2. <n>This drives at least one row of sub-pixels P to be reset. Alternatively, the black pixel insertion circuit 2 transmits the black pixel insertion input signal to the first pull-up node Q. <1> In the case of the first pull-up node Q <1> Under the control of the voltage, the third clock signal is transmitted to the first sensing signal terminal Oput2. <n>This drives at least one row of sub-pixels P to display a black screen.

[0178] For example, in the first pull-up node Q <1> When the voltage is high, the first output circuit 12 can pull up at the first pull-up node Q. <1> Under the control of the voltage, it is turned on and transmits the third clock signal received at the third clock signal terminal CLKF1 to the first sensing signal terminal Oput2. <n>The third clock signal is used as the first sensing signal, and the signal is transmitted from the first sensing signal terminal Oput1. <n>Output.

[0179] In this case, multiple pixel driving circuits in the same row of sub-pixels P are electrically connected to two gate lines GL. The first scan signal terminal Oput1 of a shift register 100... <n>One of the gate lines GL can be electrically connected to the first gate signal terminal G1 of multiple pixel driving circuits P in the corresponding row sub-pixel P, and the first scan signal terminal Oput1. <n>The output first scan signal can be transmitted via the gate line GL to the first gate signal terminal G1 of the plurality of pixel driving circuits P1. The first sensing signal terminal Oput2 of the shift register 100... <n>It can be electrically connected via another gate line GL to the second gate signal terminal G2 of multiple pixel driving circuits P1 in the corresponding row sub-pixel P, and the first sensing signal terminal Oput2 <n>The first sensing signal output can be transmitted as a second scanning signal through the gate line GL to the second gate signal terminal G2 of the plurality of pixel driving circuits P1.

[0180] For example, during the display period in a frame display phase, such as Figure 6 As shown, during the reset phase t1 and the data write phase t2, the first input circuit 11 is turned on, and the first pull-up node Q... <1> The voltage remains high, and the first output circuit 12 is at the first pull-up node Q. <1> The transistor remains on under the influence of the voltage. Since both the first clock signal and the third clock signal are high, the levels of the first scan signal and the first sensing signal output by the first output circuit 12 are also high. The switching transistor T1 operates under the first scan signal (from the first scan signal terminal Oput1). <n>Under the control of ), it is turned on to receive and transmit data signals to the first node G; the sensing transistor T3 is turned on by the second scan signal (from the first sensing signal terminal Oput2). <n>Under the control of [unclear], it is turned on, receives and transmits a reset signal to the second node S, and resets the second node S. This prepares for the subsequent light-emitting stage t3 (i.e., image display).

[0181] At a certain moment during the light-emitting process of the light-emitting device P2 (i.e. Figure 6 As shown in the diagram, during the alternation of the light-emitting stage t3 and the black insertion writing stage t4, the black insertion circuit 2 is turned on and activates the first pull-up node Q. <1> During charging, the first output circuit 12 can be connected to the first pull-up node Q. <1> It is turned on under the control of the voltage. At this time, the first clock signal can be used as the first black insertion signal from the first scan signal terminal Oput1. <n>The output is transmitted to the first gate signal terminal G1 of the corresponding row pixel driving circuit P1, and the third clock signal can be used as the second black insertion signal from the first sensing signal terminal Oput2. <n>The output is transmitted to the second gate signal terminal G2 of the corresponding row pixel driving circuit P1 so that the subsequent sub-pixel P can display a black screen.

[0182] Taking the example of the first scan signal terminal G1 and the second scan signal terminal G2 of multiple pixel driving circuits in the same row of sub-pixels P being electrically connected to a gate line GL, the method of inserting a black screen is illustrated.

[0183] For example, such as Figure 7 As shown, when the light-emitting device P2 emits light, the black plug circuit 2 is turned on and the first pull-up node Q is activated. <1> During the charging process, the first scan signal terminal Oput1 <n>The output first scan signal (i.e., the first black insertion signal) can be at a high level, while the first sensing signal terminal Oput2 <n>The output first sensing signal (also known as the second black insertion signal) can be at a low level. Based on this, sensing transistor T3 can be turned off under the control of the second black insertion signal; switching transistor T1 can be turned on under the control of the first black insertion signal, and transmit a low-level or lower-level data signal (also known as the black insertion data signal) to the first node G, making Vgs less than Vth, thereby turning off driving transistor T2, causing sub-pixel P to stop emitting light and switch to a black screen.

[0184] For example, when the light-emitting device P2 emits light, the black plug circuit 2 is turned on and the first pull-up node Q is activated. <1> During the charging process, the first scan signal terminal Oput1 <n>The output first scan signal (i.e., the first black insertion signal) can be at a low level, while the first sensing signal terminal Oput2 <n>The output first sensing signal (also known as the second black insertion signal) can be at a high level. Based on this, the switching transistor T1 can be turned off under the control of the first black insertion signal; the sensing transistor T3 is turned on under the control of the second black insertion signal, and transmits a high-level or higher-level sensing signal (also known as the black insertion sensing signal) to the second node S, making Vgs less than Vth, thereby turning off the driving transistor T2, causing the sub-pixel P to stop emitting light and switch to a black screen.

[0185] For example, the time period during which the input circuit 11 is turned on can be called the display sub-period, and the time period during which the black insertion circuit 2 is turned on can be called the black insertion sub-period. The display sub-period and the black insertion sub-period are performed sequentially.

[0186] In some embodiments, such as Figures 11-12 As shown, the shift register 100 further includes a second scanning unit 3. The second scanning unit 3 includes a second input circuit 31 and a second output circuit 32.

[0187] In some examples, such as Figures 11-12 As shown, the second input circuit 31 is connected to the display input signal terminal Iput and the second pull-up node Q. <2> Electrical connection. The second input circuit 31 is configured to transmit the display input signal to the second pull-up node Q in response to the display input signal Iput. <2> .

[0188] For example, when the display input signal level is high, the second input circuit 31 can be turned on by the display input signal to receive and transmit the display input signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases.

[0189] In some examples, such as Figures 11-12 As shown, the second output circuit 32 and the second pull-up node Q <2> The second clock signal terminal CLKE2 and the second scan signal terminal Oput1<N+1> Electrical connection. The second output circuit 32 is configured to transmit the display input signal from the second input circuit 31 to the second pull-up node Q. <2> In the case of the second pull-up node Q <2> Under the control of the voltage, the second clock signal received at the second clock signal terminal CLKE2 is transmitted to the second scan signal terminal Oput1.<N+1> This drives at least one row of sub-pixels P to display the image.

[0190] For example, in the second pull-up node Q <2> When the voltage is high, the second output circuit 32 can pull up at the second pull-up node Q. <2> Under the control of the voltage, it is turned on and transmits the second clock signal received at the second clock signal terminal CLKE2 to the second scan signal terminal Oput1.<N+1> The second clock signal is used as the second scan signal, and the second scan signal is input from the second scan signal terminal Oput1.<N+1> Output.

[0191] Since both the first input circuit 11 and the second input circuit 31 are electrically connected to the display input signal terminal Iput, when the display input signal level is high, the first input circuit 11 and the second input circuit 31 can be turned on simultaneously, and simultaneously pull up the first pull-up node Q. <1> Second pull-up node Q <2> Charging allows the first output circuit 12 and the second output circuit 32 to be turned on simultaneously.

[0192] In the display sub-period of the display period, the first scan signal output by the first output circuit 12 and the second scan signal output by the second output circuit 32 can be different, for example. This facilitates driving different rows of sub-pixels P to perform line-by-line scanning and line-by-line image display.

[0193] In some examples, such as Figures 11-12 As shown, the black plug circuit 2 is also connected to the second pull-up node Q. <2> Electrical connection. The black plug circuit 2 is further configured to transmit the black plug input signal to the first pull-up node Q. <1> At the same time, the black input signal is transmitted to the second pull-up node Q. <2> The output circuit 32 is also configured to transmit the black-insertion input signal to the second pull-up node Q in the black-insertion circuit 2. <2> In the case of the second pull-up node Q <2> Under the control of the voltage, the second clock signal is transmitted to the second scan signal terminal Oput1.<N+1> This drives at least one row of sub-pixels P to display a black screen.

[0194] For example, when the level of the first control signal is high, the level of the black insertion cascade signal is high, and the level of the second control signal is high, the black insertion circuit 2 can be turned on under the control of the first control signal, the black insertion cascade signal, and the second control signal, receive the black insertion input signal, and transmit the black insertion input signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases. The second output circuit 32 can be connected to the second pull-up node Q. <2> Under the control of the voltage, it is turned on and transmits the second clock signal received at the second clock signal terminal CLKE2 to the second scan signal terminal Oput1.<N+1> The second clock signal is used as the second scan signal, and the second scan signal is input from the second scan signal terminal Oput1.<N+1> Output.

[0195] Because the black plug circuit 2 is not only connected to the first pull-up node Q <1> Electrical connection, also with the second pull-up node Q <2> Electrical connection means that the black insertion circuit 2 is simultaneously electrically connected to the first scanning unit 1 and the second scanning unit 3. Thus, when the black insertion circuit 2 is conducting, the high-level black insertion input signal can be simultaneously transmitted to the first pull-up node Q. <1> Second pull-up node Q <2> This causes the first output circuit 12 and the second output circuit 32 to be turned on simultaneously. While the first output circuit 12 outputs the first clock signal as the first scan signal, the second output circuit 32 outputs the second clock signal as the first scan signal.

[0196] During the blackout period in the display time, the first scan signal output by the first output circuit 12 and the second scan signal output by the second output circuit 32 can, for example, be the same. This can drive the first scan signal terminal Oput1. <n>The corresponding row sub-pixel P and the second scan signal terminal Oput1 are electrically connected.<N+1> The corresponding sub-pixel P of the electrically connected row simultaneously displays a black screen.

[0197] Here, when the shift register 100 includes the first scanning unit 1, each shift register 100 can be electrically connected to at least one row of sub-pixels P, and thus the multiple rows of sub-pixels P included in the display device 2000 can be scanned line by line or a black screen can be displayed line by line through multiple shift registers 100.

[0198] When the shift register 100 includes a first scanning unit 1 and a second scanning unit 3, each shift register 100 can be electrically connected to at least two rows of sub-pixels P, wherein the at least one row of sub-pixels P connected to the first scanning unit 1 is different from the at least one row of sub-pixels P connected to the second scanning unit 3. This allows for the simultaneous display of at least two rows of sub-pixels P electrically connected to the shift register 100 in a black-and-white mode, which helps reduce the time required to insert a black-and-white mode, improves the motion blur phenomenon in dynamic images, and enhances the image display effect.

[0199] In some examples, such as Figures 15-18 As shown, the second output circuit 32 can also be connected to the fourth clock signal terminal CLKF2 and the second sensing signal terminal Oput2.<N+1> Electrical connection. The second output circuit 32 is further configured to transmit the display input signal from the second input circuit 31 to the second pull-up node Q. <2> In the case of the second pull-up node Q <2> Under the control of the voltage, the fourth clock signal received at the fourth clock signal terminal CLKF2 will be transmitted to the second sensing signal terminal Oput2.<N+1> The driver resets at least one row of sub-pixels P; or, the black insertion circuit 2 transmits the black insertion input signal to the second pull-up node Q. <2> In the case of the second pull-up node Q <2> Under the control of the voltage, the fourth clock signal is transmitted to the second sensing signal terminal Oput2.<N+1> This drives at least one row of sub-pixels P to display a black screen.

[0200] For example, in the second pull-up node Q <2> When the voltage is high, the second output circuit 32 can pull up at the second pull-up node Q. <2> Under the control of the voltage, it is turned on and transmits the fourth clock signal received at the fourth clock signal terminal CLKF2 to the second sensing signal terminal Oput2.<N+1> The fourth clock signal is used as the second sensing signal, and is transmitted from the second sensing signal terminal Oput1.<N+1> Output.

[0201] It should be noted that the process of using the second scanning unit 3 to drive the corresponding row sub-pixel P to display an image or a black screen is the same as the process of using the first scanning unit 3 to drive the corresponding row sub-pixel P to display an image or a black screen. For details, please refer to the descriptions in some of the above embodiments, which will not be repeated here.

[0202] The number of scan units included in the shift register 100 provided herein is not limited to two.

[0203] The structure of the black plug circuit 2 will be schematically described below with reference to the accompanying drawings. Of course, the structure of the black plug circuit 2 in this disclosure is not limited to this.

[0204] In some embodiments, such as Figures 9-18 As shown, the black insertion circuit 2 includes: a black insertion control sub-circuit 21, a black insertion input sub-circuit 22, and a first black insertion transmission sub-circuit 23. Where the shift register 100 also includes a second scanning unit 3, the black insertion circuit 2 may further include: a second black insertion transmission sub-circuit 24.

[0205] In some examples, such as Figures 9-18 As shown, the black insertion control sub-circuit 21 is electrically connected to the first control signal terminal BCS1, the black insertion cascade signal terminal BCR, the first voltage signal terminal V1, and the first black insertion node M. The black insertion control sub-circuit 21 is configured to transmit the black insertion cascade signal to the first black insertion node M under the control of the first control signal.

[0206] For example, when the level of the first control signal is high, the black insertion control sub-circuit 21 can be turned on under the control of the first control signal, receive and transmit the black insertion cascade signal to the first black insertion node M, charge the first black insertion node M, and increase the voltage of the first black insertion node M.

[0207] In some examples, such as Figures 9-18 As shown, the black insertion input sub-circuit 22 is electrically connected to the first black insertion node M, the black insertion input signal terminal BI, and the second black insertion node K. The black insertion input sub-circuit 22 is configured to transmit the black insertion input signal to the second black insertion node K under the control of the voltage of the first black insertion node M.

[0208] For example, when the voltage of the first black insertion node M is high, the black insertion input sub-circuit 22 can be turned on under the control of the voltage of the first black insertion node M, receive and transmit the black insertion input signal to the second black insertion node K, charge the second black insertion node K, and increase the voltage of the second black insertion node K.

[0209] In some examples, such as Figures 9-18 As shown, the first black-insertion transmission sub-circuit 23 is connected to the second control signal terminal BCS2, the second black-insertion node K, and the first pull-up node Q. <1> Electrical connection. The first black-insertion transmission sub-circuit 23 is configured, under the control of the second control signal, to transmit the black-insertion input signal from the second black-insertion node K to the first pull-up node Q. <1> .

[0210] For example, when the level of the second control signal is high, the first black-insertion transmission sub-circuit 23 can be turned on under the control of the second control signal to receive and transmit the black-insertion input signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0211] In some examples, such as Figures 15-18 As shown, the second black insertion transmission sub-circuit 24 is connected to the second control signal terminal BCS2, the second black insertion node K, and the second pull-up node Q. <2> Electrical connection. The second black-insertion transmission sub-circuit 24 is configured to, under the control of the second control signal, transmit the black-insertion input signal from the second black-insertion node K to the second pull-up node Q. <2> .

[0212] For example, when the level of the second control signal is high, the second black-insertion transmission sub-circuit 24 can be turned on under the control of the second control signal, receiving and transmitting the black-insertion input signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases.

[0213] In some examples, the second control signal terminal BCS2 and the black insertion input signal terminal BI are the same signal terminal. That is, the second control signal terminal BCS2 and the black insertion input signal terminal BI receive the same signal and transmit the same signal. In other words, the timing of the second control signal and the black insertion input signal is the same.

[0214] For example, both the second control signal and the black insertion input signal are clock signals; or, both the second control signal and the black insertion input signal are some kind of shift signal.

[0215] In other examples, the second control signal terminal BCS2 and the black bar input signal terminal BI are different signal terminals.

[0216] For example, the second control signal transmitted by the second control signal terminal BCS2 can be a timing signal, and the black insertion input signal transmitted by the black insertion input signal terminal BI can be a DC high-level signal. This DC high-level signal can, for example, be a fifth voltage signal. Regarding the fifth voltage signal, please refer to the description below; it will not be repeated here.

[0217] This simplifies the structure of the shift register 100 and the scan drive circuit 1000, and improves the yield of the shift register 100 and the scan drive circuit 1000.

[0218] The structure of the first scanning unit 1, the black insertion circuit 2, and the second scanning unit 3 will be schematically described below with reference to the accompanying drawings.

[0219] In some examples, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the black-insertion control sub-circuit 21 includes: a fifth transistor M5 and a third capacitor C3.

[0220] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the control terminal of the fifth transistor M5 is electrically connected to the first control signal terminal BCS1, the first terminal of the fifth transistor M5 is electrically connected to the black cascade signal terminal BCR, and the second terminal of the fifth transistor M5 is electrically connected to the first black cascade node M.

[0221] For example, when the level of the first control signal is high, the fifth transistor M5 can be turned on under the control of the first control signal, and transmit the black insertion cascade signal received at the black insertion cascade signal terminal BCR to the first black insertion node M, charging the first black insertion node M and increasing the voltage of the first black insertion node M.

[0222] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the first end of the third capacitor C3 is electrically connected to the first black insertion node M, and the second end of the third capacitor C3 is electrically connected to the first voltage signal terminal V1.

[0223] For example, during the process of the fifth transistor M5 being turned on and charging the first black-insertion node M, the third capacitor C3 is also charged. After the fifth transistor M5 is turned off, the third capacitor C3 can discharge, keeping the voltage of the first black-insertion node M at a high level.

[0224] In some examples, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the black input sub-circuit 22 includes: the sixth transistor M6.

[0225] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the control electrode of the sixth transistor M6 is electrically connected to the first black insertion node M, the first electrode of the sixth transistor M6 is electrically connected to the black insertion input signal terminal BI, and the second electrode of the sixth transistor M6 is electrically connected to the second black insertion node K.

[0226] For example, when the fifth transistor M5 is turned on and charges the first black insertion node M, causing the voltage of the first black insertion node M to rise, the sixth transistor M6 can be turned on under the control of the voltage of the first black insertion node M, and receive and transmit the black insertion input signal to the second black insertion node K.

[0227] In some examples, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the first black-insertion transmission sub-circuit 23 includes: a seventh transistor M7.

[0228] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the control terminal of the seventh transistor M7 is electrically connected to the second control signal terminal BCS2, the first terminal of the seventh transistor M7 is electrically connected to the second black plug node K, and the second terminal of the seventh transistor M7 is electrically connected to the first pull-up node Q. <1> Electrical connection.

[0229] For example, when the level of the second control signal is high, the seventh transistor M7 can be turned on under the control of the second control signal, transmitting the black insertion input signal from the second black insertion node K to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0230] In some examples, such as Figure 12 , Figure 16 and Figure 18 As shown, the second black-insertion transmission sub-circuit 24 includes: the eighth transistor M8.

[0231] For example, such as Figure 12 , Figure 16 and Figure 18 As shown, the control terminal of the eighth transistor M8 is electrically connected to the second control signal terminal BCS2, the first terminal of the eighth transistor M8 is electrically connected to the second black plug node K, and the second terminal of the eighth transistor M8 is electrically connected to the second pull-up node Q. <2> Electrical connection.

[0232] For example, when the level of the second control signal is high, the eighth transistor M8 can be turned on under the control of the second control signal, transmitting the black insertion input signal from the second black insertion node K to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases.

[0233] In some examples, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the first input circuit 11 includes: a first transistor M1.

[0234] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the control terminal of the first transistor M1 is electrically connected to the display input signal terminal Iput, the first terminal of the first transistor M1 is electrically connected to the display input signal terminal Iput, and the second terminal of the first transistor M1 is connected to the first pull-up node Q. <1> Electrical connection.

[0235] For example, when the display input signal level is high, the first transistor M1 can be turned on by the display input signal to receive the display input signal and transmit it to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0236] In some examples, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the first output circuit 12 includes a second transistor M2 and a first capacitor C1.

[0237] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the control electrode of the second transistor M2 is connected to the first pull-up node Q. <1> Electrically connected, the first terminal of the second transistor M2 is electrically connected to the first clock signal terminal CLKE1, and the second terminal of the second transistor M2 is electrically connected to the first scan signal terminal Oput1. <n>Electrical connection.

[0238] For example, in the first pull-up node Q <1> When the voltage is high, the second transistor M2 can be pulled up at the first pull-up node Q. <1> Under the control of the circuit, the circuit is turned on, and the first clock signal received from the first clock signal terminal CLKE1 is transmitted from the first scan signal terminal Oput1. <n>Output. Specifically, the first scan signal terminal Oput1 is activated at different time periods. <n>The function of the first scan signal output varies, as can be found in the examples above, and will not be repeated here.

[0239] For example, such as Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 As shown, the first terminal of the first capacitor C1 is connected to the first pull-up node Q. <1> Electrical connection: the second terminal of the first capacitor C1 is connected to the first scan signal terminal Oput1. <n>Electrical connection.

[0240] For example, the first transistor M1 in the first input circuit 12 is turned on, and the first pull-up node Q is activated. <1> During the charging process, the first capacitor C1 is also charged. After the first transistor M1 is turned off, the first capacitor C1 can discharge, causing the first pull-up node Q to discharge. <1> The voltage remains at a high level.

[0241] For example, when the black plug circuit 2 is turned on, and the first pull-up node Q is connected... <1> During the charging process, the first capacitor C1 is also charged. After the black plug circuit 2 is turned off, the first capacitor C1 can discharge, causing the first pull-up node Q to discharge. <1> The voltage remains at a high level.

[0242] In some examples, such as Figure 14 , Figure 16 and Figure 18 As shown, the first output circuit 12 is also connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2. <n>When electrically connected, the first output circuit 12 also includes: a ninth transistor M9 and a fourth capacitor C4.

[0243] For example, such as Figure 14 , Figure 16 and Figure 18 As shown, the control electrode of the ninth transistor M9 is connected to the first pull-up node Q. <1> Electrically connected, the first terminal of the ninth transistor M9 is electrically connected to the third clock signal terminal CLKF1, and the second terminal of the ninth transistor M9 is electrically connected to the first sensing signal terminal Oput2. <n>Electrical connection.

[0244] For example, in the first pull-up node Q <1> When the voltage is high, the ninth transistor M9 can be pulled up at the first pull-up node Q. <1> Under the control of [unclear], the third clock signal received from the third clock signal terminal CLKF1 is turned on and transmitted from the first sensing signal terminal Oput2. <n>Output. Specifically, the first sensing signal terminal Oput2 is activated at different time periods. <n>The function of the first sensing signal output varies, as can be found in the examples above, and will not be repeated here.

[0245] For example, such as Figure 14 , Figure 16 and Figure 18 As shown, the first terminal of the fourth capacitor C4 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of the fourth capacitor C4 is connected to the first sensing signal terminal Oput2. <n>Electrical connection.

[0246] For example, the first transistor M1 in the first input circuit 12 is turned on, and the first pull-up node Q is activated. <1> During the charging process, the fourth capacitor C4 is also charged. After the first transistor M1 is turned off, the fourth capacitor C4 can discharge, causing the first pull-up node Q to discharge. <1> The voltage remains at a high level.

[0247] For example, when the black plug circuit 2 is turned on, and the first pull-up node Q is connected... <1> During the charging process, the fourth capacitor C4 is also charged. After the black plug circuit 2 is turned off, the fourth capacitor C4 can discharge, causing the first pull-up node Q to discharge. <1> The voltage remains at a high level.

[0248] In some examples, such as Figure 12 , Figure 16 and Figure 18 As shown, the second input circuit 31 includes a third transistor M3.

[0249] For example, such as Figure 12 , Figure 16 and Figure 18 As shown, the control terminal of the third transistor M3 is electrically connected to the display input signal terminal Iput, the first terminal of the third transistor M3 is electrically connected to the display input signal terminal Iput, and the second terminal of the third transistor M3 is connected to the second pull-up node Q. <2> Electrical connection.

[0250] For example, when the display input signal level is high, the third transistor M3 can be turned on by the display input signal to receive the display input signal and transmit it to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases.

[0251] In some examples, such as Figure 12 , Figure 16 and Figure 18 As shown, the second output circuit 32 includes: a fourth transistor M4 and a second capacitor C2.

[0252] For example, such as Figure 12 , Figure 16 and Figure 18 As shown, the control electrode of the fourth transistor M4 is connected to the second pull-up node Q. <2> Electrically connected, the first terminal of the fourth transistor M4 is electrically connected to the second clock signal terminal CLKE2, and the second terminal of the fourth transistor M4 is electrically connected to the second scan signal terminal Oput1.<N+1> Electrical connection.

[0253] For example, in the second pull-up node Q <2> When the voltage is high, the fourth transistor M4 can be pulled up at the second pull-up node Q. <2> Under the control of the circuit, the second clock signal received from the second clock signal terminal CLKE2 is turned on from the second scan signal terminal Oput1.<N+1> Output. Specifically, the second scan signal terminal Oput1 is activated at different time periods.<N+1> The function of the output second scan signal is different, as can be found in the examples above, and will not be repeated here.

[0254] For example, such as Figure 12 , Figure 16 and Figure 18 As shown, the first terminal of the second capacitor C2 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the second capacitor C2 is connected to the second scan signal terminal Oput1.<N+1> Electrical connection.

[0255] For example, the third transistor M3 in the second input circuit 12 is turned on, and the second pull-up node Q is activated. <2> During the charging process, the second capacitor C2 is also charged. After the third transistor M3 is turned off, the second capacitor C2 can discharge, causing the second pull-up node Q to... <2> The voltage remains at a high level.

[0256] For example, when the black plug circuit 2 is turned on, and the second pull-up node Q is connected... <2> During the charging process, the second capacitor C2 is also charged. After the black plug circuit 2 is turned off, the second capacitor C2 can discharge, causing the second pull-up node Q to discharge. <2> The voltage remains at a high level.

[0257] In some examples, such as Figure 16 As shown, the second output circuit 32 is also connected to the fourth clock signal terminal CLKF2 and the second sensing signal terminal Oput2.<N+1> In the case of electrical connection, the second output circuit 32 also includes: the tenth transistor M10 and the fifth capacitor C5.

[0258] For example, such as Figure 16 As shown, the control electrode of the tenth transistor M10 is connected to the second pull-up node Q. <2> Electrical connections: The first terminal of the tenth transistor M10 is electrically connected to the fourth clock signal terminal CLKF2, and the second terminal of the tenth transistor M10 is electrically connected to the second sensing signal terminal Oput2.<N+1> Electrical connection.

[0259] For example, in the second pull-up node Q <2> When the voltage is high, the tenth transistor M10 can be pulled up at the second pull-up node Q. <2> Under the control of [unclear], the fourth clock signal received from the fourth clock signal terminal CLKF2 will be turned on from the second sensing signal terminal Oput2.<N+1> Output. Specifically, the second sensing signal terminal Oput2 is activated at different time periods.<N+1> The function of the output second sensing signal is different, as can be found in the examples above, and will not be repeated here.

[0260] For example, such as Figure 16 As shown, the first terminal of the fifth capacitor C5 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the fifth capacitor C5 is connected to the second sensing signal terminal Oput2.<N+1> Electrical connection.

[0261] For example, the third transistor M3 in the second input circuit 12 is turned on, and the second pull-up node Q is activated. <2> During the charging process, the fifth capacitor C5 is also charged. After the third transistor M3 is turned off, the fifth capacitor C5 can discharge, causing the second pull-up node Q to... <2> The voltage remains at a high level.

[0262] For example, when the black plug circuit 2 is turned on, and the second pull-up node Q is connected... <2> During the charging process, the fifth capacitor C5 will also be charged. After the black plug circuit 2 is turned off, the fifth capacitor C5 can discharge, causing the second pull-up node Q to discharge. <2> The voltage remains at a high level.

[0263] In some embodiments, such as Figure 13 and Figure 14 As shown, the first output circuit 12 is also connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR. <n>Electrical connection. The first output circuit 12 is further configured to connect to the first pull-up node Q. <1> Under the control of the voltage, the fifth clock signal received at the fifth clock signal terminal CLKD1 will be transmitted to the first shift signal terminal CR. <n>.

[0264] For example, in the first pull-up node Q <1> When the voltage is high, the first output circuit 12 can pull up at the first pull-up node Q. <1> Under the control of the voltage, it is turned on, and the fifth clock signal received at the fifth clock signal terminal CLKD1 is used as the first shift signal, and the signal is shifted from the first shift signal terminal CR. <n>Output.

[0265] The structure of the first output circuit 12 will be schematically described below with reference to the accompanying drawings.

[0266] In some examples, such as Figure 14 As shown, the first output circuit 12 also includes an eleventh transistor M11.

[0267] For example, such as Figure 14 As shown, the control electrode of the eleventh transistor M11 is connected to the first pull-up node Q. <1> Electrically connected, the first terminal of the eleventh transistor M11 is electrically connected to the fifth clock signal terminal CLKD1, and the second terminal of the eleventh transistor M11 is electrically connected to the first shift signal terminal CR. <n>Electrical connection.

[0268] For example, in the first pull-up node Q <1> When the voltage is high, the eleventh transistor M11 can pull up at the first pull-up node Q. <1> Under the control of the voltage, it is turned on, and the fifth clock signal received from the fifth clock signal terminal CLKD1 is used as the first shift signal from the first shift signal terminal CR. <n>Output.

[0269] In some embodiments, such as Figures 17-18 As shown, when the shift register 100 also includes a second scanning unit 3, the second output circuit 32 is also connected to the sixth clock signal terminal CLKD2 and the second shift signal terminal CR2.<N+1> Electrical connection. The second output circuit 32 is further configured to connect to the second pull-up node Q. <2> Under the control of the voltage, the sixth clock signal received at the sixth clock signal terminal CLKD2 will be transmitted to the second shift signal terminal CR2.<N+1> .

[0270] For example, in the second pull-up node Q <2> When the voltage is high, the second output circuit 32 can pull up at the second pull-up node Q. <2> Under the control of the voltage, it is turned on, and the sixth clock signal received at the sixth clock signal terminal CLKD2 is used as the second shift signal, and the signal is shifted from the second shift signal terminal CR2.<N+1> Output.

[0271] The structure of the second output circuit 32 will be schematically described below with reference to the accompanying drawings.

[0272] In some examples, such as Figure 18 As shown, the second output circuit 32 also includes a twelfth transistor M12.

[0273] For example, such as Figure 18 As shown, the control electrode of the twelfth transistor M12 is connected to the second pull-up node Q. <2> Electrical connections: The first terminal of the twelfth transistor M12 is electrically connected to the sixth clock signal terminal CLKD2, and the second terminal of the twelfth transistor M12 is electrically connected to the second shift signal terminal CR2.<N+1> Electrical connection.

[0274] For example, in the second pull-up node Q <2> When the voltage is high, the twelfth transistor M12 can pull up at the second pull-up node Q. <2> Under the control of the voltage, it is turned on, and the sixth clock signal received from the sixth clock signal terminal CLKD2 is used as the second shift signal from the second shift signal terminal CR2.<N+1> Output.

[0275] It should be noted that the aforementioned first shift signal terminal CR <n>and the second shift signal terminal CR2<N+1> All are used for cascading to simplify the structure of the scan drive circuit 1000 and reduce the area occupied by the scan drive circuit 1000 in the border area B. That is, when cascading is performed using shift signal terminals, the first output circuit 12 or the second output circuit 32 can be electrically connected to the corresponding shift signal terminal. When cascading is not performed using shift signal terminals, the first output circuit 12 or the second output circuit 32 may not be electrically connected to the corresponding shift signal terminal (i.e., it does not include the corresponding transistor).

[0276] In this disclosure, there are various cascading methods, which can be seen in the descriptions of some embodiments below, and will not be repeated here.

[0277] In this configuration, when the display input signal terminal Iput is electrically connected to a certain shift signal terminal, and the black screen insertion cascade signal terminal BCR is also electrically connected to a certain shift signal terminal, the shift signal terminals connected to both belong to different scanning units. This avoids the situation where the first input circuit 11, the second input circuit 31, and the black screen insertion circuit 2 of the same shift register 100 are simultaneously turned on due to being connected to the same shift signal terminal, thereby preventing conflicts between the normal image display process and the black screen insertion process.

[0278] In some embodiments, the shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0279] In some examples, such as Figures 29-30 As shown, the shift register 100 may further include a third leakage protection circuit 6. This third leakage protection circuit 6 is electrically connected to the first black-insertion node M, the fifth voltage signal terminal V5, and the third leakage protection node OFF3. Specifically, the third leakage protection circuit 6 is configured to, under the control of the voltage at the first black-insertion node M, transmit the fifth voltage signal received at the fifth voltage signal terminal V5 to the third leakage protection node OFF3.

[0280] Here, the fifth voltage signal terminal V5 can be configured, for example, to transmit a DC high-level signal (e.g., higher than or equal to the high-level portion of a clock signal).

[0281] For example, when the voltage of the first black plug node M is high, the third anti-leakage circuit 6 can be turned on under the control of the voltage of the first black plug node M, receive and transmit the fifth voltage signal to the third anti-leakage node OFF3, charge the third anti-leakage node OFF3, and increase the voltage of the third anti-leakage node OFF3.

[0282] In some examples, such as Figures 29-30 As shown, the black plug control sub-circuit 21 is also electrically connected to the third leakage protection node OFF3.

[0283] When the fifth transistor M5 in the black insertion control sub-circuit 21 is turned off and the third capacitor C3 is discharged so that the voltage of the first black insertion node M is kept at a high level, by electrically connecting the black insertion control sub-circuit 21 with the third anti-leakage node OFF3, the voltage difference between the third anti-leakage node OFF3 and the first black insertion node M can be reduced, and the first black insertion node M can be prevented from leaking through the black insertion control sub-circuit 21. In this way, the first black insertion node M can be kept at a higher and more stable voltage, so as to avoid affecting the conduction state of the black insertion input sub-circuit 22.

[0284] The structure of the third leakage protection circuit 6 and the black plug control sub-circuit 21 is illustrated below with reference to the accompanying drawings.

[0285] In some examples, such as Figure 30 As shown, the third leakage protection circuit 6 includes: the seventieth transistor M70.

[0286] For example, such as Figure 30 As shown, the control electrode of the 70th transistor M70 is electrically connected to the first black insertion node M, the first electrode of the 70th transistor M70 is electrically connected to the fifth voltage signal terminal V5, and the second electrode of the 70th transistor M70 is electrically connected to the third leakage protection node OFF3.

[0287] For example, when the voltage of the first black insertion node M is high, the seventieth transistor M70 can be turned on under the control of the voltage of the first black insertion node M, receive the fifth voltage signal, and transmit the fifth voltage signal to the third leakage protection node OFF3 to charge the third leakage protection node OFF3, thereby increasing the voltage of the third leakage protection node OFF3.

[0288] Based on this, in some examples, such as Figure 30 As shown, the black insertion control sub-circuit 21 also includes: the seventy-first transistor M71.

[0289] For example, such as Figure 30 As shown, the control terminal of the seventy-first transistor M71 is electrically connected to the first control signal terminal BCS1, the first terminal of the seventy-first transistor M71 is electrically connected to the black cascade signal terminal BCR, and the second terminal of the seventy-first transistor M71 is electrically connected to the third leakage protection node OFF3. Specifically, the first terminal of the fifth transistor M5 in the black cascade control sub-circuit 21 is electrically connected to the third leakage protection node OFF3, and is also electrically connected to the black cascade signal terminal BCR via the seventy-first transistor M71.

[0290] For example, when the level of the first control signal is high, the fifth transistor M5 and the seventy-first transistor M71 can be turned on simultaneously under the action of the first control signal. The seventy-first transistor M71 can receive and transmit the black plug cascade signal to the third leakage protection node OFF3, and the fifth transistor M5 can receive and transmit the black plug cascade signal to the first black plug node M, charging the first black plug node M.

[0291] When the level of the first control signal is low, the fifth transistor M5 and the seventy-first transistor M71 can be simultaneously turned off under the action of the first control signal. The third capacitor C3 in the black plug control sub-circuit 21 begins to discharge, keeping the voltage of the first black plug node M at a high level. During this process, the seventieth transistor M70 in the third leakage protection circuit 6 can transmit the fifth voltage signal to the third leakage protection node OFF3, charging the third leakage protection node OFF3, reducing the voltage difference between the third leakage protection node OFF3 and the first black plug node M, and making the voltage difference between the control electrode and the first electrode of the fifth transistor M5 less than zero, ensuring that the fifth transistor M5 is completely or relatively completely turned off. This can prevent the first black plug node M from leaking through the black plug control sub-circuit 21, allowing the first black plug node M to maintain a relatively high and stable voltage.

[0292] In some embodiments, the shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0293] In some examples, such as Figures 19-22 As shown, the first scan unit 1 in the shift register 100 may further include: a first reset circuit 13 and a second reset circuit 14.

[0294] For example, such as Figures 19-22 As shown, the first reset circuit 13 is connected to the first reset signal terminal STD and the first pull-up node Q. <1> And electrically connected to the first voltage signal terminal V1. The first reset circuit 13 is configured to, under the control of the first reset signal transmitted at the first reset signal terminal STD, transmit the first voltage signal received at the first voltage signal terminal V1 to the first pull-up node Q. <1> .

[0295] For example, when the level of the first reset signal is high, the first reset circuit 13 can be turned on under the control of the first reset signal, transmitting the first voltage signal received at the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0296] It should be noted that after multiple shift registers 100 are cascaded to form a scan drive circuit 1000, except for the first few stages of shift registers 100 (such as the first-stage shift register 100 and the second-stage shift register 100), the first reset signal terminal STD of the remaining stages of shift registers 100 can be connected to the first shift signal terminal CR of a subsequent stage of shift register 100. <n>The electrical connection allows the first shift signal output by the shift register 100 to serve as the first reset signal for the corresponding shift register 100.

[0297] Correspondingly, the first reset signal terminal STD of part of the shift register 100 can be electrically connected to the display reset signal line, thereby receiving the display reset signal transmitted by the display reset signal line as the first reset signal. This part of the shift register 100 can, for example, be the last two stages of shift registers 100 in the scan drive circuit 1000. This allows for cascaded reset.

[0298] For example, such as Figures 19-22 As shown, when the black insertion circuit 2 includes the black insertion control sub-circuit 21, the second reset circuit 14 is connected to the second reset signal terminal BTRST, the first black insertion node M, and the first pull-up node Q. <1> And the first voltage signal terminal V1 is electrically connected. The second reset circuit 14 is configured to, under the control of the voltage at the first black plug node M and the second reset signal transmitted at the second reset signal terminal BTRST, transmit the first voltage signal to the first pull-up node Q. <1> .

[0299] For example, when the voltage of the first black-insertion node M is high and the level of the second reset signal is high, the second reset circuit 14 can be turned on under the control of the voltage of the first black-insertion node M and the second reset signal, transmitting the first voltage signal received at the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0300] Here, the second reset circuit 14 can, for example, reset the first pull-up node Q after the black screen period (i.e., after the black screen is displayed). <1> Perform a reset.

[0301] In some examples, such as Figures 21-22 As shown, if the shift register 100 also includes a second scanning unit 3, the second scanning unit 3 may further include a third reset circuit 33 and a fourth reset circuit 34.

[0302] For example, such as Figures 21-22 As shown, the third reset circuit 33 is connected to the first reset signal terminal STD and the second pull-up node Q. <2> And the first voltage signal terminal V1 is electrically connected. The third reset circuit 33 is configured to, under the control of the first reset signal, transmit the first voltage signal to the second pull-up node Q. <2> .

[0303] For example, when the level of the first reset signal is high, the third reset circuit 33 can be turned on under the control of the first reset signal, transmitting the first voltage signal received at the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0304] Since both the third reset circuit 33 and the first reset circuit 13 are electrically connected to the first reset signal terminal STD, both the third reset circuit 33 and the first reset circuit 13 can be turned on when the level of the first reset signal is high, simultaneously affecting the first pull-up node Q. <1> Second pull-up node Q <2> Perform a pull-down reset.

[0305] For example, such as Figures 21-22 As shown, the fourth reset circuit 34 is connected to the second reset signal terminal BTRST, the first black plug node M, and the second pull-up node Q. <2> And the first voltage signal terminal V1 is electrically connected. The fourth reset circuit 34 is configured to transmit the first voltage signal to the second pull-up node Q under the control of the voltage at the first black-pin node M and the second reset signal. <2> .

[0306] For example, when the voltage of the first black-insertion node M is high and the level of the second reset signal is high, the fourth reset circuit 34 can be turned on under the control of the voltage of the first black-insertion node M and the second reset signal, transmitting the first voltage signal received at the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0307] Since both the fourth reset circuit 34 and the second reset circuit 14 are electrically connected to the first black insertion node M and the second reset signal terminal BTRST, when the voltage of the first black insertion node M is high and the level of the second reset signal is high, both the fourth reset circuit 34 and the second reset circuit 14 can be turned on. Therefore, after the black insertion period, the first pull-up node Q can be simultaneously activated. <1> Second pull-up node Q <2> Perform a pull-down reset.

[0308] The structure of the first reset circuit 13, the second reset circuit 14, the third reset circuit 33, and the fourth reset circuit 44 will be schematically described below with reference to the accompanying drawings.

[0309] In some examples, such as Figure 20 and Figure 22 As shown, the first reset circuit 13 includes: a thirteenth transistor M13.

[0310] For example, such as Figure 20 and Figure 22 As shown, the control terminal of the thirteenth transistor M13 is electrically connected to the first reset signal terminal STD, and the first terminal of the thirteenth transistor M13 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of the thirteenth transistor M13 is electrically connected to the first voltage signal terminal V1.

[0311] For example, when the level of the first reset signal is high, the thirteenth transistor M13 can be turned on under the control of the first reset signal to receive and transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0312] In some examples, such as Figure 20 and Figure 22 As shown, the second reset circuit 14 includes a fourteenth transistor M14 and a fifteenth transistor M15.

[0313] For example, such as Figure 20 and Figure 22 As shown, the control terminal of the fourteenth transistor M14 is electrically connected to the first black plug node M, and the first terminal of the fourteenth transistor M14 is connected to the first pull-up node Q. <1> Electrically connected, the second terminal of the fourteenth transistor M14 is electrically connected to the first terminal of the fifteenth transistor M15. The control terminal of the fifteenth transistor M15 is electrically connected to the second reset signal terminal BTRST, and the second terminal of the fifteenth transistor M15 is electrically connected to the first voltage signal terminal V1.

[0314] For example, when the voltage of the first black-plug node M is high and the voltage of the second reset signal is high, the fourteenth transistor M14 can be turned on under the control of the voltage of the first black-plug node M, and the fifteenth transistor M15 can be turned on under the control of the second reset signal. The fifteenth transistor M15 can receive and transmit the first voltage signal to the second terminal of the fourteenth transistor M14, and then the fourteenth transistor M14 can transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0315] In some examples, such as Figure 22 As shown, the third reset circuit 33 includes: the sixteenth transistor M16.

[0316] For example, such as Figure 22 As shown, the control terminal of the sixteenth transistor M16 is electrically connected to the first reset signal terminal STD, and the first terminal of the sixteenth transistor M16 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the sixteenth transistor M16 is electrically connected to the first voltage signal terminal V1.

[0317] For example, when the level of the first reset signal is high, the sixteenth transistor M16 can be turned on under the control of the first reset signal to receive and transmit the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0318] In some examples, such as Figure 22 As shown, the fourth reset circuit 34 includes: the seventeenth transistor M17 and the eighteenth transistor M18.

[0319] For example, such as Figure 22 As shown, the control terminal of the seventeenth transistor M17 is electrically connected to the first black plug node M, and the first terminal of the seventeenth transistor M17 is connected to the second pull-up node Q. <2> Electrically connected, the second terminal of the seventeenth transistor M17 is electrically connected to the first terminal of the eighteenth transistor M18. The control terminal of the eighteenth transistor M18 is electrically connected to the second reset signal terminal BTRST, and the second terminal of the eighteenth transistor M18 is electrically connected to the first voltage signal terminal V1.

[0320] For example, when the voltage at the first black plug node M is high and the voltage at the second reset signal is high, the seventeenth transistor M17 can be turned on under the control of the voltage at the first black plug node M, and the eighteenth transistor M18 can be turned on under the control of the second reset signal. The eighteenth transistor M18 can receive and transmit the first voltage signal to the second terminal of the seventeenth transistor M17, and then the seventeenth transistor M17 can transmit the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0321] In some embodiments, the shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0322] In some examples, such as Figures 23-25 As shown, the first scanning unit 1 in the shift register 100 may further include: a first control circuit 15.

[0323] For example, such as Figures 23-25 As shown, the first control circuit 15 and the first pull-up node Q <1> The first pull-down node QB_A, the first voltage signal terminal V1, and the second voltage signal terminal V2 are electrically connected. The first control circuit 15 is configured to transmit the second voltage signal to the first pull-down node QB_A in response to the second voltage signal received at the second voltage signal terminal V2, and to transmit the second voltage signal to the first pull-up node QB_A. <1> Under the control of the voltage, the first voltage signal received at the first voltage signal terminal V1 is transmitted to the first pull-down node QB_A.

[0324] For example, the first control circuit 15 can receive and transmit the second voltage signal to the first pull-down node QB_A under the control of the second voltage signal. At the first pull-up node Q... <1> When the voltage is high, the first control circuit 15 can pull up at the first pull-up node Q. <1> Under the control of the voltage, the first voltage signal is received and transmitted to the first pull-down node QB_A, and the first pull-down node QB_A is pulled down and reset.

[0325] In some examples, such as Figures 23-25 As shown, if the shift register 100 also includes a second scanning unit 3, the second scanning unit 3 may further include a second control circuit 35.

[0326] For example, such as Figures 23-25 As shown, the second control circuit 35 and the second pull-up node Q <2> The second pull-down node QB_B, the first voltage signal terminal V1, and the third voltage signal terminal V3 are electrically connected. The second control circuit 35 is configured to transmit the third voltage signal to the second pull-down node QB_B in response to the third voltage signal received at the third voltage signal terminal V3, and to transmit the third voltage signal to the second pull-up node QB_B. <2> Under the control of the voltage, the first voltage signal is transmitted to the second pull-down node QB_B.

[0327] For example, the second control circuit 35 can receive and transmit the third voltage signal to the second pull-down node QB_B under the control of the third voltage signal. At the second pull-up node Q... <2> When the voltage is high, the second control circuit 35 can pull up at the second pull-up node Q. <2> Under the control of the voltage, the first voltage signal is received and transmitted to the second pull-down node QB_B, and the second pull-down node QB_B is pulled down and reset.

[0328] Here, the second voltage signal terminal V2 can be configured, for example, to transmit a DC high-level signal (e.g., higher than or equal to the high-level portion of a clock signal). The third voltage signal terminal V3 can be configured, for example, to transmit a DC high-level signal (e.g., higher than or equal to the high-level portion of a clock signal). The terms "high level" and "low level" as used herein are relative. For example, the voltage value of the second voltage signal is greater than the voltage value of the first voltage signal.

[0329] Furthermore, the second voltage signal terminal V2 can be configured, for example, to transmit a DC high-level signal (e.g., a portion of the clock signal higher than or equal to the high level of the clock signal) during the display phase of a frame. The third voltage signal terminal V3 can be configured, for example, to transmit a DC high-level signal (e.g., a portion of the clock signal higher than or equal to the high level of the clock signal) during the display phase of a frame. The second and third voltage signals are inverted signals.

[0330] The structure of the first control circuit 15 and the second control circuit 35 will be schematically described below with reference to the accompanying drawings.

[0331] In some examples, such as Figure 24 and Figure 25 As shown, the first control circuit 15 includes: the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22.

[0332] For example, such as Figure 24 and Figure 25 As shown, the control terminal of the nineteenth transistor M19 is electrically connected to the second voltage signal terminal V2, the first terminal of the nineteenth transistor M19 is electrically connected to the second voltage signal terminal V2, and the second terminal of the nineteenth transistor M19 is electrically connected to the control terminal of the twentieth transistor M20 and the first terminal of the twenty-first transistor M21. The first terminal of the twentieth transistor M20 is electrically connected to the second voltage signal terminal V2, and the second terminal of the twentieth transistor M20 is electrically connected to the first pull-down node QB_A.

[0333] For example, the nineteenth transistor M19 can be turned on under the control of the second voltage signal, receiving and transmitting the second voltage signal to the control electrode of the twentieth transistor M20. The twentieth transistor M20 can be turned on under the control of the second voltage signal, receiving and transmitting the second voltage signal to the first pull-down node QB_A, charging the first pull-down node QB_A, thereby raising the voltage of the first pull-down node QB_A.

[0334] For example, such as Figure 24 and Figure 25 As shown, the control electrode of the twenty-first transistor M21 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of the twenty-first transistor M21 is electrically connected to the first voltage signal terminal V1.

[0335] For example, in the first pull-up node Q <1> When the voltage is high, the twenty-first transistor M21 can be pulled up at the first pull-up node Q. <1> The transistor M20 is turned on under the control of the first voltage signal, receiving and transmitting the first voltage signal to the control electrode of the twentieth transistor M20. The twentieth transistor M20 can be turned off under the control of the first voltage signal.

[0336] For example, such as Figure 24 and Figure 25 As shown, the control electrode of the twenty-second transistor M22 is connected to the first pull-up node Q. <1> Electrically connected, the first terminal of the twenty-second transistor M22 is electrically connected to the first pull-down node QB_A, and the second terminal of the twenty-second transistor M22 is electrically connected to the first voltage signal terminal V1.

[0337] For example, in the first pull-up node Q <1> When the voltage is high, the twenty-second transistor M22 can pull up at the first pull-up node Q. <1> Under the control of the circuit, the circuit is turned on, receives and transmits the first voltage signal to the first pull-down node QB_A, and performs a pull-down reset on the first pull-down node QB_A.

[0338] In some examples, such as Figure 24 and Figure 25 As shown, the second control circuit 35 includes: a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, and a twenty-sixth transistor M26.

[0339] For example, such as Figure 24 and Figure 25 As shown, the control terminal of the twenty-third transistor M23 is electrically connected to the third voltage signal terminal V3, the first terminal of the twenty-third transistor M23 is electrically connected to the third voltage signal terminal V3, and the second terminal of the twenty-third transistor M23 is electrically connected to the control terminal of the twenty-fourth transistor M24 and the first terminal of the twenty-fifth transistor M25. The first terminal of the twenty-fourth transistor M24 is electrically connected to the third voltage signal terminal V3, and the second terminal of the twenty-fourth transistor M24 is electrically connected to the second pull-down node QB_B.

[0340] For example, the twenty-third transistor M23 can be turned on under the control of the third voltage signal, receiving and transmitting the third voltage signal to the control electrode of the twenty-fourth transistor M24. The twenty-fourth transistor M24 can be turned on under the control of the third voltage signal, receiving and transmitting the third voltage signal to the second pull-down node QB_B, charging the second pull-down node QB_B, thereby raising the voltage of the second pull-down node QB_B.

[0341] For example, such as Figure 24 and Figure 25 As shown, the control electrode of the 25th transistor M25 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the twenty-fifth transistor M25 is electrically connected to the first voltage signal terminal V1.

[0342] For example, in the second pull-up node Q <2> When the voltage is high, the 25th transistor M25 can be pulled up at the second pull-up node Q. <2> The transistor M24 is turned on under the control of the first voltage signal, receiving and transmitting the first voltage signal to the control electrode of the 24th transistor M24. The 24th transistor M24 can be turned off under the control of the first voltage signal.

[0343] For example, such as Figure 24 and Figure 25 As shown, the control electrode of the twenty-sixth transistor M26 is connected to the second pull-up node Q. <2> Electrically connected, the first terminal of the twenty-sixth transistor M26 is electrically connected to the second pull-down node QB_B, and the second terminal of the twenty-sixth transistor M26 is electrically connected to the first voltage signal terminal V1.

[0344] For example, in the second pull-up node Q <2> When the voltage is high, the 26th transistor M26 can be pulled up at the second pull-up node Q. <2> Under the control of the circuit, the circuit is turned on, receives and transmits the first voltage signal to the second pull-down node QB_B, and performs a pull-down reset on the second pull-down node QB_B.

[0345] In some embodiments, the shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0346] In some examples, such as Figures 26-28 As shown, the first scanning unit 1 also includes: a fifth reset circuit 16, a sixth reset circuit 17, and a seventh reset circuit 18.

[0347] For example, such as Figures 26-28 As shown, the fifth reset circuit 16 is connected to the first pull-down node QB_A and the first pull-up node Q. <1> And the first voltage signal terminal V1 is electrically connected. The fifth reset circuit 16 is configured to transmit the first voltage signal to the first pull-up node Q under the control of the voltage of the first pull-down node QB_A. <1> .

[0348] For example, when the voltage of the first pull-down node QB_A is high, the fifth reset circuit 16 can be turned on under the control of the voltage of the first pull-down node QB_A, and transmit the first voltage signal received at the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0349] For example, such as Figures 26-28 As shown, the sixth reset circuit 17 is connected to the first pull-down node QB_A and the first scan signal terminal Oput1. <n>And the fourth voltage signal terminal V4 is electrically connected. The sixth reset circuit 17 is configured, under the control of the voltage of the first pull-down node QB_A, to transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the first scan signal terminal Oput1. <n>.

[0350] For example, when the voltage of the first pull-down node QB_A is high, the sixth reset circuit 17 can be turned on under the control of the voltage of the first pull-down node QB_A, and will transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the first scan signal terminal Oput1. <n>For the first scan signal terminal Oput1 <n>Perform a pull-down reset.

[0351] Here, the fourth voltage signal terminal V4 can be configured, for example, to transmit a DC low-level signal (e.g., lower than or equal to the low-level portion of a clock signal). Exemplarily, this fourth voltage signal terminal V4 is grounded. The voltage values ​​of the first voltage signal and the fourth voltage signal may or may not be equal.

[0352] For example, such as Figures 26-28 As shown, the first output circuit 12 is also connected to the third clock signal terminal CLKF1 and the first sensing signal terminal Oput2. <n>In the case of electrical connection, the sixth reset circuit 17 is also connected to the first sensing signal terminal Oput2. <n>Electrical connection. The sixth reset circuit 17 is further configured to transmit the fourth voltage signal to the first sensing signal terminal Oput2 under the control of the voltage of the first pull-down node QB_A. <n>.

[0353] For example, when the voltage of the first pull-down node QB_A is high, the sixth reset circuit 17 can be turned on under the control of the voltage of the first pull-down node QB_A, and will transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the first sensing signal terminal Oput2. <n>For the first sensing signal terminal Oput2 <n>Perform a pull-down reset.

[0354] For example, such as Figures 26-28 As shown, the first output circuit 12 is also connected to the fifth clock signal terminal CLKD1 and the first shift signal terminal CR <n>In the case of electrical connection, the sixth reset circuit 17 is also connected to the first shift signal terminal CR. <n>And the first voltage signal terminal V1 is electrically connected. The sixth reset circuit 17 is further configured to, under the control of the voltage of the first pull-down node QB_A, transmit the first voltage signal to the first shift signal terminal CR. <n>.

[0355] For example, when the voltage of the first pull-down node QB_A is high, the sixth reset circuit 17 can be turned on under the control of the voltage of the first pull-down node QB_A, transmitting the first voltage signal received at the first voltage signal terminal V1 to the first shift signal terminal CR. <n>For the first shift signal terminal CR <n>Perform a pull-down reset.

[0356] For example, such as Figures 26-28 As shown, when the black-insertion circuit 2 includes a black-insertion control sub-circuit 21, the seventh reset circuit 18 is electrically connected to the first black-insertion node M, the second control signal terminal BCS2, the first pull-down node QB_A, and the first voltage signal terminal V1. The seventh reset circuit 18 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the voltage at the first black-insertion node M and the second control signal.

[0357] For example, when the voltage of the first black insertion node M is high and the level of the second control signal is high, the seventh reset circuit 18 can be turned on under the control of the voltage of the first black insertion node M and the second control signal, and transmit the first voltage signal received at the first voltage signal terminal V1 to the first pull-down node QB_A, and pull down the first pull-down node QB_A for reset.

[0358] In some examples, such as Figures 26-28 As shown, the second scanning unit 3 also includes: an eighth reset circuit 36, a ninth reset circuit 37, and a tenth reset circuit 38.

[0359] For example, such as Figures 26-28 As shown, the eighth reset circuit 36 ​​is connected to the second pull-down node QB_B and the second pull-up node Q. <2> And the first voltage signal terminal V1 is electrically connected. The eighth reset circuit 36 ​​is configured to transmit the first voltage signal to the second pull-up node Q under the control of the voltage of the second pull-down node QB_B. <2> .

[0360] For example, when the voltage of the second pull-down node QB_B is high, the eighth reset circuit 36 ​​can be turned on under the control of the voltage of the second pull-down node QB_B, and transmit the first voltage signal received at the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0361] For example, such as Figures 26-28 As shown, the ninth reset circuit 37 is connected to the second pull-down node QB_B and the second scan signal terminal Oput1.<N+1> And the fourth voltage signal terminal V4 is electrically connected. The ninth reset circuit 37 is configured to transmit the fourth voltage signal to the second scan signal terminal Oput1 under the control of the voltage of the second pull-down node QB_B.<N+1> .

[0362] For example, when the voltage of the second pull-down node QB_B is high, the ninth reset circuit 37 can be turned on under the control of the voltage of the second pull-down node QB_B, and will transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the second scan signal terminal Oput1.<N+1> For the second scan signal terminal Oput1<N+1> Perform a pull-down reset.

[0363] For example, such as Figures 26-28 As shown, the second output circuit 32 is also connected to the fourth clock signal terminal CLKF2 and the second sensing signal terminal Oput2.<N+1> In the case of electrical connection, the ninth reset circuit 37 is also connected to the second sensing signal terminal Oput2.<N+1> Electrical connection. The ninth reset circuit 37 is further configured to transmit the fourth voltage signal to the second sensing signal terminal Oput2 under the control of the voltage of the second pull-down node QB_B.<N+1> .

[0364] For example, when the voltage of the second pull-down node QB_B is high, the ninth reset circuit 37 can be turned on under the control of the voltage of the second pull-down node QB_B, and will transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the second sensing signal terminal Oput2.<N+1> For the second sensing signal terminal Oput2<N+1> Perform a pull-down reset.

[0365] For example, such as Figures 26-28 As shown, the second output circuit 32 is also connected to the sixth clock signal terminal CLKD2 and the second shift signal terminal CR2.<N+1> In the case of electrical connection, the ninth reset circuit 37 is also connected to the second shift signal terminal CR2.<N+1> And the first voltage signal terminal V1 is electrically connected. The ninth reset circuit 37 is further configured to, under the control of the voltage of the second pull-down node QB_B, transmit the first voltage signal to the second shift signal terminal CR2.<N+1> .

[0366] For example, when the voltage of the second pull-down node QB_B is high, the ninth reset circuit 37 can be turned on under the control of the voltage of the second pull-down node QB_B, transmitting the first voltage signal received at the first voltage signal terminal V1 to the second shift signal terminal CR2.<N+1> For the second shift signal terminal CR2<N+1> Perform a pull-down reset.

[0367] For example, such as Figures 26-28 As shown, the tenth reset circuit 38 is electrically connected to the first black-insert node M, the second control signal terminal BCS2, the second pull-down node QB_B, and the first voltage signal terminal V1. The tenth reset circuit 38 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the voltage at the first black-insert node M and the second control signal.

[0368] For example, when the voltage of the first black insertion node M is high and the level of the second control signal is high, the tenth reset circuit 38 can be turned on under the control of the voltage of the first black insertion node M and the second control signal, and transmit the first voltage signal received at the first voltage signal terminal V1 to the second pull-down node QB_B, and pull down and reset the second pull-down node QB_B.

[0369] The structures of the fifth reset circuit 16, the sixth reset circuit 17, the seventh reset circuit 18, the eighth reset circuit 36, the ninth reset circuit 37, and the tenth reset circuit 38 are illustrated below with reference to the accompanying drawings.

[0370] In some examples, such as Figure 27 and Figure 28 As shown, the fifth reset circuit 16 includes: the twenty-seventh transistor M27.

[0371] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB_A, and the first terminal of the twenty-seventh transistor M27 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of the twenty-seventh transistor M27 is electrically connected to the first voltage signal terminal V1.

[0372] For example, when the voltage of the first pull-down node QB_A is high, the twenty-seventh transistor M27 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0373] In some examples, such as Figure 27 and Figure 28 As shown, the sixth reset circuit 17 includes: the twenty-eighth transistor M28, the twenty-ninth transistor M29, and the thirtieth transistor M30.

[0374] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the 28th transistor M28 is electrically connected to the first pull-down node QB_A, and the first terminal of the 28th transistor M28 is connected to the first scan signal terminal Oput1. <n>Electrical connection: The second terminal of the twenty-eighth transistor M28 is electrically connected to the fourth voltage signal terminal V4.

[0375] For example, when the voltage of the first pull-down node QB_A is high, the twenty-eighth transistor M28 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the fourth voltage signal to the first scan signal terminal Oput1. <n>For the first scan signal terminal Oput1 <n>Perform a pull-down reset.

[0376] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the twenty-ninth transistor M29 is electrically connected to the first pull-down node QB_A, and the first terminal of the twenty-ninth transistor M29 is connected to the first sensing signal terminal Oput2. <n>Electrical connection: The second terminal of the twenty-ninth transistor M29 is electrically connected to the fourth voltage signal terminal V4.

[0377] For example, when the voltage of the first pull-down node QB_A is high, the twenty-ninth transistor M29 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the fourth voltage signal to the first sensing signal terminal Oput2. <n>For the first sensing signal terminal Oput2 <n>Perform a pull-down reset.

[0378] For example, such as Figure 27 and Figure 28 As shown, the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, and the first electrode of the thirtieth transistor M30 is connected to the first shift signal terminal CR. <n>Electrical connection: The second terminal of the thirtieth transistor M30 is electrically connected to the first voltage signal terminal V1.

[0379] For example, when the voltage of the first pull-down node QB_A is high, the thirtieth transistor M30 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the first voltage signal to the first shift signal terminal CR. <n>For the first shift signal terminal CR <n>Perform a pull-down reset.

[0380] In some examples, such as Figure 27 and Figure 28 As shown, the seventh reset circuit 18 includes: the thirty-first transistor M31 and the thirty-second transistor M32.

[0381] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the thirty-first transistor M31 is electrically connected to the first black-pin node M, the first terminal of the thirty-first transistor M31 is electrically connected to the first pull-down node QB_A, and the second terminal of the thirty-first transistor M31 is electrically connected to the first terminal of the thirty-second transistor M32. The control terminal of the thirty-second transistor M32 is electrically connected to the second control signal terminal BCS2, and the second terminal of the thirty-second transistor M32 is electrically connected to the first voltage signal terminal V1.

[0382] For example, when the voltage of the first black-insertion node M is high and the level of the second control signal is high, the thirty-first transistor M31 can be turned on under the control of the voltage of the first black-insertion node M, and the thirty-second transistor M32 can be turned on under the control of the second control signal. The thirty-second transistor M32 can receive and transmit the first voltage signal to the second terminal of the thirty-first transistor M31, and the thirty-first transistor M31 can transmit the first voltage signal to the first pull-down node QB_A to pull down and reset the first pull-down node QB_A.

[0383] In some examples, such as Figure 27 and Figure 28 As shown, the eighth reset circuit 36 ​​includes: the thirty-third transistor M33.

[0384] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the thirty-third transistor M33 is electrically connected to the second pull-down node QB_B, and the first terminal of the thirty-third transistor M33 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the thirty-third transistor M33 is electrically connected to the first voltage signal terminal V1.

[0385] For example, when the voltage of the second pull-down node QB_B is high, the thirty-third transistor M33 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0386] In some examples, such as Figure 27 and Figure 28 As shown, the ninth reset circuit 37 includes: the thirty-fourth transistor M34, the thirty-fifth transistor M35, and the thirty-sixth transistor M36.

[0387] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the thirty-fourth transistor M34 is electrically connected to the second pull-down node QB_B, and the first terminal of the thirty-fourth transistor M34 is connected to the second scan signal terminal Oput1.<N+1> Electrical connection: The second terminal of the thirty-fourth transistor M34 is electrically connected to the fourth voltage signal terminal V4.

[0388] For example, when the voltage of the second pull-down node QB_B is high, the thirty-fourth transistor M34 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the fourth voltage signal to the second scan signal terminal Oput1.<N+1> For the second scan signal terminal Oput1<N+1> Perform a pull-down reset.

[0389] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the 35th transistor M35 is electrically connected to the second pull-down node QB_B, and the first terminal of the 35th transistor M35 is connected to the second sensing signal terminal Oput2.<N+1> Electrical connection: The second terminal of the thirty-fifth transistor M35 is electrically connected to the fourth voltage signal terminal V4.

[0390] For example, when the voltage of the second pull-down node QB_B is high, the thirty-fifth transistor M35 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the fourth voltage signal to the second sensing signal terminal Oput2.<N+1> For the second sensing signal terminal Oput2<N+1> Perform a pull-down reset.

[0391] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the thirty-sixth transistor M36 is electrically connected to the second pull-down node QB_B, and the first terminal of the thirty-sixth transistor M36 is connected to the second shift signal terminal CR2.<N+1> Electrical connection: The second terminal of the thirty-sixth transistor M36 is electrically connected to the first voltage signal terminal V1.

[0392] For example, when the voltage of the second pull-down node QB_B is high, the thirty-sixth transistor M36 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the first voltage signal to the second shift signal terminal CR2.<N+1> For the second shift signal terminal CR2<N+1> Perform a pull-down reset.

[0393] In some examples, such as Figure 27 and Figure 28 As shown, the tenth reset circuit 38 includes: the thirty-seventh transistor M37 and the thirty-eighth transistor M38.

[0394] For example, such as Figure 27 and Figure 28 As shown, the control terminal of the thirty-seventh transistor M37 is electrically connected to the first black plug node M, the first terminal of the thirty-seventh transistor M37 is electrically connected to the second pull-down node QB_B, and the second terminal of the thirty-seventh transistor M37 is electrically connected to the first terminal of the thirty-eighth transistor M38. The control terminal of the thirty-eighth transistor M38 is electrically connected to the second control signal terminal BCS2, and the second terminal of the thirty-eighth transistor M38 is electrically connected to the first voltage signal terminal V1.

[0395] For example, when the voltage of the first black-insertion node M is high and the level of the second control signal is high, the thirty-seventh transistor M37 can be turned on under the control of the voltage of the first black-insertion node M, and the thirty-eighth transistor M38 can be turned on under the control of the second control signal. The thirty-eighth transistor M38 can receive and transmit the first voltage signal to the second terminal of the thirty-seventh transistor M37, and the thirty-seventh transistor M37 can transmit the first voltage signal to the second pull-down node QB_B to pull down and reset the second pull-down node QB_B.

[0396] In some embodiments, the shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0397] In some examples, such as Figure 28 As shown, the fifth reset circuit 16 is also electrically connected to the second pull-down node QB_B. The fifth reset circuit 16 is further configured to transmit a first voltage signal to the first pull-up node QB_B under the control of the voltage of the second pull-down node QB_B. <1> .

[0398] For example, when the voltage of the second pull-down node QB_B is high, the fifth reset circuit 16 can be turned on under the control of the voltage of the second pull-down node QB_B, transmitting the first voltage signal received at the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0399] In some examples, such as Figure 28 As shown, the sixth reset circuit 17 is also electrically connected to the second pull-down node QB_B. The sixth reset circuit 17 is further configured to transmit a fourth voltage signal to the first scan signal terminal Oput1 under the control of the voltage of the second pull-down node QB_B. <n>The fourth voltage signal is transmitted to the first sensing signal terminal Oput2. <n>The first voltage signal is transmitted to the first shift signal terminal CR. <n>.

[0400] For example, when the voltage of the second pull-down node QB_B is high, the sixth reset circuit 17 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the fourth voltage signal to the first scan signal terminal Oput1. <n>For the first scan signal terminal Oput1 <n>Perform pull-down reset; receive and transmit the fourth voltage signal to the first sensing signal terminal Oput2. <n>For the first sensing signal terminal Oput2 <n>Perform pull-down reset; receive and transmit the first voltage signal to the first shift signal terminal CR. <n>For the first shift signal terminal CR <n>Perform a pull-down reset.

[0401] In some examples, such as Figure 28 As shown, the eighth reset circuit 36 ​​is also electrically connected to the first pull-down node QB_A. The eighth reset circuit 36 ​​is further configured to transmit a first voltage signal to the second pull-up node QB_A under the control of the voltage of the first pull-down node QB_A. <2> .

[0402] For example, when the voltage of the first pull-down node QB_A is high, the eighth reset circuit 36 ​​can be turned on under the control of the voltage of the first pull-down node QB_A, and transmit the first voltage signal received at the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0403] In some examples, such as Figure 28 As shown, the ninth reset circuit 37 is also electrically connected to the first pull-down node QB_A. The ninth reset circuit 37 is further configured to transmit the fourth voltage signal to the second scan signal terminal Oput1 under the control of the voltage of the first pull-down node QB_A.<N+1> The fourth voltage signal is transmitted to the second sensing signal terminal Oput2.<N+1> The first voltage signal is transmitted to the second shift signal terminal CR2.<N+1> .

[0404] For example, when the voltage of the first pull-down node QB_A is high, the ninth reset circuit 37 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the fourth voltage signal to the second scan signal terminal Oput1.<N+1> For the second scan signal terminal Oput1<N+1> Perform pull-down reset; receive and transmit the fourth voltage signal to the second sensing signal terminal Oput2.<N+1> For the second sensing signal terminal Oput2<N+1> Perform pull-down reset; receive and transmit the first voltage signal to the second shift signal terminal CR2.<N+1> For the second shift signal terminal CR2<N+1> Perform a pull-down reset.

[0405] In the above example, the second voltage signal and the third voltage signal can be, for example, inverse signals. This allows different structures in different reset circuits to reset the first pull-down node QB_A or the second pull-down node QB_B at different display periods, reducing the operating time of the corresponding structures and increasing the service life of the shift register 100 and the scan drive circuit 1000.

[0406] The structures of the fifth reset circuit 16, the sixth reset circuit 17, the eighth reset circuit 36, and the ninth reset circuit 37 are illustrated below with reference to the accompanying drawings.

[0407] In some examples, such as Figure 28 As shown, the fifth reset circuit 16 also includes the thirty-ninth transistor M39.

[0408] For example, such as Figure 28 As shown, the control terminal of the thirty-ninth transistor M39 is electrically connected to the second pull-down node QB_B, and the first terminal of the thirty-ninth transistor M39 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of the thirty-ninth transistor M39 is electrically connected to the first voltage signal terminal V1.

[0409] For example, when the voltage of the second pull-down node QB_B is high, the thirty-ninth transistor M39 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0410] In some examples, such as Figure 28 As shown, the sixth reset circuit 17 also includes: the fortieth transistor M40, the forty-first transistor M41, and the forty-second transistor M42.

[0411] For example, such as Figure 28 As shown, the control electrode of the 40th transistor M40 is electrically connected to the second pull-down node QB_B, and the first electrode of the 40th transistor M40 is connected to the first scan signal terminal Oput1. <n>Electrical connection: The second terminal of the 40th transistor M40 is electrically connected to the fourth voltage signal terminal V4.

[0412] For example, when the voltage of the second pull-down node QB_B is high, the fortieth transistor M40 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the fourth voltage signal to the first scan signal terminal Oput1. <n>For the first scan signal terminal Oput1 <n>Perform a pull-down reset.

[0413] For example, such as Figure 28 As shown, the control terminal of the forty-first transistor M41 is electrically connected to the second pull-down node QB_B, and the first terminal of the forty-first transistor M41 is connected to the first sensing signal terminal Oput2. <n>Electrical connection: The second terminal of the forty-first transistor M41 is electrically connected to the fourth voltage signal terminal V4.

[0414] For example, when the voltage of the second pull-down node QB_B is high, the forty-first transistor M41 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the fourth voltage signal to the first sensing signal terminal Oput2. <n>For the first sensing signal terminal Oput2 <n>Perform a pull-down reset.

[0415] For example, such as Figure 28 As shown, the control electrode of the forty-second transistor M42 is electrically connected to the second pull-down node QB_B, and the first electrode of the forty-second transistor M42 is connected to the first shift signal terminal CR. <n>Electrical connection: The second terminal of transistor M42 is electrically connected to the first voltage signal terminal V1.

[0416] For example, when the voltage of the second pull-down node QB_B is high, the forty-second transistor M42 can be turned on under the control of the voltage of the second pull-down node QB_B, receiving and transmitting the first voltage signal to the first shift signal terminal CR. <n>For the first shift signal terminal CR <n>Perform a pull-down reset.

[0417] In some examples, such as Figure 28 As shown, the eighth reset circuit 36 ​​also includes: the forty-third transistor M43.

[0418] For example, such as Figure 28 As shown, the control terminal of the forty-third transistor M43 is electrically connected to the first pull-down node QB_A, and the first terminal of the forty-third transistor M43 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the forty-third transistor M43 is electrically connected to the first voltage signal terminal V1.

[0419] For example, when the voltage of the first pull-down node QB_A is high, the forty-third transistor M43 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0420] In some examples, such as Figure 28 As shown, the ninth reset circuit 37 also includes: the forty-fourth transistor M44, the forty-fifth transistor M45, and the forty-sixth transistor M46.

[0421] For example, such as Figure 28 As shown, the control terminal of the forty-fourth transistor M44 is electrically connected to the first pull-down node QB_A, and the first terminal of the forty-fourth transistor M44 is connected to the second scan signal terminal Oput1.<N+1> Electrical connection: The second terminal of the forty-fourth transistor M44 is electrically connected to the fourth voltage signal terminal V4.

[0422] For example, when the voltage of the first pull-down node QB_A is high, the forty-fourth transistor M44 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the fourth voltage signal to the second scan signal terminal Oput1.<N+1> For the second scan signal terminal Oput1<N+1> Perform a pull-down reset.

[0423] For example, such as Figure 28 As shown, the control terminal of the forty-fifth transistor M45 is electrically connected to the first pull-down node QB_A, and the first terminal of the forty-fifth transistor M45 is connected to the second sensing signal terminal Oput2.<N+1> Electrical connection: The second terminal of the forty-fifth transistor M45 is electrically connected to the fourth voltage signal terminal V4.

[0424] For example, when the voltage of the first pull-down node QB_A is high, the forty-fifth transistor M45 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the fourth voltage signal to the second sensing signal terminal Oput2.<N+1> For the second sensing signal terminal Oput2<N+1> Perform a pull-down reset.

[0425] For example, such as Figure 28 As shown, the control terminal of the forty-sixth transistor M46 is electrically connected to the first pull-down node QB_A, and the first terminal of the forty-sixth transistor M46 is connected to the second shift signal terminal CR2.<N+1> Electrical connection: The second terminal of the forty-sixth transistor M46 is electrically connected to the first voltage signal terminal V1.

[0426] For example, when the voltage of the first pull-down node QB_A is high, the forty-sixth transistor M46 can be turned on under the control of the voltage of the first pull-down node QB_A, receiving and transmitting the first voltage signal to the second shift signal terminal CR2.<N+1> For the second shift signal terminal CR2<N+1> Perform a pull-down reset.

[0427] As described above, the display phase of a frame may include, for example, a display period and a blanking period performed sequentially. During the display period, the shift register 100 can drive the corresponding sub-pixel P in the display device 2000 to display an image; during the blanking period, the shift register 100 can drive the corresponding sub-pixel P in the display device 2000 to perform external compensation.

[0428] Based on this, in some embodiments, such as Figure 34 and Figure 35 As shown, the shift register 100 may also include: blanking circuit 4.

[0429] In some examples, such as Figure 34 and Figure 35 As shown, the blanking circuit 4 is connected to the third control signal terminal OE, the display input signal terminal Iput, the seventh clock signal terminal CLKA, and the first pull-up node Q. <1> And the first voltage signal terminal V1 is electrically connected. The blanking circuit 4 is configured to, under the control of the third control signal transmitted at the third control signal terminal OE, the display input signal, and the seventh clock signal transmitted at the seventh clock signal terminal CLKA, transmit the seventh clock signal to the first pull-up node Q. <1> .

[0430] In addition, such as Figure 34 and Figure 35 As shown, when the shift register 100 also includes a second scan unit 3, the blanking circuit 4 is also connected to the second pull-up node Q. <2> Electrical connection. The blanking circuit 4 is also configured to transmit the seventh clock signal to the second pull-up node Q. <2> .

[0431] For example, during the blanking period in the display phase of a frame, when the level of the selection control signal is high, the level of the display input signal is high, and the level of the seventh clock signal is high, the blanking circuit 4 can be turned on under the control of the third control signal, the display input signal, and the seventh clock signal, and will transmit the seventh clock signal received at the seventh clock signal terminal CLKA to the first pull-up node Q. <1> Second pull-up node Q <2> For the first pull-up node Q <1> Second pull-up node Q <2> Charge it.

[0432] First pull-up node Q <1> After the voltage increases, the first output circuit 12 can pull up at the first pull-up node Q. <1> It is turned on under the control of the voltage. If the first output circuit 12 is not connected to the first sensing signal terminal Oput2 <n>With electrical connection, the first output circuit 12 can simultaneously use the second clock signal received at the first clock signal terminal CLKE1 as both the first scan signal and the first sensing drive signal, from the first scan signal terminal Oput1. <n>Output. If the first output circuit 12 and the first sensing signal terminal Oput2... <n>If electrically connected, the first output circuit 12 can use the third clock signal received at the third clock signal terminal CLKF1 as the first sensing signal, and output it from the first sensing signal terminal Oput2. <n>Output. The first sensing signal can be used to drive the corresponding sub-pixel P for external compensation.

[0433] Second pull-up node Q <2> After the voltage increases, the second output circuit 32 can pull up at the second pull-up node Q. <2> It is turned on under the control of the voltage. If the second output circuit 32 is not connected to the second sensing signal terminal Oput2<N+1> With electrical connection, the second output circuit 32 can simultaneously use the second clock signal received at the second clock signal terminal CLKE2 as the second scan signal and the second sensing drive signal, from the second scan signal terminal Oput1.<N+1> Output. If the second output circuit 32 is connected to the second sensing signal terminal Oput2<N+1> If electrically connected, the second output circuit 32 can use the fourth clock signal received at the fourth clock signal terminal CLKF2 as the second sensing signal, and output it from the second sensing signal terminal Oput2.<N+1> Output. The corresponding sub-pixel P can be driven for external compensation using the second sensing signal.

[0434] Therefore, when the shift register 100 includes the second scan unit 3, the first scan unit 1 and the second scan unit 3 can share the blanking circuit 4. This helps to simplify the structure of the shift register 100 and the scan drive circuit 1000, and improves the yield of the shift register 100 and the scan drive circuit 1000.

[0435] Furthermore, if the shift register 100 also includes other scan units, the blanking circuit 4 may also include other blanking transport sub-circuits so that multiple scan units can share the blanking circuit 4.

[0436] In some embodiments, such as Figure 34 and Figure 35 As shown, the blanking circuit 4 includes: a selection control sub-circuit 41, a blanking input sub-circuit 42, a first blanking transmission sub-circuit 43, and a second blanking transmission sub-circuit 44.

[0437] In some examples, such as Figure 34 and Figure 35 As shown, the selection control sub-circuit 41 is electrically connected to the third control signal terminal OE, the display input signal terminal Iput, the first blanking node H, and the first voltage signal terminal V1. The selection control sub-circuit 41 is configured to transmit the display input signal to the first blanking node H under the control of the third control signal.

[0438] For example, when the level of the third control signal is high, the selection control sub-circuit 41 can be turned on under the control of the third control signal and transmit the received display input signal to the first blanking node H to charge the first blanking node H, thereby increasing the voltage of the first blanking node H.

[0439] For example, when the shift register 100 needs to output a sensing signal, the waveform timing of the third control signal can be made the same as the waveform timing of the display input signal, thereby turning on the selection control sub-circuit 41.

[0440] In some examples, such as Figure 34 and Figure 35 As shown, the blanking transmission sub-circuit 42 is electrically connected to the first blanking node H, the seventh clock signal terminal CLKA, and the second blanking node N. The blanking transmission sub-circuit 42 is configured to transmit the seventh clock signal to the second blanking node N under the control of the voltage of the first blanking node H.

[0441] For example, when the selection control sub-circuit 41 is turned on, causing the voltage of the first blanking node H to rise, the blanking transmission sub-circuit 42 can be turned on under the control of the voltage of the first blanking node H, receive the seventh clock signal transmitted by the seventh clock signal terminal CLKA, and transmit the seventh clock signal to the second blanking node N.

[0442] In some examples, such as Figure 34 and Figure 35 As shown, the first blanking transmission sub-circuit 43 is connected to the seventh clock signal terminal CLKA, the second blanking node N, and the first pull-up node Q. <1> Electrical connection. The first blanking transmission sub-circuit 43 is configured to, under the control of the seventh clock signal, transmit the seventh clock signal from the second blanking node N to the first pull-up node Q. <1> .

[0443] For example, when the level of the seventh clock signal is high, the first blanking transmission sub-circuit 43 can be turned on under the control of the seventh clock signal, and receive the seventh clock signal from the second blanking node N, and transmit the received seventh clock signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charging is performed so that the first pull-up node Q... <1> The voltage increases.

[0444] In some examples, such as Figure 34 and Figure 35 As shown, the second blanking transmission sub-circuit 44 is connected to the seventh clock signal terminal CLKA, the second blanking node N, and the second pull-up node Q. <2> Electrical connection. The second blanking transmission sub-circuit 44 is configured to, under the control of the seventh clock signal, transmit the seventh clock signal from the second blanking node N to the second pull-up node Q. <2> .

[0445] For example, when the level of the seventh clock signal is high, the second blanking transmission sub-circuit 44 can be turned on under the control of the seventh clock signal, and receive the seventh clock signal from the second blanking node N, and transmit the received seventh clock signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charging is performed, causing the second pull-up node Q to... <2> The voltage increases.

[0446] The following diagram, in conjunction with the accompanying drawings, provides a schematic description of the structure of the selection control sub-circuit 41, the blanking input sub-circuit 42, the first blanking transmission sub-circuit 43, and the second blanking transmission sub-circuit 44 included in the blanking circuit 4.

[0447] In some examples, such as Figure 34 and Figure 35 As shown, the selection control sub-circuit 41 includes: the forty-seventh transistor M47 and the sixth capacitor C6.

[0448] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the forty-seventh transistor M47 is electrically connected to the third control signal terminal OE, the first terminal of the forty-seventh transistor M47 is electrically connected to the Iput display input signal terminal, and the second terminal of the forty-seventh transistor M47 is electrically connected to the first blanking node H.

[0449] For example, when the level of the selection control signal transmitted at the selection control signal terminal OE is high, the forty-seventh transistor M47 can be turned on under the action of the selection control signal, receive and transmit the display input signal to the first blanking node H, charge the first blanking node H, and increase the voltage of the first blanking node H.

[0450] For example, such as Figure 34 and Figure 35 As shown, the first terminal of the sixth capacitor C6 is electrically connected to the first blanking node H, and the second terminal of the sixth capacitor C6 is electrically connected to the first voltage signal terminal V1.

[0451] For example, during the process of the forty-seventh transistor M47 being turned on and charging the first blanking node H, the sixth capacitor C6 is also charged. This allows the sixth capacitor C6 to discharge when the forty-seventh transistor M47 is turned off, thus keeping the first blanking node H at a high level.

[0452] In some examples, such as Figure 34 and Figure 35 As shown, the blanking input sub-circuit 42 includes: the forty-eighth transistor M48.

[0453] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the forty-eighth transistor M48 is electrically connected to the first blanking node H, the first terminal of the forty-eighth transistor M48 is electrically connected to the seventh clock signal terminal CLKA, and the second terminal of the forty-eighth transistor M48 is electrically connected to the second blanking node N.

[0454] For example, when the voltage of the first blanking node H is high, the forty-eighth transistor M48 can be turned on under the control of the voltage of the first blanking node H, and will transmit the seventh clock signal received at the seventh clock signal terminal CLKA to the second blanking node N.

[0455] In some examples, such as Figure 34 and Figure 35 As shown, the first blanking transmitter circuit 43 includes: the forty-ninth transistor M49.

[0456] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the forty-ninth transistor M49 is electrically connected to the seventh clock signal terminal CLKA, the first terminal of the forty-ninth transistor M49 is electrically connected to the second blanking node N, and the second terminal of the forty-ninth transistor M49 is electrically connected to the first pull-up node Q. <1> Electrical connection.

[0457] For example, when the level of the seventh clock signal transmitted at the seventh clock signal terminal CLKA is high, the forty-ninth transistor M49 can be turned on under the action of the seventh clock signal, receiving and transmitting the seventh clock signal from the second blanking node N to the first pull-up node Q. <1> For the first pull-up node Q <1> Charge it.

[0458] In some examples, such as Figure 34 and Figure 35 As shown, the second blanking transporter circuit 44 includes: the fiftieth transistor M50.

[0459] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 50th transistor M50 is electrically connected to the seventh clock signal terminal CLKA, the first terminal of the 50th transistor M50 is electrically connected to the second blanking node N, and the second terminal of the 50th transistor M50 is electrically connected to the second pull-up node Q. <2> Electrical connection.

[0460] For example, when the seventh clock signal is high, the fiftieth transistor M50 can be turned on by the seventh clock signal, receiving and transmitting the seventh clock signal from the second blanking node N to the second pull-up node Q. <2> For the second pull-up node Q <2> Charge it.

[0461] In some embodiments, such as Figure 34 and Figure 35 As shown, in the shift register 100, the first scanning unit 1 further includes: an eleventh reset circuit 19, a twelfth reset circuit 110 and a thirteenth reset circuit 111, and the second scanning unit 3 further includes: a fourteenth reset circuit 39, a fifteenth reset circuit 310 and a sixteenth reset circuit 311.

[0462] In some examples, such as Figure 34 and Figure 35 As shown, the eleventh reset circuit 19 is connected to the global reset signal terminal TRST and the first pull-up node Q. <1> And the first voltage signal terminal V1 is electrically connected. The eleventh reset circuit 19 is configured to, under the control of the global reset signal transmitted at the global reset signal terminal TRST, transmit the first voltage signal to the first pull-up node Q. <1> .

[0463] For example, when the global reset signal is at a high level, the eleventh reset circuit 19 can be turned on under the action of the global reset signal, transmitting the first voltage signal transmitted by the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0464] In some examples, such as Figure 34 and Figure 35 As shown, the twelfth reset circuit 110 is electrically connected to the display input signal terminal Iput, the first pull-down node QB_A, and the first voltage signal terminal V1. The twelfth reset circuit 110 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the display input signal.

[0465] For example, when the level of the input signal is high, the twelfth reset circuit 110 can be turned on by the input signal to transmit the first voltage signal to the first pull-down node QB_A and perform a pull-down reset on the first pull-down node QB_A.

[0466] In some examples, such as Figure 34 and Figure 35 As shown, when the blanking circuit 4 includes the selection control sub-circuit 41, the thirteenth reset circuit 111 is electrically connected to the first blanking node H, the seventh clock signal terminal CLKA, the first pull-down node QB_A, and the first voltage signal terminal V1. The thirteenth reset circuit 111 is configured to transmit the first voltage signal to the first pull-down node QB_A under the control of the voltage at the first blanking node H and the seventh clock signal.

[0467] For example, when the voltage of the first blanking node H is high and the level of the seventh clock signal is high, the thirteenth reset circuit 111 can be turned on under the action of the voltage of the first blanking node H and the seventh clock signal, and transmit the first voltage signal to the first pull-down node QB_A to pull down and reset the first pull-down node QB_A.

[0468] In some examples, such as Figure 34 and Figure 35 As shown, the fourteenth reset circuit 39 is connected to the global reset signal terminal TRST and the second pull-up node Q. <2> And the first voltage signal terminal V1 is connected. The fourteenth reset circuit 39 is configured to, under the control of the global reset signal, transmit the first voltage signal to the second pull-up node Q. <2> .

[0469] For example, when the global reset signal is at a high level, the fourteenth reset circuit 39 can be turned on under the action of the global reset signal, transmitting the first voltage signal transmitted at the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0470] In some examples, such as Figure 34 and Figure 35 As shown, the fifteenth reset circuit 310 is electrically connected to the display input signal terminal Iput, the second pull-down node QB_B, and the first voltage signal terminal V1. The fifteenth reset circuit 310 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the display input signal.

[0471] For example, when the level of the input signal is high, the fifteenth reset circuit 310 can be turned on by the input signal to transmit the first voltage signal to the first pull-down node QB_A and perform a pull-down reset on the first pull-down node QB_A.

[0472] In some examples, such as Figure 34 and Figure 35 As shown, the sixteenth reset circuit 311 is electrically connected to the first blanking node H, the seventh clock signal terminal CLKA, the second pull-down node QB_B, and the first voltage signal terminal V1. The sixteenth reset circuit 311 is configured to transmit the first voltage signal to the second pull-down node QB_B under the control of the voltage at the first blanking node H and the seventh clock signal.

[0473] For example, when the voltage of the first blanking node H is high and the level of the seventh clock signal is high, the sixteenth reset circuit 311 can be turned on under the action of the voltage of the first blanking node H and the seventh clock signal, and transmit the first voltage signal to the second pull-down node QB_B to perform pull-down reset on the second pull-down node QB_B.

[0474] The following diagram, in conjunction with the accompanying drawings, provides a schematic description of the structures of the eleventh reset circuit 19, the twelfth reset circuit 110, the thirteenth reset circuit 111, the fourteenth reset circuit 39, the fifteenth reset circuit 310, and the sixteenth reset circuit 311.

[0475] In some examples, such as Figure 34 and Figure 35 As shown, the eleventh reset circuit 19 includes: the fifty-first transistor M51.

[0476] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 51st transistor M51 is electrically connected to the global reset signal terminal TRST, and the first terminal of the 51st transistor M51 is connected to the first pull-up node Q. <1> Electrical connection: The second terminal of transistor M51 is electrically connected to the first voltage signal terminal V1.

[0477] For example, when the global reset signal is at a high level, the 51st transistor M51 can be turned on under the action of the global reset signal, transmitting the first voltage signal transmitted from the first voltage signal terminal V1 to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a reset.

[0478] In some examples, such as Figure 34 and Figure 35 As shown, the twelfth reset circuit 110 includes: the fifty-second transistor M52.

[0479] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 52nd transistor M52 is electrically connected to the display input signal terminal Iput, the first terminal of the 52nd transistor M52 is electrically connected to the first pull-down node QB_A, and the second terminal of the 52nd transistor M52 is electrically connected to the first voltage signal terminal V1.

[0480] For example, when the level of the input signal is high, the 52nd transistor M52 can be turned on by the input signal to transmit the first voltage signal to the first pull-down node QB_A and pull down the first pull-down node QB_A for reset.

[0481] In some examples, such as Figure 34 and Figure 35 As shown, the thirteenth reset circuit 111 includes: the fifty-third transistor M53 and the fifty-fourth transistor M54.

[0482] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 53rd transistor M53 is electrically connected to the first blanking node H, the first terminal of the 53rd transistor M53 is electrically connected to the first pull-down node QB_A, and the second terminal of the 53rd transistor M53 is electrically connected to the first terminal of the 54th transistor M54. The control terminal of the 54th transistor M54 is electrically connected to the seventh clock signal terminal CLKA, and the second terminal of the 54th transistor M54 is electrically connected to the first voltage signal terminal V1.

[0483] For example, when the voltage of the first blanking node H is high and the level of the seventh clock signal is high, the fifty-third transistor M53 can be turned on under the influence of the voltage of the first blanking node H, and the fifty-fourth transistor M54 can be turned on under the influence of the seventh clock signal. The fifty-fourth transistor M54 can receive and transmit the first voltage signal to the second terminal of the fifty-third transistor M53. The fifty-third transistor M53 can receive and transmit the first voltage signal to the first pull-down node QB_A, performing a pull-down reset on the first pull-down node QB_A.

[0484] In some examples, such as Figure 34 and Figure 35 As shown, the fourteenth reset circuit 39 includes the fifty-fifth transistor M55.

[0485] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 55th transistor M55 is electrically connected to the global reset signal terminal TRST, and the first terminal of the 55th transistor M55 is connected to the second pull-up node Q. <2> Electrical connection: The second terminal of the fifty-fifth transistor M55 is electrically connected to the first voltage signal terminal V1.

[0486] For example, when the global reset signal is at a high level, the 55th transistor M55 can be turned on under the action of the global reset signal, transmitting the first voltage signal transmitted from the first voltage signal terminal V1 to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a reset.

[0487] In some examples, such as Figure 34 and Figure 35 As shown, the fifteenth reset circuit 310 includes: the fifty-sixth transistor M56.

[0488] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the fifty-sixth transistor M56 is electrically connected to the display input signal terminal Iput, the first terminal of the fifty-sixth transistor M56 is electrically connected to the second pull-down node QB_B, and the second terminal of the fifty-sixth transistor M56 is electrically connected to the first voltage signal terminal V1.

[0489] For example, when the level of the input signal is high, the fifty-sixth transistor M56 can be turned on by the input signal to transmit the first voltage signal to the first pull-down node QB_A and pull down the first pull-down node QB_A for reset.

[0490] In some examples, such as Figure 34 and Figure 35 As shown, the sixteenth reset circuit 311 includes: the fifty-seventh transistor M57 and the fifty-eighth transistor M58.

[0491] For example, such as Figure 34 and Figure 35 As shown, the control terminal of the 57th transistor M57 is electrically connected to the first blanking node H, the first terminal of the 57th transistor M57 is electrically connected to the second pull-down node QB_B, and the second terminal of the 57th transistor M57 is electrically connected to the first terminal of the 58th transistor M58. The control terminal of the 58th transistor M58 is electrically connected to the seventh clock signal terminal CLKA, and the second terminal of the 58th transistor M58 is electrically connected to the first voltage signal terminal V1.

[0492] For example, when the voltage of the first blanking node H is high and the level of the seventh clock signal is high, the fifty-seventh transistor M57 can be turned on under the influence of the voltage of the first blanking node H, and the fifty-eighth transistor M58 can be turned on under the influence of the seventh clock signal. The fifty-eighth transistor M58 can receive and transmit the first voltage signal to the second terminal of the fifty-seventh transistor M57. The fifty-seventh transistor M57 can receive and transmit the first voltage signal to the second pull-down node QB_B, performing a pull-down reset on the second pull-down node QB_B.

[0493] In some embodiments, such as Figure 37 As shown, the shift register 100 also includes a first leakage protection circuit 5.

[0494] In some examples, such as Figure 37 As shown, the first leakage protection circuit 5 is electrically connected to the first blanking node H, the fifth voltage signal terminal V5, and the first leakage protection node OFF1. The first leakage protection circuit 5 is configured to, under the control of the voltage at the first blanking node H, transmit the fifth voltage signal received at the fifth voltage signal terminal V5 to the first leakage protection node OFF1.

[0495] For example, when the voltage of the first blanking node H is high, the first leakage protection circuit 5 can be turned on under the control of the voltage of the first blanking node H, receive and transmit the fifth voltage signal to the first leakage protection node OFF1, charge the first leakage protection node OFF1, and increase the voltage of the first leakage protection node OFF1.

[0496] In some examples, such as Figure 37 As shown, the selection control sub-circuit 41 is also electrically connected to the first leakage protection node OFF1.

[0497] When the forty-seventh transistor M47 in the selection control sub-circuit 41 is turned off and the sixth capacitor C6 is discharged so that the voltage of the first blanking node H is kept at a high level, by electrically connecting the selection control sub-circuit 41 with the first leakage protection node OFF1, the voltage difference between the first leakage protection node OFF1 and the first blanking node H can be reduced, and leakage at the first blanking node H through the selection control sub-circuit 41 can be avoided. In this way, the first blanking node H can be kept at a higher and more stable voltage, so as to avoid affecting the conduction state of the blanking input sub-circuit 42.

[0498] The structure of the first leakage protection circuit 5 and the selection control sub-circuit 41 will be schematically described below with reference to the accompanying drawings.

[0499] In some examples, such as Figure 37 As shown, the first leakage protection circuit 5 includes: the fifty-ninth transistor M59.

[0500] For example, such as Figure 37 As shown, the control electrode of the fifty-ninth transistor M59 is electrically connected to the first blanking node H, the first electrode of the fifty-ninth transistor M59 is electrically connected to the fifth voltage signal terminal V5, and the second electrode of the fifty-ninth transistor M59 is electrically connected to the first leakage protection node OFF1.

[0501] For example, when the voltage of the first blanking node H is high, the fifty-ninth transistor M59 can be turned on under the control of the voltage of the first blanking node H, receive the fifth voltage signal, and transmit the fifth voltage signal to the first leakage protection node OFF1 to charge the first leakage protection node OFF1, thereby increasing the voltage of the first leakage protection node OFF1.

[0502] Based on this, in some examples, such as Figure 37 As shown, the selection control sub-circuit 41 may also include: a sixtieth transistor M60.

[0503] For example, such as Figure 37 As shown, the control terminal of the 60th transistor M60 is electrically connected to the third control signal terminal OE, the first terminal of the 60th transistor M60 is electrically connected to the display input signal terminal Iput, and the second terminal of the 60th transistor M60 is electrically connected to the first leakage protection node OFF1. Specifically, the first terminal of the 47th transistor M47 in the selection control sub-circuit 41 is electrically connected to the first leakage protection node OFF1, and is also electrically connected to the display input signal terminal Iput via the aforementioned 60th transistor M60.

[0504] For example, when the third control signal is at a high level, the forty-seventh transistor M47 and the sixtieth transistor M60 can be turned on simultaneously under the action of the third control signal. The sixtieth transistor M60 can receive and transmit the display input signal to the first leakage protection node OFF1, and the forty-seventh transistor M47 can receive and transmit the display input signal to the first blanking node H, charging the first blanking node H.

[0505] When the third control signal is at a low level, the forty-seventh transistor M47 and the sixtieth transistor M60 can be simultaneously turned off under the action of the third control signal. The sixth capacitor C6 in the selection control sub-circuit 41 begins to discharge, keeping the voltage of the first blanking node H at a high level. During this process, the fifty-ninth transistor M59 in the first leakage protection circuit 5 can transmit the fifth voltage signal to the first leakage protection node OFF1, charging the first leakage protection node OFF1, reducing the voltage difference between the first leakage protection node OFF1 and the first blanking node H, and making the voltage difference between the control electrode and the first electrode of the forty-seventh transistor M47 less than zero, ensuring that the forty-seventh transistor M47 is completely or relatively completely turned off. This can prevent the first blanking node H from leaking through the selection control sub-circuit 41, allowing the first blanking node H to maintain a relatively high and stable voltage.

[0506] The shift register 100 may also include other circuit structures, which can be selected and configured according to actual needs.

[0507] In some embodiments, such as Figures 31-33 , Figure 36 and Figure 37 As shown, the shift register 100 also includes: a second leakage protection circuit 7.

[0508] In some examples, such as Figures 31-33 , Figure 36 and Figure 37 As shown, the second leakage protection circuit 7 is connected to the first pull-up node Q. <1> The fifth voltage signal terminal V5 and the second leakage protection node OFF2 are electrically connected. The second leakage protection circuit 7 is configured to connect to the first pull-up node Q. <1> Under the control of the voltage, the fifth voltage signal received at the fifth voltage signal terminal V5 will be transmitted to the second leakage protection node OFF2.

[0509] For example, in the first pull-up node Q <1> When the voltage is high, the second leakage protection circuit 7 can be activated at the first pull-up node Q. <1> Under the control of the voltage, it is turned on, receives and transmits the fifth voltage signal to the second leakage protection node OFF2, charges the second leakage protection node OFF2, and increases the voltage of the second leakage protection node OFF2.

[0510] The structure of the second leakage protection circuit 7 will be schematically described below with reference to the accompanying drawings.

[0511] In some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the second leakage protection circuit 7 includes: the sixty-first transistor M61.

[0512] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control electrode of the sixty-first transistor M61 is connected to the first pull-up node Q. <1> Electrically connected, the first terminal of the sixty-first transistor M61 is electrically connected to the fifth voltage signal terminal V5, and the second terminal of the sixty-first transistor M61 is electrically connected to the second leakage protection node OFF2.

[0513] For example, in the first pull-up node Q <1> When the voltage is high, the sixty-first transistor M61 can pull up at the first pull-up node Q. <1> It is turned on under the control of the voltage, receives the fifth voltage signal, and transmits the fifth voltage signal to the second leakage protection node OFF2 to charge the second leakage protection node OFF2, so that the voltage of the second leakage protection node OFF2 increases.

[0514] It should be noted that other circuits included in shift register 100 can also be electrically connected to the second leakage protection node OFF2.

[0515] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the first input circuit 11 can also be electrically connected to the second leakage protection node OFF2.

[0516] When the first input circuit 11 is turned off, the first capacitor C1 in the first output circuit 12 is discharged so that the first pull-up node Q... <1> When the voltage is kept high, by electrically connecting the first input circuit 11 to the second leakage protection node OFF2, the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q can be reduced. <1> The pressure difference between them avoids the first pull-up node Q. <1> The leakage current in the first input circuit 11 can thus cause the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the first output circuit 12.

[0517] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the first input circuit 11 also includes: the sixty-second transistor M62.

[0518] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the sixty-second transistor M62 is electrically connected to the display input signal terminal Iput, the first terminal of the sixty-second transistor M62 is electrically connected to the display input signal terminal Iput, and the second terminal of the sixty-second transistor M62 is electrically connected to the second leakage protection node OFF2. The first terminal of the first transistor M1 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the display input signal terminal Iput through the sixty-second transistor M62.

[0519] For example, when the display input signal level is high, the first transistor M1 and the sixty-second transistor M62 can be simultaneously turned on under the influence of the display input signal. The sixty-second transistor M62 can receive and transmit the display input signal to the second leakage protection node OFF2, and the first transistor M1 can receive and transmit the display input signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charge it.

[0520] When the display input signal level is low, the first transistor M1 and the sixty-second transistor M62 can be simultaneously turned off under the influence of the display input signal. The first capacitor C1 in the first output circuit 12 begins to discharge, causing the first pull-up node Q to... <1> The voltage remains high. During this process, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the first electrode of the first transistor M1 is kept less than zero, ensuring that the first transistor M1 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the first input circuit 11 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0521] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the shift register 100 also includes a second scanning unit 3, the second input circuit 31 is also electrically connected to the second leakage protection node OFF2.

[0522] When the second input circuit 31 is turned off, the second capacitor C2 in the second output circuit 32 discharges to enable the second pull-up node Q. <2> When the voltage is kept high, by electrically connecting the second input circuit 31 to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 and the second pull-up node Q can be reduced. <2> The pressure difference between them prevents the second pull-up node Q from being pulled up. <2> The leakage current in the second input circuit 31 can then cause the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the second output circuit 32.

[0523] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the first terminal of the third transistor M3 in the second input circuit 31 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the display input signal terminal Iput through the sixty-second transistor M62.

[0524] For example, when the display input signal level is high, the third transistor M3 and the sixty-second transistor M62 can be simultaneously turned on under the influence of the display input signal. The sixty-second transistor M62 can receive and transmit the display input signal to the second leakage protection node OFF2, and the third transistor M3 can receive and transmit the display input signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charge it.

[0525] When the display input signal level is low, the third transistor M3 and the sixty-second transistor M62 can be simultaneously turned off under the influence of the display input signal. The second capacitor C2 in the second output circuit 32 begins to discharge, causing the second pull-up node Q... <2> The voltage remains high during this process. The first pull-up node Q... <1> The voltage remains high, and the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage of the second leakage protection node OFF2 and the second pull-up node Q. <2> The voltage difference between the control electrode and the first electrode of the third transistor M3 is maintained, ensuring that the third transistor M3 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the second input circuit 31 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0526] In addition, the second input circuit 31 shares the sixty-second transistor M62 in the first input circuit 11, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0527] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the black plug circuit 2 is also electrically connected to the second leakage protection node OFF2.

[0528] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the black insertion circuit 2 includes the first black insertion transmission sub-circuit 23, the first black insertion transmission sub-circuit 23 further includes: the sixty-third transistor M63.

[0529] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the sixty-third transistor M63 is electrically connected to the second control signal terminal BCS2, the first terminal of the sixty-third transistor M63 is electrically connected to the second black insertion node K, and the second terminal of the sixty-third transistor M63 is electrically connected to the second leakage protection node OFF2. The first terminal of the seventh transistor M7 in the first black insertion transmission sub-circuit 23 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the second black insertion node K through the sixty-third transistor M63.

[0530] For example, when the second control signal is at a high level, the seventh transistor M7 and the sixty-third transistor M63 can be simultaneously turned on under the action of the second control signal. The sixty-third transistor M63 can receive the black insertion input signal from the second black insertion node K and send the black insertion input signal to the second leakage protection node OFF2. The seventh transistor M7 can receive and transmit the black insertion input signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charge it.

[0531] When the second control signal is low, the seventh transistor M7 and the sixty-third transistor M63 can be simultaneously turned off under the action of the second control signal. The first capacitor C1 in the first output circuit 12 begins to discharge, causing the first pull-up node Q to... <1> The voltage remains high. During this process, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the first electrode of the seventh transistor M7 is maintained, ensuring that the seventh transistor M7 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the first black-plug transmission sub-circuit 23 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0532] In some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the first terminal of the eighth transistor M8 in the second black-insertion transmission sub-circuit 24 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the second black-insertion node OFF2 through the sixty-third transistor M63.

[0533] For example, when the second control signal is at a high level, the eighth transistor M8 and the sixty-third transistor M63 can be simultaneously turned on under the action of the second control signal. The sixty-third transistor M63 can receive the black insertion input signal from the second black insertion node K and send the black insertion input signal to the second leakage protection node OFF2. The eighth transistor M8 can receive and transmit the black insertion input signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charge it.

[0534] When the second control signal is low, the eighth transistor M8 and the sixty-third transistor M63 can be simultaneously turned off under the action of the second control signal. The second capacitor C2 in the second output circuit 22 begins to discharge, causing the second pull-up node Q... <2> The voltage remains high during this process. The first pull-up node Q... <1> The voltage remains high, and the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage of the second leakage protection node OFF2 and the second pull-up node Q. <2> The voltage difference between the control electrode and the first electrode of the seventh transistor M7 is maintained, ensuring that the voltage difference between them is less than zero, thus ensuring that the eighth transistor M8 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the second black-plug transmission sub-circuit 24 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0535] In addition, the second black insertion transmission sub-circuit 24 shares the sixty-third transistor M63 in the first black insertion transmission sub-circuit 23, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0536] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the first scanning unit 1 also includes a first reset circuit 13, the first reset circuit 13 is also electrically connected to the second leakage protection node OFF2.

[0537] First pull-up node Q <1> When the voltage level is high and the first reset circuit 13 is not working, by electrically connecting the first reset circuit 13 to the second leakage protection node OFF2, the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q can be reduced. <1> The pressure difference between them avoids the first pull-up node Q. <1> The leakage current in the first reset circuit 13 can then cause the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the first output circuit 12.

[0538] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the first reset circuit 13 also includes: the sixty-fourth transistor M64.

[0539] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the sixty-fourth transistor M64 is electrically connected to the first reset signal terminal STD, the first terminal of the sixty-fourth transistor M64 is electrically connected to the second leakage protection node OFF2, and the second terminal of the sixty-fourth transistor M64 is electrically connected to the first voltage signal terminal V1. The second terminal of the thirteenth transistor M13 in the first reset circuit 13 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the first voltage signal terminal V1 through the sixty-fourth transistor M64.

[0540] For example, when the first reset signal is high, the thirteenth transistor M13 and the sixty-fourth transistor M64 can be simultaneously turned on under the action of the first reset signal. The sixty-fourth transistor M64 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the thirteenth transistor M13 can transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0541] When the first reset signal is low, transistors thirteen (M13) and sixty-fourth (M64) can be simultaneously turned off under the action of the first reset signal. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 is kept below zero, ensuring that the thirteenth transistor M13 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the first reset circuit 13 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0542] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the second scanning unit 3 also includes a third reset circuit 33, the third reset circuit 33 is also electrically connected to the second leakage protection node OFF2.

[0543] First pull-up node Q <1> High level, second pull-up node Q <2> When the voltage level is high and the third reset circuit 33 is not working, by electrically connecting the third reset circuit 13 to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 and the second pull-up node Q can be reduced. <2> The pressure difference between them prevents the second pull-up node Q from being pulled up. <2> The leakage current in the third reset circuit 33 can then cause the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the second output circuit 32.

[0544] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the second terminal of the sixteenth transistor M16 in the third reset circuit 33 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-fourth transistor M64.

[0545] For example, when the first reset signal is high, the sixteenth transistor M16 and the sixty-fourth transistor M64 can be simultaneously turned on under the action of the first reset signal. The sixty-fourth transistor M64 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the sixteenth transistor M16 can transmit the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0546] When the first reset signal is low, transistors 16 (M16) and 64 (M64) can be simultaneously turned off under the action of the first reset signal. At the first pull-up node Q... <1> voltage and the second pull-up node Q <2> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage of the second leakage protection node OFF2 and the second pull-up node Q. <2> The voltage difference between the control electrode and the second electrode of the sixteenth transistor M16 is maintained, ensuring that the sixteenth transistor M16 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the third reset circuit 33 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0547] In addition, the third reset circuit 33 shares the sixty-fourth transistor M64 in the first reset circuit 13, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0548] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the first scanning unit 1 also includes a second reset circuit 14, the second reset circuit 14 is also electrically connected to the second leakage protection node OFF2.

[0549] First pull-up node Q <1> When the voltage level is high and the second reset circuit 14 is not working, by electrically connecting the second reset circuit 14 to the second leakage protection node OFF2, the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q can be reduced. <1> The pressure difference between them avoids the first pull-up node Q. <1> The leakage current in the second reset circuit 14 can then cause the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the first output circuit 12.

[0550] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the second reset circuit 14 also includes: the sixty-fifth transistor M65.

[0551] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the 65th transistor M65 is electrically connected to the second reset signal terminal BTRST, the first terminal of the 65th transistor M65 is electrically connected to the second leakage protection node OFF2, and the second terminal of the 65th transistor M65 is electrically connected to the first voltage signal terminal V1. In the second reset circuit 14, the second terminal of the 15th transistor M15 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the first voltage signal terminal V1 via the 65th transistor M65.

[0552] For example, when the second reset signal is high and the voltage of the first black plug node M is high, the fourteenth transistor M14 can be turned on under the influence of the voltage of the first black plug node M, and the fifteenth transistor M15 and the sixty-fifth transistor M65 can be turned on simultaneously under the influence of the second reset signal. The sixty-fifth transistor M65 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the fifteenth transistor M15 and the fourteenth transistor M14 can transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0553] When the second reset signal is low and the voltage at the first black-pin node M is low, transistors fourteenth M14, fifteenth M15, and sixty-fifth M65 can be turned off. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 is maintained, ensuring that the fifteenth transistor M15 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current through the second reset circuit 14 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0554] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the second scanning unit 3 also includes a fourth reset circuit 34, the fourth reset circuit 34 is also electrically connected to the second leakage protection node OFF2.

[0555] First pull-up node Q <1> High level, second pull-up node Q <2> When the voltage level is high and the fourth reset circuit 34 is not working, by electrically connecting the fourth reset circuit 34 to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 and the second pull-up node Q can be reduced. <2> The pressure difference between them prevents the second pull-up node Q from being pulled up. <2> The leakage current in the fourth reset circuit 34 can then cause the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the second output circuit 32.

[0556] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the second terminal of the eighteenth transistor M18 in the fourth reset circuit 34 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-fifth transistor M65.

[0557] For example, when the second reset signal is high and the voltage of the first black plug node M is high, the seventeenth transistor M17 can be turned on under the influence of the voltage of the first black plug node M, and the eighteenth transistor M18 and the sixty-fifth transistor M65 can be turned on simultaneously under the influence of the second reset signal. The sixty-fifth transistor M65 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the eighteenth transistor M18 and the seventeenth transistor M17 can transmit the first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0558] When the second reset signal is low and the voltage at the first black-pin node M is low, transistors 17 M17, 18 M18, and 65 M65 can be turned off. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage of the second leakage protection node OFF2 and the second pull-up node Q. <2> The voltage difference between the control electrode and the second electrode of the eighteenth transistor M18 is maintained, ensuring that the eighteenth transistor M18 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the fourth reset circuit 34 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0559] In addition, the fourth reset circuit 34 shares the sixty-fifth transistor M65 in the second reset circuit 14, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0560] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the first scanning unit 1 also includes a fifth reset circuit 16, the fifth reset circuit 16 is also electrically connected to the second leakage protection node OFF2.

[0561] First pull-up node Q <1> When the voltage level is high and the fifth reset circuit 16 is not working, by electrically connecting the fifth reset circuit 16 to the second leakage protection node OFF2, the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q can be reduced. <1> The pressure difference between them avoids the first pull-up node Q. <1> The leakage current in the fifth reset circuit 16 can then cause the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the first output circuit 12.

[0562] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the fifth reset circuit 16 also includes: the sixty-sixth transistor M66.

[0563] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the sixty-sixth transistor M66 is electrically connected to the first pull-down node QB_A, the first terminal of the sixty-sixth transistor M66 is electrically connected to the second leakage protection node OFF2, and the second terminal of the sixty-sixth transistor M66 is electrically connected to the first voltage signal terminal V1. The second terminal of the twenty-seventh transistor M27 in the fifth reset circuit 16 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the first voltage signal terminal V1 through the sixty-sixth transistor M66.

[0564] For example, when the voltage at the first pull-down node QB_A is high, the twenty-seventh transistor M27 and the sixty-sixth transistor M66 can be simultaneously turned on under the influence of the voltage at the first pull-down node QB_A. The sixty-sixth transistor M66 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the twenty-seventh transistor M27 can transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0565] When the voltage of the first pull-down node QB_A is low, the voltage of the first pull-up node Q... <1> The voltage is high. Transistor M27 (twenty-seventh) and transistor M66 (sixty-sixth) can be turned off. Transistor M61 (sixty-first) in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the 27th transistor M27 is maintained, ensuring that the 27th transistor M27 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the fifth reset circuit 16 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0566] It should be noted that, as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the fifth reset circuit 16 is also electrically connected to the second pull-down node QB_B, the fifth reset circuit 16 further includes: the sixty-seventh transistor M67.

[0567] For example, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the control terminal of the sixty-seventh transistor M67 is electrically connected to the second pull-down node QB_B, the first terminal of the sixty-seventh transistor M67 is electrically connected to the second leakage protection node OFF2, and the second terminal of the sixty-seventh transistor M67 is electrically connected to the first voltage signal terminal V1. The second terminal of the thirty-ninth transistor M39 in the fifth reset circuit 16 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the first voltage signal terminal V1 through the sixty-seventh transistor M67.

[0568] For example, when the voltage at the second pull-down node QB_B is high, the thirty-ninth transistor M39 and the sixty-seventh transistor M67 can be simultaneously turned on under the influence of the voltage at the second pull-down node QB_B. The sixty-seventh transistor M67 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the thirty-ninth transistor M39 can transmit the first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0569] When the voltage of the second pull-down node QB_B is low, the voltage of the first pull-up node Q... <1> The voltage is high. Transistor M39 (39th) and transistor M67 (67th) can be turned off. Transistor M61 (61st) in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the 39th transistor M39 is kept less than zero, ensuring that the 39th transistor M39 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the fifth reset circuit 16 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0570] In some embodiments, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, when the second scanning unit 3 also includes an eighth reset circuit 36, the eighth reset circuit 36 ​​is also electrically connected to the second leakage protection node OFF2.

[0571] First pull-up node Q <1> High level, second pull-up node Q <2> When the voltage level is high and the eighth reset circuit 36 ​​is not working, by electrically connecting the eighth reset circuit 36 ​​to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 and the second pull-up node Q can be reduced. <2> The pressure difference between them prevents the second pull-up node Q from being pulled up. <2> The leakage current in the eighth reset circuit 36 ​​can then cause the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the second output circuit 32.

[0572] Based on this, in some examples, such as Figure 32 , Figure 33 , Figure 36 and Figure 37 As shown, the second terminal of the thirty-third transistor M33 in the eighth reset circuit 36 ​​is electrically connected to the second leakage protection node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-sixth transistor M66.

[0573] For example, when the voltage at the second pull-down node QB_B is high, the voltage at the first pull-down node QB_A is also high. The thirty-third transistor M33 can be turned on by the voltage at the second pull-down node QB_B, and the sixty-sixth transistor M66 can be turned on by the voltage at the first pull-down node QB_A. The sixty-sixth transistor M66 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the thirty-third transistor M33 can transmit this first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0574] When the voltage of the second pull-down node QB_B is low, the voltage of the first pull-down node QB_A is low, and the voltage of the first pull-up node QB_B is also low. <1> The voltage is high. The thirty-third transistor M33 and the sixty-sixth transistor M66 can be turned off. The sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the 33rd transistor M33 is maintained, ensuring that the 33rd transistor M33 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the eighth reset circuit 36 ​​causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0575] It should be noted that, as Figure 36 and Figure 37 As shown, when the eighth reset circuit 36 ​​is also electrically connected to the first pull-down node QB_A, the second terminal of the forty-third transistor M43 in the eighth reset circuit 36 ​​is electrically connected to the second leakage protection node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-seventh transistor M67.

[0576] For example, when the voltage at the second pull-down node QB_B is high, the voltage at the first pull-down node QB_A is also high. The forty-third transistor M43 and the sixty-seventh transistor M67 can then conduct. The sixty-seventh transistor M67 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and the forty-third transistor M43 can transmit this first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0577] When the voltage of the second pull-down node QB_B is low, the voltage of the first pull-down node QB_A is low, and the voltage of the first pull-up node QB_B is also low. <1> The voltage is high. Transistor M43 (43rd) and transistor M67 (67th) can be turned off. Transistor M61 (61st) in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the 43rd transistor M43 is kept below zero, ensuring that the 43rd transistor M43 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the eighth reset circuit 36 ​​causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0578] In addition, the eighth reset circuit 36 ​​shares the sixty-sixth transistor M66 and the sixty-seventh transistor M67 in the fifth reset circuit 16, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0579] In some embodiments, such as Figure 36 and Figure 37 As shown, when the first scanning unit 1 also includes an eleventh reset circuit 19, the eleventh reset circuit 19 is also electrically connected to the second leakage protection node OFF2.

[0580] First pull-up node Q <1> When the voltage level is high and the eleventh reset circuit 19 is not working, by electrically connecting the eleventh reset circuit 19 to the second leakage protection node OFF2, the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q can be reduced. <1> The pressure difference between them avoids the first pull-up node Q. <1> Through leakage current in the eleventh reset circuit 19, the first pull-up node Q can be made to... <1> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the first output circuit 12.

[0581] Based on this, in some examples, such as Figure 36 and Figure 37 As shown, the eleventh reset circuit 19 also includes the sixty-eighth transistor M68.

[0582] For example, such as Figure 36 and Figure 37 As shown, the control terminal of the sixty-eighth transistor M68 is electrically connected to the global reset signal terminal TRST, the first terminal of the sixty-eighth transistor M68 is electrically connected to the second leakage protection node OFF2, and the second terminal of the sixty-eighth transistor M68 is electrically connected to the first voltage signal terminal V1. The second terminal of the fifty-first transistor M51 in the eleventh reset circuit 19 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the first voltage signal terminal V1 via the sixty-eighth transistor M68.

[0583] For example, when the global reset signal is high, transistors M51 (51) and M68 (68) can be simultaneously turned on under the influence of the global reset signal. Transistor M68 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and transistor M51 can transmit this first voltage signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Perform a pull-down reset.

[0584] When the global reset signal is low, transistors M51 (51) and M68 (68) can be simultaneously turned off under the influence of the global reset signal. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the second electrode of the 51st transistor M51 is kept below zero, ensuring that the 51st transistor M51 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the eleventh reset circuit 19 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0585] In some embodiments, such as Figure 36 and Figure 37 As shown, when the second scanning unit 3 also includes a fourteenth reset circuit 39, the fourteenth reset circuit 39 is also electrically connected to the second leakage protection node OFF2.

[0586] First pull-up node Q <1> High level, second pull-up node Q <2> When the voltage level is high and the fourteenth reset circuit 39 is not working, by electrically connecting the fourteenth reset circuit 39 to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 and the second pull-up node Q can be reduced. <2> The pressure difference between them prevents the second pull-up node Q from being pulled up. <2> The leakage current in the fourteenth reset circuit 39 can then cause the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage to avoid affecting the conduction state of the second output circuit 32.

[0587] Based on this, in some examples, such as Figure 36 and Figure 37 As shown, the second terminal of the fifty-fifth transistor M55 in the fourteenth reset circuit 39 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the first voltage signal terminal V1 through the sixty-eighth transistor M68.

[0588] For example, when the global reset signal is high, transistors M55 (55th) and M68 (68th) can be simultaneously turned on under the influence of the global reset signal. Transistor M68 can receive and transmit the first voltage signal to the second leakage protection node OFF2, and transistor M55 can transmit this first voltage signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Perform a pull-down reset.

[0589] When the global reset signal is low, transistors M55 (55th) and M68 (68th) can be simultaneously turned off under the influence of the global reset signal. At the first pull-up node Q... <1> voltage and the second pull-up node Q <2> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage of the second leakage protection node OFF2 and the second pull-up node Q. <2> The voltage difference between the control electrode and the second electrode of the 55th transistor M55 is maintained, ensuring that the 55th transistor M55 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the fourteenth reset circuit 39 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0590] In addition, the fourteenth reset circuit 39 shares the sixty-eighth transistor M68 in the eleventh reset circuit 19, which helps to simplify the structure of the shift register 100 and reduce the area occupied by the shift register 100.

[0591] In some embodiments, such as Figure 36 and Figure 37 As shown, when the shift register 100 also includes a blanking circuit 4, the blanking circuit 4 is also electrically connected to the second leakage protection node OFF2.

[0592] Based on this, in some examples, such as Figure 36 and Figure 37 As shown, when the blanking circuit 4 includes the first blanking transporter circuit 43, the first blanking transporter circuit 43 further includes: the sixty-ninth transistor M69.

[0593] For example, such as Figure 36 and Figure 37 As shown, the control terminal of the sixty-ninth transistor M69 is electrically connected to the seventh clock signal terminal CLKA, the first terminal of the sixty-ninth transistor M69 is electrically connected to the second blanking node N, and the second terminal of the sixty-ninth transistor M69 is electrically connected to the second leakage protection node OFF2. The first terminal of the forty-ninth transistor M49 in the first blanking transmitter circuit 43 is electrically connected to the second leakage protection node OFF2, and is also electrically connected to the second blanking node N through the sixty-ninth transistor M69.

[0594] For example, when the seventh clock signal is high, transistors M49 and M69 can be simultaneously turned on under the influence of the seventh clock signal. Transistor M69 can receive the seventh clock signal from the second blanking node N and transmit it to the second leakage protection node OFF2. Transistor M49 can receive and transmit the seventh clock signal to the first pull-up node Q. <1> For the first pull-up node Q <1> Charge it.

[0595] When the seventh clock signal is low, transistors M49 and M69 can be simultaneously turned off under the influence of the seventh clock signal. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the first electrode of the forty-ninth transistor M49 is kept below zero, ensuring that the forty-ninth transistor M49 is completely or partially turned off. This avoids the first pull-up node Q. <1> The leakage current in the first blanking transmission sub-circuit 43 causes the first pull-up node Q to... <1> It can maintain a relatively high and stable voltage.

[0596] In some examples, such as Figure 36 and Figure 37 As shown, the first terminal of the fiftieth transistor M50 in the second blanking transmission sub-circuit 44 is electrically connected to the second leakage protection node OFF2, and is electrically connected to the second blanking node N through the sixty-ninth transistor M69.

[0597] For example, when the seventh clock signal is high, the 50th transistor M50 and the 69th transistor M69 can be simultaneously turned on under the influence of the seventh clock signal. The 69th transistor M69 can receive the seventh clock signal from the second blanking node N and transmit the seventh clock signal to the second leakage protection node OFF2. The 50th transistor M50 can receive and transmit the seventh clock signal to the second pull-up node Q. <2> For the second pull-up node Q <2> Charge it.

[0598] When the seventh clock signal is low, transistors 50 (M50) and 69 (M69) can be simultaneously turned off under the influence of the seventh clock signal. At the first pull-up node Q... <1> When the voltage remains high, the sixty-first transistor M61 in the second leakage protection circuit 7 can transmit the fifth voltage signal to the second leakage protection node OFF2, charging the second leakage protection node OFF2 and reducing the voltage difference between the second leakage protection node OFF2 and the first pull-up node Q. <1> The voltage difference between the control electrode and the first electrode of the 50th transistor M50 is maintained, ensuring that the 50th transistor M50 is completely or partially turned off. This avoids the second pull-up node Q. <2> The leakage current in the second blanking transmission sub-circuit 44 causes the second pull-up node Q to... <2> It can maintain a relatively high and stable voltage.

[0599] In some embodiments of this disclosure, the scan driving circuit 1000 provided, such as Figures 38-42 As shown, the scan drive circuit 1000 includes a multi-stage cascaded shift register 100, comprising multiple first shift register groups C and multiple second shift register groups D. The first shift register groups C and the second shift register groups D are arranged alternately.

[0600] In some examples, the shift registers 100 at each level described above may include a first scan unit 1.

[0601] In other examples, such as Figures 38-42 As shown, the shift registers 100 at each level may include a first scan unit 1 and a second scan unit 3.

[0602] The following is a schematic description of the structure of the scan drive circuit 1000, taking the shift registers 100 at each level, including the first scan unit 1 and the second scan unit 3, as an example.

[0603] In some examples, the first shift register group C may ...

Claims

1. A shift register, characterized by, The shift register is applied to a display device, and the display device comprises multiple rows of sub-pixels; the shift register is electrically connected with at least one row of sub-pixels; The shift register comprises a first scanning unit, a second scanning unit and a black insertion circuit; The first scanning unit comprises a first input circuit and a first output circuit; The first input circuit is electrically connected with a display input signal end and a first pull-up node; the first input circuit is configured to transmit a display input signal received at the display input signal end to the first pull-up node; The first output circuit is electrically connected with the first pull-up node, a first clock signal end and a first scanning signal end; the first output circuit is configured to, in the case that the first input circuit transmits the display input signal to the first pull-up node, transmit a first clock signal received at the first clock signal end to the first scanning signal end under the control of the voltage of the first pull-up node, drive the at least one row of sub-pixels to perform image display; The black insertion circuit is electrically connected with a first control signal end, a black insertion cascade signal end, a second control signal end, a black insertion input signal end, the first pull-up node and a first voltage signal end; the black insertion circuit is configured to, under the control of a first control signal transmitted by the first control signal end, a black insertion cascade signal transmitted by the black insertion cascade signal end and a second control signal transmitted by the second control signal end, transmit a black insertion input signal received at the black insertion input signal end to the first pull-up node; The first output circuit is further configured to, in the case that the black insertion circuit transmits the black insertion input signal to the first pull-up node, transmit the first clock signal to the first scanning signal end under the control of the voltage of the first pull-up node, drive the at least one row of sub-pixels to perform black picture display; The first output circuit is further electrically connected with a third clock signal end and a first sensing signal end; The first output circuit is further configured to, in the case that the first input circuit transmits the display input signal to the first pull-up node, transmit a third clock signal received at the third clock signal end to the first sensing signal end under the control of the voltage of the first pull-up node, drive the at least one row of sub-pixels to perform reset; or, in the case that the black insertion circuit transmits the black insertion input signal to the first pull-up node, transmit the third clock signal to the first sensing signal end under the control of the voltage of the first pull-up node, drive the at least one row of sub-pixels to perform black picture display; The second scanning unit comprises a second input circuit and a second output circuit; The second input circuit is electrically connected with the display input signal end and a second pull-up node; the second input circuit is configured to transmit the display input signal to the second pull-up node in response to the display input signal; The second output circuit is electrically connected with the second pull-up node, a second clock signal terminal and a second scan signal terminal; the second output circuit is configured to, under the control of the voltage of the second pull-up node, transmit the second clock signal received at the second clock signal terminal to the second scan signal terminal to drive the at least one row of sub-pixels to display images when the second input circuit transmits the display input signal to the second pull-up node; The black insertion circuit is also electrically connected with the second pull-up node; the black insertion circuit is further configured to transmit the black insertion input signal to the second pull-up node while transmitting the black insertion input signal to the first pull-up node; The second output circuit is further configured to, under the control of the voltage of the second pull-up node, transmit the second clock signal to the second scan signal terminal to drive the at least one row of sub-pixels to display a black screen when the black insertion circuit transmits the black insertion input signal to the second pull-up node; The black insertion circuit comprises a black insertion control sub-circuit, a black insertion input sub-circuit and a first black insertion transmission sub-circuit. The black insertion control sub-circuit is electrically connected with the first control signal terminal, the black insertion cascade signal terminal, the first voltage signal terminal and a first black insertion node; the black insertion control sub-circuit is configured to transmit the black insertion cascade signal to the first black insertion node under the control of the first control signal; The black insertion input sub-circuit is electrically connected with the first black insertion node, the black insertion input signal terminal and a second black insertion node; the black insertion input sub-circuit is configured to transmit the black insertion input signal to the second black insertion node under the control of the voltage of the first black insertion node; The first black insertion transmission sub-circuit is electrically connected with the second control signal terminal, the second black insertion node and the first pull-up node; the first black insertion transmission sub-circuit is configured to transmit the black insertion input signal from the second black insertion node to the first pull-up node under the control of the second control signal. The shift register further comprises a first anti-leakage circuit and a selection control sub-circuit. The first anti-leakage circuit is electrically connected with a first blanking node, a fifth voltage signal terminal and a first anti-leakage node; the first anti-leakage circuit is configured to transmit the fifth voltage signal received at the fifth voltage signal terminal to the first anti-leakage node under the control of the voltage of the first blanking node; the selection control sub-circuit is also electrically connected with the first anti-leakage node.

2. The shift register of claim 1, wherein The black insertion circuit further comprises a second black insertion transmission sub-circuit; The second black insertion transmission sub-circuit is electrically connected with the second control signal terminal, the second black insertion node and the second pull-up node; the second black insertion transmission sub-circuit is configured to transmit the black insertion input signal from the second black insertion node to the second pull-up node under the control of the second control signal.

3. The shift register of claim 2, wherein The first input circuit comprises a first transistor; a control electrode of the first transistor is electrically connected with the display input signal end, a first electrode of the first transistor is electrically connected with the display input signal end, and a second electrode of the first transistor is electrically connected with the first pull-up node; The first output circuit comprises a second transistor and a first capacitor; a control electrode of the second transistor is electrically connected with the first pull-up node, a first electrode of the second transistor is electrically connected with the first clock signal end, and a second electrode of the second transistor is electrically connected with the first scan signal end; a first end of the first capacitor is electrically connected with the first pull-up node, and a second end of the first capacitor is electrically connected with the first scan signal end; in the case that the shift register further comprises a second scan unit, The second input circuit comprises a third transistor; a control electrode of the third transistor is electrically connected with the display input signal end, a first electrode of the third transistor is electrically connected with the display input signal end, and a second electrode of the third transistor is electrically connected with the second pull-up node; The second output circuit comprises a fourth transistor and a second capacitor; a control electrode of the fourth transistor is electrically connected with the second pull-up node, a first electrode of the fourth transistor is electrically connected with the second clock signal end, and a second electrode of the fourth transistor is electrically connected with the second scan signal end; a first end of the second capacitor is electrically connected with the second pull-up node, and a second end of the second capacitor is electrically connected with the second scan signal end; in the case that the black insertion circuit comprises a black insertion control sub-circuit, a black insertion input sub-circuit, a first black insertion transmission sub-circuit and a second black insertion transmission sub-circuit, The black insertion control sub-circuit comprises a fifth transistor and a third capacitor; a control electrode of the fifth transistor is electrically connected with the first control signal end, a first electrode of the fifth transistor is electrically connected with the black insertion cascade signal end, and a second electrode of the fifth transistor is electrically connected with the first black insertion node; a first end of the third capacitor is electrically connected with the first black insertion node, and a second end of the third capacitor is electrically connected with the first voltage signal end; The black insertion input sub-circuit comprises a sixth transistor; a control electrode of the sixth transistor is electrically connected with the first black insertion node, a first electrode of the sixth transistor is electrically connected with the black insertion input signal end, and a second electrode of the sixth transistor is electrically connected with the second black insertion node; The first black insertion transmission sub-circuit comprises a seventh transistor; a control electrode of the seventh transistor is electrically connected with the second control signal end, a first electrode of the seventh transistor is electrically connected with the second black insertion node, and a second electrode of the seventh transistor is electrically connected with the first pull-up node; The second black insertion transmission sub-circuit comprises an eighth transistor; a control electrode of the eighth transistor is electrically connected with the second control signal end, a first electrode of the eighth transistor is electrically connected with the second black insertion node, and a second electrode of the eighth transistor is electrically connected with the second pull-up node.

4. The shift register according to claim 1, wherein In a case where the shift register further comprises a second scan unit, The second output circuit is further electrically connected with a fourth clock signal terminal and a second sensing signal terminal; The second output circuit is further configured to, in a case where the second input circuit transmits the display input signal to the second pull-up node, transmit a fourth clock signal received at the fourth clock signal terminal to the second sensing signal terminal under control of a voltage of the second pull-up node, and drive the at least one row of sub-pixels to reset; or, in a case where the black insertion circuit transmits the black insertion input signal to the second pull-up node, transmit the fourth clock signal to the second sensing signal terminal under control of a voltage of the second pull-up node, and drive the at least one row of sub-pixels to display a black screen.

5. The shift register of claim 4, wherein, The first output circuit further comprises a ninth transistor and a fourth capacitor; The control electrode of the ninth transistor is electrically connected with the first pull-up node, the first electrode of the ninth transistor is electrically connected with the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected with the first sensing signal terminal; The first end of the fourth capacitor is electrically connected with the first pull-up node, and the second end of the fourth capacitor is electrically connected with the first sensing signal terminal; The second output circuit further comprises a tenth transistor and a fifth capacitor; The control electrode of the tenth transistor is electrically connected with the second pull-up node, the first electrode of the tenth transistor is electrically connected with the fourth clock signal terminal, and the second electrode of the tenth transistor is electrically connected with the second sensing signal terminal; The first end of the fifth capacitor is electrically connected with the second pull-up node, and the second end of the fifth capacitor is electrically connected with the second sensing signal terminal.

6. The shift register of claim 1, wherein, The first output circuit is further electrically connected with a fifth clock signal terminal and a first shift signal terminal; The first output circuit is further configured to transmit a fifth clock signal received at the fifth clock signal terminal to the first shift signal terminal under control of a voltage of the first pull-up node.

7. The shift register of claim 6, wherein, The first output circuit further comprises an eleventh transistor; The control electrode of the eleventh transistor is electrically connected with the first pull-up node, the first electrode of the eleventh transistor is electrically connected with the fifth clock signal terminal, and the second electrode of the eleventh transistor is electrically connected with the first shift signal terminal.

8. The shift register of claim 6, wherein, In a case where the shift register further comprises a second scan unit, The second output circuit is further electrically connected with a sixth clock signal terminal and a second shift signal terminal; The second output circuit is further configured to transmit a sixth clock signal received at the sixth clock signal terminal to the second shift signal terminal under control of a voltage of the second pull-up node.

9. The shift register of claim 8, wherein, The second output circuit further comprises a twelfth transistor; The control electrode of the twelfth transistor is electrically connected with the second pull-up node, the first electrode of the twelfth transistor is electrically connected with the sixth clock signal terminal, and the second electrode of the twelfth transistor is electrically connected with the second shift signal terminal.

10. The shift register of claim 2, wherein, The first scan unit further comprises a first reset circuit and a second reset circuit; The first reset circuit is electrically connected with the first reset signal end, the first pull-up node and the first voltage signal end; the first reset circuit is configured to transmit the first voltage signal received at the first voltage signal end to the first pull-up node under the control of the first reset signal transmitted by the first reset signal end; The second reset circuit is electrically connected with the second reset signal end, the first black plug node, the first pull-up node and the first voltage signal end; the second reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the first black plug node and the second reset signal transmitted by the second reset signal end; The second scan unit further comprises a third reset circuit and a fourth reset circuit; The third reset circuit is electrically connected with the first reset signal end, the second pull-up node and the first voltage signal end; the third reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the first reset signal; The fourth reset circuit is electrically connected with the second reset signal end, the first black plug node, the second pull-up node and the first voltage signal end; the fourth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the first black plug node and the second reset signal.

11. The shift register of claim 10, wherein The first reset circuit comprises a thirteenth transistor; The control electrode of the thirteenth transistor is electrically connected with the first reset signal end, the first electrode of the thirteenth transistor is electrically connected with the first pull-up node, and the second electrode of the thirteenth transistor is electrically connected with the first voltage signal end; The second reset circuit comprises a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is electrically connected with the first black plug node, the first electrode of the fourteenth transistor is electrically connected with the first pull-up node, and the second electrode of the fourteenth transistor is electrically connected with the first electrode of the fifteenth transistor; The control electrode of the fifteenth transistor is electrically connected with the second reset signal end, and the second electrode of the fifteenth transistor is electrically connected with the first voltage signal end; The third reset circuit comprises a sixteenth transistor; The control electrode of the sixteenth transistor is electrically connected with the first reset signal end, the first electrode of the sixteenth transistor is electrically connected with the second pull-up node, and the second electrode of the sixteenth transistor is electrically connected with the first voltage signal end; The fourth reset circuit comprises a seventeenth transistor and an eighteenth transistor; The control electrode of the seventeenth transistor is electrically connected with the first black plug node, the first electrode of the seventeenth transistor is electrically connected with the second pull-up node, and the second electrode of the seventeenth transistor is electrically connected with the first electrode of the eighteenth transistor; The control electrode of the eighteenth transistor is electrically connected with the second reset signal end, and the second electrode of the eighteenth transistor is electrically connected with the first voltage signal end.

12. The shift register of claim 2, wherein, The first scan unit further comprises The first control circuit is electrically connected with the first pull-up node, the first pull-down node, the first voltage signal terminal and the second voltage signal terminal; the first control circuit is configured to transmit the second voltage signal to the first pull-down node in response to the second voltage signal received at the second voltage signal terminal, and transmit the first voltage signal received at the first voltage signal terminal to the first pull-down node under the control of the voltage of the first pull-up node; The second scanning unit further comprises: The second control circuit is electrically connected with the second pull-up node, the second pull-down node, the first voltage signal terminal and the third voltage signal terminal; the second control circuit is configured to transmit the third voltage signal to the second pull-down node in response to the third voltage signal received at the third voltage signal terminal, and transmit the first voltage signal to the second pull-down node under the control of the voltage of the second pull-up node.

13. The shift register of claim 12, wherein, The first control circuit comprises a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a twenty-second transistor; The control electrode of the nineteenth transistor is electrically connected with the second voltage signal terminal, the first electrode of the nineteenth transistor is electrically connected with the second voltage signal terminal, and the second electrode of the nineteenth transistor is electrically connected with the control electrode of the twentieth transistor and the first electrode of the twenty-first transistor; The first electrode of the twentieth transistor is electrically connected with the second voltage signal terminal, and the second electrode of the twentieth transistor is electrically connected with the first pull-down node; The control electrode of the twenty-first transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-first transistor is electrically connected with the first voltage signal terminal; The control electrode of the twenty-second transistor is electrically connected with the first pull-up node, the first electrode of the twenty-second transistor is electrically connected with the first pull-down node, and the second electrode of the twenty-second transistor is electrically connected with the first voltage signal terminal; The second control circuit comprises a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor; The control electrode of the twenty-third transistor is electrically connected with the third voltage signal terminal, the first electrode of the twenty-third transistor is electrically connected with the third voltage signal terminal, and the second electrode of the twenty-third transistor is electrically connected with the control electrode of the twenty-fourth transistor and the first electrode of the twenty-fifth transistor; The first electrode of the twenty-fourth transistor is electrically connected with the third voltage signal terminal, and the second electrode of the twenty-fourth transistor is electrically connected with the second pull-down node; The control electrode of the twenty-fifth transistor is electrically connected with the second pull-up node, and the second electrode of the twenty-fifth transistor is electrically connected with the first voltage signal terminal; The control electrode of the twenty-sixth transistor is electrically connected with the second pull-up node, the first electrode of the twenty-sixth transistor is electrically connected with the second pull-down node, and the second electrode of the twenty-sixth transistor is electrically connected with the first voltage signal terminal.

14. The shift register of claim 12, wherein, The first scanning unit further comprises a fifth reset circuit, a sixth reset circuit and a seventh reset circuit; The fifth reset circuit is electrically connected with the first pull-down node, the first pull-up node and the first voltage signal terminal; the fifth reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the first pull-down node; The sixth reset circuit is electrically connected with the first pull-down node, the first scanning signal terminal and the fourth voltage signal terminal; the sixth reset circuit is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal to the first scanning signal terminal under the control of the voltage of the first pull-down node; In the case that the first output circuit is further electrically connected with a third clock signal terminal and a first sensing signal terminal, The sixth reset circuit is further electrically connected with the first sensing signal terminal; the sixth reset circuit is further configured to transmit the fourth voltage signal to the first sensing signal terminal under the control of the voltage of the first pull-down node; In the case that the first output circuit is further electrically connected with a fifth clock signal terminal and a first shift signal terminal, The sixth reset circuit is further electrically connected with the first shift signal terminal and the first voltage signal terminal; the sixth reset circuit is further configured to transmit the first voltage signal to the first shift signal terminal under the control of the voltage of the first pull-down node; In the case that the black insertion circuit comprises a black insertion control sub-circuit, The seventh reset circuit is electrically connected with the first black insertion node, the second control signal terminal, the first pull-down node and the first voltage signal terminal; the seventh reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the voltage of the first black insertion node and the second control signal; The second scanning unit further comprises an eighth reset circuit, a ninth reset circuit and a tenth reset circuit; The eighth reset circuit is electrically connected with the second pull-down node, the second pull-up node and the first voltage signal terminal; the eighth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the second pull-down node; The ninth reset circuit is electrically connected with the second pull-down node, the second scanning signal terminal and the fourth voltage signal terminal; the ninth reset circuit is configured to transmit the fourth voltage signal to the second scanning signal terminal under the control of the voltage of the second pull-down node; In the case that the second output circuit is further electrically connected with a fourth clock signal terminal and a second sensing signal terminal, The ninth reset circuit is further electrically connected with the second sensing signal terminal; the ninth reset circuit is further configured to transmit the fourth voltage signal to the second sensing signal terminal under the control of the voltage of the second pull-down node; In the case that the second output circuit is further electrically connected with a sixth clock signal terminal and a second shift signal terminal, The ninth reset circuit is further electrically connected with the second shift signal end and the first voltage signal end; the ninth reset circuit is further configured to transmit the first voltage signal to the second shift signal end under the control of the voltage of the second pull-down node; The tenth reset circuit is electrically connected with the first black insertion node, the second control signal end, the second pull-down node and the first voltage signal end; the tenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the voltage of the first black insertion node and the second control signal.

15. The shift register of claim 14, wherein, The fifth reset circuit comprises a twenty-seventh transistor; The control electrode of the twenty-seventh transistor is electrically connected with the first pull-down node, the first electrode of the twenty-seventh transistor is electrically connected with the first pull-up node, and the second electrode of the twenty-seventh transistor is electrically connected with the first voltage signal end; The sixth reset circuit comprises a twenty-eighth transistor, a twenty-ninth transistor and a thirtieth transistor; The control electrode of the twenty-eighth transistor is electrically connected with the first pull-down node, the first electrode of the twenty-eighth transistor is electrically connected with the first scan signal end, and the second electrode of the twenty-eighth transistor is electrically connected with the fourth voltage signal end; The control electrode of the twenty-ninth transistor is electrically connected with the first pull-down node, the first electrode of the twenty-ninth transistor is electrically connected with the first sensing signal end, and the second electrode of the twenty-ninth transistor is electrically connected with the fourth voltage signal end; The control electrode of the thirtieth transistor is electrically connected with the first pull-down node, the first electrode of the thirtieth transistor is electrically connected with the first shift signal end, and the second electrode of the thirtieth transistor is electrically connected with the first voltage signal end; The seventh reset circuit comprises a thirty-first transistor and a thirty-second transistor; The control electrode of the thirty-first transistor is electrically connected with the first black insertion node, the first electrode of the thirty-first transistor is electrically connected with the first pull-down node, and the second electrode of the thirty-first transistor is electrically connected with the first electrode of the thirty-second transistor; The control electrode of the thirty-second transistor is electrically connected with the second control signal end, and the second electrode of the thirty-second transistor is electrically connected with the first voltage signal end; The eighth reset circuit comprises a thirty-third transistor; The control electrode of the thirty-third transistor is electrically connected with the second pull-down node, the first electrode of the thirty-third transistor is electrically connected with the second pull-up node, and the second electrode of the thirty-third transistor is electrically connected with the first voltage signal end; The ninth reset circuit comprises a thirty-fourth transistor, a thirty-fifth transistor and a thirty-sixth transistor; The control electrode of the thirty-fourth transistor is electrically connected with the second pull-down node, the first electrode of the thirty-fourth transistor is electrically connected with the second scan signal end, and the second electrode of the thirty-fourth transistor is electrically connected with the fourth voltage signal end; The control electrode of the thirty-fifth transistor is electrically connected with the second pull-down node, the first electrode of the thirty-fifth transistor is electrically connected with the second sensing signal end, and the second electrode of the thirty-fifth transistor is electrically connected with the fourth voltage signal end; The control electrode of the thirty-sixth transistor is electrically connected with the second pull-down node, the first electrode of the thirty-sixth transistor is electrically connected with the second shift signal end, and the second electrode of the thirty-sixth transistor is electrically connected with the first voltage signal end; The tenth reset circuit comprises a thirty-seventh transistor and a thirty-eighth transistor; The control electrode of the thirty-seventh transistor is electrically connected with the first black insertion node, the first electrode of the thirty-seventh transistor is electrically connected with the second pull-down node, and the second electrode of the thirty-seventh transistor is electrically connected with the first electrode of the thirty-eighth transistor; The control electrode of the thirty-eighth transistor is electrically connected with the second control signal end, and the second electrode of the thirty-eighth transistor is electrically connected with the first voltage signal end.

16. The shift register of claim 14, wherein The fifth reset circuit is further electrically connected with the second pull-down node, and the fifth reset circuit is further configured to transmit the first voltage signal to the first pull-up node under the control of the voltage of the second pull-down node; The sixth reset circuit is further electrically connected with the second pull-down node, and the sixth reset circuit is further configured to transmit the fourth voltage signal to the first scanning signal end, transmit the fourth voltage signal to the first sensing signal end, and transmit the first voltage signal to the first shift signal end under the control of the voltage of the second pull-down node; The eighth reset circuit is further electrically connected with the first pull-down node, and the eighth reset circuit is further configured to transmit the first voltage signal to the second pull-up node under the control of the voltage of the first pull-down node; The ninth reset circuit is further electrically connected with the first pull-down node, and the ninth reset circuit is further configured to transmit the fourth voltage signal to the second scanning signal end, transmit the fourth voltage signal to the second sensing signal end, and transmit the first voltage signal to the second shift signal end.

17. The shift register of claim 16, wherein The fifth reset circuit further comprises a thirty-ninth transistor; The control electrode of the thirty-ninth transistor is electrically connected with the second pull-down node, the first electrode of the thirty-ninth transistor is electrically connected with the first pull-up node, and the second electrode of the thirty-ninth transistor is electrically connected with the first voltage signal end; The sixth reset circuit further comprises a fourth-ten transistor, a fourth-ten transistor and a fourth-twenty transistor; The control electrode of the fourth-ten transistor is electrically connected with the second pull-down node, the first electrode of the fourth-ten transistor is electrically connected with the first scanning signal end, and the second electrode of the fourth-ten transistor is electrically connected with the fourth voltage signal end; The control electrode of the forty-first transistor is electrically connected with the second pull-down node, the first electrode of the forty-first transistor is electrically connected with the first sensing signal end, and the second electrode of the forty-first transistor is electrically connected with the fourth voltage signal end; The control electrode of the forty-second transistor is electrically connected with the second pull-down node, the first electrode of the forty-second transistor is electrically connected with the first shift signal end, and the second electrode of the forty-second transistor is electrically connected with the first voltage signal end; The eighth reset circuit further includes a forty-third transistor; The control electrode of the forty-third transistor is electrically connected with the first pull-down node, the first electrode of the forty-third transistor is electrically connected with the second pull-up node, and the second electrode of the forty-third transistor is electrically connected with the first voltage signal end; The ninth reset circuit further includes a forty-fourth transistor, a forty-fifth transistor and a forty-sixth transistor; The control electrode of the forty-fourth transistor is electrically connected with the first pull-down node, the first electrode of the forty-fourth transistor is electrically connected with the second scanning signal end, and the second electrode of the forty-fourth transistor is electrically connected with the fourth voltage signal end; The control electrode of the forty-fifth transistor is electrically connected with the first pull-down node, the first electrode of the forty-fifth transistor is electrically connected with the second sensing signal end, and the second electrode of the forty-fifth transistor is electrically connected with the fourth voltage signal end; The control electrode of the forty-sixth transistor is electrically connected with the first pull-down node, the first electrode of the forty-sixth transistor is electrically connected with the second shift signal end, and the second electrode of the forty-sixth transistor is electrically connected with the first voltage signal end.

18. The shift register of claim 12, wherein, The shift register further includes a blanking circuit; The blanking circuit is electrically connected with a third control signal end, the display input signal end, a seventh clock signal end, the first pull-up node and the first voltage signal end; The blanking circuit is configured to transmit the seventh clock signal to the first pull-up node under the control of a third control signal transmitted by the third control signal end, the display input signal and a seventh clock signal transmitted by the seventh clock signal end; In the case that the shift register further includes a second scanning unit, The blanking circuit is further electrically connected with the second pull-up node; and the blanking circuit is further configured to transmit the seventh clock signal to the second pull-up node.

19. The shift register of claim 18, wherein, The blanking circuit includes the selection control sub-circuit, a blanking input sub-circuit, a first blanking transmission sub-circuit and a second blanking transmission sub-circuit; The selection control sub-circuit is electrically connected with the third control signal end, the display input signal end, the first blanking node and the first voltage signal end; and the selection control sub-circuit is configured to transmit the display input signal to the first blanking node under the control of the third control signal; The blanking transmission sub-circuit is electrically connected with the first blanking node, the seventh clock signal terminal and the second blanking node; the blanking transmission sub-circuit is configured to transmit the seventh clock signal to the second blanking node under the control of the voltage of the first blanking node; The first blanking transmission sub-circuit is electrically connected with the seventh clock signal terminal, the second blanking node and the first pull-up node; the first blanking transmission sub-circuit is configured to transmit the seventh clock signal from the second blanking node to the first pull-up node under the control of the seventh clock signal; The second blanking transmission sub-circuit is electrically connected with the seventh clock signal terminal, the second blanking node and the second pull-up node; the second blanking transmission sub-circuit is configured to transmit the seventh clock signal from the second blanking node to the second pull-up node under the control of the seventh clock signal.

20. The shift register of claim 19, wherein, The selection control sub-circuit comprises a forty-seventh transistor and a sixth capacitor; The control electrode of the forty-seventh transistor is electrically connected with the third control signal terminal, the first electrode of the forty-seventh transistor is electrically connected with the display input signal terminal, and the second electrode of the forty-seventh transistor is electrically connected with the first blanking node; The first end of the sixth capacitor is electrically connected with the first blanking node, and the second end of the sixth capacitor is electrically connected with the first voltage signal terminal; The blanking input sub-circuit comprises a forty-eighth transistor; The control electrode of the forty-eighth transistor is electrically connected with the first blanking node, the first electrode of the forty-eighth transistor is electrically connected with the seventh clock signal terminal, and the second electrode of the forty-eighth transistor is electrically connected with the second blanking node; The first blanking transmission sub-circuit comprises a forty-ninth transistor; The control electrode of the forty-ninth transistor is electrically connected with the seventh clock signal terminal, the first electrode of the forty-ninth transistor is electrically connected with the second blanking node, and the second electrode of the forty-ninth transistor is electrically connected with the first pull-up node; The second blanking transmission sub-circuit comprises a fiftieth transistor; The control electrode of the fiftieth transistor is electrically connected with the seventh clock signal terminal, the first electrode of the fiftieth transistor is electrically connected with the second blanking node, and the second electrode of the fiftieth transistor is electrically connected with the second pull-up node.

21. The shift register of claim 19, wherein, The first scanning unit further comprises an eleventh reset circuit, a twelfth reset circuit and a thirteenth reset circuit; The eleventh reset circuit is electrically connected with a global reset signal terminal, the first pull-up node and the first voltage signal terminal; the eleventh reset circuit is configured to transmit the first voltage signal to the first pull-up node under the control of a global reset signal transmitted by the global reset signal terminal; The twelfth reset circuit is electrically connected with the display input signal end, the first pull-down node and the first voltage signal end; the twelfth reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the display input signal; In the case where the blanking circuit comprises a selection control sub-circuit, The thirteenth reset circuit is electrically connected with the first blanking node, the seventh clock signal end, the first pull-down node and the first voltage signal end; the thirteenth reset circuit is configured to transmit the first voltage signal to the first pull-down node under the control of the voltage of the first blanking node and the seventh clock signal; The second scanning unit further comprises a fourteenth reset circuit, a fifteenth reset circuit and a sixteenth reset circuit; The fourteenth reset circuit is electrically connected with the global reset signal end, the second pull-up node and the first voltage signal end; the fourteenth reset circuit is configured to transmit the first voltage signal to the second pull-up node under the control of the global reset signal; The fifteenth reset circuit is electrically connected with the display input signal end, the second pull-down node and the first voltage signal end; the fifteenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the display input signal; The sixteenth reset circuit is electrically connected with the first blanking node, the seventh clock signal end, the second pull-down node and the first voltage signal end; the sixteenth reset circuit is configured to transmit the first voltage signal to the second pull-down node under the control of the voltage of the first blanking node and the seventh clock signal.

22. The shift register of claim 21, wherein, The eleventh reset circuit comprises a fifty-first transistor; The control electrode of the fifty-first transistor is electrically connected with the global reset signal end, the first electrode of the fifty-first transistor is electrically connected with the first pull-up node, and the second electrode of the fifty-first transistor is electrically connected with the first voltage signal end; The twelfth reset circuit comprises a fifty-second transistor; The control electrode of the fifty-second transistor is electrically connected with the display input signal end, the first electrode of the fifty-second transistor is electrically connected with the first pull-down node, and the second electrode of the fifty-second transistor is electrically connected with the first voltage signal end; The thirteenth reset circuit comprises a fifty-third transistor and a fifty-fourth transistor; The control electrode of the fifty-third transistor is electrically connected with the first blanking node, the first electrode of the fifty-third transistor is electrically connected with the first pull-down node, and the second electrode of the fifty-third transistor is electrically connected with the first electrode of the fifty-fourth transistor; The control electrode of the fifty-fourth transistor is electrically connected with the seventh clock signal end, and the second electrode of the fifty-fourth transistor is electrically connected with the first voltage signal end; The fourteenth reset circuit comprises a fifty-fifth transistor; The control electrode of the 55th transistor is electrically connected with the global reset signal terminal, the first electrode of the 55th transistor is electrically connected with the second pull-up node, and the second electrode of the 55th transistor is electrically connected with the first voltage signal terminal; The 15th reset circuit comprises a 56th transistor; The control electrode of the 56th transistor is electrically connected with the display input signal terminal, the first electrode of the 56th transistor is electrically connected with the second pull-down node, and the second electrode of the 56th transistor is electrically connected with the first voltage signal terminal; The 16th reset circuit comprises a 57th transistor and a 58th transistor; The control electrode of the 57th transistor is electrically connected with the first blanking node, the first electrode of the 57th transistor is electrically connected with the second pull-down node, and the second electrode of the 57th transistor is electrically connected with the first electrode of the 58th transistor; The control electrode of the 58th transistor is electrically connected with the seventh clock signal terminal, and the second electrode of the 58th transistor is electrically connected with the first voltage signal terminal.

23. The shift register of claim 1, wherein, The first leakage prevention circuit comprises a 59th transistor; The control electrode of the 59th transistor is electrically connected with the first blanking node, the first electrode of the 59th transistor is electrically connected with the fifth voltage signal terminal, and the second electrode of the 59th transistor is electrically connected with the first leakage prevention node; The selection control sub-circuit further comprises a 60th transistor; The control electrode of the 60th transistor is electrically connected with a third control signal terminal, the first electrode of the 60th transistor is electrically connected with the display input signal terminal, and the second electrode of the 60th transistor is electrically connected with the first leakage prevention node; The first electrode of the 47th transistor of the selection control sub-circuit is electrically connected with the first leakage prevention node and is electrically connected with the display input signal terminal through the 60th transistor.

24. The shift register according to any one of claims 1 to 23, wherein, The shift register further comprises a second leakage prevention circuit; The second leakage prevention circuit is electrically connected with the first pull-up node, the fifth voltage signal terminal and a second leakage prevention node; the second leakage prevention circuit is configured to transmit a fifth voltage signal received at the fifth voltage signal terminal to the second leakage prevention node under the control of the voltage of the first pull-up node; The first input circuit is further electrically connected with the second leakage prevention node; In the case that the shift register further comprises a second scanning unit, the second input circuit is further electrically connected with the second leakage prevention node; The black insertion circuit is further electrically connected with the second leakage prevention node; In the case that the first scanning unit further comprises a first reset circuit and a second reset circuit, and the second scanning unit further comprises a third reset circuit and a fourth reset circuit, the first reset circuit, the second reset circuit, the third reset circuit and the fourth reset circuit are all electrically connected with the second leakage prevention node; In a case where the first scan unit further includes a fifth reset circuit and the second scan unit further includes an eighth reset circuit, the fifth reset circuit and the eighth reset circuit are also electrically connected with the second leakage prevention node; In a case where the shift register further includes a blanking circuit, the blanking circuit is also electrically connected with the second leakage prevention node; In a case where the first scan unit further includes an eleventh reset circuit and the second scan unit further includes a fourteenth reset circuit, the eleventh reset circuit and the fourteenth reset circuit are also electrically connected with the second leakage prevention node.

25. The shift register according to claim 24, wherein the second leakage prevention circuit comprises a sixty-first transistor; a control electrode of the sixty-first transistor is electrically connected with the first pull-up node, a first electrode of the sixty-first transistor is electrically connected with the fifth voltage signal terminal, and a second electrode of the sixty-first transistor is electrically connected with the second leakage prevention node; the first input circuit further comprises a sixty-second transistor; a control electrode of the sixty-second transistor is electrically connected with the display input signal terminal, a first electrode of the sixty-second transistor is electrically connected with the display input signal terminal, and a second electrode of the sixty-second transistor is electrically connected with the second leakage prevention node; a first electrode of the first transistor is electrically connected with the second leakage prevention node and the display input signal terminal through the sixty-second transistor; a first electrode of the third transistor in the second input circuit is electrically connected with the second leakage prevention node and the display input signal terminal through the sixty-second transistor; in a case where the black insertion circuit comprises a first black insertion transmission sub-circuit, the first black insertion transmission sub-circuit further comprises a sixty-third transistor; a control electrode of the sixty-third transistor is electrically connected with the second control signal terminal, a first electrode of the sixty-third transistor is electrically connected with a second black insertion node, and a second electrode of the sixty-third transistor is electrically connected with the second leakage prevention node; a first electrode of the seventh transistor in the first black insertion transmission sub-circuit is electrically connected with the second leakage prevention node and the second black insertion node through the sixty-third transistor; a first electrode of the eighth transistor in the second black insertion transmission sub-circuit is electrically connected with the second leakage prevention node and the second black insertion node through the sixty-third transistor; the first reset circuit further comprises a sixty-fourth transistor; a control electrode of the sixty-fourth transistor is electrically connected with the first reset signal terminal, a first electrode of the sixty-fourth transistor is electrically connected with the second leakage prevention node, and a second electrode of the sixty-fourth transistor is electrically connected with the first voltage signal terminal; a second electrode of the thirteenth transistor in the first reset circuit is electrically connected with the second leakage prevention node and the first voltage signal terminal through the sixty-fourth transistor; a second electrode of the sixteenth transistor in the third reset circuit is electrically connected with the second leakage prevention node and the first voltage signal terminal through the sixty-fourth transistor; The second reset circuit further includes a sixty-fifth transistor; a control electrode of the sixty-fifth transistor is electrically connected with the second reset signal terminal, a first electrode of the sixty-fifth transistor is electrically connected with the second anti-leakage node, and a second electrode of the sixty-fifth transistor is electrically connected with the first voltage signal terminal; a second electrode of a fifteenth transistor in the second reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-fifth transistor; a second electrode of an eighteenth transistor in the fourth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-fifth transistor; The fifth reset circuit further includes a sixty-sixth transistor; a control electrode of the sixty-sixth transistor is electrically connected with the second pull-down node, a first electrode of the sixty-sixth transistor is electrically connected with the second anti-leakage node, and a second electrode of the sixty-sixth transistor is electrically connected with the first voltage signal terminal; a second electrode of a twenty-seventh transistor in the fifth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-sixth transistor; a second electrode of a thirty-third transistor in the eighth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-sixth transistor; In a case where the fifth reset circuit is further electrically connected with a second pull-down node, the fifth reset circuit further includes a sixty-seventh transistor; a control electrode of the sixty-seventh transistor is electrically connected with the second pull-down node, a first electrode of the sixty-seventh transistor is electrically connected with the second anti-leakage node, and a second electrode of the sixty-seventh transistor is electrically connected with the first voltage signal terminal; a second electrode of a thirty-ninth transistor in the fifth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-seventh transistor; a second electrode of a forty-third transistor in the eighth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-seventh transistor; In a case where the first scan unit further includes an eleventh reset circuit, The eleventh reset circuit further includes a sixty-eighth transistor; a control electrode of the sixty-eighth transistor is electrically connected with a global reset signal terminal, a first electrode of the sixty-eighth transistor is electrically connected with the second anti-leakage node, and a second electrode of the sixty-eighth transistor is electrically connected with the first voltage signal terminal; a second electrode of a fifty-first transistor in the eleventh reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-eighth transistor; a second electrode of a fifty-fifth transistor in the fourteenth reset circuit is electrically connected with the second anti-leakage node and electrically connected with the first voltage signal terminal through the sixty-eighth transistor; In a case where the blanking circuit includes a first blanking transmission sub-circuit, The first blanking transmission sub-circuit further includes a sixty-ninth transistor; The control electrode of the sixty-ninth transistor is electrically connected with a seventh clock signal terminal, the first electrode of the sixty-ninth transistor is electrically connected with a second blanking node, and the second electrode of the sixty-ninth transistor is electrically connected with the second anti-leakage node; The first electrode of the forty-ninth transistor in the first blanking transmission sub-circuit is electrically connected with the second anti-leakage node and is electrically connected with the second blanking node through the sixty-ninth transistor; The first electrode of the fiftieth transistor in the second blanking transmission sub-circuit is electrically connected with the second anti-leakage node and is electrically connected with the second blanking node through the sixty-ninth transistor.

26. The shift register of any one of claims 1-23, wherein, The shift register further comprises a third anti-leakage circuit; The third anti-leakage circuit is electrically connected with a first black insertion node, a fifth voltage signal terminal and a third anti-leakage node; the third anti-leakage circuit is configured to, under the control of the voltage of the first black insertion node, transmit a fifth voltage signal received at the fifth voltage signal terminal to the third anti-leakage node; The black insertion control sub-circuit is further electrically connected with the third anti-leakage node.

27. The shift register of claim 26, wherein, The third anti-leakage circuit comprises a seventieth transistor; The control electrode of the seventieth transistor is electrically connected with the first black insertion node, the first electrode of the seventieth transistor is electrically connected with the fifth voltage signal terminal, and the second electrode of the seventieth transistor is electrically connected with the third anti-leakage node; The black insertion control sub-circuit further comprises a seventy-first transistor; The control electrode of the seventy-first transistor is electrically connected with the first control signal terminal, the first electrode of the seventy-first transistor is electrically connected with a black insertion cascade signal terminal, and the second electrode of the seventy-first transistor is electrically connected with the third anti-leakage node; The first electrode of the fifth transistor in the black insertion control sub-circuit is electrically connected with the third anti-leakage node and is electrically connected with the black insertion cascade signal terminal through the seventy-first transistor.

28. A scan driving circuit, comprising: The scan driving circuit comprises a plurality of levels of cascaded shift registers as claimed in any one of claims 1 to 27.

29. The scan driving circuit according to claim 28, wherein, The plurality of levels of shift registers comprise a plurality of first shift register groups and a plurality of second shift register groups; the first shift register groups and the second shift register groups are arranged alternately; In the case where the shift register comprises a first scan unit and a second scan unit, The first shift register groups comprise 2N-level shift registers, and the second shift register groups comprise 2N-level shift registers; wherein N is a positive integer; The scan driving circuit further comprises: a first control signal line group comprising a first sub-control signal line and a second sub-control signal line; the first sub-control signal line is electrically connected with the first control signal terminals of the shift registers in the first shift register groups, and the second sub-control signal line is electrically connected with the first control signal terminals of the shift registers in the second shift register groups; and, The first clock signal line group comprises 8N first sub clock signal lines; the 8N first sub clock signal lines are respectively electrically connected with the first clock signal end and the second clock signal end of each shift register in the first shift register group and the first clock signal end and the second clock signal end of each shift register in the second shift register group; In the case that the first output circuit of the shift register is further electrically connected with the third clock signal end and the first sensing signal end, and the second output circuit is further electrically connected with the fourth clock signal end and the second sensing signal end, The scan driving circuit further comprises a second clock signal line group; The second clock signal line group comprises 4N second sub clock signal lines; the 4N second sub clock signal lines are respectively electrically connected with the third clock signal end and the fourth clock signal end of each shift register in the first shift register group and are respectively electrically connected with the third clock signal end and the fourth clock signal end of each shift register in the second shift register group; Alternatively, the second clock signal line group comprises 8N second sub clock signal lines; the 8N second sub clock signal lines are respectively electrically connected with the third clock signal end and the fourth clock signal end of each shift register in the first shift register group and the third clock signal end and the fourth clock signal end of each shift register in the second shift register group; In the case that the first output circuit of the shift register is further electrically connected with the fifth clock signal end and the first shift signal end, and the second output circuit is further electrically connected with the sixth clock signal end and the second shift signal end, The scan driving circuit further comprises a third clock signal line group; The third clock signal line group comprises 4N third sub clock signal lines; the 4N third sub clock signal lines are respectively electrically connected with the fifth clock signal end and the sixth clock signal end of each shift register in the first shift register group and are respectively electrically connected with the fifth clock signal end and the sixth clock signal end of each shift register in the second shift register group; or, 2N third sub clock signal lines in the 4N third sub clock signal lines are respectively electrically connected with the fifth clock signal end of each shift register in the first shift register group, and the other 2N third sub clock signal lines are respectively electrically connected with the fifth clock signal end of each shift register in the second shift register group; Alternatively, the third clock signal line group comprises 8N third sub clock signal lines; the 8N third sub clock signal lines are respectively electrically connected with the fifth clock signal end and the sixth clock signal end of each shift register in the first shift register group and the fifth clock signal end and the sixth clock signal end of each shift register in the second shift register group.

30. The scan driving circuit according to claim 29, wherein, The scan driving circuit further comprises a second control signal line group; The second control signal line group comprises a third sub control signal line and a fourth sub control signal line; The third sub control signal line is electrically connected with the second control signal end of each shift register in the first shift register group; and the fourth sub control signal line is electrically connected with the second control signal end of each shift register in the second shift register group.

31. The scan driving circuit according to claim 30, wherein, The third sub-control signal line is also electrically connected with the black insertion input signal end of each shift register in the first shift register group. The fourth sub-control signal line is also electrically connected with the black insertion input signal end of each shift register in the second shift register group.

32. The scan driving circuit according to claim 29, wherein, In the multi-stage shift register, The display input signal end of the shift register after the first at least one stage is electrically connected with the first shift signal end in the previous shift register. The black insertion cascade signal end of the shift register after the first at least two stages is electrically connected with the second shift signal end in the previous shift register; or, in the case that the shift register further comprises a second anti-creeping circuit, the black insertion cascade signal end of the shift register after the first at least two stages is electrically connected with the second anti-creeping node of the previous shift register.

33. The scan driving circuit according to claim 29, wherein, In the multi-stage shift register, The display input signal end of the shift register after the first at least one stage is electrically connected with the second shift signal end in the previous shift register. The black insertion cascade signal end of the shift register after the first at least two stages is electrically connected with the first shift signal end in the previous shift register.

34. The scan driving circuit according to any one of claims 29-33, wherein, In the first shift register group, at least two stages of shift registers share a black insertion circuit. In the second shift register group, at least two stages of shift registers share a black insertion circuit.

35. A display device comprising: The display device comprises: a plurality of rows of sub-pixels; and The scan driving circuit according to any one of claims 28-34; wherein a stage of shift registers in the scan driving circuit is electrically connected with at least one row of sub-pixels.

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