Array substrate, method for preparing same, and display device

Abstract

The present application discloses an array substrate, a preparation method thereof, and a display device. The preparation method includes providing a substrate and depositing a first transparent metal oxide conductive layer; patterning the first transparent metal oxide conductive layer by using a first photomask to form a common electrode and a transparent conductive layer; reducing the transparent conductive layer by using a plasma reducing gas to form a bottom gate; depositing a buffer layer and an active layer; patterning the active layer by using a second photomask to form a conductive channel; depositing a second transparent metal oxide conductive layer; patterning the second transparent metal oxide conductive layer by using a third photomask to form a first conductive layer and a second conductive layer; reducing the first conductive layer and the second conductive layer by using a plasma reducing gas to obtain a source electrode and a drain electrode; depositing a first passivation layer and a gate metal layer; and patterning the gate metal layer by using a fourth photomask to form a top gate. By the above method, the problem in the prior art that the device stability cannot be ensured while taking cost into account is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Thin-film transistors (TFTs) are an indispensable oxide device in the field of liquid crystal displays. Developing new LCDs requires more stable and superior performance. Traditional TFTs typically have either a bottom-gate or top-gate structure, both of which are single-gate structures. These structures are unstable and susceptible to environmental influences. For example, the conductive channel is easily affected by ambient light, resulting in increased leakage current and malfunctioning LCD devices.

[0003] In order to solve the problems such as poor stability of the single-gate structure, the existing improvement method is generally to use low-temperature polycrystalline silicon (LTPS) or single-crystal silicon to replace the existing amorphous structure materials. However, due to its polycrystalline structure or single-crystal structure, the device performance uniformity is poor and it is not suitable for the preparation of large-size display panels. At the same time, due to the limitations of existing material technology, the cost of using low-temperature polycrystalline silicon (LTPS) or single-crystal silicon as the active layer will be greatly increased. Summary of the Invention

[0004] The present application mainly provides an array substrate and a preparation method thereof, and a display device, so as to solve the problem in the prior art that display devices cannot ensure device stability while taking into account cost.

[0005] To solve the above technical problems, the present application adopts a technical solution: providing a method for preparing an array substrate for use in a liquid crystal display device, comprising:

[0006] providing a substrate, and depositing a first transparent metal oxide conductive layer on the substrate;

[0007] patterning the first transparent metal oxide conductive layer using a first photomask to form a common electrode and a transparent conductive layer spaced apart from each other;

[0008] reducing the transparent conductive layer using plasma reducing gas to form a bottom grid;

[0009] Depositing a buffer layer and an active layer in sequence; patterning the active layer using a second photomask to form a conductive channel;

[0010] Depositing a second transparent metal oxide conductive layer; patterning the second transparent metal oxide conductive layer using a third photomask to form a pixel electrode, a first conductive layer, and a second conductive layer;

[0011] The first conductive layer and the second conductive layer are reduced by a plasma reducing gas to form a source electrode and a drain electrode;

[0012] A first passivation layer and a gate metal layer are sequentially deposited; the gate metal layer is patterned using a fourth photomask to form a top gate;

[0013] A second passivation layer is deposited.

[0014] Among them, the step of patterning the first transparent metal oxide conductive layer using a first photomask to form a common electrode and a transparent conductive layer spaced apart from each other includes:

[0015] A first photoresist layer is deposited on the first transparent metal oxide conductive layer;

[0016] The first photoresist layer is patterned using a first photomask to form a first photoresist segment and a second photoresist segment spaced apart from each other; the thickness of the first photoresist segment is greater than the thickness of the second photoresist segment;

[0017] Using the first photoresist segment and the second photoresist segment as a barrier layer, the first transparent metal oxide conductive layer is etched to obtain the common electrode corresponding to the first photoresist segment and the transparent conductive layer corresponding to the second photoresist segment.

[0018] Among them, the step of reducing the transparent conductive layer using a plasma reducing gas to form a bottom gate includes:

[0019] The first photoresist segment and the second photoresist segment are ashed;

[0020] While thinning the first photoresist segment, the second photoresist segment is removed to expose the transparent conductive layer;

[0021] Using the first photoresist segment as a barrier layer, the transparent conductive layer is reduced by a plasma reducing gas to form the bottom gate;

[0022] The first photoresist segment is removed to expose the common electrode.

[0023] Among them, the first photoresist layer is a positive photoresist; the thickness of the first photoresist segment is 2 - 4 μm, and the thickness of the second photoresist segment is 0.5 - 1.5 μm; the first photomask includes an opaque region corresponding to the first photoresist segment, a semi-transparent region corresponding to the second photoresist segment, and a fully transparent region corresponding to the remaining positions.

[0024] Among them, the step of patterning the active layer using a second photomask to form a conductive channel includes:

[0025] A second photoresist layer is deposited on the active layer;

[0026] The second photoresist layer is patterned using a second photomask to form a third photoresist segment;

[0027] Using the third photoresist segment as a barrier layer, the active layer is etched to obtain a conductive channel corresponding to the third photoresist segment;

[0028] The third photoresist is removed to expose the conductive channel.

[0029] Wherein, the second photoresist layer is a positive photoresist; the thickness of the third photoresist segment is 0.5 - 1.5 μm; the second photomask includes an opaque region corresponding to the third photoresist segment and a fully transparent region corresponding to the remaining positions.

[0030] Wherein, the step of patterning the second transparent metal oxide conductive layer using a third photomask to form a pixel electrode, a first conductive layer, and a second conductive layer includes:

[0031] A third photoresist layer is deposited on the second transparent metal oxide conductive layer;

[0032] The third photoresist layer is patterned using a third photomask to form a fourth photoresist segment and a fifth photoresist segment; the thickness of the fourth photoresist segment is greater than the thickness of the fifth photoresist segment;

[0033] Using the fourth photoresist segment and the fifth photoresist segment as barrier layers, the second transparent metal oxide conductive layer is etched to obtain the pixel electrode corresponding to the fourth photoresist segment and the first conductive layer and the second conductive layer corresponding to the fifth photoresist segment.

[0034] Wherein, the step of reducing the first conductive layer and the second conductive layer using a plasma reducing gas to form a source electrode and a drain electrode includes:

[0035] The fourth photoresist segment and the fifth photoresist segment are ashed;

[0036] While thinning the fourth photoresist segment, the fifth photoresist segment is removed to expose the first conductive layer and the second conductive layer;

[0037] Using the fourth photoresist segment as a barrier layer, the first conductive layer and the second conductive layer are reduced using a plasma reducing gas to form the source electrode and the drain electrode;

[0038] The fourth photoresist segment is removed to expose the pixel electrode.

[0039] Among them, the third photoresist layer is a positive photoresist; the thickness of the fourth photoresist segment is 2 - 4 μm, and the thickness of the fifth photoresist segment is 0.5 - 1.5 μm; the third photomask includes an opaque region corresponding to the fourth photoresist segment, a semi-transparent region corresponding to the fifth photoresist segment, and a fully transparent region corresponding to the remaining positions.

[0040] Among them, the step of patterning the gate metal layer with a fourth photomask to form a top gate includes:

[0041] Deposit a fourth photoresist layer on the gate metal layer;

[0042] Pattern the fourth photoresist layer with a fourth photomask to form a sixth photoresist segment;

[0043] Use the sixth photoresist segment as a blocking layer to etch the gate metal layer to obtain the top gate corresponding to the sixth photoresist segment;

[0044] Remove the sixth photoresist segment to expose the top gate.

[0045] Among them, the fourth photoresist layer is a positive photoresist; the thickness of the sixth photoresist segment is 0.5 - 1.5 μm; the fourth photomask includes an opaque region corresponding to the sixth photoresist segment and a fully transparent region corresponding to the remaining positions.

[0046] Among them, the method further includes: forming vias in the first passivation layer and the buffer layer so that the top gate and the bottom gate are connected through the vias;

[0047] The material of the first transparent metal oxide conductive layer includes one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the first transparent metal oxide conductive layer is 550 - 4000 μm;

[0048] The plasma reducing gas includes any one of hydrogen and carbon monoxide;

[0049] The material of the active layer includes any one of amorphous silicon, amorphous indium gallium zinc oxide, low-temperature polycrystalline silicon, and single-crystalline silicon;

[0050] The material of the second transparent metal oxide conductive layer includes one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the second transparent metal oxide conductive layer is 400 - 1700 μm;

[0051] The material of the gate metal layer includes one or more of molybdenum, aluminum, copper, and titanium; the thickness of the gate metal layer is 3500 - 4500 μm;

[0052] The first photomask, the second photomask, the third photomask, and the fourth photomask include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask photomask, and a single-slit photomask.

[0053] To solve the above technical problems, another technical solution adopted by this application is: to provide an array substrate, which is formed by using any one of the above preparation methods.

[0054] To solve the above technical problems, another technical solution adopted by this application is: to provide a display device, including:

[0055] A display panel, including the array substrate as described above;

[0056] A backlight module, disposed on one side of the display panel, for providing backlight for the display panel.

[0057] The beneficial effect of this application is: Different from the prior art, this application discloses an array substrate, a preparation method thereof, and a display device. The preparation method includes: providing a substrate, depositing a first transparent metal oxide conductive layer on the substrate; using a first photomask to pattern the first transparent metal oxide conductive layer to form spaced-apart common electrodes and a transparent conductive layer; using a plasma reducing gas to reduce the transparent conductive layer to form a bottom gate; sequentially depositing a buffer layer and an active layer; using a second photomask to pattern the active layer to form a conductive channel; depositing a second transparent metal oxide conductive layer; using a third photomask to pattern the second transparent metal oxide conductive layer to form pixel electrodes, a first conductive layer, and a second conductive layer; using a plasma reducing gas to reduce the first conductive layer and the second conductive layer to obtain a source electrode and a drain electrode; sequentially depositing a first passivation layer and a gate metal layer; using a fourth photomask to pattern the gate metal layer to form a top gate; depositing a second passivation layer. Through the above method, the problem that the display device in the prior art cannot ensure the device stability while taking into account the cost can be effectively solved. Description of the Drawings

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where:

[0059] Figure 1 is a schematic flowchart of the preparation method of the array substrate provided by this application;

[0060] Figure 2 is Figure 1Schematic structural diagram corresponding to step S1;

[0061] Figure 3 is Figure 1 Flow schematic diagram of step S2;

[0062] Figure 4 is Figure 3 Schematic structural diagram corresponding to step S21;

[0063] Figure 5 is Figure 3 Schematic structural diagram corresponding to step S22;

[0064] Figure 6 is Figure 3 Schematic structural diagram corresponding to step S23;

[0065] Figure 7 is Figure 1 Flow schematic diagram of step S3;

[0066] Figure 8 is Figure 7 Schematic structural diagram corresponding to step S32;

[0067] Figure 9 is Figure 7 Schematic structural diagram corresponding to step S33;

[0068] Figure 10 is Figure 7 Schematic structural diagram corresponding to step S34;

[0069] Figure 11 is Figure 1 Flow schematic diagram of step S4;

[0070] Figure 12 is Figure 11 Schematic structural diagram corresponding to step S41;

[0071] Figure 13 is Figure 11 Schematic structural diagram corresponding to step S42;

[0072] Figure 14 is Figure 11 Schematic structural diagram corresponding to step S43;

[0073] Figure 15 is Figure 11 Schematic structural diagram corresponding to step S44;

[0074] Figure 16 is Figure 1 Flow schematic diagram of step S5;

[0075] Figure 17 isFigure 16 Schematic structural diagram corresponding to step S51 in

[0076] Figure 18 is Figure 16 Schematic structural diagram corresponding to step S52 in

[0077] Figure 19 is Figure 16 Schematic structural diagram corresponding to step S53 in

[0078] Figure 20 is Figure 1 Schematic flow diagram of step S6 in

[0079] Figure 21 is Figure 20 Schematic structural diagram corresponding to step S62 in

[0080] Figure 22 is Figure 20 Schematic structural diagram corresponding to step S63 in

[0081] Figure 23 is Figure 20 Schematic structural diagram corresponding to step S64 in

[0082] Figure 24 is Figure 1 Schematic flow diagram of step S7 in

[0083] Figure 25 is Figure 24 Schematic structural diagram corresponding to step S71 in

[0084] Figure 26 is Figure 24 Schematic structural diagram corresponding to step S72 in

[0085] Figure 27 is Figure 24 Schematic structural diagram corresponding to step S73 in

[0086] Figure 28 is Figure 24 Schematic structural diagram corresponding to step S74 in

[0087] Figure 29 is Figure 1 Schematic structural diagram corresponding to step S8 in

[0088] Figure 30 Schematic structural diagram of the pixel unit

[0089] Figure 31 is Figure 30 Partial cross-sectional view of the TFT in along the b-b direction

[0090] Figure 32It is a schematic structural diagram of the display device provided by this application.

[0091] Reference numerals in the drawings:

[0092] Display device 600; Backlight module 500; Display panel 400; Liquid crystal layer 300; Color filter substrate 200; Array substrate 100; Substrate 1; First transparent metal oxide conductive layer 2; Common electrode 21; Transparent conductive layer 22; Bottom gate 23; First photomask X; Light-blocking region A; Semi-transmissive region B; Fully transmissive region C; First photoresist layer 3; First photoresist segment 31; Second photoresist segment 32; Buffer layer 4; Active layer 5; Conductive channel 51; Second photomask Y; Third photomask Z; Fourth photomask W; Second photoresist layer 6; Third photoresist segment 61; Second transparent metal oxide conductive layer 7; Pixel electrode 71; First conductive layer 72; Second conductive layer 73; Source electrode 74; Drain electrode 75; Third photoresist layer 8; Fourth photoresist segment 81; Fifth photoresist segment 82; First passivation layer 9; Gate metal layer 10; Top gate 101; Fourth photoresist layer 11; Sixth photoresist segment 111; Second passivation layer 12; Via 13. Detailed implementation manners

[0093] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

[0094] The terms "first", "second", and "third" in the embodiments of this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0095] As used herein, the term "embodiment" means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0096] Refer to Figures 1 to 2 , Figure 1 which is a schematic flowchart of a method for manufacturing an array substrate provided by the present application. Figure 2 is Figure 1 a schematic structural diagram corresponding to step S1 in

[0097] See Figure 1 , the present application provides a method for manufacturing an array substrate 100 to manufacture and form an array substrate 100 for use in a liquid crystal display device. The manufacturing method includes:

[0098] S1: Provide a substrate 1, and deposit a first transparent metal oxide conductive layer 2 on the substrate 1.

[0099] Specifically, first, a substrate 1 is provided. The substrate 1 can be a glass substrate 1 or a transparent substrate 1 made of other materials. A first transparent metal oxide conductive layer 2 is deposited on one surface of the substrate 1. Among them, the material of the first transparent metal oxide conductive layer 2 can include one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide, or other materials can also be selected. Preferably, the material of the first transparent metal oxide conductive layer 2 is indium zinc oxide. The first transparent metal oxide conductive layer 2 can be a single-layer structure or a stacked layer of multiple materials. The thickness of the first transparent metal oxide conductive layer 2 is in the range of 550 - 4000 μm. Any one of LPE (Liquid Phase Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy), and MBE (Molecular Beam Epitaxy) can be used to deposit the first transparent metal oxide conductive layer 2 on the substrate 1, or methods such as inkjet printing or evaporation can also be used to form the first transparent metal oxide conductive layer 2. After step S1, the structure as shown in Figure 2 can be obtained.

[0100] Refer to Figures 3 to 6 , Figure 3 is Figure 1 a schematic flowchart of step S2 in Figure 4 is Figure 3 a schematic structural diagram corresponding to step S21 in Figure 5 is Figure 3 a schematic structural diagram corresponding to step S22 in Figure 6 is Figure 3Schematic structural diagram corresponding to step S23.

[0101] S2: Use the first photomask X to pattern the first transparent metal oxide conductive layer 2 to form spaced-apart common electrodes 21 and transparent conductive layers 22.

[0102] Specifically, the step of using the first photomask X to pattern the first transparent metal oxide conductive layer 2 to form spaced-apart common electrodes 21 and transparent conductive layers 22 in step S2 specifically includes:

[0103] S21: Deposit a first photoresist layer 3 on the first transparent metal oxide conductive layer 2.

[0104] Specifically, deposit the first photoresist layer 3 on the side of the first transparent metal oxide conductive layer 2 away from the substrate 1, wherein the first photoresist layer 3 is a positive photoresist. After step S21, the structure as shown in Figure 4 can be obtained.

[0105] S22: Use the first photomask X to pattern the first photoresist layer 3 to form spaced-apart first photoresist segments 31 and second photoresist segments 32; the thickness of the first photoresist segments 31 is greater than the thickness of the second photoresist segments 32.

[0106] Specifically, use the first photomask X to pattern the first photoresist layer 3. Among them, the first photomask X includes an opaque region A, a semi-transparent region B, and a fully transparent region C. The opaque region A and the semi-transparent region B are spaced apart from each other so that the first photoresist layer 3 forms spaced-apart first photoresist segments 31 and second photoresist segments 32. The opaque region A corresponds to the first photoresist segments 31, the semi-transparent region B corresponds to the second photoresist segments 32, and the fully transparent region C corresponds to the remaining positions except the first photoresist segments 31 and the second photoresist segments 32. The thickness of the first photoresist segments 31 is greater than the thickness of the second photoresist segments 32. Among them, the thickness of the first photoresist segments 31 is in the range of 2-4 μm, and the thickness of the second photoresist segments 32 is in the range of 0.5-1.5 μm. The first photomask X can include any one of a grayscale photomask, a halftone photomask, a phase-shift mask photomask, and a single-slit photomask. Preferably, the first photomask X is a halftone photomask. After step S22, the structure as shown in Figure 5 can be obtained.

[0107] S23: Use the first photoresist segments 31 and the second photoresist segments 32 as a barrier layer to etch the first transparent metal oxide conductive layer 2 to obtain the common electrodes 21 corresponding to the first photoresist segments 31 and the transparent conductive layers 22 corresponding to the second photoresist segments 32.

[0108] Specifically, using the first photoresist segment 31 and the second photoresist segment 32 as the barrier layers, the first transparent metal oxide conductive layer 2 is etched to obtain the spaced-apart common electrodes 21 and the transparent conductive layer 22. The common electrode 21 corresponds to the position of the first photoresist segment 31, and the transparent conductive layer 22 corresponds to the position of the second photoresist segment 32. The common electrode 21 and the transparent conductive layer 22 are arranged on the same layer. After step S23, the structure as shown in Figure 6 can be obtained.

[0109] Referring to Figures 7 to 10 , Figure 7 which Figure 1 is the schematic flow chart of step S3 in Figure 8 and Figure 7 is the schematic structural diagram corresponding to step S32 in Figure 9 and Figure 7 is the schematic structural diagram corresponding to step S33 in Figure 10 and Figure 7 is the schematic structural diagram corresponding to step S34 in

[0110] S3: The transparent conductive layer 22 is reduced by using a plasma reducing gas to form the bottom gate 23.

[0111] Specifically, the step of reducing the transparent conductive layer 22 by using a plasma reducing gas in step S3 to form the bottom gate 23 includes:

[0112] S31: Ashing the first photoresist segment 31 and the second photoresist segment 32.

[0113] S32: While thinning the first photoresist segment 31, the second photoresist segment 32 is removed to expose the transparent conductive layer 22.

[0114] Specifically, since the thickness of the first photoresist segment 31 is greater than that of the second photoresist segment 32, while thinning the first photoresist segment 31, the second photoresist segment 32 is removed until the transparent conductive layer 22 covered by the second photoresist segment 32 is exposed. After step S32, the structure as shown in Figure 8 can be obtained.

[0115] S33: Using the first photoresist segment 31 as the barrier layer, the transparent conductive layer 22 is reduced by using a plasma reducing gas to form the bottom gate 23.

[0116] Specifically, using the first photoresist segment 31 as a blocking layer, the common electrode 21 located below the first photoresist segment 31 is blocked, and a plasma reducing gas is used to reduce the exposed transparent conductive layer 22, so that through the reduction of the plasma reducing gas, the metal oxide is converted into metal to form the bottom gate 23. The plasma reducing gas may include any one of hydrogen and carbon monoxide, or may be other plasma reducing gases. Preferably, the plasma reducing gas is hydrogen. After step S33, the structure as shown in Figure 9 can be obtained.

[0117] S34: Remove the first photoresist segment 31 to expose the common electrode 21.

[0118] Specifically, remove the first photoresist segment 31 located above the common electrode 21 to expose the common electrode 21. After step S34, the structure as shown in Figure 10 can be obtained.

[0119] It can be understood that in this embodiment, by using the gas reduction technology, the transparent conductive layer 22 is reduced by the plasma reducing gas, and the bottom gate 23 can be directly formed. Both the bottom gate 23 and the common electrode 21 are formed by the first transparent metal oxide conductive layer 2. The bottom gate 23 and the common electrode 21 are arranged in the same layer. That is, by using the gas reduction technology, only one layer of the first transparent metal oxide conductive layer 2 needs to be deposited on the substrate 1 and the first photomask X is used to prepare and generate the bottom gate 23 and the common electrode 21, saving the process and effectively reducing the cost.

[0120] Refer to Figures 11 to 15 , Figure 11 which Figure 1 is the flow schematic diagram of step S4 in Figure 12 and Figure 11 is the structure schematic diagram corresponding to step S41 in Figure 13 and Figure 11 is the structure schematic diagram corresponding to step S42 in Figure 14 and Figure 11 is the structure schematic diagram corresponding to step S43 in Figure 15 and Figure 11 is the structure schematic diagram corresponding to step S44 in

[0121] S4: Deposit the buffer layer 4 and the active layer 5 in sequence; use the second photomask Y to pattern the active layer 5 to form the conductive channel 51.

[0122] Specifically, first, in the structure obtained in step S3 Figure 10On the structure shown, a buffer layer 4 and an active layer 5 are sequentially deposited such that the buffer layer 4 and the active layer 5 cover the common electrode 21, the bottom gate 23, and the substrate 1. Among them, the material of the buffer layer 4 can be an insulating material with a high light transmittance. The material of the active layer 5 can be selected from, but not limited to, amorphous silicon (a-Si), amorphous indium gallium zinc oxide (IGZO), low-temperature polycrystalline silicon (LTPS), single-crystalline silicon, etc. Preferably, the material of the active layer 5 is amorphous silicon, and the thickness of the active layer 5 is 400 - 1700 μm. Among them, any one of LPE (liquid phase deposition), MOCVD (metal-organic chemical vapor deposition), HVPE (hydride vapor deposition), and MBE (molecular beam epitaxy) can be used to deposit the buffer layer 4 and the active layer 5, or methods such as inkjet printing or evaporation can also be used to form the buffer layer 4 and the active layer 5. It can be understood that depositing the buffer layer 4 can avoid the problem of short circuit caused by the mutual contact between different conductive layers of the prepared array substrate 100, and improve the performance of the array substrate 100.

[0123] The step of patterning the active layer 5 with the second photomask Y to form the conductive channel 51 in step S4 specifically includes:

[0124] S41: Deposit a second photoresist layer 6 on the active layer 5.

[0125] Specifically, deposit the second photoresist layer 6 on the side of the active layer 5 away from the substrate 1. The second photoresist layer 6 is a positive photoresist. Among them, after step S41, the structure as shown in Figure 12 can be obtained.

[0126] S42: Pattern the second photoresist layer 6 with the second photomask Y to form a third photoresist segment 61.

[0127] Specifically, pattern the second photoresist layer 6 with the second photomask Y. Among them, the second photomask YY only includes an opaque region A and a fully transparent region C, so that the second photoresist layer 6 forms a third photoresist segment 61. Among them, the opaque region A corresponds to the third photoresist segment 61, and the fully transparent region C corresponds to the remaining positions except the third photoresist segment 61. The thickness of the third photoresist segment 61 is in the range of 0.5 - 1.5 μm. The second photomask Y can include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask photomask, and a single-slit photomask. Preferably, the second photomask Y is a halftone photomask. After step S42, the structure as shown in Figure 13 can be obtained.

[0128] S43: Use the third photoresist segment 61 as a blocking layer to etch the active layer 5 to obtain the conductive channel 51 corresponding to the third photoresist segment 61.

[0129] Specifically, using the third photoresist segment 61 as a blocking layer, the active layer 5 is etched to obtain a conductive channel 51, and the conductive channel 51 is located below the position corresponding to the third photoresist segment 61. After step S43, the structure as shown in Figure 14 can be obtained.

[0130] S44: Remove the third photoresist to expose the conductive channel 51.

[0131] Specifically, the third photoresist segment 61 is removed to expose the conductive channel 51 located below the third photoresist segment 61. After step S44, the structure as shown in Figure 15 can be obtained.

[0132] Refer to Figures 16 to 19 , Figure 16 which is Figure 1 a schematic flow chart of step S5 in Figure 17 and Figure 16 is a schematic structural diagram corresponding to step S51 in Figure 18 and Figure 16 is a schematic structural diagram corresponding to step S52 in Figure 19 and Figure 16 is a schematic structural diagram corresponding to step S53 in

[0133] S5: Deposit a second transparent metal oxide conductive layer 7; use a third photomask Z to pattern the second transparent metal oxide conductive layer 7 to form a pixel electrode 71, a first conductive layer 72, and a second conductive layer 73.

[0134] Specifically, on the structure as shown in Figure 15 , a second transparent metal oxide conductive layer 7 is deposited, such that the second transparent metal oxide conductive layer 7 covers the buffer layer 4 and the conductive channel 51. Among them, the material of the second transparent metal oxide conductive layer 7 includes one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; preferably, the material of the second transparent metal oxide conductive layer 7 is indium zinc oxide, and the second transparent metal oxide conductive layer 7 can be a single-layer structure or a stacked layer of multiple materials. The thickness of the second transparent metal oxide conductive layer 7 is 400 - 1700 μm.

[0135] The step of using the third photomask Z to pattern the second transparent metal oxide conductive layer 7 to form a pixel electrode 71, a first conductive layer 72, and a second conductive layer 73 described in step S5 specifically includes:

[0136] S51: Deposit a third photoresist layer 8 on the second transparent metal oxide conductive layer 7.

[0137] Specifically, a third photoresist layer 8 is deposited on the side of the second transparent metal oxide conductive layer 7 away from the substrate 1. The third photoresist layer 8 is a positive photoresist. After step S51, the structure shown in Figure 17 can be obtained.

[0138] S52: The third photoresist layer 8 is patterned using a third photomask Z to form a fourth photoresist segment 81 and a fifth photoresist segment 82; the thickness of the fourth photoresist segment 81 is greater than the thickness of the fifth photoresist segment 82.

[0139] Specifically, the third photoresist layer 8 is patterned using a third photomask Z. The third photomask Z includes an opaque region A, a semi-transparent region B, and a fully transparent region C. The opaque region A is adjacent to the semi-transparent region B, so that the third photoresist layer 8 forms a fourth photoresist segment 81 and a fifth photoresist segment 82, and the fourth photoresist segment 81 and the fifth photoresist segment 82 are arranged. The opaque region A corresponds to the fourth photoresist segment 81, the semi-transparent region B corresponds to the fifth photoresist segment 82, and the fully transparent region C corresponds to the remaining positions except the fourth photoresist segment 81 and the fifth photoresist segment 82. The thickness of the fourth photoresist segment 81 is greater than the thickness of the fifth photoresist segment 82. The thickness of the fourth photoresist segment 81 is in the range of 2 - 4 μm, and the thickness of the fifth photoresist segment 82 is in the range of 0.5 - 1.5 μm. The third photomask Z can include any one of a grayscale photomask, a halftone photomask, a phase-shifting mask photomask, and a single-slit photomask. Preferably, the third photomask Z is a halftone photomask. After step S52, the structure shown in Figure 18 can be obtained.

[0140] S53: Using the fourth photoresist segment 81 and the fifth photoresist segment 82 as a barrier layer, the second transparent metal oxide conductive layer 7 is etched to obtain a pixel electrode 71 corresponding to the fourth photoresist segment 81, and a first conductive layer 72 and a second conductive layer 73 corresponding to the fifth photoresist segment 82.

[0141] Specifically, using the fourth photoresist segment 81 and the fifth photoresist segment 82 as a barrier layer, the second transparent metal oxide conductive layer 7 is etched to obtain a pixel electrode 71, a first conductive layer 72, and a second conductive layer 73. The pixel electrode 71 is located below the position corresponding to the fourth photoresist segment 81, and the first conductive layer 72 and the second conductive layer 73 are located below the position corresponding to the fifth photoresist segment 82. The first conductive layer 72 and the second conductive layer 73 are spaced apart and are respectively located on both sides of the conductive channel 51. The first conductive layer 72 is adjacent to the pixel electrode 71. After step S53, the structure shown in Figure 19 can be obtained.

[0142] Refer to Figures 20 to 23 , Figure 20 which Figure 1 is the flowchart of step S6 in Figure 21 which Figure 20Schematic diagram corresponding to step S62 Figure 22 is Figure 20 Schematic diagram corresponding to step S63 Figure 23 is Figure 20 Schematic diagram corresponding to step S64

[0143] S6: Use a plasma reducing gas to reduce the first conductive layer 72 and the second conductive layer 73 to form a source electrode 74 and a drain electrode 75

[0144] Specifically, the step of using a plasma reducing gas to reduce the first conductive layer 72 and the second conductive layer 73 to form a source electrode 74 and a drain electrode 75 described in step S6 includes

[0145] S61: Asher process the fourth photoresist segment 81 and the fifth photoresist segment 82

[0146] S62: Thin the fourth photoresist segment 81 while removing the fifth photoresist segment 82 to expose the first conductive layer 72 and the second conductive layer 73

[0147] Specifically, since the thickness of the fourth photoresist segment 81 is greater than the thickness of the fifth photoresist segment 82, thin the fourth photoresist segment 81 while removing the fifth photoresist segment 82 until the first conductive layer 72 and the second conductive layer 73 covered by the fifth photoresist segment 82 are exposed. After step S62, the structure as shown in Figure 21 can be obtained

[0148] S63: Use the fourth photoresist segment 81 as a barrier layer and use a plasma reducing gas to reduce the first conductive layer 72 and the second conductive layer 73 to form a source electrode 74 and a drain electrode 75

[0149] Specifically, use the fourth photoresist segment 81 as a barrier layer to block the pixel electrode 71 located below the fourth photoresist segment 81, and use a plasma reducing gas to reduce the exposed first conductive layer 72 and the second conductive layer 73, so that the first conductive layer 72 and the second conductive layer 73 are converted from metal oxides to metals under the reduction of the plasma reducing gas, so that the first conductive layer 72 forms a source electrode 74 and the second conductive layer 73 forms a drain electrode 75. The source electrode 74 and the drain electrode 75 are arranged at intervals and are respectively located on both sides of the conductive channel 51, and the source electrode 74 is adjacent to the pixel electrode 71. The plasma reducing gas can include any one of hydrogen and carbon monoxide, or other plasma reducing gases. Preferably, the plasma reducing gas is hydrogen. The structure as shown in Figure 22 can be obtained by step S63

[0150] S64: Remove the fourth photoresist segment 81 to expose the pixel electrode 71

[0151] Specifically, the fourth photoresist layer 81 is removed, so that the pixel electrode 71 covered by the fourth photoresist layer 81 is exposed. After step S64, the structure as shown in Figure 23 can be obtained.

[0152] It can be understood that in this embodiment, the gas reduction technology is adopted, and the first conductive layer 72 and the second conductive layer 73 are reduced by the plasma reducing gas to form the source electrode 74 and the drain electrode 75, without separately depositing the source electrode 74 metal layer and the drain electrode 75 metal layer to prepare the source electrode 74 and the drain electrode 75, saving the process and cost.

[0153] Referring to Figures 24 to 28 , Figure 24 which is Figure 1 the schematic flow chart of step S7 in Figure 25 which is Figure 24 the schematic structural diagram corresponding to step S71 in Figure 26 which is Figure 24 the schematic structural diagram corresponding to step S72 in Figure 27 which is Figure 24 the schematic structural diagram corresponding to step S73 in Figure 28 which is Figure 24 the schematic structural diagram corresponding to step S74 in

[0154] S7: Deposit the first passivation layer 9 and the gate metal layer 10 in sequence; use the fourth photomask W to pattern the gate metal layer 10 to form the top gate 101.

[0155] Specifically, on the structure shown in Figure 23 obtained in step S6, the first passivation layer 9 and the gate metal layer 10 are deposited in sequence on the side of the pixel electrode 71, the source electrode 74 and the drain electrode 75 away from the substrate 1, so that the first passivation layer 9 and the gate metal layer 10 cover the pixel electrode 71, the source electrode 74, the conductive channel 51 and the drain electrode 75. Among them, any one of liquid phase deposition, metal organic chemical vapor deposition, hydride vapor deposition and molecular beam deposition can be used to deposit the first passivation layer 9 and the gate metal layer 10, or methods such as inkjet printing or evaporation can also be used to form the first passivation layer 9 and the gate metal layer 10. Among them, the material of the first passivation layer 9 can include any one of silicon oxide and silicon nitride, or can include both silicon oxide and silicon nitride at the same time. Depositing the first passivation layer 9 can avoid the problem of device short circuit caused by the mutual contact between different conductive layers of the array substrate 100. The material of the gate metal layer 10 can include one or more of molybdenum, aluminum, copper and titanium, and the thickness of the gate metal layer is in the range of 3500-4500 μm.

[0156] The step of patterning the gate metal layer 10 with the fourth photomask W to form the top gate 101 described in step S7 includes:

[0157] S71: Deposit a fourth photoresist layer 11 on the gate metal layer 10.

[0158] Specifically, deposit the fourth photoresist layer 11 on the side of the gate metal layer 10 away from the substrate 1, such that the fourth photoresist layer 11 covers the gate metal layer 10. The fourth photoresist layer 11 is a positive photoresist. After step S71, the structure as shown in Figure 25 can be obtained.

[0159] S72: Pattern the fourth photoresist layer 11 using a fourth photomask W to form a sixth photoresist segment 111.

[0160] Specifically, pattern the fourth photoresist layer 11 using the fourth photomask W. The fourth photomask W only includes an opaque region A and a fully transparent region C, such that the fourth photoresist layer 11 forms the sixth photoresist segment 111. The sixth photoresist segment 111 corresponds to the position of the opaque region A, and the fully transparent region C corresponds to the remaining positions other than the sixth photoresist segment 111. The thickness of the sixth photoresist segment 111 is in the range of 0.5 - 1.5 μm. The fourth photomask W can include any one of a grayscale photomask, a halftone photomask, a phase-shift mask photomask, and a single-slit photomask. After step S72, the structure as shown in Figure can be obtained.

[0161] S73: Use the sixth photoresist segment 111 as a mask to etch the gate metal layer 10 to obtain a top gate 101 corresponding to the sixth photoresist segment 111.

[0162] Specifically, use the sixth photoresist segment 111 as a mask to etch the gate metal layer 10, and etch away the remaining positions of the gate metal layer 10 except those covered by the sixth photoresist segment 111 to obtain the top gate 101 below the sixth photoresist segment 111. After step S73, the structure as shown in ​ can be obtained.

[0163] S74: Remove the sixth photoresist segment 111 to expose the top gate 101.

[0164] Specifically, remove the sixth photoresist segment 111 on the side of the top gate 101 away from the substrate 1 to expose the top gate 101. After step S74, the structure as shown in ​ can be obtained.

[0165] Refer to ​ , ​ which ​ is the schematic structural diagram corresponding to step S8 in

[0166] S8: Deposit a second passivation layer 12.

[0167] Specifically, in the structure obtained in step S74 ​In the structure shown, a second passivation layer 12 is deposited on the side of the top gate 101 away from the substrate 1. The material of the second passivation layer 12 can be the same as that of the first passivation layer 9. Depositing the second passivation layer 12 can further prevent the problem of short circuit caused by the mutual contact between different conductive layers of the array substrate 100. After step S8, the structure as shown in ​ can be obtained. ​ The structure shown is also the structure finally formed by the preparation method of the array substrate 100 provided in this application.

[0168] Referring to ​ , ​ which is a schematic structural diagram of a pixel unit. ​ It is ​ a partial cross-sectional view of the TFT in

[0169] in the direction of b-b. ​ and ​ as shown, a pixel unit includes a pixel electrode 71 and a corresponding TFT. In this embodiment, the TFT is a double-gate TFT. ​ The structure shown is ​ a cross-sectional view of the TFT in the pixel unit of

[0170] in the direction of a-a.

[0171] Further, the preparation method of the array substrate 100 provided in this embodiment further includes:

[0172] A via 13 is provided in the first passivation layer 9 and the buffer layer 4 to connect the top gate 101 and the bottom gate 23 through the via 13. ​ Specifically, in this embodiment, as shown in

[0173] The array substrate 100 prepared by the preparation method of the array substrate 100 provided in this embodiment has a double-gate structure for the TFT, ensuring the stability of the device, having more excellent electrical properties, enabling the device to be made smaller while keeping the length of the conductive channel 51 unchanged, which is beneficial for manufacturing high-resolution products. The bottom gate 23 and the common electrode 21 are arranged in the same layer and are both formed by patterning the first transparent metal oxide conductive layer 2 with the first photomask X. The pixel electrode 71, the source electrode 74, and the drain electrode 75 are all formed by patterning the second transparent metal oxide conductive layer 7 with the second photomask Y. At the same time, a gas reduction process is adopted, and the metal oxide is reduced and converted into metal by a plasma reducing gas to prepare and form the bottom gate 23, as well as the source electrode 74 and the drain electrode 75, simplifying the process and reducing the process cost, and solving the problem in the prior art that it is impossible to ensure the device stability while taking into account the preparation cost.

[0174] Refer to ​ , ​ which is a schematic structural diagram of the display device provided in the present application.

[0175] The present application also provides a display device 600, which includes a display panel 400 and a backlight module 500. The backlight module 500 is arranged on one side of the display panel 400 and is used to provide backlight for the display panel 400. In one embodiment, the display panel 400 can be a liquid crystal display panel 400. As ​ shown, the display panel 400 includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The color filter substrate 200 is disposed opposite to the array substrate 100, and the liquid crystal layer 300 is clamped between the array substrate 100 and the color filter substrate 200.

[0176] Among them, the array substrate 100 is the array substrate 100 prepared by the preparation method of the above-mentioned array substrate 100, and its structure is the same as that ​ shown and will not be described in detail. In the above structure, the TFT of the array substrate 100 has a double-gate structure, ensuring the stability of the device, having more excellent electrical properties, including stronger current driving ability, larger carrier mobility, and steeper subthreshold slope. At the same time, the double-gate device can effectively suppress the short-channel effect, enabling the TFT device to be smaller while keeping the length of the conductive channel 51 unchanged, which is beneficial for improving the resolution of the display device 600. At the same time, the process is simplified, the process cost is reduced, and the problem in the prior art that it is impossible to ensure the device stability while taking into account the preparation cost is effectively solved, improving the display performance of the display device 600.

[0177] The above are only embodiments of the present application, and do not thereby limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall equally be included within the patent protection scope of the present application.

Claims

1. A method for manufacturing an array substrate, which is used to manufacture an array substrate applied to a liquid crystal display device, characterized in that Including: Providing a substrate, and depositing a first transparent metal oxide conductive layer on the substrate; wherein, the first transparent metal oxide conductive layer is a single-layer structure; Using a first photomask to pattern the first transparent metal oxide conductive layer to form spaced-apart common electrodes and a transparent conductive layer; the common electrodes and the transparent conductive layer are arranged on the same layer and are both single-layer structures; Reducing the transparent conductive layer with a plasma reducing gas to form a bottom gate; wherein, the bottom gate is a single-layer structure, and the material of the bottom gate is metal; Depositing a buffer layer and an active layer in sequence; using a second photomask to pattern the active layer to form a conductive channel; Depositing a second transparent metal oxide conductive layer; using a third photomask to pattern the second transparent metal oxide conductive layer to form a pixel electrode, a first conductive layer, and a second conductive layer; Reducing the first conductive layer and the second conductive layer with a plasma reducing gas to form a source electrode and a drain electrode; Depositing a first passivation layer and a gate metal layer in sequence; using a fourth photomask to pattern the gate metal layer to form a top gate; Depositing a second passivation layer.

2. The preparation method according to claim 1, wherein The step of using the first photomask to pattern the first transparent metal oxide conductive layer to form spaced-apart common electrodes and a transparent conductive layer includes: Depositing a first photoresist layer on the first transparent metal oxide conductive layer; Using the first photomask to pattern the first photoresist layer to form spaced-apart first photoresist segments and second photoresist segments; the thickness of the first photoresist segments is greater than the thickness of the second photoresist segments; Using the first photoresist segments and the second photoresist segments as barrier layers to etch the first transparent metal oxide conductive layer to obtain the common electrodes corresponding to the first photoresist segments and the transparent conductive layer corresponding to the second photoresist segments.

3. The preparation method according to claim 2, characterized in that, The step of reducing the transparent conductive layer with a plasma reducing gas to form a bottom gate includes: Ashing the first photoresist segments and the second photoresist segments; Thinning the first photoresist segments while removing the second photoresist segments to expose the transparent conductive layer; Using the first photoresist segments as barrier layers and reducing the transparent conductive layer with a plasma reducing gas to form the bottom gate; Removing the first photoresist segments to expose the common electrodes.

4. The preparation method according to claim 1, characterized in that The step of using the second photomask to pattern the active layer to form a conductive channel includes: Depositing a second photoresist layer on the active layer; Using the second photomask to pattern the second photoresist layer to form a third photoresist segment; Using the third photoresist segment as a barrier layer to etch the active layer to obtain a conductive channel corresponding to the third photoresist segment; Removing the third photoresist to expose the conductive channel.

5. The preparation method according to claim 1, characterized in that, The step of using the third photomask to pattern the second transparent metal oxide conductive layer to form a pixel electrode, a first conductive layer, and a second conductive layer includes: Depositing a third photoresist layer on the second transparent metal oxide conductive layer; Pattern the third photoresist layer with a third photomask to form a fourth photoresist segment and a fifth photoresist segment; the thickness of the fourth photoresist segment is greater than that of the fifth photoresist segment; Using the fourth photoresist segment and the fifth photoresist segment as a barrier layer, etch the second transparent metal oxide conductive layer to obtain the pixel electrode corresponding to the fourth photoresist segment and the first conductive layer and the second conductive layer corresponding to the fifth photoresist segment.

6. The preparation method according to claim 5, wherein, The step of reducing the first conductive layer and the second conductive layer with a plasma reducing gas to form source and drain electrodes includes: Ashing the fourth photoresist segment and the fifth photoresist segment; Thinning the fourth photoresist segment while removing the fifth photoresist segment to expose the first conductive layer and the second conductive layer; Using the fourth photoresist segment as a barrier layer, reducing the first conductive layer and the second conductive layer with a plasma reducing gas to form the source and drain electrodes; Removing the fourth photoresist segment to expose the pixel electrode.

7. The preparation method according to claim 1, wherein The step of patterning the gate metal layer with a fourth photomask to form a top gate includes: Depositing a fourth photoresist layer on the gate metal layer; Patterning the fourth photoresist layer with a fourth photomask to form a sixth photoresist segment; Using the sixth photoresist segment as a barrier layer, etching the gate metal layer to obtain the top gate corresponding to the sixth photoresist segment; Removing the sixth photoresist segment to expose the top gate.

8. The preparation method according to claim 1, characterized in that, The method further includes: forming vias in the first passivation layer and the buffer layer to connect the top gate and the bottom gate through the vias; The material of the first transparent metal oxide conductive layer includes one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the first transparent metal oxide conductive layer is 550 - 4000 μm; The plasma reducing gas includes any one of hydrogen and carbon monoxide; The material of the active layer includes any one of amorphous silicon, amorphous indium gallium zinc oxide, low-temperature polycrystalline silicon, and single-crystalline silicon; The material of the second transparent metal oxide conductive layer includes one or more of indium tin oxide, indium zinc oxide, and aluminum tin oxide; the thickness of the second transparent metal oxide conductive layer is 400 - 1700 μm; The material of the gate metal layer includes one or more of molybdenum, aluminum, copper, and titanium; the thickness of the gate metal layer is 3500 - 4500 μm; The first photomask, the second photomask, the third photomask, and the fourth photomask include any one of a grayscale photomask, a halftone photomask, a phase-shift mask photomask, and a single-slit photomask.

9. An array substrate, characterized in that, The array substrate is prepared by the preparation method described in any one of claims 1 - 8.

10. A display device, characterized in that, Including: A display panel including the array substrate described in claim 9; A backlight module disposed on one side of the display panel for providing backlight to the display panel.

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