LDO circuit, LDO and SOC system

Abstract

Embodiments of the present disclosure provide an LDO circuit, an LDO, and an SOC system, which are applied to the technical field of linear voltage regulator circuits. The LDO circuit includes amplifier A BG , amplifier A ref , amplifier A x , and an LDO main structure; the non-inverting input terminal of amplifier A BG is connected to a reference current, and the inverting input terminal is grounded through resistor R BG2 and connected to the output terminal through resistor R BG1 ; the non-inverting input terminal of amplifier A ref is connected to the output terminal of amplifier A BG , and the inverting input terminal is grounded through resistor R ref2 and connected to the output terminal through resistor R ref1 ; the non-inverting input terminal of amplifier A x is connected to the output terminal of amplifier A BG , and the inverting input terminal is grounded through resistor R x2 and connected to the output terminal through resistor R x1 ; the V ref port of the LDO main structure is connected to the output terminal of amplifier A ref ; the V x port is connected to the output terminal of amplifier A x ; the output terminal is connected to the circuit output terminal. In this way, the PSR parameter can be further reduced, thereby reducing the influence of external noise on the Multi core VCO module in the frequency synthesizer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, in particular to the technical field of linear regulator circuits, and specifically to an LDO circuit, an LDO and a SOC system. Background Art

[0002] With the continuous development of System on Chip (Soc), the requirements for Low Dropout Regulator (LDO) are becoming more and more stringent. For example, the application of multi-core voltage-controlled oscillator (Multi core VCO) in phase-locked loop requires LDO to support large load current while ensuring that the loop phase margin is greater than 45° and has a high gain from power supply to output, that is, power supply rejection ratio (PSR), to prevent noise from coupling from the LDO input to the multi core VCO.

[0003] LDO has strict requirements on the loop phase margin and PSR within the target load current range. However, due to the development of off-chip capacitors, the equivalent series resistance (ESR) of many off-chip capacitors is only tens of milliohms in the range of 0-1M, so it is impossible to achieve the purpose of establishing a zero point in the LDO loop. As a result, it is basically impossible for the current LDO circuit to ensure that the phase margin is greater than 45° within the target load current range, which ultimately leads to LDO output voltage oscillation.

[0004] There are three reasons why an LDO cannot work properly: (1) The PSR index of the LDO is too high, causing the noise at the LDO input to couple to the LDO output; (2) The ESR zero point of the LDO cannot be established in the loop, causing the loop phase margin to be less than 45°, resulting in LDO output voltage oscillation; (3) The LDO load current is too large, causing the LDO output to be abnormal.

[0005] Based on the above reasons that cause LDO to not work properly, it can be seen that the current LDO circuit has the following main problems: (1) It is necessary to sacrifice power consumption and increase the error amplifier gain to reduce PSR. (2) External capacitors and ESR resistors are required to establish a zero-point compensation loop. When the ESR resistor is too small, the loop will oscillate. (3) It cannot meet the requirements of larger load currents. Excessive load currents will cause traditional LDOs to not work properly. Summary of the invention

[0006] The present disclosure provides an LDO circuit, an LDO and a SOC system.

[0007] According to a first aspect of the present disclosure, a LDO circuit is provided. The LDO circuit comprises: an amplifier A BG , Amplifier A ref , Amplifier A x And the LDO main structure;

[0008] The amplifier A BG Used to generate voltage V according to reference current BG Provided to the amplifier A ref and the amplifier A x ;

[0009] The amplifier A ref To generate voltage V ref Provided to the LDO main structure;

[0010] The amplifier A x To generate voltage V x Provided to the LDO main structure;

[0011] The LDO main structure is used to ref and V x Generate output voltage;

[0012] The amplifier A BG The non-inverting input terminal is connected to the reference current, and the inverting input terminal is connected to the reference current through the resistor R BG2 Ground and through resistor R BG1 Connect to the output terminal;

[0013] The amplifier A ref The non-inverting input of the amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R ref2 Ground and through resistor R ref1 Connect to the output terminal;

[0014] The amplifier A x The non-inverting input of the amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R x2 Ground and through resistor R x1 Connect to the output terminal;

[0015] The LDO main structure V ref port with the amplifier A ref The output terminal is connected to V x port with the amplifier A x The output end is connected to the output end of the circuit.

[0016] According to the above aspects and any possible implementation, an implementation is further provided, wherein the LDO main structure includes an error amplifier A EA , transistor M L , transistor M Y , transistor M Q , transistor M X , transistor M P , feedback resistor R S , external capacitor C1, equivalent resistor R esr And the load resistance R load ;

[0017] The error amplifier A EA The non-inverting input of the amplifier A ref The output terminal is connected to the inverting input terminal through the feedback resistor R S Connect the positive power supply terminal to the output terminal of the circuit and the amplifier A x The output terminal is connected, and the negative power supply terminal is grounded;

[0018] The transistor M L The gate of the error amplifier A EA The output terminal is connected, the source is grounded, and the drain is connected to the transistor M Y The source of the transistor M Y The drain is connected to the power supply voltage through the resistor R5, and the gate is connected to the load resistor R load ground; the transistor M Q The source of the transistor M is connected to the power supply voltage through the resistor R4, the drain is grounded through the resistor R3, and the gate is grounded; X The gate is grounded through resistor R3, the source is connected to the power supply voltage, the drain is connected to the circuit output terminal, and the substrate is connected to the transistor M P The gate of the transistor M P The source is connected to the power supply voltage, the drain is connected to the circuit output and through the load resistor R load One end of the off-chip capacitor C1 is grounded, and the other end is connected to the ground through the equivalent resistor R esr Connect to the circuit output terminal.

[0019] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the LDO main structure further includes a zero point compensation structure;

[0020] The zero compensation structure is used to generate a feedback voltage V Feedback supplied to the error amplifier A EA ;

[0021] The power input port of the zero compensation structure is connected to the power supply voltage, VFeedback port and the error amplifier A EA Connect and pass the feedback resistor R S Connect to the circuit output terminal.

[0022] According to the above aspects and any possible implementation, an implementation is further provided, wherein the zero compensation structure includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, an amplifier A esr , fast start resistor R on And RC filter structure;

[0023] The source of the transistor M3 is connected to the power supply voltage, the gate is grounded through the resistor R3, the substrate is connected to the gate of the transistor M4, and the drain is connected to the amplifier A esr The in-phase input terminal of the transistor M1 is connected to the drain of the transistor M1; the source of the transistor M4 is connected to the power supply voltage, and the substrate is connected to the transistor M X The gate is connected to the drain of the transistor M2 and connected to the fast start resistor R on With the amplifier A esr The inverting input terminal of the amplifier A is connected; esr The output end is connected to the gate of the transistor M1 and is connected to the gate of the transistor M2 through the RC filter structure; the source of the transistor M1 is grounded through the resistor R1, and the source of the transistor M2 is grounded through the resistor R2.

[0024] According to the above aspects and any possible implementation manner, there is further provided an implementation manner, wherein the LDO main structure further includes an overcurrent protection structure;

[0025] The overcurrent protection structure is used to generate an overcurrent protection voltage V ctrl Provided to the transistor M Y ;

[0026] The input ports of the overcurrent protection structure are respectively connected to the transistor M X and the transistor M P The drain terminal is connected to the voltage output port, and the voltage output port is connected to the circuit output terminal. ctrl port and the transistor M Y The gate connection.

[0027] According to the above aspects and any possible implementation, an implementation is further provided, wherein the overcurrent protection structure includes a transistor P1, a transistor P2, a transistor N1, a transistor N2, a transistor N3, and an off-chip capacitor C2;

[0028] The source of transistor P1 is connected to the b1 With the MX The drain of the transistor is connected to the gate of the transistor P2, and the drain is connected to the drain of the transistor N1; the source of the transistor P2 is connected to the source of the transistor P2 through the resistor R b2 With the transistor M P The drain of the transistor N1 is connected to the drain of the transistor N2, and the gate and the drain are connected to each other; the source of the transistor N1 is grounded, the gate is connected to the gate of the transistor N2, and the drain and the gate are connected to each other; the source of the transistor N2 is grounded, and the gate is connected to the gate of the transistor N3; the source of the transistor N3 is grounded, and the drain is connected to the gate of the transistor M2; one end of the off-chip capacitor C1 is connected to the gate of the transistor M2 respectively. P The drain is connected to the output end of the circuit and the other end is grounded.

[0029] According to the above aspects and any possible implementation, an implementation is further provided, wherein the amplifier A BG , the amplifier A ref and the amplifier A x It is a non-inverting amplifier.

[0030] According to the above aspects and any possible implementation, a further implementation is provided, wherein the resistor R ref2 It is an adjustable resistor.

[0031] According to a second aspect of the present disclosure, a LDO is provided, comprising the LDO circuit as described above.

[0032] According to a third aspect of the present disclosure, a SOC system is provided, comprising the LDO circuit as described above.

[0033] The embodiment of the present application provides an LDO circuit, an LDO and a SOC system, the LDO circuit includes an amplifier A BG , Amplifier A ref , Amplifier A x And the LDO main structure, amplifier A BG The non-inverting input terminal is connected to the reference current, and the inverting input terminal is connected to the reference current through the resistor R BG2 Ground and through resistor R BG1 Connect to the output terminal; amplifier A ref The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R ref2 Ground and through resistor R ref1 Connect to the output terminal; amplifier A x The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R x2 Ground and through resistor Rx1 Connected to the output terminal; V of the LDO main structure ref Port and Amplifier A ref The output terminal is connected to V x Port and Amplifier A x The output end is connected to the output end of the circuit; based on this, the amplifier A BG Generate voltage V according to reference current BG Provided to amplifier A ref and amplifier A x , amplifier A ref Generate reference voltage V ref Provided to the LDO main structure, amplifier A x Generates a stable voltage V x Provided to the LDO main structure, providing power supply voltage for the error amplifier in the LDO main structure, increasing the gain of the error amplifier to reduce the PSR index, so that the LDO main structure can be adjusted according to the voltage V ref and V x An output voltage is generated to further reduce the PSR parameter, thereby reducing the influence of external noise on the Multi core VCO module in the frequency synthesizer.

[0034] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:

[0036] Figure 1 A schematic diagram of an LDO circuit according to an embodiment of the present disclosure is shown;

[0037] Figure 2 A schematic diagram of an LDO main structure according to an embodiment of the present disclosure is shown;

[0038] Figure 3 A schematic diagram showing a zero compensation structure according to an embodiment of the present disclosure is shown;

[0039] Figure 4 A schematic diagram of an overcurrent protection structure according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0042] In the present disclosure, the amplifier A BG Generate voltage V according to reference current BG Provided to amplifier A ref and amplifier A x , amplifier A ref Generate reference voltage V ref Provided to the LDO main structure, amplifier A x Generates a stable voltage V x Provided to the LDO main structure, providing power supply voltage for the error amplifier in the LDO main structure, increasing the gain of the error amplifier to reduce the PSR index, so that the LDO main structure can be adjusted according to the voltage V ref and V x Generate an output voltage to further reduce the PSR parameter, thereby reducing the impact of external noise on the VCO module in the frequency synthesizer.

[0043] Figure 1 FIG. 1 shows a schematic diagram of an LDO circuit according to an embodiment of the present disclosure. Figure 1 As shown, the LDO circuit includes an amplifier A BG , Amplifier A ref , Amplifier A x And the LDO main structure LDO_MAIN.

[0044] Amplifier A BG The non-inverting input terminal and the reference current BG in Connect the inverting input through the resistor R BG2 Ground and through resistor R BG1 Connect to the output terminal; amplifier A ref The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R ref2 Ground and through resistor R ref1Connect to the output terminal; amplifier A x The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R x2 Ground and through resistor R x1 Connected to the output terminal; V of LDO main structure LDO_MAIN ref Port and Amplifier A ref The output terminal is connected to V x Port and Amplifier A x The output end is connected to the output end of the circuit.

[0045] Among them, amplifier A BG Used to adjust the reference current BG in Generated voltage V BG Provided to amplifier A ref and amplifier A x ; Amplifier A ref To generate voltage V ref Provided to the LDO main structure LDO_MAIN, that is, the last stage loop LDO_MAIN module; amplifier A x To generate voltage V x Provided to the LDO main structure LDO_MAIN; the LDO main structure is used to ref and V x Generates an output voltage.

[0046] In some embodiments, the reference current may be an output current of a bandgap voltage reference (Bandgap) in the chip. BG Convert the output current of Bandgap to amplifier A BG output voltage, and also serves to isolate noise for the subsequent stage.

[0047] In some embodiments, the amplifier A ref The generated voltage V ref It can be the reference voltage of the LDO main structure LDO_MAIN.

[0048] In some embodiments, the amplifier A x Generates a stable voltage V x , is the error amplifier A in the next-level LDO main structure LDO_MAIN EA Provides a supply voltage that allows the LDO to produce lower PSR parameters.

[0049] In some embodiments, R BG1 , R BG2 , R ref1 , Rref2 , R x1 and R x2 It can be a voltage divider fixed resistor.

[0050] In some embodiments, the amplifier A BG , Amplifier A ref and amplifier A x The positive power supply terminals are respectively connected to a power supply voltage, and the negative power supply terminals are respectively grounded.

[0051] In some embodiments, V in Amplifier A BG , Amplifier A ref and amplifier A x The power supply voltage can also be set to V in It is the input voltage of the LDO main structure LDO_MAIN.

[0052] According to the embodiments of the present disclosure, the following technical effects are achieved:

[0053] The LDO circuit includes an amplifier A BG , Amplifier A ref , Amplifier A x And the LDO main structure, amplifier A BG The non-inverting input terminal is connected to the reference current, and the inverting input terminal is connected to the reference current through the resistor R BG2 Ground and through resistor R BG1 Connect to the output terminal; amplifier A ref The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R ref2 Ground and through resistor R ref1 Connect to the output terminal; amplifier A x The non-inverting input of amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R x2 Ground and through resistor R x1 Connected to the output terminal; V of the LDO main structure ref Port and Amplifier A ref The output terminal is connected to V x Port and Amplifier A x The output end is connected to the output end of the circuit; based on this, the amplifier A BG Generate voltage V according to reference current BG Provided to amplifier A ref and amplifier A x , amplifier A ref Generate reference voltage V ref Provided to the LDO main structure, amplifier A x Generates a stable voltage Vx Provided to the LDO main structure, providing power supply voltage for the error amplifier in the LDO main structure, increasing the gain of the error amplifier to reduce the PSR index, so that the LDO main structure can be adjusted according to the voltage V ref and V x Generate output voltage to further reduce PSR parameters, thereby reducing the impact of external noise on the VCO module in the frequency synthesizer

[0054] like Figure 2 As shown, the main structure of the LDO includes an error amplifier A EA , transistor M L , transistor M Y , transistor M Q , transistor M X , transistor M P , feedback resistor R S , external capacitor C1, equivalent resistor R esr And the load resistance R load ;

[0055] Error Amplifier A EA The non-inverting input of amplifier A ref The output terminal is connected to the inverting input terminal through the feedback resistor R S Connect to the circuit output terminal, and the positive power supply terminal to the amplifier A x The output terminal is connected, and the negative power supply terminal is grounded;

[0056] Transistor M L The gate of the error amplifier A EA The output terminal is connected, the source is grounded, and the drain is connected to the transistor M Y The source connection of transistor M Y The drain is connected to the power supply voltage through resistor R5, and the gate is connected to the load resistor R load Ground; transistor M Q The source of transistor M is connected to the power supply voltage through resistor R4, the drain is grounded through resistor R3, and the gate is grounded; X The gate is connected to the ground through the resistor R3, the source is connected to the power supply voltage, the drain is connected to the circuit output terminal, and the substrate is connected to the transistor M P The gate connection of transistor M P The source is connected to the power supply voltage, the drain is connected to the circuit output terminal and the load resistor R load Ground; one end of the off-chip capacitor C1 is grounded, and the other end is connected to the ground through an equivalent resistor R esr Connect to the circuit output terminal.

[0057] In some embodiments, the equivalent resistance R esr is the resistance generated by the off-chip capacitor C1. V xA is the error amplifier EA The supply voltage, V out is the circuit output voltage of the overall LDO circuit. R1, R2, R3, R4 and R5 can be fixed resistors.

[0058] In some embodiments, the LDO main structure is the last loop in the LDO circuit, which is mainly composed of the error amplifier A EA and transistor M P In the LDO circuit, an equivalent resistor R is required. esr However, due to the limited resistance of the off-chip capacitor C1, the LDO circuit cannot be guaranteed to be stable in a wide load current range. Therefore, the transistor M P Can be used as a regulating tube, accompanied by transistor M P By moving the gate sub-pole, the LDO circuit can support a wider load current range, such as 0 to 1A load current.

[0059] According to an embodiment of the present disclosure, the error amplifier A EA and transistor M P The main structure of LDO is formed by transistor M P It can be used as a regulating tube, so that the LDO circuit can support a wider load current range.

[0060] like Figure 2 As shown, the above LDO main structure also includes a zero point compensation structure;

[0061] The zero compensation structure is used to generate the feedback voltage V Feedback Provided to the error amplifier A EA ;

[0062] The power input port of the zero compensation structure is connected to the power supply voltage, V Feedback Port and error amplifier A EA Connect and pass the feedback resistor R S Connect to the circuit output terminal.

[0063] In some embodiments, transistor M P As a power tube, the error amplifier A EA The role of feedback voltage V Feedback With reference voltage V ref Compare and generate an error voltage for controlling the gate of the power tube, so as to adjust the conduction current flowing through the power tube and make the circuit output voltage V out Stablize.

[0064] According to the embodiment of the present disclosure, the ESR zero compensation structure replaces the parasitic resistance R esrThe zero point structure is established in the loop, and the generated zero point can be closer to the origin as the load current increases, solving the problem of parasitic resistance R of the off-chip capacitor C1. esr Too small or too large a load current can cause the LDO circuit to work abnormally, that is, the resistance R of capacitor C1 esr At the milliohm level, the ESR zero point fails, causing the LDO loop to be unstable.

[0065] like Figure 3 As shown, the zero compensation structure includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, an amplifier A esr , fast start resistor R on And RC filter structure;

[0066] The source of transistor M3 is connected to the power supply voltage, the gate is grounded through resistor R3, the substrate is connected to the gate of transistor M4, and the drain is connected to amplifier A esr The non-inverting input terminal of the transistor M1 is connected to the drain of the transistor M1; the source of the transistor M4 is connected to the power supply voltage, and the substrate is connected to the transistor M X The gate is connected to the drain of transistor M2 and the drain is connected to the drain of transistor M2 through the fast start resistor R on With amplifier A esr The inverting input terminal of amplifier A is connected esr The output end is connected to the gate of the transistor M1 and is connected to the gate of the transistor M2 through the RC filtering structure; the source of the transistor M1 is grounded through the resistor R1, and the source of the transistor M2 is grounded through the resistor R2.

[0067] In some embodiments, the RC filter structure includes a fixed resistor R and a capacitor C. One end of the capacitor C is grounded, and the other end is connected to the resistor R and the gate of the transistor M2 respectively.

[0068] In some embodiments, transistor M3 is the same size as transistor M4 and is P The branch currents are in a mirror relationship, and the mirror ratio is n1:n2. The transistor M1 and the transistor M2 have the same size.

[0069] In some embodiments, the zero point of the zero point compensation structure can be compensated in the overall loop of the LDO main structure LDO_MAIN, as follows:

[0070] Set the mirror current of transistor M3 and transistor M4 to I in , amplifier A esr The output node is V N The resistor feedback node is V Feedback ;

[0071] Mirror current I inEqual to the sum of the two branch currents:

[0072] I in =I x +I y (1)

[0073] Current I in With M P The branch currents are in a mirror relationship and the mirror ratio is n1:n2, then:

[0074]

[0075] According to the amplifier A esr Output Node V N Write down the V N The current formula flowing through M1 and M2 is:

[0076]

[0077] I in =V N ·g m1 (4)

[0078] Since M1 and M2 have the same size, we have:

[0079] g m1 =g m2 (5)

[0080] Combine equations (1), (2), (3), (4), and (5) and solve for I y We can get:

[0081]

[0082] by I y The feedback resistance R S The voltage across the terminals and V Feedback Node voltage:

[0083] V Rs =I y ·R s (7)

[0084] V Feedback =I y ·R s +V out (8)

[0085] The error amplifier gain A EA and adjust the tube gain g mp From r0, we can know:

[0086] V out =(V ref-V Feedback )·A EA ·g mp r0 (9)

[0087] Combining formulas (6), (7), (8), and (9), we can obtain:

[0088]

[0089] Formula (10) can be simplified to get:

[0090]

[0091] Calculate the zero point:

[0092]

[0093] It can be seen that based on the above analysis and theoretical deduction, the zero point of the zero point compensation structure can be compensated in the overall loop of the LDO main structure LDO_MAIN.

[0094] According to the embodiments of the present disclosure, the zero point of the zero point compensation structure can be compensated in the overall loop of the LDO main structure LDO_MAIN through the above-mentioned zero point compensation structure, and the zero point compensation structure is relatively simple during design and debugging, and has fewer associated parameters.

[0095] like Figure 3 As shown, the above LDO main structure also includes an overcurrent protection structure;

[0096] The overcurrent protection structure is used to generate an overcurrent protection voltage V ctrl Provided to transistor M Y ;

[0097] The input ports of the overcurrent protection structure are connected to the transistor M X and transistor M P The drain terminal is connected to the voltage output port, and the voltage output port is connected to the circuit output terminal. ctrl Port and transistor M Y The gate connection.

[0098] In some embodiments, transistor M Y It can be used as an overcurrent adjustment tube. When the load current exceeds the rated current 1A, the overcurrent protection structure will turn V ctrl Set to 0 to disconnect the LDO loop and protect the circuit.

[0099] According to the embodiments of the present disclosure, since the load current range is relatively wide, through the above-mentioned overcurrent protection structure, even if the load current is too large, it will not cause serious impacts such as breakdown and damage to the LDO circuit.

[0100] like Figure 4As shown, the above-mentioned overcurrent protection structure includes a transistor P1, a transistor P2, a transistor N1, a transistor N2, a transistor N3 and an off-chip capacitor C2;

[0101] The source of transistor P1 is connected to the b1 With M X The drain of transistor P2 is connected to the gate of transistor P2, and the drain is connected to the drain of transistor N1; the source of transistor P2 is connected to the gate of transistor P2 through resistor R b2 With transistor M P The drain of transistor N1 is connected to the drain of transistor N2, and the gate and drain are connected to each other; the source of transistor N1 is grounded, the gate is connected to the gate of transistor N2, and the drain and gate are connected to each other; the source of transistor N2 is grounded, and the gate is connected to the gate of transistor N3; the source of transistor N3 is grounded, and the drain is connected to the gate of transistor M2; one end of the off-chip capacitor C1 is connected to the transistor M2 respectively P The drain is connected to the output end of the circuit and the other end is grounded.

[0102] In some embodiments, M X M P The mirror branch has a mirror ratio of 1:n. b1 and resistor R b2 is a fixed resistor.

[0103] Set the LDO output load current to I load , the reference current of the overcurrent protection structure is I ref The working status of the LDO circuit is as follows:

[0104] 1)LDO_MAIN loop operates normally

[0105] when When V x voltage is pulled to ground, then V ctrl The voltage is pulled to the power supply and the LDO main loop operates normally.

[0106] 2) The overcurrent protection structure starts and the LDO_MAIN loop is disconnected

[0107] when When V x The voltage slowly rises from 0. load When it increases to a certain preset value, V ctrl is pulled to ground, and the LDO_MAIN loop is disconnected, triggering the overcurrent protection.

[0108] According to the embodiments of the present disclosure, the overcurrent protection structure described above can be designed and debugged more concisely and has fewer associated parameters.

[0109] In some embodiments, the amplifier A BG , Amplifier A ref and amplifier A x It is a non-inverting amplifier.

[0110] In some embodiments, based on the infinite open-loop gain of the non-inverting amplifier and the almost zero voltage difference between the two input terminals of the operational amplifier, a non-inverting amplifier can be selected as the amplifier of the LDO circuit in order to amplify the input signal level without changing the phase of the output signal.

[0111] According to an embodiment of the present disclosure, by setting the amplifier A BG , Amplifier A ref and amplifier A x As a non-inverting amplifier, the efficiency of the entire LDO circuit can be improved, and further the next-stage LDO main structure LDO_MAIN can be isolated from noise.

[0112] In some embodiments, the resistor R ref2 It is an adjustable resistor.

[0113] In some embodiments, the reference voltage V ref Based on this, an adjustable resistor can be added to calibrate the reference voltage V ref , that is, the voltage-dividing fixed resistor R ref2 Set as adjustable resistor R ref2 .

[0114] According to the embodiment of the present disclosure, in order to avoid the influence of factors such as temperature and process, the resistor R ref2 It is an adjustable resistor that provides a stable reference voltage for the next-level LDO main structure LDO_MAIN.

[0115] According to an embodiment of the present disclosure, the present disclosure further provides an LDO, comprising the LDO circuit as described above.

[0116] According to an embodiment of the present disclosure, the present disclosure further provides a SOC system, comprising the LDO circuit as described above.

[0117] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An LDO circuit, characterized in that: include: Amplifier A BG , Amplifier A ref , Amplifier A x And the LDO main structure; The amplifier A BG Used to generate voltage V according to reference current BG Provided to the amplifier A ref and the amplifier A x ; The amplifier A ref To generate voltage V ref Provided to the LDO main structure; The amplifier A x To generate voltage V x Provided to the LDO main structure; The LDO main structure is used to ref and V x Generate output voltage; The amplifier A BG The non-inverting input terminal is connected to the reference current, and the inverting input terminal is connected to the reference current through the resistor R BG2 Ground and through resistor R BG1 Connect to the output terminal; The amplifier A ref The non-inverting input of the amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R ref2 Ground and through resistor R ref1 Connect to the output terminal; The amplifier A x The non-inverting input of the amplifier A BG The output terminal is connected to the inverting input terminal through the resistor R x2 Ground and through resistor R x1 Connect to the output terminal; The LDO main structure V ref port with the amplifier A ref The output terminal is connected to V x port with the amplifier A x The output end is connected to the output end of the circuit; the output end is connected to the output end of the circuit; The LDO main structure includes an error amplifier A EA , transistor M L , transistor M Y , transistor M Q , transistor M X , transistor M P , feedback resistor R S , external capacitor C1, equivalent resistor R esr And the load resistance R load ; The error amplifier A EA The non-inverting input of the amplifier A ref The output terminal is connected to the inverting input terminal through the feedback resistor R S Connect the positive power supply terminal to the output terminal of the circuit and the amplifier A x The output end is connected, and the negative power supply end is grounded; the transistor M L The gate of the error amplifier A EA The output terminal is connected, the source is grounded, and the drain is connected to the transistor M Y The source of the transistor M Y The drain is connected to the power supply voltage through the resistor R5, and the gate is connected to the load resistor R load ground; the transistor M Q The source of the transistor M is connected to the power supply voltage through the resistor R4, the drain is grounded through the resistor R3, and the gate is grounded; X The gate is grounded through resistor R3, the source is connected to the power supply voltage, the drain is connected to the circuit output terminal, and the substrate is connected to the transistor M P The gate of the transistor M P The source is connected to the power supply voltage, the drain is connected to the circuit output and through the load resistor R load One end of the off-chip capacitor C1 is grounded, and the other end is connected to the ground through the equivalent resistor R esr Connected to the output terminal of the circuit; The LDO main structure also includes a zero-point compensation structure; the zero-point compensation structure is used to generate a feedback voltage V Feedback supplied to the error amplifier A EA The power input port of the zero compensation structure is connected to the power supply voltage, V Feedback port and the error amplifier A EA Connect and pass the feedback resistor R S The zero compensation structure includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, an amplifier A esr , fast start resistor R on and RC filter structure; the source of the transistor M3 is connected to the power supply voltage, the gate is grounded through the resistor R3, the substrate is connected to the gate of the transistor M4, and the drain is connected to the amplifier A esr The in-phase input terminal of the transistor M1 is connected to the drain of the transistor M1; the source of the transistor M4 is connected to the power supply voltage, and the substrate is connected to the transistor M X The gate is connected to the drain of the transistor M2 and connected to the fast start resistor R on With the amplifier A esr The inverting input terminal of the amplifier A is connected; esr The output end is connected to the gate of the transistor M1 and is connected to the gate of the transistor M2 through the RC filter structure; the source of the transistor M1 is grounded through the resistor R1, and the source of the transistor M2 is grounded through the resistor R2; The LDO main structure also includes an overcurrent protection structure; the overcurrent protection structure is used to generate an overcurrent protection voltage V ctrl Provided to the transistor M Y The input port of the overcurrent protection structure is respectively connected to the transistor M X and the transistor M P The drain terminal is connected to the voltage output port, and the voltage output port is connected to the circuit output terminal. ctrl port and the transistor M Y The overcurrent protection structure includes a transistor P1, a transistor P2, a transistor N1, a transistor N2, a transistor N3 and an off-chip capacitor C2; the source of the transistor P1 is connected through a resistor R b1 With the M X The drain of the transistor is connected to the gate of the transistor P2, and the drain is connected to the drain of the transistor N1; the source of the transistor P2 is connected to the gate of the transistor P2 through the resistor R b2 With the transistor M P The drain of the transistor N1 is connected to the drain of the transistor N2, and the gate and the drain are connected to each other; the source of the transistor N1 is grounded, the gate is connected to the gate of the transistor N2, and the drain and the gate are connected to each other; the source of the transistor N2 is grounded, and the gate is connected to the gate of the transistor N3; the source of the transistor N3 is grounded, and the drain is connected to the gate of the transistor M2; one end of the off-chip capacitor C1 is connected to the gate of the transistor M2 respectively. P The drain is connected to the output end of the circuit and the other end is grounded.

2. The LDO circuit according to claim 1, characterized in that: The amplifier A BG , the amplifier A ref and the amplifier A x It is a non-inverting amplifier.

3. The LDO circuit according to claim 1, characterized in that: The resistor R ref2 It is an adjustable resistor.

4. An LDO, characterized in that: The method comprises the LDO circuit according to any one of claims 1 to 3.

5. A SOC system, characterized in that: The method comprises the LDO circuit according to any one of claims 1 to 3.

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