A charge pump and low dropout linear regulator circuit

Abstract

The present application relates to the technical field of analog circuit, and discloses a charge pump.The charge pump comprises a first voltage boosting control circuit, a second voltage boosting control circuit, a first voltage lifting circuit and a second voltage lifting circuit.The first voltage boosting control circuit can generate a first multiplex signal at a first node and a second multiplex signal at a second node in response to an input voltage and a control signal.The second voltage boosting control circuit comprises a third node and a fourth node.The first voltage lifting circuit is connected between the first node and the third node, and the second voltage lifting circuit is connected between the second node and the fourth node.When the control signal is a first level signal, the first voltage lifting circuit lifts the voltage of the third node to a first multiplex voltage according to the first multiplex signal, and the second voltage boosting control circuit outputs a target voltage in response to the first multiplex voltage of the third node and the input voltage.The same is true when the control signal is a second level signal.Therefore, the embodiment does not need to increase an additional circuit to drive the charge pump.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog circuit, in particular to a charge pump and low-dropout linear voltage regulator circuit. BACKGROUND

[0002] The charge pump is a kind of voltage converter that can convert the input first voltage into the second voltage for output, for example, the first voltage is low voltage, and the second voltage is high voltage, that is, the charge pump is used for boosting the input voltage.

[0003] For the charge pump that converts voltage by driving different power switch tubes, in order to successfully drive the charge pump so that the charge pump can work normally, different control signals are generally needed to drive different power switch tubes in the charge pump. The conventional method generally generates each control signal required by the charge pump by adding an additional driving circuit, however, this method of adding an additional driving circuit will inevitably increase the circuit complexity, and also increase the power consumption. SUMMARY

[0004] One purpose of an embodiment of the present application is to provide a charge pump and low-dropout linear voltage regulator circuit that can solve the defects existing in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a charge pump, comprising:

[0006] A first boost control circuit comprising a first node and a second node, the first boost control circuit can be applied with an input voltage and a control signal, in response to the control signal and the input voltage, a first multiplex signal is generated at the first node, and a second multiplex signal is also generated at the second node;

[0007] A second boost control circuit comprising a third node and a fourth node, the second boost control circuit can be applied with an input voltage;

[0008] A first voltage lifting circuit connected between the first node and the third node;

[0009] A second voltage lifting circuit connected between the second node and the fourth node;

[0010] When the control signal is a first level signal, the first voltage lifting circuit lifts the voltage of the third node to a first multiplex voltage according to the first multiplex signal, and the second boost control circuit outputs a target voltage in response to the first multiplex voltage of the third node and the input voltage, the target voltage is equal to N times the input voltage, N is a positive number greater than 1;

[0011] When the control signal is a second level signal, the second voltage lifting circuit lifts the voltage of the fourth node to a first multiplex voltage according to the second multiplex signal, and the second voltage boosting control circuit outputs a target voltage in response to the first multiplex voltage of the fourth node and the input voltage.

[0012] Optionally, the first voltage boosting control circuit comprises:

[0013] a first signal inverting circuit, electrically connected to the first node and the first voltage lifting circuit, and capable of being applied with the control signal and the input voltage, and generating a first multiplex signal at the first node in response to the control signal and the input voltage;

[0014] a second signal inverting circuit, electrically connected to the first node, the first signal inverting circuit and the first voltage lifting circuit respectively, and also electrically connected to the second node and the second voltage lifting circuit, and capable of being applied with the input voltage, and generating a second multiplex signal at the second node in response to the input voltage and the first multiplex signal.

[0015] Optionally, the first signal inverting circuit is configured to control the voltage of the first multiplex signal to be a second multiplex voltage in response to the first level signal and the input voltage when the control signal is a first level signal, and control the voltage of the first multiplex signal to be a third multiplex voltage in response to the second level signal and the input voltage when the control signal is a second level signal.

[0016] Optionally, the first multiplex voltage is greater than the second multiplex voltage, and the second multiplex voltage is greater than the third multiplex voltage.

[0017] Optionally, the second signal inverting circuit is configured to control the voltage of the second multiplex signal to be a third multiplex voltage in response to the second multiplex voltage and the input voltage when the first multiplex signal is the second multiplex voltage, and control the voltage of the second multiplex signal to be the second multiplex voltage in response to the third multiplex voltage and the input voltage when the first multiplex signal is the third multiplex voltage.

[0018] Optionally, the second voltage boosting control circuit is configured to control the second voltage lifting circuit to generate the second multiplex voltage at the fourth node in response to the first multiplex voltage of the third node and the input voltage when the second multiplex signal is the third multiplex voltage, and control the first voltage lifting circuit to generate the second multiplex voltage at the third node in response to the first multiplex voltage of the fourth node and the input voltage when the first multiplex signal is the third multiplex voltage.

[0019] Optionally, when the voltage of the third node is the second multiplex voltage, if the first multiplex signal changes from the third multiplex voltage to the second multiplex voltage, the first voltage lifting circuit lifts the voltage of the third node from the second multiplex voltage to the first multiplex voltage according to the first multiplex signal.

[0020] When the voltage of the fourth node is the second multiplex voltage, if the second multiplex signal changes from the third multiplex voltage to the second multiplex voltage, the second voltage lifting circuit lifts the voltage of the fourth node from the second multiplex voltage to the first multiplex voltage according to the second multiplex signal.

[0021] Optionally, the second voltage lifting control circuit includes a first switch circuit and a second switch circuit.

[0022] The first switch circuit, the second switch circuit and the first voltage lifting circuit are commonly connected at the third node, and the first switch circuit, the second switch circuit and the second voltage lifting circuit are commonly connected at the fourth node, and the first switch circuit and the second switch circuit can be applied with an input voltage.

[0023] The first switch circuit is configured to output a target voltage in response to the first multiplex voltage of the third node and the second multiplex voltage of the fourth node, and the second switch circuit is configured to output a target voltage in response to the first multiplex voltage of the fourth node and the second multiplex voltage of the third node.

[0024] Optionally, the first switch circuit, the first voltage lifting circuit and the first signal inverting circuit form a first loop, and the first switch circuit is configured to turn on the first loop in response to the first multiplex voltage of the fourth node and the input voltage when the control signal is a first level signal, so that the input voltage charges the first voltage lifting circuit through the first loop to generate the second multiplex voltage at the third node.

[0025] Optionally, the second switch circuit, the second voltage lifting circuit and the second signal inverting circuit form a second loop, and the second switch circuit is configured to turn on the second loop in response to the first multiplex voltage of the third node and the input voltage when the control signal is a first level signal, so that the input voltage charges the second voltage lifting circuit through the second loop to generate the second multiplex voltage at the fourth node.

[0026] In a second aspect, an embodiment of the present application provides a low-dropout linear voltage stabilizing circuit, including the charge pump as described above.

[0027] In the charge pump provided by the embodiment of the present application, the charge pump comprises a first voltage boosting control circuit, a second voltage boosting control circuit, a first voltage lifting circuit and a second voltage lifting circuit. The first voltage boosting control circuit comprises a first node and a second node, and generates a first multiplex signal at the first node and a second multiplex signal at the second node in response to an input voltage and a control signal. The second voltage boosting control circuit comprises a third node and a fourth node. The first voltage lifting circuit is connected between the first node and the third node, and the second voltage lifting circuit is connected between the second node and the fourth node. When the control signal is a first level signal, the first voltage lifting circuit lifts the voltage of the third node to a first multiplex voltage according to the first multiplex signal, and the second voltage boosting control circuit outputs a target voltage in response to the first multiplex voltage of the third node and the input voltage. When the control signal is a second level signal, the second voltage lifting circuit lifts the voltage of the fourth node to the first multiplex voltage according to the second multiplex signal, and the second voltage boosting control circuit outputs the target voltage in response to the first multiplex voltage of the fourth node and the input voltage. Therefore, the embodiment can multiplex the control signal in the circuit node and generate the multiplex voltage, without increasing the additional circuit to generate each control signal required for driving the charge pump, thereby facilitating the simplification of the circuit structure and the reduction of power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0028] The one or more embodiments are only illustrative and are not intended to limit the embodiments, and the elements with the same reference numerals in the drawings represent the similar elements, unless otherwise specified. The drawings do not constitute a proportional limit.

[0029] Figure 1 is a structural schematic diagram of a low-dropout linear voltage regulator provided by an embodiment of the present application;

[0030] Figure 2 is a structural schematic diagram of a low-dropout linear voltage regulator provided by another embodiment of the present application;

[0031] Figure 3 is a structural schematic diagram of a low-dropout linear voltage regulator provided by still another embodiment of the present application;

[0032] Figure 4 is a circuit structural schematic diagram of a low-dropout linear voltage regulator provided by an embodiment of the present application;

[0033] Figure 5 is a working state schematic diagram of a charge pump provided by an embodiment of the present application;

[0034] Figure 6 is a working state schematic diagram of a charge pump provided by another embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] It should be noted that the various features of the embodiments of the present application can be combined with each other without conflict, and all fall within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0037] The embodiment of the present application provides a low-dropout linear voltage regulator circuit. Please refer to Figure 1 , the low-dropout linear voltage regulator circuit 100 includes an error amplifier circuit 11, a charge pump 12, a transmission switch tube 13 and a feedback circuit 14.

[0038] The error amplifier circuit 11 includes a first input end and a second input end, the first input end of the error amplifier circuit 11 is used to be applied with a reference voltage Vref, and the second input end of the error amplifier circuit 11 is electrically connected with the feedback circuit 14, and is used to output a voltage V1 in response to the reference voltage Vref and the voltage fed back by the feedback circuit 14.

[0039] The charge pump 12 is electrically connected with the error amplifier circuit 11, and the charge pump 12 is used to perform voltage conversion processing on the voltage V1 output by the error amplifier circuit 11, and output a voltage V2.

[0040] The transmission switch tube 13 includes a control end 13a, an input end 13b and an output end 13c, the control end 13a of the transmission switch tube 13 is electrically connected with the charge pump 12, the input end 13b of the transmission switch tube 13 is used to be applied with a voltage Vin, and the output end 13c of the transmission switch tube 13 is electrically connected with the feedback circuit 14, and the transmission switch tube 13 is used to output a voltage Vout at the output end 13c of the transmission switch tube 13 according to the voltage Vin in response to the voltage V2.

[0041] Feedback circuit 14 is electrically connected to the output terminal 13c of transmission switch 13 and the second input terminal of error amplifier circuit 11, respectively. It is used to generate feedback voltage Vfb according to voltage Vout and feed it to error amplifier circuit 11 so that error amplifier circuit 11 adjusts output voltage V1 according to reference voltage Vref and feedback voltage Vfb, thereby causing charge pump 12 to adjust output voltage V2, and then causing transmission switch 13 to adjust voltage Vout output from output terminal 13c. After continuous adjustment, voltage Vout eventually stabilizes at a preset voltage value.

[0042] The feedback voltage Vfb can be equal to the voltage Vout, or it can be in other proportions to the voltage Vout.

[0043] In some embodiments, please refer to Figure 4 The feedback circuit 14 includes a first resistor R1 and a second resistor R2.

[0044] One end of the first resistor R1 is electrically connected to the output terminal 13c of the transmission switch 13, and the other end of the first resistor R1 is electrically connected to one end of the second resistor R2 and the second input terminal of the error amplifier circuit 11. The other end of the second resistor R2 is grounded.

[0045] The first resistor R1 and the second resistor R2 are used to divide the voltage Vout to generate a feedback voltage Vfb at the connection point of the first resistor R1 and the second resistor R2. The feedback voltage Vfb = Vout * R2 / (R1 + R2). From this formula, it can be seen that the feedback voltage Vfb is proportional to Vout, Vfb:Vout = R2:(R1 + R2). By adjusting the values ​​of the first resistor R1 and the second resistor R2, the proportional relationship between the feedback voltage Vfb and the voltage Vout can be adjusted.

[0046] In some embodiments, such as Figure 4As shown, the first input terminal of the error amplifier circuit 11 is a non-inverting input terminal, and the second input terminal is an inverting input terminal. That is, a reference voltage Vref is applied to the non-inverting input terminal of the error amplifier circuit 11, and a feedback voltage Vfb is applied to the inverting input terminal. Therefore, when the voltage Vout is high, the feedback voltage Vfb is also high, making the reference voltage Vref less than the feedback voltage Vfb. That is, there is a negative phase voltage difference between the reference voltage Vref and the feedback voltage Vfb. In this case, the error amplifier circuit 11 reduces the output amplified voltage V1 to lower the voltage Vout. When the voltage Vout is low, the feedback voltage Vfb is also low, making the reference voltage Vref greater than the feedback voltage Vfb. That is, there is a positive phase voltage difference between the reference voltage and the feedback voltage Vfb. In this case, the error amplifier circuit 11 increases the output amplified voltage V1 to raise the voltage Vout. Therefore, by continuously adjusting the voltage Vout, the voltage Vout can eventually be stabilized at Vref*(R1+R2) / R2.

[0047] In some embodiments, please refer to Figure 2 The error amplifier circuit 11 includes a differential circuit 111 and a current mirror circuit 112.

[0048] The differential circuit 111 is supplied with a reference voltage and is electrically connected to the feedback circuit 14 to generate a first differential current I1 and a second differential current I2 in response to the reference voltage and the feedback voltage Vfb.

[0049] The current mirror circuit 112 is electrically connected to the differential circuit 111. The current mirror circuit 112 includes an output node 112a, which is electrically connected to the charge pump 12. It is used to generate a voltage V1 at the output node 112a in response to the first differential current I1 and the second differential current I2.

[0050] In some embodiments, please refer to Figure 3 The current mirror circuit 112 includes a first mirror unit 1121, a second mirror unit 1122 and a third mirror unit 1123.

[0051] The first mirror unit 1121 is electrically connected to the differential circuit 111 and is used to mirror the first differential current I1 to obtain the first mirror current I3.

[0052] The second mirror unit 1122 is electrically connected to the differential circuit 111 and is used to mirror the second differential current I2 to obtain the second mirror current I4.

[0053] The third mirror unit 1123 is electrically connected to the first mirror unit 1121, and is electrically connected to the second mirror unit 1122 and the charge pump 12 at the output node 112a, respectively, to mirror the first mirror current I3 and obtain the third mirror current I5.

[0054] Output node 112a is used to generate voltage V1, wherein the current output by output node 112a is the current obtained by the combined action of the third mirror current I5 and the second mirror current I4.

[0055] In some embodiments, please continue reading Figure 4 The differential circuit 111 includes a first MOSFET M1 and a second MOSFET M2.

[0056] The source of the first MOSFET M1 and the source of the second MOSFET M2 are both subjected to a bias current Ibias. The gate of the first MOSFET M1 is electrically connected to the feedback circuit 14, and the drain of the first MOSFET M1 is electrically connected to the first mirror unit 1121. The gate of the second MOSFET M2 is used to be subjected to a reference voltage Vref, and the drain of the second MOSFET M2 is electrically connected to the second mirror unit 1122.

[0057] The bias current Ibias is equal to the sum of the first differential current I1 and the second differential current I2. The currents that the first differential current I1 and the second differential current I2 receive from the bias current Ibias can depend on the reference voltage Vref and the feedback voltage Vfb.

[0058] In some embodiments, such as Figure 4 As shown, the first mirror unit 1121 includes a third MOS transistor M3 and a fourth MOS transistor M4.

[0059] The drain and gate of the third MOSFET M3 and the gate of the fourth MOSFET M4 are electrically connected to the differential circuit 111. The source of the third MOSFET M3 is grounded. The drain of the fourth MOSFET M4 is electrically connected to the third mirror unit 1123. The source of the fourth MOSFET M4 is grounded.

[0060] The current flowing through the fourth MOSFET M4 is the first mirror current I3 obtained by mirroring the first differential current I1. The first mirror current I3 = S4*I1 / S3, where S4 is the width-to-length ratio of the fourth MOSFET M4 and S3 is the width-to-length ratio of the third MOSFET M3.

[0061] In some embodiments, such as Figure 4 As shown, the second mirror unit 1122 includes a fifth MOS transistor M5 and a sixth MOS transistor M6.

[0062] The drain of the fifth MOSFET M5, the gate of the fifth MOSFET M5, and the gate of the sixth MOSFET M6 are all electrically connected to the differential circuit 111. The source of the fifth MOSFET M5 is grounded. The drain of the sixth MOSFET M6 is electrically connected to the third mirror unit 1123 at the output node 112a. The source of the sixth MOSFET M6 is grounded.

[0063] The current flowing through the sixth MOSFET M6 is the second mirror current I4 obtained by mirroring the second differential current I2. The second mirror current I4 = S6*I2 / S5, where S6 is the width-to-length ratio of the sixth MOSFET M6 and S5 is the width-to-length ratio of the fifth MOSFET M5.

[0064] In some embodiments, such as Figure 4 As shown, the third mirror unit 1123 includes a seventh MOSFET M7 and an eighth MOSFET M8.

[0065] An external voltage VDD is applied to the source of the seventh MOSFET M7 and the source of the eighth MOSFET M8. The gate and drain of the seventh MOSFET M7 and the gate of the eighth MOSFET M8 are electrically connected to the first mirror unit 1121. The drain of the eighth MOSFET M8 is electrically connected to the second mirror unit 1122 and the charge pump 12 at the output node 112a.

[0066] The current flowing through the eighth MOSFET M8 is the third mirror current I5 obtained by mirroring the first mirror current I3. The third mirror current I5 = S8*I3 / S7, where S8 is the width-to-length ratio of the eighth MOSFET M8 and S7 is the width-to-length ratio of the seventh MOSFET M7.

[0067] Therefore, by Figure 4 It can be seen that the current I6 output by the output node 112a can be expressed as the current difference between the third mirror current I5 and the second mirror current I4. When the third mirror current I5 is greater than the second mirror current I4, that is, when the current I6 is positive, the voltage V1 of the output node 112a increases. When the third mirror current I5 is less than the second mirror current I4, that is, when the current I6 is negative, the voltage V1 of the output node 112a decreases.

[0068] In some embodiments, such as Figure 4 As shown, the error amplifier circuit 11 also includes an undervoltage protection circuit 113.

[0069] The undervoltage protection circuit 113 is electrically connected to the current mirror circuit 112 and the charge pump 12 respectively, and is used to prevent the voltage V1 of the output node 112a from being too low, so as to prevent the charge pump 12 from failing to work properly due to the low voltage V1.

[0070] The undervoltage protection circuit 113 includes a ninth MOSFET M9. The source of the ninth MOSFET M9 is electrically connected to the current mirror circuit 112 and the charge pump 12 at the output node 112a. The drain of the ninth MOSFET M9 is electrically connected to the current mirror circuit 112. The gate of the ninth MOSFET M9 is grounded.

[0071] When the voltage V1 is lower than a certain value, the ninth MOSFET M9 is in the off state. At this time, the ninth MOSFET M9 blocks the sixth MOSFET M6 from drawing current down from the output node 112a, thereby preventing the voltage V1 from being too low.

[0072] In some embodiments, such as Figure 4 As shown, the transmission switch 13 is an NMOS transistor Np. Please refer to the following: Figure 2 The gate of NMOS transistor Np is the control terminal 13a of the transfer switch 13, the drain of NMOS transistor Np is the input terminal 13b of the transfer switch 13, and the source of NMOS transistor Np is the output terminal 13c of the transfer switch 13.

[0073] In this embodiment, by controlling the voltage difference between the gate voltage and the source voltage of the NMOS transistor Np to be greater than the threshold voltage of the NMOS transistor Np, the NMOS transistor Np can be turned on, and at this time the source of the NMOS transistor Np can output voltage Vout.

[0074] Therefore, by using the source follower structure constructed from NMOS transistor Np as the output stage of the low dropout linear regulator circuit 100, this embodiment can improve the response speed of the low dropout linear regulator circuit 100, which is beneficial for the low dropout linear regulator circuit 100 to quickly respond to the transient current load brought by the digital circuit during the process of providing power supply to the digital circuit.

[0075] Since the conduction of NMOS transistor Np requires that the gate voltage of NMOS transistor Np be greater than the source voltage of NMOS transistor Np, when the gate voltage of NMOS transistor Np is low, the source voltage of NMOS transistor Np is also low. If the source voltage of NMOS transistor Np is to be increased, the gate voltage of NMOS transistor Np needs to be increased. Therefore, in some embodiments, the charge pump 12 is used to boost the voltage V1 output by the error amplifier circuit 11 to obtain a voltage V2 that is greater than voltage V1, for example, voltage V2 is about twice the voltage V1.

[0076] By setting a charge pump 12 between the error amplifier circuit 11 and the NMOS transistor Np, the output voltage V1 of the error amplifier circuit 11 can be increased, resulting in a voltage V2 which is applied to the gate of the NMOS transistor Np to drive the NMOS transistor Np. This increases the output voltage Vout at the source of the NMOS transistor Np, preventing the voltage Vout from being limited by the output voltage V1 of the error amplifier circuit 11.

[0077] In some embodiments, please continue reading Figure 2 The charge pump 12 includes a first boost control circuit 121, a second boost control circuit 122, a first voltage boost circuit 123, and a second voltage boost circuit 124.

[0078] The first boost control circuit 121 includes a first node 121a and a second node 121b. The first boost control circuit 121 can be applied with an input voltage and a control signal clk. Here, the input voltage is the voltage V1 output by the error amplifier circuit 11. The control signal can be any signal that can control the operation of the first boost control circuit 121. For example, the control signal is a clock signal. The clock signal includes a first level signal and a second level signal. The first level signal and the second level signal are different level signals. For example, the first level signal is a high level signal and the second level signal is a low level signal, or the first level signal is a low level signal and the second level signal is a high level signal. The first boost control circuit 121 can be applied with a clock signal that alternates between the first level signal and the second level signal to respond to the corresponding level signal and operate in the corresponding state.

[0079] The first boost control circuit 121 responds to the control signal and the input voltage, generates a first multiplexed signal at the first node 121a, and also generates a second multiplexed signal at the second node 121b.

[0080] The first multiplexed signal and the second multiplexed signal are signals obtained by the first boost control circuit 121 based on the multiplexing of the control signal. The voltage of the first multiplexed signal and the voltage of the second multiplexed signal can change with the level of the control signal. At the same time, the voltage of the first multiplexed signal and the voltage of the second multiplexed signal are different.

[0081] In some embodiments, please continue reading Figure 3 The first boost control circuit 121 includes a first signal inverting circuit 1211 and a second signal inverting circuit 1212.

[0082] The first signal inverting circuit 1211 is electrically connected to the first voltage boosting circuit 123 at the first node 121a. It can be subjected to control signals and input voltages, and in response to the control signals and input voltages, it generates a first multiplexed signal at the first node 121a.

[0083] The second signal inverting circuit 1212 is electrically connected to the first signal inverting circuit 1211 and the first voltage boosting circuit 123 at the first node 121a, and is also electrically connected to the second voltage boosting circuit 124 at the second node 121b. It can be applied an input voltage and, in response to the input voltage and the first multiplexed signal, generates a second multiplexed signal at the second node 121b.

[0084] In some embodiments, the first signal inverting circuit 1211 is used to control the voltage of the first multiplexed signal to a second multiplexed voltage in response to the first level signal and the input voltage when the control signal is a first level signal, and the first signal inverting circuit 1211 is used to control the voltage of the first multiplexed signal to a third multiplexed voltage in response to the second level signal and the input voltage when the control signal is a second level signal.

[0085] It is understandable that when the first level signal and the second level signal of the control signal are flipped, the voltage of the first multiplexed signal is also flipped accordingly. When the control signal is flipped from the second level signal to the first level signal, the first multiplexed signal is flipped from the third multiplexed voltage to the second multiplexed voltage. When the control signal is flipped from the first level signal to the second level signal, the first multiplexed signal is flipped from the second multiplexed voltage to the third multiplexed voltage.

[0086] In some embodiments, the second multiplexing voltage is greater than the third multiplexing voltage.

[0087] In some embodiments, please refer to Figure 4 The first signal inverting circuit 1211 includes a first PMOS transistor PM1 and a first NMOS transistor NM1.

[0088] An input voltage can be applied to the source of the first PMOS transistor PM1. A control signal can be applied to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1. The drains of the first PMOS transistor PM1 and the first NMOS transistor NM1 are electrically connected to the second signal inverting circuit 1212 and the first voltage boosting circuit 123 respectively at the first node 121a. The source of the first NMOS transistor NM1 is grounded.

[0089] In this embodiment, when the control signal is a first level signal (low level signal), the first PMOS transistor PM1 is in the on state in response to the low level signal, and the first NMOS transistor NM1 is in the off state in response to the low level signal. At this time, the first PMOS transistor PM1 generates a second multiplexed voltage at the first node 121a according to the input voltage. Here, the second multiplexed voltage is close to the input voltage. When the control signal is a second level signal (high level signal), the first PMOS transistor PM1 is in the off state in response to the high level signal, and the first NMOS transistor NM1 is in the on state in response to the high level signal. At this time, the first NMOS transistor NM1 pulls the voltage of the first node 121a down to a third multiplexed voltage close to the ground voltage.

[0090] Therefore, this embodiment can directly reuse the control signal and generate the first multiplexed signal at the circuit node (first node 121a), without the need to add additional circuitry to generate the control signal required to drive the charge pump 12, which helps to simplify the circuit structure and reduce power consumption.

[0091] In some embodiments, the second signal inverting circuit 1212 is used to control the voltage of the second multiplexed signal to be a third multiplexed voltage in response to the second multiplexed voltage and the input voltage when the first multiplexed signal is a second multiplexed voltage. The second signal inverting circuit is also used to control the voltage of the second multiplexed signal to be a second multiplexed voltage in response to the third multiplexed voltage and the input voltage when the first multiplexed signal is a third multiplexed voltage.

[0092] It is understandable that when the second and third multiplexed voltages of the first multiplexed signal flip, the voltage of the second multiplexed signal also flips accordingly. When the first multiplexed signal flips from the third multiplexed voltage to the second multiplexed voltage, the second multiplexed signal flips from the second multiplexed voltage to the third multiplexed voltage. When the first multiplexed signal flips from the second multiplexed voltage to the third multiplexed voltage, the second multiplexed signal flips from the third multiplexed voltage to the second multiplexed voltage.

[0093] In some embodiments, such as Figure 4 As shown, the second signal inverting circuit 1212 includes a second PMOS transistor PM2 and a second NMOS transistor NM2.

[0094] The source of the second PMOS transistor PM2 can be supplied with an input voltage. The gates of the second PMOS transistor PM2 and the second NMOS transistor NM2 can be supplied with control signals. The drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 are electrically connected to the first signal inverting circuit 1211 and the first voltage boosting circuit 123 respectively at the second node 121b. The source of the second NMOS transistor NM2 is grounded.

[0095] In this embodiment, when the first multiplexing signal is the second multiplexing voltage (high voltage), the second PMOS transistor PM2 is in the off state in response to the high voltage, and the second NMOS transistor NM2 is in the on state in response to the high voltage. At this time, the second PMOS transistor PM2 pulls the voltage of the second node 121b down to the third multiplexing voltage. When the first multiplexing signal is the third multiplexing voltage (low voltage), the second PMOS transistor PM2 is in the on state in response to the low voltage, and the second NMOS transistor NM2 is in the off state in response to the low voltage. At this time, the second PMOS transistor PM2 generates the second multiplexing voltage at the second node 121b according to the input voltage.

[0096] Therefore, this embodiment can directly reuse the first multiplexed signal to generate the second multiplexed signal at the circuit node (second node 121b), without the need to add additional circuitry to generate the control signal required to drive the charge pump 12, which helps to simplify the circuit structure and reduce power consumption.

[0097] Please continue reading. Figure 2 The second boost control circuit 122 includes a third node 122a and a fourth node 122b, and the second boost control circuit 122 can be applied with an input voltage.

[0098] The first voltage boosting circuit 123 is connected between the first node 121a and the third node 122a.

[0099] The second voltage boosting circuit 124 is connected between the second node 121b and the fourth node 122b.

[0100] When the control signal is a first level signal, the first voltage boosting circuit 123 boosts the voltage of the third node 122a to the first multiplexed voltage according to the first multiplexed signal. The second boost control circuit 122 responds to the first multiplexed voltage and the input voltage of the third node 122a and outputs the target voltage. The target voltage is equal to N times the input voltage, where N is a positive number greater than 1.

[0101] It is understandable that the target voltage is the voltage after the input voltage has been boosted by N times. Here, the target voltage is the voltage V2 output by the charge pump 12.

[0102] When the control signal is a second level signal, the second voltage boosting circuit 124 boosts the voltage of the fourth node 122b to the first multiplexed voltage according to the second multiplexed signal. The second boost control circuit 122 responds to the first multiplexed voltage of the fourth node 122b and the input voltage, and outputs the target voltage.

[0103] In some embodiments, the first voltage boosting circuit 123 may include one capacitor or multiple capacitors. When the first voltage boosting circuit 123 includes one capacitor, please refer to [the following text is missing]. Figure 4 The first voltage boosting circuit 123 includes a capacitor C1, one end of which is connected to the first node 121a, and the other end of which is connected to the third node 122a. When the first voltage boosting circuit 123 includes multiple capacitors, one end of the multiple capacitors connected in series is connected to the first node 121a, and the other end of the multiple capacitors connected in series is connected to the third node 122a.

[0104] In some embodiments, the second voltage boosting circuit 124 may include one capacitor or multiple capacitors. When the second voltage boosting circuit 124 includes one capacitor, please refer to [the relevant documentation]. Figure 4 The second voltage boosting circuit 124 includes a capacitor C2, one end of which is connected to the second node 121b, and the other end of which is connected to the fourth node 122b. When the second voltage boosting circuit 124 includes multiple capacitors, one end of the multiple capacitors connected in series is connected to the second node 121b, and the other end of the multiple capacitors connected in series is connected to the fourth node 122b.

[0105] In some embodiments, the second boost control circuit 122 is used to control the second voltage boost circuit 124 to generate the second multiplexed voltage at the fourth node 122b in response to the first multiplexed voltage and the input voltage at the third node 122a when the control signal is a first level signal, i.e., the first multiplexed signal is the second multiplexed voltage and the second multiplexed signal is the third multiplexed voltage; the second boost control circuit 122 is used to control the first voltage boost circuit 123 to generate the second multiplexed voltage at the third node 121a when the control signal is a second level signal, i.e., the first multiplexed signal is the third multiplexed voltage.

[0106] As mentioned above, when the control signal is a first-level signal, the voltage of the fourth node 122b is the second multiplexed voltage, and the second multiplexed signal is the third multiplexed voltage. In some embodiments, when the control signal changes from the first-level signal to the second-level signal, that is, when the second multiplexed signal changes from the third multiplexed voltage to the second multiplexed voltage, the second voltage boosting circuit 124 boosts the voltage of the fourth node 122b from the second multiplexed voltage to the first multiplexed voltage according to the second multiplexed voltage of the second node 121b. At this time, the first multiplexed voltage is the sum of the voltage of the fourth node 122b (second multiplexed voltage) and the voltage of the second node 121b (second multiplexed voltage) when the control signal was the first-level signal at the previous moment, that is, the first multiplexed voltage is twice the second multiplexed voltage.

[0107] As mentioned above, when the control signal is a second-level signal, the voltage of the third node 122a is the second multiplexed voltage, and the first multiplexed signal is the third multiplexed voltage. In some embodiments, when the control signal changes from a second-level signal to a first-level signal, that is, when the first multiplexed signal changes from the third multiplexed voltage to the second multiplexed voltage, the first voltage boosting circuit 123 boosts the voltage of the third node 122a from the second multiplexed voltage to the first multiplexed voltage according to the second multiplexed voltage of the first node 121a. At this time, the first multiplexed voltage is the sum of the voltage of the third node 122a (second multiplexed voltage) and the voltage of the first node 121a (second multiplexed voltage) when the control signal was a second-level signal at the previous moment, that is, the first multiplexed voltage is twice the second multiplexed voltage.

[0108] In some embodiments, please continue reading Figure 3 The second boost control circuit 122 includes a first switching circuit 1221 and a second switching circuit 1222.

[0109] The first switching circuit 1221, the second switching circuit 1222, and the first voltage boosting circuit 123 are connected together at the third node 122a. The first switching circuit 1221, the second switching circuit 1222, and the second voltage boosting circuit 124 are connected together at the fourth node 122b. Both the first switching circuit 1221 and the second switching circuit 1222 can be applied with input voltage.

[0110] As mentioned above, when the control signal is a first level signal, the voltage of the third node 122a is the first multiplexed voltage, and the voltage of the fourth node 122b is the second multiplexed voltage. In some embodiments, the first switching circuit 1221 is used to respond to the first multiplexed voltage of the third node 122a and the second multiplexed voltage of the fourth node 122b to output the target voltage.

[0111] As mentioned above, when the control signal is a second-level signal, the voltage of the fourth node 122b is the first multiplexed voltage, and the voltage of the third node 122a is the second multiplexed voltage. In some embodiments, the second switching circuit 1222 is used to respond to the first multiplexed voltage of the fourth node 122b and the second multiplexed voltage of the third node 122a to output the target voltage.

[0112] When the control signal is a first-level signal, the second multiplexed voltage of the fourth node 122b can control the first switching circuit 1221, so that the first switching circuit 1221 outputs the target voltage according to the first multiplexed voltage of the third node 122a. When the control signal is a second-level signal, the second multiplexed voltage of the third node 122a can control the second switching circuit 1222, so that the second switching circuit 1222 outputs the target voltage according to the first multiplexed voltage of the fourth node 122b. Therefore, this embodiment generates multiplexed voltages directly at the circuit nodes (third node 122a and fourth node 122b) to drive the charge pump 12, without the need for additional circuitry to generate the control signal required to drive the charge pump 12, thereby simplifying the circuit structure and reducing power consumption.

[0113] In some embodiments, the first switching circuit 1221, the first voltage boosting circuit 123, and the first signal inverting circuit 1211 can form a first loop. As mentioned above, when the control signal is a second-level signal, the first multiplexed signal is a third multiplexed voltage, and the voltage of the fourth node 122b is the first multiplexed voltage. At this time, the first switching circuit 1221 can respond to the first multiplexed voltage of the fourth node 122b and the input voltage to turn on the first loop. The input voltage charges the first voltage boosting circuit 123 through the first loop to generate a second multiplexed voltage at the third node 122a. This allows the first voltage boosting circuit 123 to boost the voltage of the third node 122a from the second multiplexed voltage to the first multiplexed voltage when the subsequent control signal flips from the second-level signal to the first-level signal.

[0114] In some embodiments, please continue reading Figure 4 The first switching circuit 1221 includes a third NMOS transistor NM3 and a third PMOS transistor PM3.

[0115] The source of the third NMOS transistor NM3 is used to apply the input voltage. The gates of the third NMOS transistor NM3 and the third PMOS transistor PM3 are electrically connected to the second switching circuit 1222 and the second voltage boosting circuit 124 at the fourth node 122b, respectively. The drain of the third NMOS transistor NM3 is electrically connected to the second switching circuit 1222, the first voltage boosting circuit 123 and the drain of the third PMOS transistor PM3 at the third node 122a, respectively. The source of the third PMOS transistor PM3 is used to output the target voltage.

[0116] When the control signal is a second-level signal, please refer to [link / reference]. Figure 5 The third NMOS transistor NM3 is in the on state in response to the input voltage and the first multiplexed voltage of the fourth node 122b, the third PMOS transistor PM3 is in the off state in response to the first multiplexed voltage of the fourth node 122b, and the first NMOS transistor NM1 is in the on state in response to the second level signal. At this time, the third NMOS transistor NM3, capacitor C1 (first voltage boosting circuit 123) and the first NMOS transistor NM1 form the first loop. The input voltage is to charge capacitor C1 to generate the second multiplexed voltage at the third node 122a.

[0117] In some embodiments, the second switching circuit 1222, the second voltage boosting circuit 124, and the second signal inverting circuit 1212 can form a second loop. As mentioned above, when the control signal is a first level signal, the second multiplexed signal is a third multiplexed voltage, and the voltage of the third node 122a is a first multiplexed voltage. At this time, the second switching circuit 1222 can respond to the first multiplexed voltage of the third node 122a and the input voltage to turn on the second loop. The input voltage charges the second voltage boosting circuit 124 through the second loop to generate a second multiplexed voltage at the fourth node 122b. This allows the second voltage boosting circuit 124 to boost the voltage of the fourth node 122b from the second multiplexed voltage to the first multiplexed voltage when the subsequent control signal flips from the first level signal to the second level signal.

[0118] In some embodiments, please continue reading Figure 4 The second switching circuit 1222 includes a fourth NMOS transistor NM4 and a fourth PMOS transistor PM4.

[0119] The source of the fourth NMOS transistor NM4 is used to apply the input voltage. The gates of the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are electrically connected to the first switching circuit 1221 and the first voltage boosting circuit 123 at the third node 122a, respectively. The drain of the fourth NMOS transistor NM4 is electrically connected to the first switching circuit 1221, the second voltage boosting circuit 124 and the drain of the fourth PMOS transistor PM4 at the fourth node 122b, respectively. The source of the fourth PMOS transistor PM4 is used to output the target voltage.

[0120] When the control signal is the first level signal, please refer to [link / reference]. Figure 6 The fourth NMOS transistor NM4 is in the on state in response to the input voltage and the first multiplexed voltage of the third node 122a, the fourth PMOS transistor PM4 is in the off state in response to the first multiplexed voltage of the third node 122a, and the second NMOS transistor NM2 is in the on state in response to the second multiplexed voltage of the first node 121a. At this time, the fourth NMOS transistor NM4, capacitor C2 (second voltage boosting circuit 124) and the second NMOS transistor NM2 form a second loop. The input voltage is to charge capacitor C2 to generate the second multiplexed voltage at the fourth node 122b.

[0121] When the control signal is a first-level signal, the first multiplexed voltage of the third node 122a can control the second switching circuit 1222 to conduct the second circuit that charges the second voltage boosting circuit 124 with its input voltage, thereby generating a second multiplexed voltage at the fourth node 122b. When the control signal is a second-level signal, the first multiplexed voltage of the fourth node 122b can control the first switching circuit 1221 to conduct the first circuit that charges the first voltage boosting circuit 123 with its input voltage, thereby generating a second multiplexed voltage at the third node 122a. Therefore, this embodiment drives the charge pump 12 by directly generating multiplexed voltages at the circuit nodes (third node 122a and fourth node 122b), without the need for additional circuitry to generate the control signal required to drive the charge pump 12, thus simplifying the circuit structure and reducing power consumption.

[0122] To further illustrate the working principle of the charge pump 12 provided in the embodiments of the present invention, the following is a detailed explanation. Figure 5 and Figure 6 The charge pump 12 is described.

[0123] like Figure 5As shown, when the control signal is the second level signal (high level signal), the first PMOS transistor PM1 is in the off state in response to the high level signal, the first NMOS transistor NM1 is in the on state in response to the high level signal and pulls the voltage of the first node 121a to the third multiplexed voltage, the second NMOS transistor NM2 is in the off state in response to the third multiplexed voltage of the first node 121a, and the second PMOS transistor PM2 is in the on state in response to the third multiplexed voltage of the first node 121a and the input voltage, generating the second multiplexed voltage at the second node 121b. Capacitor C2, based on the second multiplexed voltage of the second node 121b, raises the voltage of the fourth node 122b from the second multiplexed voltage to the first multiplexed voltage. When the voltage is applied, the third NMOS transistor NM3 is in the on state in response to the first multiplexed voltage of the fourth node 122b and the input voltage, while the third PMOS transistor PM3 is in the off state in response to the first multiplexed voltage of the fourth node 122b. Thus, the input voltage charges the second capacitor C1 through the first circuit formed by the third NMOS transistor NM3, capacitor C2, and the first NMOS transistor, thereby generating the second multiplexed voltage at the third node 122a. The fourth PMOS transistor PM4 is in the on state in response to the second multiplexed voltage of the third node 122a and the first multiplexed voltage of the fourth node 122b, transmitting the first multiplexed voltage of the fourth node 122b, so as to output the target voltage at the source of the fourth PMOS transistor PM4.

[0124] like Figure 6 As shown, when the control signal is a first-level signal (low-level signal), the first PMOS transistor PM1 is in the on state in response to the low-level signal, and the first NMOS transistor NM1 is in the off state in response to the low-level signal. At this time, the first PMOS transistor PM1 generates a second multiplexed voltage at the first node 121a according to the input voltage. Capacitor C1 raises the voltage of the third node 122a from the second multiplexed voltage to the first multiplexed voltage according to the second multiplexed voltage of the first node 121a. The fourth NMOS transistor NM4 is in the on state in response to the first multiplexed voltage of the third node 122a and the input voltage. The fourth PMOS transistor PM4 is in the off state in response to the first multiplexed voltage of the third node 122a. In the off state, simultaneously, the second NMOS transistor NM2 is in the on state in response to the second multiplexed voltage of the first node 121a, and pulls the voltage of the second node 121b to the third multiplexed voltage. Thus, the input voltage charges the second capacitor C2 through the second circuit formed by the fourth NMOS transistor NM4, capacitor C2 and the second NMOS transistor NM2, so as to generate the second multiplexed voltage at the fourth node 122b. The third PMOS transistor PM3 is in the on state in response to the second multiplexed voltage of the fourth node 122b and the first multiplexed voltage of the third node 122a, and transmits the first multiplexed voltage of the third node 122a, so as to output the target voltage at the source of the third PMOS transistor PM3.

[0125] Finally, it should be noted that the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments are not intended to impose additional limitations on the content of the present invention; their purpose is to provide a more thorough and comprehensive understanding of the disclosure of the present invention. Furthermore, within the framework of the present invention, the above-mentioned technical features can be combined with each other, and many other variations of different aspects of the present invention as described above exist, all of which are considered to be within the scope of the present invention specification. Moreover, those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A charge pump, characterized in that, include: A first boost control circuit includes a first node and a second node. The first boost control circuit can be applied with an input voltage and a control signal. In response to the control signal and the input voltage, the first boost control circuit generates a first multiplexed signal at the first node and also generates a second multiplexed signal at the second node. The second boost control circuit includes a third node and a fourth node, and the second boost control circuit can be applied an input voltage; A first voltage boosting circuit is connected between the first node and the third node; A second voltage boosting circuit is connected between the second node and the fourth node; When the control signal is a first level signal, the first voltage boost circuit boosts the voltage of the third node to the first multiplexed voltage according to the first multiplexed signal. The second boost control circuit responds to the first multiplexed voltage of the third node and the input voltage, and outputs a target voltage. The target voltage is equal to N times the input voltage, where N is a positive number greater than 1. When the control signal is a second level signal, the second voltage boost circuit boosts the voltage of the fourth node to the first multiplexed voltage according to the second multiplexed signal. The second boost control circuit responds to the first multiplexed voltage of the fourth node and the input voltage, and outputs the target voltage.

2. The charge pump according to claim 1, characterized in that, The first boost control circuit includes: The first signal inverting circuit is electrically connected to the first voltage boosting circuit at the first node. It can be subjected to the control signal and the input voltage, and in response to the control signal and the input voltage, generates a first multiplexed signal at the first node. The second signal inverting circuit is electrically connected to the first signal inverting circuit and the first voltage boosting circuit at the first node, and is also electrically connected to the second voltage boosting circuit at the second node. It can be subjected to the input voltage and, in response to the input voltage and the first multiplexed signal, generates a second multiplexed signal at the second node.

3. The charge pump according to claim 2, characterized in that, The first signal inverting circuit is used to control the voltage of the first multiplexed signal to a second multiplexed voltage in response to the first level signal and the input voltage when the control signal is a first level signal. The first signal inverting circuit is also used to control the voltage of the first multiplexed signal to a third multiplexed voltage in response to the second level signal and the input voltage when the control signal is a second level signal. The first multiplexed voltage is greater than the second multiplexed voltage, and the second multiplexed voltage is greater than the third multiplexed voltage.

4. The charge pump according to claim 3, characterized in that, The second signal inverting circuit is used to control the voltage of the second multiplexed signal to be a third multiplexed voltage in response to the second multiplexed voltage and the input voltage when the first multiplexed signal is a second multiplexed voltage. The second signal inverting circuit is also used to control the voltage of the second multiplexed signal to be a second multiplexed voltage in response to the third multiplexed voltage and the input voltage when the first multiplexed signal is a third multiplexed voltage.

5. The charge pump according to claim 3, characterized in that, The second boost control circuit is used to control the second voltage boost circuit to generate a second multiplexed voltage at the fourth node in response to the first multiplexed voltage of the third node and the input voltage when the second multiplexed signal is a third multiplexed voltage. The second boost control circuit is used to control the first voltage boost circuit to generate a second multiplexed voltage at the third node in response to the first multiplexed voltage of the fourth node and the input voltage when the first multiplexed signal is a third multiplexed voltage.

6. The charge pump according to claim 5, characterized in that, When the voltage of the third node is the second multiplexing voltage, if the first multiplexing signal changes from the third multiplexing voltage to the second multiplexing voltage, the first voltage boosting circuit will boost the voltage of the third node from the second multiplexing voltage to the first multiplexing voltage according to the first multiplexing signal. When the voltage of the fourth node is the second multiplexing voltage, if the second multiplexing signal changes from the third multiplexing voltage to the second multiplexing voltage, the second voltage boosting circuit will boost the voltage of the fourth node from the second multiplexing voltage to the first multiplexing voltage according to the second multiplexing signal.

7. The charge pump according to claim 5, characterized in that, The second boost control circuit includes a first switching circuit and a second switching circuit; The first switching circuit, the second switching circuit, and the first voltage boosting circuit are connected together at the third node, and the first switching circuit, the second switching circuit, and the second voltage boosting circuit are connected together at the fourth node. Both the first switching circuit and the second switching circuit can be applied with an input voltage. The first switching circuit is used to output a target voltage in response to the first multiplexing voltage of the third node and the second multiplexing voltage of the fourth node. The second switching circuit is used to output a target voltage in response to the first multiplexing voltage of the fourth node and the second multiplexing voltage of the third node.

8. The charge pump according to claim 7, characterized in that, The first switching circuit, the first voltage boosting circuit, and the first signal inverting circuit can form a first loop. The first switching circuit is used to respond to the first multiplexed voltage of the fourth node and the input voltage when the control signal is a second level signal, and to turn on the first loop so that the input voltage charges the first voltage boosting circuit through the first loop to generate a second multiplexed voltage at the third node.

9. The charge pump according to claim 7, characterized in that, The second switching circuit, the second voltage boosting circuit, and the second signal inverting circuit can form a second loop. The second switching circuit is used to respond to the first multiplexed voltage of the third node and the input voltage when the control signal is a first level signal, and to turn on the second loop so that the input voltage charges the second voltage boosting circuit through the second loop to generate a second multiplexed voltage at the fourth node.

10. A low-dropout linear voltage regulator circuit, characterized in that, Includes the charge pump as described in any one of claims 1 to 9.

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