A low dropout linear voltage regulator

Abstract

This disclosure provides a low-dropout linear regulator (LDO), comprising: an error amplifier, a buffer, a power transistor, a voltage divider negative feedback unit, and a temperature detection unit. The error amplifier includes at least a first output load and a second output load, wherein the equivalent output impedance of the second output load is greater than the equivalent output impedance of the first output load. The temperature detection unit is used to detect the current operating ambient temperature. When the current operating ambient temperature is greater than or equal to a first temperature threshold, the temperature detection unit drives the error amplifier to use the second output load as the current output load. This disclosure performs real-time detection of the operating ambient temperature through the temperature detection unit. When the detected ambient temperature exceeds the temperature threshold, an enable signal is generated to drive the error amplifier to switch its output load, changing its current output load to an output load with a higher equivalent impedance. This improves the gain of the error amplifier, thereby increasing the loop gain and ultimately improving the accuracy of the LDO output voltage.

Description

Technical Field

[0001] This disclosure relates to the field of electronic equipment technology, and in particular to a low dropout linear regulator, a power management chip, and an electronic device. Background Technology

[0002] Low dropout regulators (LDOs), as core modules of power management chips, are widely used in mobile devices, automotive electronics, and industrial control. With the advancement of technology, electronic components in aerospace, automotive, and industrial control fields often face extreme temperature conditions, making the demand for LDO chips with high-temperature resistance increasingly prominent. However, at high temperatures, the carrier mobility of MOSFETs decreases, and the transconductance... The gain of the error amplifier decreases, thus reducing the gain of the error amplifier. The loop gain of the LDO decreases due to the influence of the error amplifier gain, which also decreases at high temperatures, resulting in a decrease in the accuracy of the LDO output voltage.

[0003] To address the aforementioned issues, a common technique involves designing an LDO with a process-temperature-aware (PT-aware) current source. When the process temperature varies from -20°C to 80°C, the PT-aware current serves as the tail current source for the error amplifier, biasing the input transistors of the error amplifier in the subthreshold region, thus generating PT-aware current. This maintains a stable bandwidth for the gain stage, ensuring the transient switching speed of the LDO system at different temperatures. However, the aforementioned PT-sensitive current source technology only maintains a constant bias current for the error amplifier, improving the bandwidth's susceptibility to temperature and the transient response at elevated temperatures. But the constant bias current... This causes the current to increase with temperature, which in turn causes the load output impedance of EA to decrease with increasing temperature, and the loop gain still decreases significantly with increasing temperature. Moreover, this solution is only effective in the normal temperature range of -20℃ to 80℃, and there is no data to support it for high temperature conditions above 125℃. It does not effectively improve the situation of LDO output accuracy deterioration at high temperatures. Summary of the Invention

[0004] The purpose of this disclosure is to provide a low dropout linear regulator, a power management chip, and an electronic device to solve the problems of reduced loop gain, reduced accuracy, and deteriorated performance of LDOs at high temperatures in the prior art.

[0005] The embodiments of this disclosure adopt the following technical solution: a low dropout linear regulator, comprising: an error amplifier, a buffer, a power transistor, a voltage divider negative feedback unit, and a temperature detection unit; wherein, the error amplifier includes at least a first output load and a second output load, the equivalent output impedance of the second output load being greater than the equivalent output impedance of the first output load; the temperature detection unit is used to detect the current operating ambient temperature of the low dropout linear regulator, when the current operating ambient temperature is less than a first temperature threshold, the temperature detection unit drives the error amplifier to use the first output load as the current output load, and when the current operating ambient temperature is greater than or equal to the first temperature threshold, the temperature detection unit drives the error amplifier to use the second output load as the current output load.

[0006] In some embodiments, the first temperature threshold is 125°C.

[0007] In some embodiments, the error amplifier includes: an input transistor pair unit, a load switching unit, a first output load, and a second output load; wherein the output terminal of the input transistor pair unit is connected to the input terminal of the load switching unit, the output terminal of the load switching unit is simultaneously connected to the input terminals of the first output load and the second output load, the output terminals of the first output load and the second output load are simultaneously connected to the output terminal of the error amplifier, and the control terminal of the load switching unit is connected to the output terminal of the temperature detection unit.

[0008] In some embodiments, the input transistor unit includes: a first current source, a first P-type transistor, a second P-type transistor, and a first to a fourth transistor; wherein, the gate of the first P-type transistor is connected to a reference voltage, the gate of the second P-type transistor is connected to a voltage divider resistor fed back by the voltage divider negative feedback unit, the sources of both the first and second P-type transistors are connected to the output terminal of the first current source, the drain of the first P-type transistor is connected to the collector of the first transistor, the collector of the first transistor is connected to the base of the first transistor, and the second P-type transistor... The drain of the first transistor is connected to the collector of the second transistor, the collector of the second transistor is connected to the base of the second transistor, the base of the third transistor is connected to the collector of the first transistor, and the base of the fourth transistor is connected to the collector of the second transistor. The emitters of all transistors from the first to the fourth are grounded. The load switching unit includes: a first switching transistor to a fourth switching transistor and a first inverter; wherein the source of the first switching transistor and the source of the third switching transistor are both connected to the collector of the third transistor, and the source of the second switching transistor and the source of the fourth switching transistor are both connected to the collector of the fourth transistor. The first output load comprises: a collector-connected inverter, the input terminal of the first inverter, the gate of the first switching transistor, and the gate of the second switching transistor, all connected to the output terminal of the temperature detection unit; the gates of the third and fourth switching transistors are also connected to the output terminal of the first inverter; the first output load comprises: a third P-type transistor, a fourth P-type transistor, a first N-type transistor, and a second N-type transistor; wherein the gates of the first N-type transistor and the second N-type transistor are both connected to a bias voltage; the source of the first N-type transistor is connected to the drain of the first switching transistor; the source of the second N-type transistor is connected to the drain of the second switching transistor; the drains of the first N-type transistor, the drains of the third P-type transistor, and the gates of the third P-type transistor are connected; the drain of the second N-type transistor is connected to the drain of the fourth P-type transistor and leads out to the output terminal of the first output load; the gate of the fourth P-type transistor is connected to the gate of the third P-type transistor; and the sources of the third P-type transistor and the fourth P-type transistor are connected to a power supply voltage; the second output load comprises: a fifth P-type transistor, a sixth P-type transistor, a third N-type transistor, and a fourth N-type transistor;In this configuration, the gates of the third N-type transistor and the fourth N-type transistor are both connected to a bias voltage. The source of the third N-type transistor is connected to the drain of the third switching transistor. The source of the fourth N-type transistor is connected to the drain of the fourth switching transistor. The drains of the third N-type transistor, the drains of the fifth P-type transistor, and the gate of the fifth P-type transistor are connected. The drain of the fourth N-type transistor is connected to the drain of the sixth P-type transistor and leads to the output terminal of the second output load. The gate of the sixth P-type transistor is connected to the gate of the fifth P-type transistor. The sources of the fifth P-type transistor and the sixth P-type transistor are connected to a power supply voltage.

[0009] In some embodiments, the transistor size in the first output load is different from the transistor size in the second output load, so that the equivalent output impedance of the second output load is greater than the equivalent output impedance of the first output load.

[0010] In some embodiments, the error amplifier further includes a compensation unit; the compensation unit includes a first capacitor, a second capacitor, and a transmission gate; the first plate of the first capacitor and the first plate of the second capacitor are both connected to the collector of the fourth transistor, the second plate of the first capacitor is connected to the output terminal of the low-dropout linear regulator, the second plate of the second capacitor is connected to the input terminal of the transmission gate, the output terminal of the transmission gate is connected to the output terminal of the low-dropout linear regulator, and the control terminal of the transmission gate is connected to the output terminal of the temperature detection unit.

[0011] In some embodiments, the temperature detection unit includes: a fifth transistor, a first voltage-dividing resistor, a second voltage-dividing resistor, a second current source, a fifth N-type transistor, a Schmitt trigger, and a second inverter; wherein, The collector of the fifth transistor is connected to the power supply voltage, the base of the fifth transistor is connected to a preset bias voltage, the emitter of the fifth transistor is connected to one end of the first voltage divider resistor, the other end of the first voltage divider resistor is connected to one end of the second voltage divider resistor, the other end of the second voltage divider resistor is grounded, the gate of the fifth N-type transistor is connected to one end of the second voltage divider resistor, the source of the fifth N-type transistor is grounded, the drain of the fifth N-type transistor, the output terminal of the second current source, and the input terminal of the Schmitt trigger are connected, the output terminal of the Schmitt trigger is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the temperature detection unit.

[0012] This disclosure also provides a power management chip, which includes at least the low dropout linear regulator described above.

[0013] This disclosure also provides an electronic device, which includes at least the power management chip described above.

[0014] The beneficial effects of this embodiment are as follows: the ambient temperature is detected in real time by the temperature detection unit. When the ambient temperature exceeds the temperature threshold, an enable signal is generated to drive the error amplifier to switch the output load, so that the current output load is switched to the output load with a higher equivalent impedance, thereby improving the gain of the error amplifier, thereby improving the loop gain and achieving the purpose of improving the output voltage accuracy of the LDO. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a common LDO structure in the prior art; Figure 2 This is a schematic diagram of the low-dropout linear regulator in the first embodiment of this disclosure; Figure 3 This is a schematic diagram of the error amplifier structure in the first embodiment of this disclosure; Figure 4 This is a circuit diagram of the temperature detection unit in the first embodiment of this disclosure; Figure 5 This is a schematic diagram showing the simulation results of the output voltage curves of a conventional LDO in the first embodiment of this disclosure and the LDO in this embodiment. Detailed Implementation

[0017] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0018] Figure 1The diagram illustrates a common LDO structure in the prior art, which mainly consists of an error amplifier EA, a buffer, a power transistor MPASS, and a voltage divider resistor for negative feedback. When the output voltage increases, the voltage divider resistor increases the voltage VFB, which is fed back to the positive terminal of EA, thereby controlling the output VEA to increase. After passing through the buffer, this controls VG to increase, which in turn reduces the PMOS power transistor current and VOUT, forming a negative feedback loop. When the temperature rises, the transconductance of the power transistor and the internal MOS of the operational amplifier increases. As the current decreases, the equivalent output resistance ROUT decreases, the loop gain Av decreases, and consequently, the LDO output voltage accuracy deteriorates.

[0019] To address the aforementioned problems, the first embodiment of this disclosure provides a low-dropout linear regulator. This low-dropout linear regulator has a temperature detection function and, combined with signal control, switches the output load in the error amplifier, thereby increasing the gain at high temperatures to stabilize the output voltage. Its schematic diagram is shown below. Figure 2 As shown, it mainly includes: an error amplifier EA, a buffer, a power transistor MPASS, a voltage divider negative feedback unit 10, and a temperature detection unit 20; wherein, the error amplifier EA includes at least a first output load ROUT1 and a second output load ROUT2, and the equivalent output impedance of the second output load ROUT2 is greater than the equivalent output impedance of the first output load ROUT1; the temperature detection unit 20 is used to detect the current operating ambient temperature of the low dropout linear regulator. When the current operating ambient temperature is less than a first temperature threshold, the temperature detection unit drives the error amplifier to use the first output load ROUT1 as the current output load. When the current operating ambient temperature is greater than or equal to the first temperature threshold, the temperature detection unit drives the error amplifier to use the second output load ROUT2 as the current output load.

[0020] In this embodiment, the first temperature threshold is typically set to 125°C. In actual implementation, the first temperature threshold can also be set independently according to the actual working environment requirements and accuracy requirements of the LDO. It should be noted that there is a positive correlation between the first temperature threshold and the equivalent output impedance of the second output load ROUT2. This embodiment does not limit the specific value of the equivalent output impedance of the second output load ROUT2. The specific value of the equivalent output impedance of the actual second output load ROUT2 can be determined according to the actual temperature threshold.

[0021] The error amplifier in this embodiment mainly includes an input transistor pair unit, a load switching unit, a first output load, and a second output load. The output terminal of the input transistor pair unit is connected to the input terminal of the load switching unit. The output terminal of the load switching unit is simultaneously connected to the input terminals of the first output load and the second output load. The output terminals of the first output load and the second output load are simultaneously connected to the output terminal of the error amplifier. The control terminal of the load switching unit is connected to the output terminal of the temperature detection unit to realize the switching between the first output load and the second output load based on the signal output by the temperature detection unit.

[0022] Figure 3 The following is a schematic diagram of the error amplifier in this embodiment. Figure 3 The specific implementation of the input transistor pair unit 31, the load switching unit 32, the first output load ROUT1, and the second output load ROUT2 is described below. Specifically, the input transistor pair unit includes: a first current source I1, a first P-type transistor PM1, a second P-type transistor PM2, and first transistors N1 to fourth transistors N4; wherein, the gate of the first P-type transistor PM1 is connected to the reference voltage VREF, the gate of the second P-type transistor PM2 is connected to the voltage divider resistor VFB fed back by the voltage divider negative feedback unit, and the sources of both the first P-type transistor PM1 and the second P-type transistor PM2 are connected to the output terminal of the first current source I1. The drain of transistor 1 is connected to the collector of transistor N1, the collector of transistor N1 is connected to the base of transistor N1, the drain of transistor PM2 is connected to the collector of transistor N2, the collector of transistor N2 is connected to the base of transistor N2, the base of transistor N3 is connected to the collector of transistor N1, the base of transistor N4 is connected to the collector of transistor N2, and the emitters of transistors N1 to N4 are all grounded.

[0023] The load switching unit 32 includes: a first switching transistor ND1 to a fourth switching transistor ND4 and a first inverter; wherein the source of the first switching transistor ND1 and the source of the third switching transistor ND3 are both connected to the collector of the third transistor N3, the source of the second switching transistor ND2 and the source of the fourth switching transistor ND4 are both connected to the collector of the fourth transistor N4, the input terminal of the first inverter INT1, the gate of the first switching transistor ND1 and the gate of the second switching transistor ND2 are both connected to the output terminal of the temperature detection unit 20 to receive the enable signal VD output by the temperature detection unit 20, and the gate of the third switching transistor ND3 and the gate of the fourth switching transistor ND4 are both connected to the output terminal of the first inverter INT1.

[0024] The first output load ROUT1 includes: a third P-type transistor PM3, a fourth P-type transistor PM4, a first N-type transistor NM1, and a second N-type transistor NM2; wherein the gate of the first N-type transistor NM1 and the gate of the second N-type transistor NM2 are both connected to a bias voltage VB, the source of the first N-type transistor NM1 is connected to the drain of the first switching transistor ND1, the source of the second N-type transistor NM2 is connected to the drain of the second switching transistor ND2, the drain of the first N-type transistor NM1, the drain of the third P-type transistor PM3, and the gate of the third P-type transistor PM3 are connected, the drain of the second N-type transistor NM2 is connected to the drain of the fourth P-type transistor PM4 and leads out the output terminal of the first output load, the gate of the fourth P-type transistor PM4 is connected to the gate of the third P-type transistor PM3, and the source of the third P-type transistor PM3 and the source of the fourth P-type transistor PM3 are connected to the power supply voltage VDD.

[0025] The second output load includes: a fifth P-type transistor PM5, a sixth P-type transistor PM6, a third N-type transistor NM3, and a fourth N-type transistor NM4; wherein, the gates of the third N-type transistor NM3 and the fourth N-type transistor NM4 are both connected to a bias voltage VB, the source of the third N-type transistor NM3 is connected to the drain of the third switching transistor ND3, the source of the fourth N-type transistor NM4 is connected to the drain of the fourth switching transistor ND4, the drains of the third N-type transistor NM3, the drains of the fifth P-type transistor PM5, and the gate of the fifth P-type transistor PM5 are connected, the drain of the fourth N-type transistor NM4 is connected to the drain of the sixth P-type transistor PM6 and leads out to the output terminal of the second output load, the gate of the sixth P-type transistor PM6 is connected to the gate of the fifth P-type transistor PM5, and the sources of the fifth P-type transistor PM5 and the sixth P-type transistor PM6 are connected to the power supply voltage VDD.

[0026] It is important to note that the output terminal of the second output load is connected to the output terminal of the first output load to form the output terminal VEA of the error amplifier EA. Meanwhile, the transistor sizes in the first output load and the second output load are different, so that the equivalent output impedance of the second output load is greater than that of the first output load. The specific values ​​or ratios of the transistor sizes in the first and second output loads need to be determined in conjunction with the first temperature threshold, transistor type, transistor fabrication process, etc. This embodiment will not provide a detailed explanation; in actual implementation, it can be determined through simulation and other methods combined with actual requirements.

[0027] During actual operation, ROUT1 and ROUT2 are controlled by the load switching unit, with only one set being active. Under normal operating temperature conditions (i.e., when the current operating ambient temperature is less than the first temperature threshold), ND1 and ND2 are open, while ND3 and ND4 are closed. This means that the first load set ROUT1 is active, while the second set ROUT2 is closed, maintaining the normal gain of EA and the loop. However, under high temperature conditions (i.e., when the current operating ambient temperature is greater than or equal to the first temperature threshold), the VD switching switch state causes ND1 and ND2 to close, while ND3 and ND4 are open. This closes the first load set ROUT1 and makes the second set ROUT2 active, increasing the equivalent impedance of EA output, increasing EA gain and loop gain, compensating for gain attenuation at high temperatures, and thus maintaining the output accuracy of the LDO.

[0028] In some embodiments, the error amplifier further includes a compensation unit 33, such as Figure 3 As shown, the compensation unit 33 can adopt a Cascode compensation structure, including: a first capacitor C1, a second capacitor C2, and a transmission gate TG; the first plates of the first and second capacitors are both connected to the collector of the fourth transistor, the second plate of the first capacitor is connected to the output terminal of the low-dropout linear regulator, the second plate of the second capacitor is connected to the input terminal of the transmission gate, the output terminal of the transmission gate is connected to the output terminal of the low-dropout linear regulator, and the control terminal of the transmission gate is connected to the output terminal of the temperature detection unit. Since ND1 to ND4 are switching transistors, they can be considered as a short circuit during operation. Therefore, the compensation capacitor is located between the bottom current mirrors N3 and N4 and the Cascode transistors NM1 to NM4, with the other end connected to the LDO output voltage VOUT. Under normal circumstances, capacitor C1 is effective and C2 is ineffective. At high temperatures, as the output load switches, the transmission gate on the right side of C2 opens, and C1 and C2 are effective simultaneously, thereby maintaining the stability of the loop at high temperatures.

[0029] It should be noted that the error amplifier used in this embodiment is a symmetrical OTA error amplifier. Figure 3 This is a structural optimization based on the conventional standard symmetrical OTA error amplifier structure. When using other types of error amplifiers in practice, the same improvement idea can be used to improve other types of error amplifiers so that they have at least two different loads and can perform load switching function according to temperature conditions.

[0030] The enable signal VD of the load switching unit of the error amplifier is generated by the temperature detection unit 20, and its circuit schematic is shown below. Figure 4As shown, it mainly includes: a fifth transistor N5, a first voltage divider resistor RT1, a second voltage divider resistor RT2, a second current source I2, a fifth N-type transistor NM5, a Schmitt trigger ST, and a second inverter INT2; wherein, the collector of the fifth transistor N5 is connected to the power supply voltage VDD, the base of the fifth transistor N5 is connected to the preset bias voltage VB, the emitter of the fifth transistor N5 is connected to one end of the first voltage divider resistor RT1, the other end of the first voltage divider resistor RT1 is connected to one end of the second voltage divider resistor RT2, the other end of the second voltage divider resistor RT2 is grounded, the gate of the fifth N-type transistor NM5 is connected to one end of the second voltage divider resistor RT2, the source of the fifth N-type transistor NM5 is grounded, the drain of the fifth N-type transistor NM5, the output terminal of the second current source I2 is connected to the input terminal of the Schmitt trigger ST, the output terminal of the Schmitt trigger ST is connected to the input terminal of the second inverter INT2, and the output terminal of the second inverter INT2 serves as the output terminal of the temperature detection unit 20, outputting an enable signal VD. In this embodiment, the base of N5 is fixed biased with VB. VB drops across the two voltage divider resistors below after passing through VBE. After voltage division, it generates the gate voltage VGT of NM5 on the right, thereby controlling the current of NM5. When the temperature rises, VBE of N5 decreases, thus increasing the gate voltage of NM5. At the same time, VTH of NM5 decreases, and the current of NM5 increases, exceeding the current of the top current source. This pulls down the current, lowering the comparator node VT. The output is then shaped by a Schmitt trigger and an inverter. Here, the Schmitt trigger prevents the chip temperature from constantly switching and flickering near the over-temperature point, thus improving the reliability of the circuit.

[0031] In some embodiments, the temperature detection unit can also be configured to configure multiple temperature thresholds and output multiple or more different enable signals according to the temperature range of the current working environment temperature. At the same time, the error amplifier is configured with output loads corresponding to different temperature ranges, and the switching of different output loads is achieved by combining different enable signals, so as to achieve more precise error amplifier gain control.

[0032] Assuming VFB=VOUT=1.2V, Figure 5 Simulation results of the output voltage VOUT curves of a conventional LDO and the LDO of this embodiment are shown. Based on Figure 5 It can be seen that in this embodiment, the curve of VOUT changing with temperature is significantly tightened when the LDO is at a high temperature of 125°C and above. Taking heavy load ILOAD=100mA as an example, when there is no high temperature load switching, the VOUT curve has a significant shift and decrease in accuracy at temperatures of 125°C and above, while the curve with high temperature load switching is flattened at 125°C, which effectively suppresses the trend of VOUT accuracy deterioration.

[0033] This embodiment uses a temperature detection unit to detect the ambient temperature in real time. When the ambient temperature exceeds the temperature threshold, an enable signal is generated to drive the error amplifier to switch the output load, so that the current output load is switched to an output load with a higher equivalent impedance, thereby improving the gain of the error amplifier, and thus improving the loop gain, and achieving the purpose of improving the output voltage accuracy of the LDO.

[0034] Based on the same inventive concept, the second embodiment of this disclosure provides a power management chip, which includes at least the low dropout linear regulator provided in the first embodiment of this disclosure. Through the low dropout linear regulator with an error amplifier that improves the gain by output load switching and a temperature detection circuit, the power management chip can have a stable output even in high-temperature environments, ensuring stable power supply to the load.

[0035] Based on the same inventive concept, the third embodiment of this disclosure provides an electronic device, which includes at least the power management chip provided in the second embodiment of this disclosure, in order to ensure stable operation of the device in a high-temperature environment.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A low-dropout linear regulator, characterized in that, include: The system includes an error amplifier, a buffer, a power transistor, a voltage divider negative feedback unit, and a temperature detection unit; among which, The error amplifier includes at least a first output load and a second output load, wherein the equivalent output impedance of the second output load is greater than the equivalent output impedance of the first output load; The temperature detection unit is used to detect the current operating ambient temperature of the low dropout linear regulator. When the current operating ambient temperature is less than a first temperature threshold, the temperature detection unit drives the error amplifier to use the first output load as the current output load. When the current operating ambient temperature is greater than or equal to the first temperature threshold, the temperature detection unit drives the error amplifier to use the second output load as the current output load.

2. The low-dropout linear regulator according to claim 1, characterized in that, The first temperature threshold is 125°C.

3. The low-dropout linear regulator according to claim 1, characterized in that, The error amplifier includes: The system includes an input transistor unit, a load switching unit, a first output load, and a second output load; among which... The output terminal of the input transistor unit is connected to the input terminal of the load switching unit. The output terminal of the load switching unit is simultaneously connected to the input terminals of the first output load and the second output load. The output terminals of the first output load and the second output load are simultaneously connected to the output terminal of the error amplifier. The control terminal of the load switching unit is connected to the output terminal of the temperature detection unit.

4. The low-dropout linear regulator according to claim 3, characterized in that, The input transistor unit includes: a first current source, a first P-type transistor, a second P-type transistor, and a first to a fourth transistor; wherein, the gate of the first P-type transistor is connected to a reference voltage, the gate of the second P-type transistor is connected to a voltage divider resistor fed back by the voltage divider negative feedback unit, the sources of the first P-type transistor and the second P-type transistor are both connected to the output terminal of the first current source, the drain of the first P-type transistor is connected to the collector of the first transistor, the collector of the first transistor is connected to the base of the first transistor, the drain of the second P-type transistor is connected to the collector of the second transistor, the collector of the second transistor is connected to the base of the second transistor, the base of the third transistor is connected to the collector of the first transistor, the base of the fourth transistor is connected to the collector of the second transistor, and the emitters of the first to fourth transistors are all grounded; The load switching unit includes: a first switching transistor to a fourth switching transistor and a first inverter; wherein the source of the first switching transistor and the source of the third switching transistor are both connected to the collector of the third transistor, the source of the second switching transistor and the source of the fourth switching transistor are both connected to the collector of the fourth transistor, the input terminal of the first inverter, the gate of the first switching transistor and the gate of the second switching transistor are both connected to the output terminal of the temperature detection unit, and the gate of the third switching transistor and the gate of the fourth switching transistor are both connected to the output terminal of the first inverter; The first output load includes: a third P-type transistor, a fourth P-type transistor, a first N-type transistor, and a second N-type transistor; wherein the gates of the first N-type transistor and the second N-type transistor are both connected to a bias voltage, the source of the first N-type transistor is connected to the drain of the first switching transistor, the source of the second N-type transistor is connected to the drain of the second switching transistor, the drains of the first N-type transistor, the drains of the third P-type transistor, and the gate of the third P-type transistor are connected, the drain of the second N-type transistor is connected to the drain of the fourth P-type transistor and leads out to the output terminal of the first output load, the gate of the fourth P-type transistor is connected to the gate of the third P-type transistor, and the sources of the third P-type transistor and the fourth P-type transistor are connected to a power supply voltage; The second output load includes: a fifth P-type transistor, a sixth P-type transistor, a third N-type transistor, and a fourth N-type transistor; wherein the gates of the third N-type transistor and the fourth N-type transistor are both connected to a bias voltage, the source of the third N-type transistor is connected to the drain of the third switching transistor, the source of the fourth N-type transistor is connected to the drain of the fourth switching transistor, the drains of the third N-type transistor, the drains of the fifth P-type transistor, and the gate of the fifth P-type transistor are connected, the drain of the fourth N-type transistor is connected to the drain of the sixth P-type transistor and leads out to the output terminal of the second output load, the gate of the sixth P-type transistor is connected to the gate of the fifth P-type transistor, and the sources of the fifth P-type transistor and the sixth P-type transistor are connected to a power supply voltage.

5. The low-dropout linear regulator according to claim 4, characterized in that, The transistor size in the first output load is different from that in the second output load, so that the equivalent output impedance of the second output load is greater than that of the first output load.

6. The low-dropout linear regulator according to claim 4, characterized in that, The error amplifier further includes a compensation unit; the compensation unit includes a first capacitor, a second capacitor, and a transmission gate; the first plate of the first capacitor and the first plate of the second capacitor are both connected to the collector of the fourth transistor, the second plate of the first capacitor is connected to the output terminal of the low-dropout linear regulator, the second plate of the second capacitor is connected to the input terminal of the transmission gate, the output terminal of the transmission gate is connected to the output terminal of the low-dropout linear regulator, and the control terminal of the transmission gate is connected to the output terminal of the temperature detection unit.

7. The low-dropout linear regulator according to any one of claims 1 to 6, characterized in that, The temperature detection unit includes: a fifth transistor, a first voltage-dividing resistor, a second voltage-dividing resistor, a second current source, a fifth N-type transistor, a Schmitt trigger, and a second inverter; wherein, The collector of the fifth transistor is connected to the power supply voltage, the base of the fifth transistor is connected to a preset bias voltage, the emitter of the fifth transistor is connected to one end of the first voltage divider resistor, the other end of the first voltage divider resistor is connected to one end of the second voltage divider resistor, the other end of the second voltage divider resistor is grounded, the gate of the fifth N-type transistor is connected to one end of the second voltage divider resistor, the source of the fifth N-type transistor is grounded, the drain of the fifth N-type transistor, the output terminal of the second current source, and the input terminal of the Schmitt trigger are connected, the output terminal of the Schmitt trigger is connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the temperature detection unit.

8. A power management chip, characterized in that, It includes at least the low-dropout linear regulator as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, It includes at least the power management chip as described in claim 8.

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