Power conversion circuit and electronic device

Abstract

The embodiment of the application discloses a power conversion circuit and electronic equipment, the power conversion circuit includes first buck circuit, second buck circuit, first low dropout linear regulator, switch logic module and switch; the switch logic module is used for generating corresponding switch signal according to the pulse width modulation frequency that first buck circuit and second buck circuit output respectively; the switch is used for switching to the first gear according to the switch signal generated by the switch logic module, to connect the voltage input end of the second buck circuit to the voltage output end of the first buck circuit, or the switch is used for switching to the second gear according to the switch signal generated by the switch logic module, to connect the voltage input end of the second buck circuit to the voltage output end of the first low dropout linear regulator. The power conversion circuit and electronic equipment disclosed by the embodiment of the application can realize power noise reduction without increasing additional power loss of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, in particular to a power conversion circuit and an electronic device. BACKGROUND

[0002] At present, ceramic capacitors are widely used in the design of notebook computer mainboards. The ceramic capacitors can stabilize voltage and reduce voltage ripple at the output end of the notebook computer mainboard power supply circuit. However, when the power supply circuit is in light load, in order to improve the conversion efficiency of the power supply, the pulse width modulation (PWM) frequency is reduced to the range that can be heard by human ears, and the ceramic capacitor generates high-frequency noise. The prior art usually sets the PWM frequency of the power supply circuit to a fixed frequency mode and controls the PWM frequency outside the range that can be heard by human ears, but this method reduces the conversion efficiency of the power supply and additionally causes excessive power loss. SUMMARY

[0003] Embodiments of the present application disclose a power conversion circuit and an electronic device, which can realize power noise reduction without increasing additional power loss of the circuit.

[0004] Embodiments of the present application disclose a power conversion circuit, characterized in that the power conversion circuit comprises a first buck circuit, a second buck circuit, a first low-dropout linear regulator, a switch logic module and a switch; an output voltage of the first buck circuit is higher than an output voltage of the second buck circuit; the switch logic module is connected with the first buck circuit and the second buck circuit respectively, and the switch is connected with the switch logic module;

[0005] The switch logic module is configured to generate corresponding switch signals according to pulse width modulation frequencies respectively output by the first buck circuit and the second buck circuit.

[0006] The switch is configured to switch to a first gear according to the switch signals generated by the switch logic module, so as to connect a voltage input end of the second buck circuit to a voltage output end of the first buck circuit; or

[0007] The switch is configured to switch to a second gear according to the switch signals generated by the switch logic module, so as to connect the voltage input end of the second buck circuit to a voltage output end of the first low-dropout linear regulator.

[0008] As an optional implementation, the power conversion circuit is characterized in that the switch logic module is configured to generate a first switch signal for switching the switch to the first gear when it is detected that the pulse width modulation frequency of the first buck circuit is less than a frequency threshold.

[0009] As an optional implementation, the power conversion circuit, characterized in that the switch logic module is configured to generate a second switch signal for switching the switch to the second gear when it is detected that the pulse width modulation frequency of the second voltage reduction circuit is less than the frequency threshold.

[0010] As an optional implementation, the power conversion circuit, characterized in that the second voltage reduction circuit comprises a driving module, an HMOS tube and an LMOS tube; the driving module is configured to control the HMOS tube to open and the LMOS tube to close when the switch is switched to the second gear.

[0011] As an optional implementation, the power conversion circuit, characterized in that the switch is further configured to connect the voltage input ends of the first voltage reduction circuit and the second voltage reduction circuit to the voltage output end of the external power supply when the switch is switched to the third gear according to the switch signal generated by the switch logic module.

[0012] As an optional implementation, the power conversion circuit, characterized in that the power conversion circuit further comprises a first current detection module;

[0013] The first current detection module is configured to generate a first detection signal when it is detected that the difference between the output current of the first voltage reduction circuit and the input current of the first low dropout linear regulator is greater than a first current threshold.

[0014] The switch logic module is further configured to generate a third switch signal for switching the switch to the third gear according to the first detection signal when the switch is switched to the first gear.

[0015] As an optional implementation, the power conversion circuit, characterized in that the voltage output end of the first voltage reduction circuit is connected to the voltage input end of the first low dropout linear regulator.

[0016] As an optional implementation, the power conversion circuit, characterized in that the power conversion circuit further comprises a second current detection module;

[0017] The second current detection module is configured to generate a second detection signal when it is detected that the current flowing through the HMOS tube included in the second voltage reduction circuit is greater than a second current threshold.

[0018] The switch logic module is further configured to generate a third switch signal for switching the switch to the third gear according to the second detection signal.

[0019] As an optional implementation, the power conversion circuit, characterized in that the switch logic module is further configured to generate a third switch signal for switching the switch to the third gear when it is detected that the pulse width modulation frequencies of the first and second voltage reduction circuits are both greater than the frequency threshold.

[0020] The embodiments of the present application disclose an electronic device, comprising any one of the power conversion circuits disclosed by the embodiments of the present application.

[0021] Compared with the related art, the embodiments of the present application have the following beneficial effects:

[0022] The embodiments of the present application disclose a power conversion circuit, which comprises a switch logic module capable of generating corresponding switch signals according to the pulse width modulation frequencies output by a first voltage reduction circuit and a second voltage reduction circuit; according to the switch signals generated by the switch logic module, the switch can be switched to a first gear to connect the voltage input end of the second voltage reduction circuit to the voltage output end of the first voltage reduction circuit; or, the switch can be switched to a second gear to connect the voltage input end of the second voltage reduction circuit to the voltage output end of the first low-dropout linear voltage regulator.

[0023] It can be seen that, by using the power conversion circuit disclosed by the embodiments of the present application, in the case that the power supply circuit is in light load, the connection between the voltage input end and the voltage output end of the first voltage reduction circuit and the second voltage reduction circuit can be changed by switching different gears, so as to change the PWM frequency of the voltage reduction circuit, so that the power supply noise jumps out of the audible frequency range of human ears, while the conversion efficiency is guaranteed unchanged and no additional power loss is generated. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 is a structural schematic diagram of a power conversion circuit disclosed by the embodiments of the present application;

[0026] Figure 2 is a structural schematic diagram of another power conversion circuit disclosed by the embodiments of the present application;

[0027] Figure 3 is a structural schematic diagram of another power conversion circuit disclosed by the embodiments of the present application;

[0028] Figure 4is a structural schematic diagram of another power conversion circuit disclosed by the embodiment of the present application.

[0029] Figure 5 is a structural schematic diagram of an electronic device disclosed by the embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] It should be noted that the terms "comprising" and "having" and any variations thereof in the embodiments of the present application and the drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to the process, method, product or device.

[0032] The embodiments of the present application disclose a power conversion circuit and an electronic device, which can realize power noise reduction without increasing additional power consumption of a circuit.

[0033] The technical solutions of the present application will be described in detail below in conjunction with specific embodiments.

[0034] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a power conversion circuit disclosed by the embodiment of the present application. The power conversion circuit disclosed by the embodiment of the present application can be applied to the power mainboard design of a notebook computer, but is not limited thereto. The power conversion circuit at least includes a first voltage reduction circuit 101, a second voltage reduction circuit 102, a switch logic module 103, a switch 104 and a first low-dropout linear voltage regulator 105, wherein:

[0035] The output voltage of the first voltage reduction circuit 101 is higher than the output voltage of the second voltage reduction circuit 102.

[0036] The switch logic module 103 is connected with the first voltage reduction circuit 101 and the second voltage reduction circuit 102 respectively, and the switch logic module 103 can generate corresponding switch signals according to the pulse width modulation frequencies respectively output by the first voltage reduction circuit 101 and the second voltage reduction circuit 102.

[0037] The switch 104 is connected with the switch logic module 103.

[0038] The switch 104 can be switched to the first gear according to the switch signal generated by the switch logic module 103, so as to connect the voltage input end of the second voltage reduction circuit 102 to the voltage output end of the first voltage reduction circuit 101; or,

[0039] The switch 104 can be switched to the second gear according to the switch signal generated by the switch logic module 103, so as to connect the voltage input end of the second voltage reduction circuit 102 to the voltage output end of the first low dropout linear regulator 105.

[0040] In some embodiments, the output voltage of the first voltage reduction circuit 101 can be 5 volts, and the output voltage of the second voltage reduction circuit 102 can be 3.3 volts. Among them, the output voltage of the first low dropout linear regulator 105 and the first voltage reduction circuit 101 can be the same.

[0041] The voltage reduction circuit, also known as the voltage reduction type BUCK circuit, is a direct current to direct current conversion circuit, the output voltage is lower than the input voltage, and has the effect of reducing the voltage difference of the circuit, which can avoid the damage of the circuit caused by too high voltage. The voltage reduction type BUCK circuit is widely used in mobile phones, computers and other electronic products.

[0042] It should be further pointed out that the switch 104 can include but is not limited to a two-gear switch or a three-gear switch.

[0043] The pulse width modulation (PWM) frequency is the ratio of the on time to the cycle time in a period, usually called the duty cycle. The more the on time, the greater the frequency.

[0044] In some embodiments, the low dropout regulator (LDO) has the advantages of low cost, low noise and small static current compared with traditional linear voltage regulators. The chips of traditional linear voltage regulators require that the input voltage be at least 2V-3V higher than the output voltage, otherwise they cannot work normally. But in some cases, such as converting 5-volt voltage to 3.3-volt voltage, the voltage difference between the input and the output is only 1.7v, which cannot meet the working conditions of traditional linear voltage regulators. For this situation, the LDO type voltage conversion chip can solve this problem. The LDO chip can include AMS1117, spx3819, TLV702x.

[0045] It can be seen that, in general, in the power supply circuit design of a notebook computer, the voltage output end of the power conversion circuit usually uses a ceramic capacitor to stabilize the voltage and reduce the voltage ripple. When the load of the power conversion circuit is light, in order to improve the conversion efficiency, the PWM frequency is reduced to within the range that can be heard by the human ear, that is, within 20Khz. The power conversion circuit disclosed in the embodiments of the present application, in the case of light load of the power supply circuit, is switched to different gears by the switch 104, flexibly changes the connection of the voltage output end of the first voltage reduction circuit 101 and the voltage input end of the second voltage reduction circuit 102, thereby changing the PWM frequency of the voltage reduction circuit, so that the power supply noise jumps out of the audio range that can be heard by the human ear, while ensuring that the conversion efficiency remains unchanged and no additional power loss is generated.

[0046] For further reference Figure 2 In one embodiment, the switch logic module 103 is connected with the first voltage reduction circuit 101, and the switch logic module 103 can generate a corresponding switch signal according to the pulse width modulation frequency output by the first voltage reduction circuit 101.

[0047] The switch logic module 103 can be used to generate a first switch signal for switching the switch 104 to the first gear when it is detected that the pulse width modulation frequency of the first voltage reduction circuit 101 is less than the frequency threshold.

[0048] The switch 104 is connected with the switch logic module 103, and the switch 104 can be switched to the first gear according to the first switch signal generated by the switch logic module 103, so as to connect the voltage input end of the second voltage reduction circuit 102 to the voltage output end of the first voltage reduction circuit 101.

[0049] The power conversion circuit can further include at least a first current detection module 107.

[0050] The first current detection module 107 can be used to generate a first detection signal when it is detected that the difference between the output current of the first voltage reduction circuit 101 and the input current of the first low dropout linear voltage regulator 105 is greater than the first current threshold.

[0051] The switch logic module 103 can be used to generate a third switch signal for switching the switch 104 to the third gear according to the first detection signal when the switch 104 is switched to the first gear.

[0052] The switch 104 can also be used to connect the voltage input ends of the first voltage reduction circuit 101 and the second voltage reduction circuit 102 to the voltage output end of the external power supply 106 when the switch 104 is switched to the third gear according to the third switch signal generated by the switch logic module 103.

[0053] The switch logic module 103 can be configured to generate a third switch signal for switching the switch 104 to the third gear when it is detected that the pulse width modulation frequencies of the first and second voltage reduction circuits 101 and 102 are both greater than a frequency threshold.

[0054] The state in which the pulse width modulation frequencies of the first and second voltage reduction circuits 101 and 102 are both greater than the frequency threshold is a normal working state of the circuit, and the switch 104 is in the third gear at this time. The voltage input ends of the first and second voltage reduction circuits 101 and 102 can be connected to the external power supply 106.

[0055] It should be further noted that the frequency threshold can be 20Khz. Because the maximum frequency at which the human ear can hear sound is 20Khz. For example, when the load connected to the first voltage reduction circuit 101 is in a light load state, the PWM frequency is reduced to within 20Khz, and the ceramic capacitor at the output end of the circuit produces high-frequency noise audible to the human ear. In view of this situation, in the power switching circuit of the embodiment of the present application, the switch 104 can be switched to the first gear, i.e. the voltage input end of the second voltage reduction circuit 102 can be connected to the voltage output end of the first voltage reduction circuit 101. By using the output voltage of the first voltage reduction circuit 101 as the input voltage of the second voltage reduction circuit 102, the load of the first voltage reduction circuit 101 will increase, and the PWM frequency will rise above 20KHz, out of the range of human audible frequency, so that the ceramic capacitor at the voltage output end of the first voltage reduction circuit 101 is prevented from emitting noise.

[0056] Since the PWM frequency of the first voltage reduction circuit 101 is lower than 20KHz, it means that the original load is very light, so even if the load of the second voltage reduction circuit 102 is relatively heavy, the first voltage reduction circuit 101 can fully bear the input voltage of the second voltage reduction circuit 102.

[0057] The first current detection module 107 can be configured to generate a first detection signal when it is detected that the difference between the output current of the first buck circuit 101 and the input current of the first low-dropout linear regulator 105 is greater than a first current threshold. For example, the first current threshold can be 1 ampere, which is not limited in particular. For example, when the difference between the output current of the first buck circuit 101 and the input current of the first low-dropout linear regulator 105 is greater than 1 ampere, it means that even if the first buck circuit 101 does not serve as the input voltage of the second buck circuit 102, the load of the first buck circuit 101 itself can cause the PWM frequency to exceed the frequency threshold, in which case the switch 104 is switched to the second gear, the voltage input end of the second buck circuit 102 is connected to the voltage output end of the external power supply 106, and the normal working state is restored. The output current of the first buck circuit 101 and the input current of the first low-dropout linear regulator 105 can be detected by a current detection module, and then a difference value can be obtained by a subtractor.

[0058] The above embodiment can be applied to the case where the first buck circuit 101 is in a light load state and the load of the second buck circuit 102 is heavy.

[0059] In some embodiments, when the first buck circuit 101 is in a light load state and the second buck circuit 102 is also in a light load state, the switch 104 is switched to the second gear, which can be specifically referred to in Figure 3 .

[0060] It can be seen that when the first buck circuit 101 is in a light load state, the switch 104 is switched to the first gear, so that the first buck circuit 101 can bear part of the load of the second buck circuit 102, so that the load state is switched from the light load state to the normal load state. Therefore, the power conversion circuit will not reduce the PWM frequency to the range that can be heard by the human ear in order to improve the conversion efficiency. The power conversion circuit of the embodiment of the present application can realize power noise reduction and also guarantee the original conversion efficiency.

[0061] Please refer to Figure 3 , the second buck circuit 102 can at least include an LMOS tube 1021, an HMOS tube 1022, a driving module 1023, and a second current detection module 1024.

[0062] The switch logic module 103 is connected with the second buck circuit 102, and the switch logic module 103 can generate a corresponding switch signal according to the pulse width modulation frequency output by the second buck circuit 102.

[0063] The switch logic module 103 can be configured to generate a second switch signal for switching the switch 104 to the second gear when it is detected that the pulse width modulation frequency of the second buck circuit 102 is less than the frequency threshold.

[0064] The switch 104 is connected with the switch logic module 103.

[0065] The switch 104 can be switched to the second gear according to the second switch signal generated by the switch logic module 103, so as to connect the voltage input end of the second buck circuit 102 to the voltage output end of the first low-dropout linear regulator 105.

[0066] The drive module 1023 can be used to control the HMOS tube 1022 to be turned on and the LMOS tube 1021 to be turned off when the switch 104 is switched to the second gear.

[0067] The voltage output end of the first buck circuit 101 can be connected with the voltage input end of the first low-dropout linear regulator 105.

[0068] The power conversion circuit can further include a second current detection module 108.

[0069] The second current detection module 108 can be used to generate a second detection signal when it is detected that the current flowing through the HMOS tube 1022 included in the second buck circuit 102 is greater than a second current threshold value.

[0070] The switch logic module 103 can be used to generate a third switch signal for switching the switch 104 to the third gear according to the second detection signal.

[0071] The switch 104 can also be used to connect the voltage input ends of the first buck circuit 101 and the second buck circuit 102 to the voltage output end of the external power supply 106 when it is switched to the third gear according to the third switch signal generated by the switch logic module 103.

[0072] The switch logic module 103 can be used to generate a third switch signal for switching the switch 104 to the third gear when it is detected that the pulse width modulation frequencies of the first buck circuit 101 and the second buck circuit 102 are both greater than a frequency threshold value.

[0073] The state in which the pulse width modulation frequencies of the first buck circuit 101 and the second buck circuit 102 are both greater than the frequency threshold value is the normal working state of the circuit, and at this time the switch 104 is in the third gear. The voltage input ends of the first buck circuit 101 and the second buck circuit 102 can be connected to the external power supply 106.

[0074] It should be further explained that when the load connected to the second voltage reduction circuit 102 is in a light load state, the PWM frequency is reduced to within the frequency threshold, and the ceramic capacitor at the output of the circuit produces high-frequency noise audible to the human ear. In the case where the PWM frequency is lower than 20 kHz, the load current is usually in the order of milliamperes. In the power switching circuit of the embodiment of the present application, the switch 104 can be switched to the second gear, i.e. the voltage input of the second voltage reduction circuit 102 can be connected to the voltage output of the first low-dropout linear regulator 105, at the same time, the HMOS tube included in the second voltage reduction circuit is turned on and the LMOS is turned off, i.e. the second voltage reduction circuit stops the PWM pulse and the first low-dropout linear regulator 105 supplies power externally. The input voltage of the first low-dropout linear regulator 105 is actually the voltage output of the first voltage reduction circuit 101. For example, the output voltage of the first voltage reduction circuit 101 is 5 volts, and the output voltage of the second voltage reduction circuit 102 is 3.3 volts. In this case, the conversion efficiency of the first low-dropout linear regulator 105 is 3.3 / 5 = 66%, which is basically the same as the conversion efficiency when the second voltage reduction circuit is in a light load state, and does not cause excessive power loss.

[0075] For example, the second current threshold can be 0.5 amperes. When the current flowing through the HMOS tube 1022 included in the second voltage reduction circuit 102 is greater than the second current threshold, it means that in this case even if the voltage input of the second voltage reduction circuit 102 is not connected to the voltage output of the first low-dropout linear regulator 105, the load of the second voltage reduction circuit 102 itself can cause the PWM frequency to exceed the frequency threshold. In this case, the switch 104 is switched to the third gear, the voltage input of the second voltage reduction circuit 102 is connected to the voltage output of the external power supply 106, and the normal working state is restored.

[0076] In some embodiments, if both the first voltage reduction circuit 101 and the second voltage reduction circuit 102 are in a light load state, i.e. the PWM frequency is reduced to within the frequency threshold, the ceramic capacitor at the output of the circuit produces high-frequency noise audible to the human ear. In this case, the switch 104 is switched to the second gear, the second voltage reduction circuit 102 stops the PWM pulse, and the output voltage is supplied by the first low-dropout linear regulator 105, which can keep the circuit conversion efficiency unchanged. However, because the input voltage of the first low-dropout linear regulator 105 is actually the output voltage of the first voltage reduction circuit 101, at this time, the load of the first voltage reduction circuit 101 is increased because of the additional output of the first low-dropout linear regulator 105, and the PWM frequency will jump out of the audible frequency range of the human ear, so that the high-frequency noise of the ceramic capacitors at the outputs of the first voltage reduction circuit and the second voltage reduction circuit disappears.

[0077] When the loads of the first buck circuit 101 and the second buck circuit 102 are both heavy, the PWM frequencies of the first buck circuit 101 and the second buck circuit 102 both exceed the frequency threshold, the switch 104 is switched to the third gear, and the input voltages of the first buck circuit 101 and the second buck circuit 102 are both the external power supply 106. When the PWM frequency exceeds 20 KHz, the noise generated by the power conversion circuit cannot be heard by the human ear.

[0078] As can be seen, in the embodiment of the present application, when the second buck circuit 102 is in a light load state, the second buck circuit 102 can stop the PWM pulse and the first low dropout linear regulator 105 is used to supply power externally. In this case, the conversion efficiency of the power conversion circuit is basically the same as that in the original light load state, and no additional high loss is caused, and power noise reduction can be achieved.

[0079] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of another power conversion circuit disclosed in the embodiment of the present application. For example, the power supply architecture of a notebook computer can include two groups of DC power conversion circuits of 3.3 volts and 5 volts, and therefore a dual-channel power management chip solution can be used. The power management chip can be TPS51285 of TI or RT8249 of RICHTEK.

[0080] In some embodiments, the power management chip can include two groups of BUCK line controllers, such as Figure 4 Channel 1 BUCK Controller and Channel 2 BUCK Controller in the above, which can be used to form two groups of DC power conversion circuits with different output voltages together with peripheral MOS, inductors, capacitors, resistors and other components, which are the first buck circuit 101 and the second buck circuit 102. The output voltage of the first buck circuit can be 5 volts, and the output voltage of the second buck circuit can be 3.3 volts. Due to the power supply state and timing requirements of the notebook computer, the power management chip can further include two low dropout linear regulators, which are Figure 4LDO5 and the first low dropout linear regulator 105. Although the output voltage of LDO5 and the first buck circuit 101 is 5 volts, and the output voltage of the first low dropout linear regulator 105 and the second buck circuit 102 is 3.3 volts, the timing requirements and the load capacity of the two low dropout linear regulators and the two buck circuits are different. The load capacity of the two low dropout linear regulators is much smaller than that of the two buck circuits, but they are powered up earlier than the Channel 1BUCK Controller of the first buck circuit 101 and the Channel 2BUCK Controller of the second buck circuit 102, which are responsible for supplying power to the bottommost chip of the entire notebook computer system, that is, the power supply that is powered up first in the entire power-up sequence. Usually, after the adapter is connected, the first low dropout linear regulator and LDO5 work first, outputting 3.3V and 5V respectively, of which 5V is used as the working voltage of the IC chip to ensure the normal operation of the IC body, and 3.3V is used to supply power to the Embedded Chip (EC) chip in the notebook computer system. The EC then pushes out two groups of enable signals EN1 and EN2, and the POWER-ONSEQUENCE CLEAR FAULT LATCH module controls the Channel 1BUCK Controller of the first buck circuit 101 and the Channel 2BUCK Controller of the second buck circuit 102 to start when the EC1 and EC2 enable signals are received by the circuit, outputting 5V and 3.3V as the working voltage of the large load device, which can be a solid state hard disk and a fan, etc. Under normal circumstances, the input voltages of 3.3V and 5V are the output voltages of the external power supply 106 connected to the VIN pin in the Figure 4 The 5V_PWM and 3.3V_PWM connected to the input end of the switch logic module 103 represent the PWM frequency of the first buck circuit and the PWM frequency of the second buck circuit respectively.

[0081] The CS1 pin is the voltage output end of the first buck circuit 101, and the BYP1 pin is short-circuited with the first low dropout linear regulator 105, so the BYP1 pin is connected to the voltage input end of the first low dropout linear regulator 105. The CS1 pin and the BYP1 pin are simultaneously connected to the subtractor for calculating the current difference. The REF module is a reference voltage that can provide an accurate reference voltage for analog functions.

[0082] The power conversion circuit of the embodiment of the application can be applied to a power management chip of a notebook computer, and the classification of the working modes is shown in Table 1 below.

[0083]

[0084] Table 1 Classification of working modes of power conversion circuit

[0085] It can be seen that, by using the power conversion circuit disclosed in the embodiments of the present application, in the case that the power circuit is in light load, different switch gears are switched, the connection of the voltage input end and the voltage output end of the first voltage reduction circuit 101 and the second voltage reduction circuit 102 is changed, the PWM frequency of the voltage reduction circuit is changed, the power supply noise jumps out of the audible frequency range of human ears, the conversion efficiency is ensured unchanged, and no additional power loss is generated.

[0086] It can be seen that, by using the power conversion circuit disclosed in the embodiments of the present application, in the case that the power circuit is in light load, different switch gears are switched, the connection of the voltage input end and the voltage output end of the first voltage reduction circuit 101 and the second voltage reduction circuit 102 is changed, the PWM frequency of the voltage reduction circuit is changed, the power supply noise jumps out of the audible frequency range of human ears, the conversion efficiency is ensured unchanged, and no additional power loss is generated.

[0087] Please refer to Figure 5 , Figure 5 is a structural schematic diagram of an electronic device disclosed in the embodiments of the present application. As shown in Figure 5 , the electronic device can include any one of the power conversion circuits disclosed in the embodiments of the present application.

[0088] It should be understood that, throughout the specification, "one embodiment" or "an embodiment" means that the specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also know that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0089] In various embodiments of the present application, it should be understood that the size of the sequence number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0090] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed to multiple network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiments of the present application.

[0091] In addition, each of the functional units in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0092] When the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the present application essentially, or the part that contributes to the prior art, or all or a part of the technical solutions, can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc., and specifically can be a processor in the computer device) to perform all or part of the steps of the methods according to the embodiments of the present application.

[0093] Those skilled in the art can understand that all or part of the steps of the above-mentioned methods in the embodiments can be completed by a program instructing relevant hardware, and the program can be stored in a computer-readable storage medium, including a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, a magnetic disk storage, a magnetic tape storage, or any other medium that can be used to carry or store data.

[0094] The power conversion circuit and the electronic device disclosed in the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above embodiment description is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description should not be understood as a limitation on the present application.

Claims

1. A power conversion circuit, characterized in that, The device includes a first step-down circuit, a second step-down circuit, a first low-dropout linear regulator, a switching logic module, and a switch; the output voltage of the first step-down circuit is higher than the output voltage of the second step-down circuit; the switching logic module is connected to the first step-down circuit and the second step-down circuit respectively, and the switch is connected to the switching logic module. The switching logic module is configured to generate a first switching signal for switching the switch to a first position when the pulse width modulation frequency of the first buck circuit is detected to be less than a frequency threshold; and to generate a second switching signal for switching the switch to a second position when the pulse width modulation frequency of the second buck circuit is detected to be less than the frequency threshold. The switch is used to switch to the first position according to the first switch signal generated by the switch logic module, so as to connect the voltage input terminal of the second step-down circuit to the voltage output terminal of the first step-down circuit; or, The switch is used to switch to the second position according to the second switch signal generated by the switch logic module, so as to connect the voltage input terminal of the second step-down circuit to the voltage output terminal of the first low dropout linear regulator.

2. The power conversion circuit according to claim 1, characterized in that, The second step-down circuit includes a driving module, an HMOS transistor, and an LMOS transistor; the driving module is used to control the HMOS transistor to turn on and the LMOS transistor to turn off when the switch is switched to the second position.

3. The power conversion circuit according to claim 1 or 2, characterized in that, The switch is also used to connect the voltage input terminals of the first step-down circuit and the second step-down circuit to the voltage output terminal of an external power supply when switching to the third position according to the switch signal generated by the switch logic module.

4. The power conversion circuit according to claim 3, characterized in that, The power conversion circuit further includes a first current detection module; The first current detection module is used to generate a first detection signal when it detects that the difference between the output current of the first buck circuit and the input current of the first low-dropout linear regulator is greater than a first current threshold. The switch logic module is further configured to generate a third switch signal for switching the switch to the third position based on the first detection signal when the switch is switched to the first position.

5. The power conversion circuit according to claim 4, characterized in that, The voltage output terminal of the first step-down circuit is connected to the voltage input terminal of the first low-dropout linear regulator.

6. The power conversion circuit according to claim 3, characterized in that, The power conversion circuit also includes a second current detection module; The second current detection module is used to generate a second detection signal when it detects that the current flowing through the HMOS transistor included in the second buck circuit is greater than a second current threshold. The switch logic module is further configured to generate a third switch signal for switching the switch to the third gear position based on the second detection signal.

7. The power conversion circuit according to claim 3, characterized in that, The switching logic module is further configured to generate a third switching signal for switching the switch to the third gear when it is detected that the pulse width modulation frequencies of the first buck circuit and the second buck circuit are both greater than the frequency threshold.

8. An electronic device, characterized in that, include: The power conversion circuit as described in any one of claims 1-7.

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