Transient response enhancement circuits for LDOs and low dropout linear regulators

Abstract

Embodiments of this disclosure provide a transient response improvement circuit and a low-dropout linear regulator applied to an LDO, including: a differential comparator circuit, an undervoltage current comparator circuit, an undervoltage compensation circuit, an overvoltage current comparator circuit, and an overvoltage compensation circuit. Specifically, the differential comparator circuit compares the Vref and V... FB Compare and convert it into current, V FB Corresponding to I1; the undervoltage current comparator circuit generates I3, which is positively correlated with I1. After undervoltage, it outputs a level signal based on the increase in I3; the undervoltage compensation circuit provides a first compensation current based on the level signal output by the undervoltage current comparator circuit; the overvoltage current comparator circuit generates I7, which is positively correlated with I1. After overvoltage, it outputs a level signal based on the decrease in I7; the overvoltage compensation circuit provides a second compensation current based on the level signal output by the overvoltage current comparator circuit. This addresses how to improve the transient response capability of the LDO.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to transient response improvement circuits and low dropout linear regulators applied to LDOs. Background Technology

[0002] Low dropout linear regulators (LDOs) are common power supply chips characterized by simple structure, low cost, and low output voltage ripple, and are widely used in the electronics, automotive, and aerospace fields.

[0003] In practical applications, LDOs frequently encounter sudden load changes, such as rapid transitions from heavy load to light load or vice versa. Due to limitations in the LDO loop bandwidth and slew rate, load shifts can cause undervoltage and overshoot in the output voltage, resulting in poor transient response. This can negatively impact subsequent circuitry. Therefore, improving the transient response of LDOs is a crucial issue that needs to be addressed. Summary of the Invention

[0004] The embodiments described herein provide a transient response enhancement circuit for LDOs, a low-dropout linear regulator, to improve the transient response capability of LDOs without substantially increasing power consumption and / or area.

[0005] According to a first aspect of this disclosure, a transient response enhancement circuit for an LDO is provided, the transient response enhancement circuit comprising: a differential comparator circuit, an undervoltage current comparator circuit, an undervoltage compensation circuit, an overvoltage current comparator circuit, and an overvoltage compensation circuit; wherein the differential comparator circuit is configured to compare two voltage signals, a reference voltage and a feedback voltage, and convert the two voltage signals into two current signals, wherein the current signal corresponding to the feedback voltage is a first current, the current signal corresponding to the reference voltage is a second current, the reference voltage is the input reference voltage of the error amplifier in the low dropout linear regulator, and the feedback voltage is... The voltage is the feedback voltage of the output voltage of the low-dropout linear regulator; the undervoltage current comparison circuit is configured to generate a third current positively correlated with the first current, and to compare the magnitudes of the third current and the fourth current via a Schmitt trigger, and after the output voltage becomes undervoltage, output a high-level signal when the increase of the third current is greater than a first current threshold, and output a low-level signal when the increase of the third current is less than a second current threshold, wherein the first current threshold is the steady-state difference between the fourth current and the third current, and the second current threshold is less than the first current threshold; the undervoltage compensation circuit is configured to... The circuit is configured to generate a fifth current positively correlated with the first current and a sixth current positively correlated with the change in the first current. Based on the level signal output by the undervoltage current comparison circuit, a first compensation current is controlled to be input to the output of the error amplifier. The first compensation current is positively correlated with the mirror current of the sixth current. The overvoltage current comparison circuit is configured to generate a seventh current positively correlated with the first current and an eighth current equal to the steady-state value of the seventh current. It compares the magnitudes of the eighth and ninth currents using a Schmitt trigger, and after an overvoltage occurs in the output voltage, when the value of the seventh current decreases... When the current is greater than the third current threshold, a high-level signal is output. When the decrease in the seventh current is less than the fourth current threshold, a low-level signal is output. The ninth current is the sum of the seventh current and the third current threshold, and the fourth current threshold is less than the third current threshold. The overvoltage compensation circuit is configured to generate a tenth current that is positively correlated with the first current and an eleventh current that is positively correlated with the change in the first current. The second compensation current is input to the output of the error amplifier according to the level signal output by the overvoltage current comparison circuit. The second compensation current is positively correlated with the mirror current of the eleventh current.

[0006] Optionally, the undervoltage current comparison circuit includes: first to fifth transistors and a first Schmitt trigger, wherein the control electrode of the first transistor is coupled to the differential comparison circuit, the first transistor is configured to mirror the first current to generate the third current, the first electrode of the first transistor is coupled to ground, and the second electrode of the first transistor is coupled to the input terminal of the first Schmitt trigger; the control electrodes of the second, third, and fourth transistors are all coupled to the differential comparison circuit, the second, third, and fourth transistors generate three currents respectively according to the current source in the differential comparison circuit, the first electrodes of the second, third, and fourth transistors are all coupled to the power supply voltage, the second electrodes of the second and third transistors are all coupled to the input terminal of the first Schmitt trigger, the second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor, the control electrode of the fifth transistor is coupled to the output terminal of the first Schmitt trigger, and the second electrode of the fifth transistor is coupled to the input terminal of the first Schmitt trigger, the sum of the three currents is the fourth current; the output terminal of the first Schmitt trigger, as the output terminal of the undervoltage current comparison circuit, is also coupled to the undervoltage compensation circuit.

[0007] Optionally, the undervoltage compensation circuit includes: a sixth to eleventh transistor and a first compensation output module, wherein the control electrode of the sixth transistor is coupled to the differential comparator circuit, the sixth transistor is configured to mirror the first current to generate the fifth current, the first electrode of the sixth transistor is coupled to ground, and the second electrode of the sixth transistor is coupled to the second electrode of the seventh transistor; the control electrode of the seventh transistor is coupled to the differential comparator circuit, the seventh transistor generates current according to the current source in the differential comparator circuit, and the first electrode of the seventh transistor is coupled to the power supply voltage; the control electrodes of the eighth and ninth transistors are both coupled to the second electrode of the seventh transistor, and the eighth transistor and the ninth transistor... The first terminal of each transistor is coupled to the power supply voltage. The second terminal of the eighth transistor is coupled to the control terminal of the eighth transistor. The second terminal of the ninth transistor is coupled to the second terminal of the tenth transistor. The current flowing through the eighth transistor is the sixth current, and the current flowing through the ninth transistor is the mirror current of the sixth current. The control terminal of the tenth transistor is coupled to the level signal output by the undervoltage current comparator circuit. The first terminal of the tenth transistor is coupled to the control terminal and the second terminal of the eleventh transistor. The first terminal of the eleventh transistor is coupled to ground. The first compensation output module is configured to output the first compensation current based on the mirror current of the sixth current.

[0008] Optionally, the overvoltage current comparison circuit includes: a twelfth to seventeenth transistor, a second Schmitt trigger, and an inverter, wherein the control electrode of the twelfth transistor is coupled to the differential comparison circuit, the twelfth transistor is configured to mirror the first current to generate the seventh current, the first electrode of the twelfth transistor is coupled to ground, and the second electrode of the twelfth transistor is coupled to the input terminal of the second Schmitt trigger; the control electrode of the thirteenth transistor is coupled to the differential comparison circuit, the thirteenth transistor generates the eighth current according to the current source in the differential comparison circuit, the first electrode of the thirteenth transistor is coupled to the power supply voltage, and the second electrode of the thirteenth transistor is coupled to the input terminal of the second Schmitt trigger; the control electrodes of the fourteenth, fifteenth, and sixteenth transistors are all coupled to the... The second terminal of the sixteenth transistor and the first current source, the first terminals of the fourteenth, fifteenth, and sixteenth transistors are all coupled to ground. The second terminal of the fourteenth transistor is coupled to the input terminal of the second Schmitt trigger. The second terminal of the fifteenth transistor is coupled to the first terminal of the seventeenth transistor. The second terminal of the seventeenth transistor is coupled to the input terminal of the second Schmitt trigger. The control terminal of the seventeenth transistor is coupled to the output terminal of the second Schmitt trigger. The output terminal of the second Schmitt trigger is also coupled to the input terminal of the inverter. The output terminal of the inverter serves as the output terminal of the overvoltage current comparator circuit and is coupled to the overvoltage compensation circuit. The ninth current is the sum of the current flowing through the twelfth transistor, the current flowing through the fourteenth transistor, and the current flowing through the fifteenth transistor.

[0009] Optionally, the overvoltage compensation circuit includes: eighteenth to twenty-third transistors and a second compensation output module, wherein the control electrode of the eighteenth transistor is coupled to the differential comparator circuit, the eighteenth transistor is configured to mirror the first current to generate the tenth current, the first electrode of the eighteenth transistor is coupled to ground, and the second electrode of the eighteenth transistor is coupled to the second electrode of the nineteenth transistor; the control electrode of the nineteenth transistor is coupled to the differential comparator circuit, the nineteenth transistor generates current according to the current source in the differential comparator circuit, and the first electrode of the nineteenth transistor is coupled to the power supply voltage; the control electrodes of the twentieth and twenty-first transistors are both coupled to the second electrode of the eighteenth transistor, and the twentieth transistor and the twenty-first transistor... The first terminal of each transistor is coupled to ground. The second terminal of the twentieth transistor is coupled to the control terminal of the twentieth transistor. The second terminal of the twentieth transistor is coupled to the first terminal of the twentieth transistor. The current flowing through the twentieth transistor is the eleventh current, and the current flowing through the twentieth transistor is the mirror current of the eleventh current. The control terminal of the twentieth transistor is coupled to the level signal output by the overvoltage current comparison circuit. The second terminal of the twentieth transistor is coupled to the control terminal and the second terminal of the twentieth transistor. The first terminal of the twentieth transistor is coupled to ground. The second compensation output module is configured to output the second compensation current based on the mirror current of the eleventh current.

[0010] Optionally, the first compensation output module includes: a twenty-fourth transistor or a twenty-fifth transistor, wherein the control electrode of the twenty-fourth transistor is coupled to the control electrode of the eleventh transistor, the first electrode of the twenty-fourth transistor is coupled to the ground terminal, and the second electrode of the twenty-fourth transistor outputs the first compensation current; the control electrode of the twenty-fifth transistor is coupled to the control electrode of the ninth transistor, the first electrode of the twenty-fifth transistor is coupled to the power supply voltage, and the second electrode of the twenty-fifth transistor outputs the first compensation current.

[0011] Optionally, the second compensation output module includes: a twenty-sixth transistor or a twenty-seventh transistor, wherein the control electrode of the twenty-sixth transistor is coupled to the control electrode of the twenty-third transistor, the first electrode of the twenty-sixth transistor is coupled to the power supply voltage, and the second electrode of the twenty-sixth transistor outputs the second compensation current; the control electrode of the twenty-seventh transistor is coupled to the control electrode of the twenty-first transistor, the first electrode of the twenty-seventh transistor is coupled to the ground terminal, and the second electrode of the twenty-seventh transistor outputs the second compensation current.

[0012] Optionally, the differential comparator circuit includes: transistors 28 to 40, a second current source, a first resistor, and an input stage module. The first terminals of transistors 28 and 29 are both coupled to a power supply voltage. The control terminal of transistor 28 is coupled to the control terminal of transistor 29, the second terminal of transistor 28, and the first terminal of transistor 30. The second terminal of transistor 29 is coupled to one end of the first resistor. The second terminal of transistor 30 is coupled to the second current source and the control terminal of transistor 30. The other end of the first resistor is coupled to the second terminal of transistor 31 and the control terminal of transistor 32. The control terminal of transistor 31 is coupled to the... One end of the first resistor is connected to the first terminal of the thirty-first transistor, which is coupled to the second terminal of the thirty-second transistor. The first terminal of the thirty-second transistor is coupled to ground. The control terminal of the thirty-third transistor is coupled to the control terminal of the twenty-ninth transistor. The first terminal of the thirty-third transistor is coupled to the power supply voltage. The second terminal of the thirty-third transistor is coupled to the first terminal of the thirty-fourth transistor. The control terminal of the thirty-fourth transistor is coupled to the control terminal of the thirty-tenth transistor. The second terminal of the thirty-fourth transistor is coupled to the second terminal of the thirty-fifth transistor, the control terminal of the thirty-sixth transistor, and the control terminal of the thirty-seventh transistor. The control terminal of the thirty-fifth transistor is coupled to the control terminal of the thirty-first transistor. The thirty-fifth transistor... The first terminal of the transistor is coupled to the second terminal of the thirty-sixth transistor. The first terminals of both the thirty-sixth and thirty-seventh transistors are coupled to ground. The second terminal of the thirty-seventh transistor is coupled to the first terminal of the thirty-eighth transistor. The control terminal of the thirty-eighth transistor is coupled to the control terminal of the thirty-fifth transistor. The second terminal of the thirty-eighth transistor is coupled to the second terminal of the thirty-ninth transistor. The control terminal of the thirty-ninth transistor is coupled to the control terminal of the thirty-fourth transistor. The first terminal of the thirty-ninth transistor is coupled to the second terminal of the fortieth transistor. The control terminal of the fortieth transistor is coupled to the control terminal of the thirty-third transistor. The first terminal of the fortieth transistor is coupled to the power supply voltage, which flows through the thirty-sixth transistor. The current flowing through the thirty-seventh transistor is the first current, and the current flowing through the thirty-seventh transistor is the second current; the input stage module includes forty-first to forty-third transistors, wherein the control electrode of the forty-first transistor is coupled to the control electrode of the twenty-ninth transistor, the first electrode of the forty-first transistor is coupled to the power supply voltage, the second electrode of the forty-first transistor is coupled to the first electrode of the forty-second transistor and the first electrode of the forty-third transistor respectively, the control electrode of the forty-second transistor is coupled to the feedback voltage, the control electrode of the forty-third transistor is coupled to the reference voltage, the second electrode of the forty-second transistor is coupled to the second electrode of the thirty-sixth transistor, and the second electrode of the forty-third transistor is coupled to the second electrode of the thirty-seventh transistor;Alternatively, the input stage module includes transistors forty-four to forty-seven, wherein the control electrode of transistor forty-four is coupled to the control electrode of transistor thirty-two, the first electrode of transistor forty-four is coupled to ground, the second electrode of transistor forty-four is coupled to the first electrode of transistor forty-five, the control electrode of transistor forty-five is coupled to the control electrode of transistor thirty-one, the second electrode of transistor forty-five is coupled to the first electrodes of transistors forty-six and forty-seven, the control electrode of transistor forty-six is ​​coupled to the feedback voltage, the control electrode of transistor forty-seven is coupled to the reference voltage, the second electrode of transistor forty-six is ​​coupled to the second electrode of transistor thirty-three, and the second electrode of transistor forty-seven is coupled to the second electrode of transistor forty.

[0013] Optionally, the undervoltage compensation circuit further includes a third compensation output module corresponding to each stage of the amplifier after the error amplifier. Each third compensation output module corresponds to a stage of the amplifier, and each third compensation output module has the same structure as the first compensation output module. The output of each third compensation output module is coupled to the output terminal of an amplifier. The overvoltage compensation circuit further includes a fourth compensation output module corresponding to each stage of the amplifier after the error amplifier. Each fourth compensation output module corresponds to a stage of the amplifier, and each fourth compensation output module has the same structure as the second compensation output module. The output of each fourth compensation output module is coupled to the output terminal of an amplifier.

[0014] According to a second aspect of this disclosure, a low-dropout linear regulator is provided, the low-dropout linear regulator including a transient response enhancement circuit for an LDO according to any one of the first aspects.

[0015] The transient response enhancement circuit for LDOs disclosed in this embodiment first converts the change in feedback voltage corresponding to undervoltage or overvoltage conditions into a change in first current through a differential comparator circuit. Then, a third current positively correlated with the first current is constructed. Under voltage conditions, an undervoltage current comparator circuit and an undervoltage compensation circuit work together to ensure that when the increase of the third current exceeds the first current threshold (i.e., when the feedback voltage drop reaches a certain value), a compensation current is applied to the output of the error amplifier, thereby increasing the slew rate and improving the transient response capability. The magnitude of the compensation current is related to the feedback voltage drop, enabling dynamic adjustment. Similarly, a seventh current positively correlated with the first current is constructed. Under overvoltage conditions, an overvoltage current comparator circuit and an overvoltage compensation circuit work together to ensure that when the decrease of the seventh current exceeds the third current threshold (i.e., when the feedback voltage rise reaches a certain value), a compensation current is applied to the output of the error amplifier, thereby increasing the slew rate and improving the transient response capability. The magnitude of the compensation current is also related to the feedback voltage rise, enabling dynamic adjustment as well. In summary, the transient response enhancement circuit of the present disclosure can dynamically improve the slew rate of the LDO loop; by determining the degree of dynamic adjustment of the slew rate based on the change in feedback voltage, the transient response capability can be effectively improved. Moreover, the increase in power consumption is small and basically does not require an increase in circuit area. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0017] Figure 1 , 5 A schematic block diagram of a transient response enhancement circuit applied to an LDO according to an embodiment of the present disclosure is shown, as well as a schematic diagram of the transient response enhancement circuit coupled to different types of low dropout linear regulators.

[0018] Figure 2 An exemplary circuit diagram of a transient response enhancement circuit applied to an LDO according to an embodiment of the present disclosure is shown;

[0019] Figure 3 , 4 Exemplary circuit diagrams of two structures of the undervoltage compensation circuit and the first compensation output module therein, according to embodiments of the present disclosure, are shown.

[0020] Figure 6 , 7 Exemplary circuit diagrams of two structures of the overvoltage compensation circuit and the second compensation output module therein, according to embodiments of the present disclosure, are shown.

[0021] Figure 8 , 9Two exemplary circuit diagrams of the differential comparator circuit according to embodiments of the present disclosure are shown;

[0022] Figure 10 A waveform diagram of a key signal applied to a transient response enhancement circuit of an LDO according to an embodiment of the present disclosure is shown.

[0023] Figure 11 An exemplary circuit diagram of another undervoltage compensation circuit according to an embodiment of the present disclosure is shown;

[0024] Figure 12 An exemplary circuit diagram of another overvoltage compensation circuit according to an embodiment of the present disclosure is shown;

[0025] Figure 13 A schematic diagram of a transient response enhancement circuit for an LDO coupled to a low-dropout linear regulator according to an embodiment of the present disclosure is shown.

[0026] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0029] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. In all embodiments of this disclosure, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0030] To improve the transient response capability of LDOs, a transient response enhancement circuit for LDOs is proposed. The transient response enhancement circuit in this embodiment determines the degree of dynamic adjustment of the slew rate based on the change in feedback voltage, effectively improving transient response capability. Moreover, the circuit is simple, with minimal increase in power consumption and virtually no need to increase circuit area. The transient response enhancement circuit for LDOs of this disclosure will be described in detail below.

[0031] Figure 1 A schematic block diagram of a transient response enhancement circuit 100 applied to an LDO according to an embodiment of the present disclosure is shown. The transient response enhancement circuit 100 is coupled to a low dropout linear regulator (LDO), such as... Figure 1 As shown, the transient response enhancement circuit 100 includes: a differential comparator circuit 110, an undervoltage current comparator circuit 120, an undervoltage compensation circuit 130, an overvoltage current comparator circuit 140, and an overvoltage compensation circuit 150.

[0032] The differential comparator circuit 110 is configured to compare the reference voltage Vref and the feedback voltage V. FB Two voltage signals are compared and converted into two current signals, where the feedback voltage V FB The corresponding current signal is the first current I1, and the current signal corresponding to the reference voltage Vref is the second current I2. The reference voltage Vref is the input reference voltage of the error amplifier EA in the low dropout linear regulator, and the feedback voltage V... FB This is the feedback voltage for the output voltage Vout of the low-dropout linear regulator. In this embodiment, the reference voltage Vref is constant, and the differential comparator circuit 110 is used to obtain a voltage that accurately reflects the feedback voltage Vout. FB The changing current, i.e., when the feedback voltage V FB When the voltage changes, a value that varies with the feedback voltage V can be obtained. FBThe varying current. In practical applications, the differential comparator circuit 110 can be implemented using existing differential comparators. The specific structure is not limited; it can be an input pair of P-type MOSFETs or an input pair of N-type MOSFETs. Both simple and slightly complex cascode structures are acceptable, as long as the feedback voltage V... FB If a change can cause a current difference between the two branches (the two branches corresponding to the differential inputs respectively), then this disclosure can be applied.

[0033] The undervoltage current comparison circuit 120 is coupled to the differential comparison circuit 110 and the undervoltage compensation circuit 130, respectively. It is configured to generate a third current I3 that is positively correlated with the first current I1, and to compare the magnitudes of the third current I3 and the fourth current I4 through a Schmitt trigger. After the output voltage Vout is undervoltage, when the increment of the third current I3 is greater than the first current threshold Ith1, a high-level signal is output, and when the increment of the third current I3 is less than the second current threshold Ith2, a low-level signal is output. The first current threshold Ith1 is the steady-state difference between the fourth current I4 and the third current I3 (the current value when the circuit is in steady state), and the second current threshold Ith2 is less than the first current threshold Ith1.

[0034] Since the change in the first current I1 can reflect the feedback voltage V FB The change in voltage V, therefore, the third current I3, which is positively correlated with the first current I1, can also reflect the feedback voltage V. FB The change. Specifically, in this embodiment of the disclosure, the increase in the third current I3 is used to reflect the feedback voltage V after the output voltage Vout is undervoltage. FB The change in the third current I3 is controlled by setting a high-level signal when the increase in the third current I3 exceeds the first current threshold Ith1. This is to control the feedback voltage V. FB When the change in voltage exceeds a certain value (this value can be adaptively set according to actual needs, and the magnitude of the first current threshold Ith1 can be determined based on this value), a high-level signal is output to control the subsequent undervoltage compensation circuit 130 to provide compensation current Ic1 to the LDO loop, thereby improving the slew rate. Additionally, this embodiment also sets "outputting a low-level signal when the increase in the third current I3 is less than the second current threshold Ith2" because with the action of the compensation current, the feedback voltage V... FB The current will gradually increase, and the change will gradually decrease when it reaches a certain value. When it decreases to a certain value, no compensation current is needed. At this time, a low-level signal is output to control the subsequent undervoltage compensation circuit 130 not to provide compensation current to the LDO loop.

[0035] The undervoltage compensation circuit 130 is coupled to the differential comparator circuit 110 and the undervoltage current comparator circuit 120 respectively. It is configured to generate a fifth current I5 that is positively correlated with the first current I1 and a sixth current I6 that is positively correlated with the change of the first current I1. The first compensation current Ic1 is input to the output terminal of the error amplifier EA according to the level signal output by the undervoltage current comparator circuit 120. The first compensation current Ic1 is positively correlated with the mirror current I6' of the sixth current.

[0036] The undervoltage compensation circuit 130 mainly controls whether to provide compensation current to the LDO loop based on the level signal output by the undervoltage current comparator circuit 120. Specifically, it provides the first compensation current Ic1 when the level signal output by the undervoltage current comparator circuit 120 is a high level signal, and does not provide the first compensation current Ic1 when the output level signal is a low level signal, that is, the first compensation current Ic1 is zero at this time.

[0037] Based on the above description, it can be seen that in this embodiment of the present disclosure, a switch is essentially set up to control when to provide compensation current to the LDO after undervoltage. This method controls the current when the feedback voltage V... FB The compensation current only occurs after the change in voltage (the decrease during undervoltage) reaches a certain value. This prevents an unintended error from being introduced into the LDO loop under balanced conditions when mismatches occur in the system. Furthermore, the magnitude of the first compensation current Ic1 changes with the first current I1, i.e., the feedback voltage V. FB It changes with the temperature. This dynamic adjustment capability is more effective than directly applying a fixed current.

[0038] The overvoltage current comparison circuit 140 is coupled to the differential comparison circuit 110 and the overvoltage compensation circuit 150, respectively. It is configured to generate a seventh current I7 that is positively correlated with the first current I1, an eighth current I8 that is equal to the steady-state value of the seventh current I7, and compare the magnitudes of the eighth current I8 and the ninth current I9 through a Schmitt trigger. After the output voltage Vout is overvoltaged, when the drop in the seventh current I7 is greater than the third current threshold Ith3, a high-level signal is output, and when the drop in the seventh current I7 is less than the fourth current threshold Ith4, a low-level signal is output. The ninth current I9 is ​​the sum of the seventh current I7 and the third current threshold Ith3, and the fourth current threshold Ith4 is less than the third current threshold Ith3.

[0039] Since the change in the first current I1 can reflect the feedback voltage V FB The change in voltage V, therefore, the seventh current I7, which is positively correlated with the first current I1, can also reflect the feedback voltage V. FBThe change. Specifically, in this embodiment, the design uses the decrease in the value of the seventh current I7 to reflect the feedback voltage V after the output voltage Vout is over-voltage. FB The change in the value of the seventh current I7 is set to "output a high-level signal when the drop in the seventh current I7 is greater than the third current threshold Ith3" in order to control the feedback voltage V. FB When the change in voltage exceeds a certain value (this value can be adaptively set according to actual needs, and the magnitude of the third current threshold Ith3 can be determined based on this value), a high-level signal is output to control the subsequent overvoltage compensation circuit 150 to provide compensation current to the LDO loop, thereby improving the slew rate. Additionally, this embodiment also sets "a low-level signal to be output when the drop in the seventh current I7 is less than the fourth current threshold Ith4" because with the effect of the compensation current, the feedback voltage V... FB The change will gradually decrease, and the change will gradually become smaller when it reaches a certain value. When it decreases to a certain value, no compensation current is needed. At this time, a low-level signal is output to control the subsequent overvoltage compensation circuit 150 not to provide compensation current to the LDO loop.

[0040] The overvoltage compensation circuit 150 is coupled to the differential comparator circuit 110 and the overvoltage current comparator circuit 140, respectively, and is configured to generate a tenth current I10 that is positively correlated with the first current I1 and an eleventh current I11 that is positively correlated with the change of the first current I1. The second compensation current Ic2 is input to the output terminal of the error amplifier EA according to the level signal output by the overvoltage current comparator circuit 140. The second compensation current Ic2 is positively correlated with the mirror current I11' of the eleventh current.

[0041] The overvoltage compensation circuit 150 mainly controls whether to provide compensation current to the LDO loop based on the level signal output by the overvoltage current comparator circuit 140. Specifically, it provides a second compensation current Ic2 when the level signal output by the overvoltage current comparator circuit 140 is a high level signal, and does not provide a second compensation current Ic2 when the output level signal is a low level signal, that is, the second compensation current Ic2 is zero at this time.

[0042] Based on the above description, it can be seen that in this embodiment of the present disclosure, a switch is essentially set up to control when to provide compensation current to the LDO after an overvoltage. This method controls the current when the feedback voltage V... FB The compensation current only occurs after the change in voltage (the increase during overvoltage) reaches a certain value. This prevents an unintended error from being introduced into the LDO loop under balanced conditions when mismatches occur in the system. Furthermore, the magnitude of the second compensation current Ic2 changes with the first current I1, i.e., the feedback voltage V. FB It changes with the temperature. This dynamic adjustment capability is more effective than directly applying a fixed current.

[0043] From the above description, it can be seen that the transient response enhancement circuit applied to LDO in the embodiments of this disclosure first uses the differential comparator circuit 110 to obtain the feedback voltage V corresponding to the undervoltage or overvoltage condition of the output voltage Vout. FB The change is converted into a change in the first current I1, and then a third current I3, which is positively correlated with the first current I1, is constructed. In the case of undervoltage, the undervoltage current comparison circuit 120 and the undervoltage compensation circuit 130 play a role, so that when the increase of the third current I3 is greater than the first current threshold Ith1, that is, when the feedback voltage V... FB Once the voltage drop reaches a certain value, a compensation current is applied to the output of the error amplifier EA, thereby increasing the slew rate and improving the transient response. The magnitude of the compensation current is related to the feedback voltage V. FB The decrease in voltage is related to the amount of voltage drop, enabling dynamic adjustment. Similarly, a seventh current I7, positively correlated with the first current I1, is constructed. During overvoltage, this current is utilized by the overvoltage current comparison circuit 140 and the overvoltage compensation circuit 150 to ensure that the decrease in the seventh current I7 is greater than the third current threshold Ith3, i.e., the feedback voltage V... FB Once the voltage rise reaches a certain value, a compensation current is applied to the output of the error amplifier EA, thereby increasing the slew rate and improving the transient response. The magnitude of the compensation current is related to the feedback voltage V. FB The transient response enhancement circuit of this disclosure can dynamically improve the slew rate of the LDO loop, which is related to the rise in voltage and can also be dynamically adjusted. In summary, the transient response enhancement circuit of this disclosure can dynamically improve the slew rate of the LDO loop; with feedback voltage V... FB The change in voltage is used to determine the degree of dynamic adjustment of the slew rate, which can effectively improve transient response capability. Moreover, the circuit is simple, the increase in power consumption is small, and there is basically no need to increase the circuit area.

[0044] Furthermore, such as Figure 2As shown, the undervoltage current comparison circuit 120 includes: first to fifth transistors (M1-M5) and a first Schmitt trigger 1. The control electrode of the first transistor M1 is coupled to the differential comparator circuit 110. The first transistor M1 is configured to mirror the first current I1 to generate a third current I3. The first electrode of the first transistor M1 is coupled to ground, and the second electrode of the first transistor M1 is coupled to the input terminal of the first Schmitt trigger 1. The control electrodes of the second transistor M2, the third transistor M3, and the fourth transistor M4 are all coupled to the differential comparator circuit 110. The second transistor M2, the third transistor M3, and the fourth transistor M4 generate currents according to the current source (i.e., Ib2 in subsequent steps) in the differential comparator circuit 110. Three currents are generated. The first terminals of the second transistor M2, the third transistor M3, and the fourth transistor M4 are all coupled to the power supply voltage VDD. The second terminals of the second transistor M2 and the third transistor M3 are both coupled to the input terminal of the first Schmitt trigger 1. The second terminal of the fourth transistor M4 is coupled to the first terminal of the fifth transistor M5. The control terminal of the fifth transistor M5 is coupled to the output terminal of the first Schmitt trigger 1. The second terminal of the fifth transistor M5 is coupled to the input terminal of the first Schmitt trigger 1. The sum of the three currents is the fourth current I4. The output terminal A of the first Schmitt trigger 1 is also coupled to the undervoltage compensation circuit 130 as the output terminal of the undervoltage current comparator circuit 120.

[0045] Furthermore, such as Figure 2As shown, the undervoltage compensation circuit 130 includes: sixth to eleventh transistors (M6-M11), and a first compensation output module 131. The control electrode of the sixth transistor M6 is coupled to a differential comparator circuit 110. The sixth transistor M6 is configured to mirror the first current I1 to generate a fifth current I5. The first electrode of the sixth transistor M6 is coupled to ground, and the second electrode of the sixth transistor M6 is coupled to the second electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the differential comparator circuit 110. The seventh transistor M7 generates current according to the current source in the differential comparator circuit 110. The first electrode of the seventh transistor M7 is coupled to the power supply voltage VDD. The control electrodes of the eighth transistor M8 and the ninth transistor M9 are both coupled to the second electrode of the seventh transistor M7. The first terminal of the ninth transistor M9 is coupled to the power supply voltage VDD. The second terminal of the eighth transistor M8 is coupled to the control terminal of the eighth transistor M8. The second terminal of the ninth transistor M9 is coupled to the second terminal of the tenth transistor M10. The current flowing through the eighth transistor M8 is the sixth current I6, and the current flowing through the ninth transistor M9 is the mirror current I6' of the sixth current. The control terminal of the tenth transistor M10 is coupled to the level signal output by the undervoltage current comparator circuit 120. The first terminal of the tenth transistor M10 is coupled to the control terminal and the second terminal of the eleventh transistor M11. The first terminal of the eleventh transistor M11 is coupled to the ground terminal. The first compensation output module 131 is configured to output a first compensation current Ic1 based on the mirror current I6' of the sixth current.

[0046] Furthermore, such as Figure 3 As shown, the first compensation output module 131 includes: a twenty-fourth transistor M24, wherein the control electrode of the twenty-fourth transistor M24 is coupled to the control electrode of the eleventh transistor M11, the first electrode of the twenty-fourth transistor M24 is coupled to the ground terminal, and the second electrode of the twenty-fourth transistor M24 outputs a first compensation current Ic1; or, as shown Figure 4 As shown, the first compensation output module 131 includes: a twenty-fifth transistor M25, wherein the control electrode of the twenty-fifth transistor M25 is coupled to the control electrode of the ninth transistor M9, the first electrode of the twenty-fifth transistor M25 is coupled to the power supply voltage VDD, and the second electrode of the twenty-fifth transistor M25 outputs a first compensation current Ic1. Figure 3 and Figure 4 The diagram shows two structures of the first compensation output module 131, in which... Figure 3 The power transistors suitable for LDOs are P-type MOSFETs. Figure 4 This applies to situations where the power transistor in an LDO is an N-type MOSFET. Figure 1 In the LDO, the power transistor M0 connected to the error amplifier EA is an N-type MOS transistor. Figure 1 The LDO is just a schematic diagram; it can also be represented as follows: Figure 5(The case of the P-type MOS transistor is shown).

[0047] Furthermore, such as Figure 2 As shown, the overvoltage current comparator circuit 140 includes: transistors 12 to 17 (M12-M17), a second Schmitt trigger 2, an inverter INV1, and a first current source Ib1. The control electrode of the 12th transistor M12 is coupled to the differential comparator circuit 110. The 12th transistor M12 is configured to mirror the first current I1 to generate a seventh current I7. The first electrode of the 12th transistor M12 is coupled to ground, and the second electrode of the 12th transistor M12 is coupled to the input terminal of the second Schmitt trigger 2. The control electrode of the 13th transistor M13 is coupled to the differential comparator circuit 110. The 13th transistor M13 generates an eighth current I8 according to the current source in the differential comparator circuit 110. The first electrode of the 13th transistor M13 is coupled to the power supply voltage VDD, and the second electrode of the 13th transistor M13 is coupled to the input terminal of the second Schmitt trigger 2. The control electrodes of the 14th transistor M14, 15th transistor M15, and 16th transistor M16 are... The first terminals of transistors M14, M15, and M16 are all coupled to ground. The second terminal of transistor M14 is coupled to the input of the second Schmitt trigger 2. The second terminal of transistor M15 is coupled to the first terminal of transistor M17. The second terminal of transistor M17 is coupled to the input of the second Schmitt trigger 2. The control terminal of transistor M17 is coupled to the output of the second Schmitt trigger 2. The output of the second Schmitt trigger 2 is also coupled to the input of inverter INV1. The output terminal B of inverter INV1 is coupled to the overvoltage compensation circuit 150 as the output of overvoltage current comparator circuit 140. The ninth current I9 is ​​the sum of the current flowing through transistor M12, transistor M14, and transistor M15.

[0048] Furthermore, such as Figure 2As shown, the overvoltage compensation circuit 150 includes: eighteenth to twenty-third transistors (M18-M23) and a second compensation output module 151. The control electrode of the eighteenth transistor M18 is coupled to a differential comparator circuit 110. The eighteenth transistor M18 is configured to mirror the first current I1 to generate a tenth current I10. The first electrode of the eighteenth transistor M18 is coupled to ground, and the second electrode of the eighteenth transistor M18 is coupled to the second electrode of the nineteenth transistor M19. The control electrode of the nineteenth transistor M19 is coupled to the differential comparator circuit 110. The nineteenth transistor M19 generates current according to the current source in the differential comparator circuit 110, and the first electrode of the nineteenth transistor M19 is coupled to the power supply voltage VDD. The control electrodes of the twentieth transistor M20 and the twenty-first transistor M21 are both coupled to the second electrode of the eighteenth transistor M18. The first terminal of the 21st transistor M21 is coupled to the ground terminal. The second terminal of the 20th transistor M20 is coupled to the control terminal of the 20th transistor M20. The second terminal of the 21st transistor M21 is coupled to the first terminal of the 22nd transistor M22. The current flowing through the 20th transistor M20 is the 11th current I11, and the current flowing through the 21st transistor M21 is the mirror current I11' of the 11th current. The control terminal of the 22nd transistor M22 is coupled to the level signal output by the overvoltage current comparator circuit 140. The second terminal of the 22nd transistor M22 is coupled to the control terminal and the second terminal of the 23rd transistor M23. The first terminal of the 23rd transistor M23 is coupled to the ground terminal. The second compensation output module 151 is configured to output a second compensation current Ic2 based on the mirror current I11' of the 11th current.

[0049] Furthermore, such as Figure 6 As shown, the second compensation output module 151 includes: a twenty-sixth transistor M26, wherein the control electrode of the twenty-sixth transistor M26 is coupled to the control electrode of the twenty-third transistor M23, the first electrode of the twenty-sixth transistor M26 is coupled to the power supply voltage VDD, and the second electrode of the twenty-sixth transistor M26 outputs a second compensation current Ic2; or, as shown Figure 7 As shown, the second compensation output module 151 includes: a twenty-seventh transistor M27, wherein the control electrode of the twenty-seventh transistor M27 is coupled to the control electrode of the twenty-first transistor M21, the first electrode of the twenty-seventh transistor M27 is coupled to the ground terminal, and the second electrode of the twenty-seventh transistor M27 outputs a second compensation current Ic2. Figure 6 and Figure 7 The diagram shows two structures of the second compensation output module 151, in which... Figure 6 The power transistors suitable for LDOs are P-type MOSFETs. Figure 7 This applies to situations where the power transistor in an LDO is an N-type MOSFET.

[0050] Furthermore, such as Figure 8As shown, an exemplary circuit diagram of a differential comparator circuit 110 is provided, including: transistors 28 to 40 (M28-M40), a second current source Ib2, a first resistor R1, and an input stage module 111. The first terminals of transistors 28 (M28) and 29 (M29) are both coupled to the power supply voltage VDD. The control terminal of transistor 28 (M28) is coupled to the control terminal of transistor 29 (M29), the second terminal of transistor 28 (M28), and the first terminal of transistor 30 (M30). The second terminal of transistor 29 (M29) is coupled to one end of the first resistor R1. The second terminal of transistor 30 (M30) is coupled to the second current source. Ib2, the control terminal of the 30th transistor M30; the other end of the first resistor R1 is coupled to the second terminal of the 31st transistor M31 and the control terminal of the 32nd transistor M32, respectively. The control terminal of the 31st transistor M31 is coupled to one end of the first resistor R1, the first terminal of the 31st transistor M31 is coupled to the second terminal of the 32nd transistor M32, and the first terminal of the 32nd transistor M32 is coupled to ground; the control terminal of the 33rd transistor M33 is coupled to the control terminal of the 29th transistor M29, the first terminal of the 33rd transistor M33 is coupled to the power supply voltage VDD, and the second terminal of the 33rd transistor M33 is coupled to the control terminal of the 34th transistor M34. The control terminal of the thirty-fourth transistor M34 is coupled to the control terminal of the thirtieth transistor M30. The second terminal of the thirty-fourth transistor M34 is coupled to the second terminal of the thirty-fifth transistor M35, the control terminals of the thirty-sixth transistor M36, and the control terminals of the thirty-seventh transistor M37. The control terminal of the thirty-fifth transistor M35 is coupled to the control terminal of the thirty-first transistor M31. The first terminal of the thirty-fifth transistor M35 is coupled to the second terminal of the thirty-sixth transistor M36. The first terminals of the thirty-sixth transistor M36 and the thirty-seventh transistor M37 are both coupled to ground. The second terminal of the thirty-seventh transistor M37 is coupled to the first terminal of the thirty-eighth transistor M38. The control terminal of the thirty-eighth transistor M38 is coupled to the control terminal of the thirty-fifth transistor M35. The second terminal of the thirty-eighth transistor M38 is coupled to the second terminal of the thirty-ninth transistor M39. The control terminal of the thirty-ninth transistor M39 is coupled to the control terminal of the thirty-fourth transistor M34. The first terminal of the thirty-ninth transistor M39 is coupled to the second terminal of the fortieth transistor M40. The control terminal of the fortieth transistor M40 is coupled to the control terminal of the thirty-third transistor M33. The first terminal of the fortieth transistor M40 is coupled to the power supply voltage VDD. The current flowing through the thirty-sixth transistor M36 is the first current I1, and the current flowing through the thirty-seventh transistor M37 is the second current I2.Input stage module 111 includes transistors 41 to 43, wherein the control electrode of transistor 41 M41 is coupled to the control electrode of transistor 29 M29, the first electrode of transistor 41 M41 is coupled to the power supply voltage VDD, the second electrode of transistor 41 M41 is coupled to the first electrode of transistor 42 M42 and transistor 43 M43 respectively, and the control electrode of transistor 42 M42 is coupled to the feedback voltage V. FB The control electrode of the forty-third transistor M43 is coupled to the reference voltage Vref; the second electrode of the forty-second transistor M42 is coupled to the second electrode of the thirty-sixth transistor M36; and the second electrode of the forty-third transistor M43 is coupled to the second electrode of the thirty-seventh transistor M37. It should be noted that the aforementioned M2, M3, M4, M7, M13, and M19 are coupled to the differential comparator circuit 110, specifically, the control electrodes of M2, M3, M4, M7, M13, and M19 are all coupled to the control electrode of M28 in the differential comparator circuit 110. Similarly, the aforementioned M1, M6, M12, and M18 are coupled to the differential comparator circuit 110, specifically, the control electrodes of M1, M6, M12, and M18 are all coupled to the control electrode of M36 in the differential comparator circuit 110.

[0051] Furthermore, such as Figure 9 As shown, another exemplary circuit diagram of a differential comparator circuit 110 is also provided. Figure 9 and Figure 8 In comparison, only the structure of the input-level module 111 is different; everything else is the same. Figure 8 The input stage module 111 includes M42 and M43, which are P-type MOS transistors, forming a P-type input pair structure. Figure 9 M46 and M47 are N-type MOS transistors, which have an N-type input pair structure. Figure 9 In the input stage module 111, transistors 44 to 47 (M44-M47) are included. The control electrode of transistor 44 (M44) is coupled to the control electrode of transistor 32 (M32). The first electrode of transistor 44 (M44) is coupled to ground. The second electrode of transistor 44 (M44) is coupled to the first electrode of transistor 45 (M45). The control electrode of transistor 45 (M45) is coupled to the control electrode of transistor 31 (M31). The second electrode of transistor 45 (M45) is coupled to the first electrodes of transistors 46 (M46) and 47 (M47). The control electrode of transistor 46 (M46) is coupled to the feedback voltage V. FB The control terminal of the forty-seventh transistor M47 is coupled to the reference voltage Vref; the second terminal of the forty-sixth transistor M46 is coupled to the second terminal of the thirty-third transistor M33; and the second terminal of the forty-seventh transistor M47 is coupled to the second terminal of the fortieth transistor M40. It should be noted that... Figure 8 and Figure 9The example is for illustration that the differential comparator circuit 110 in the embodiments of this disclosure can be either a pair of P-type MOS transistors or a pair of N-type MOS transistors.

[0052] Furthermore, in combination Figure 2-7 The working principle of the transient response enhancement circuit 100 in the embodiments of this disclosure will be described in detail:

[0053] When the system is in equilibrium without any sudden load changes, V FB Equal to parameter Vref, I1 and I2 are equal. In the undervoltage current comparator circuit 120, I3 = a I1, where 'a' is the proportional gain, the current flowing through M2 is equal to I3, and the current I4 is equal to the sum of the currents flowing through M2, M3, and M4. Therefore, I4 is greater than I3, and the output terminal A of Schmitt1 is at a low voltage, i.e., a low-level signal. I5 = b I1, where b is also a proportionality coefficient, I6 is the difference between the current flowing through M7 and the current flowing through I5. At this time, the current flowing through M7 is also I5, therefore I6 and I6' = 0. Since point A is a low-level signal, switch M10 is off, and Ic1 = 0. In the overvoltage current comparison circuit 140, I7 = e I1 and e are also proportional coefficients. The current I8 flowing through M13 is equal to I7, while the current I9 is ​​equal to the sum of the currents flowing through M12, M14, and M15. Therefore, I9 is ​​greater than I8. Thus, the output of Schmitt2 is high voltage, and after passing through inverter INV1, point B becomes low voltage. I10 = f I1 and f are also proportional coefficients. I11 is the difference between the current flowing through M19 and the current flowing through I10. At this time, the current flowing through M19 is also I10. Therefore, I11 and I11' = 0. Since point B is a low-level signal, M22 is in the off state, and Ic2 = 0.

[0054] When the load suddenly changes from light load to heavy load, and the LDO output voltage Vout becomes undervoltage, V FB If I decreases, I1 will increase. I1, I1=gm1 V FB ,by Figure 8 For example, where gm1 is the transconductance of the input transistor M42, if it is Figure 9 Then gm1 is the transconductance of the input transistor M46. V FB For V FB The amount of voltage drop. When I1 increases If I1, then I3 will increase a. I1, when a When I1 is greater than the sum of the currents flowing through M3 and M4, the sum of the currents through M3 and M4 is the first current threshold Ith1. That is, when I4 is greater than I3, the output terminal A of the undervoltage current comparator circuit 120 will become a high-level signal, corresponding to a change in the output voltage Vout. FB The decrease in change is greater than V1_R=I th1 / (gm1 When a), A is a high-level signal, and M10 is closed; when I1 increases... If I1, then I5 will increase b. The difference between I1, I5 and the current flowing through M7 will also increase. I1, therefore I6 equals b I1, I6'=c I6, Ic1=d I6', where c and d are the corresponding mirror ratios, and combining all the formulas above, we get Ic1=b c d I1. If the LDO's power transistor is a P-type MOSFET, it will pull the gate terminal low, increasing the power transistor's capability. If the LDO's power transistor is an N-type MOSFET, it will pull the gate terminal high, increasing the power transistor's capability. When a When I1 drops below the current flowing through M3, the current flowing through M3 becomes the second current threshold Ith2. Point A will then return to a low-level signal, corresponding to a change in the output voltage Vout. That is, when V... FB The change gradually decreases until it is less than V1_F=I th2 / (gm1 When a), A becomes a low-level signal, M10 is turned off, and Ic1=0. As mentioned above, V1_R and The size of V1_F can be set reasonably according to system requirements. In practical applications, it can be determined first based on the needs. V1_R and The value of V1_F is then used to further determine I based on gm1 and a. th1 and I th2 Value. It can be seen that Ic1 only has current when A is a high-level signal, i.e., V. FB The decrease reached Current will only flow after V1_R, such as Figure 10As shown. Without this judgment switch, when mismatches occur in the entire system, the current flowing through M7 in the balanced state may be less than I5, resulting in current flowing through I6. Consequently, a current Ic1 will continuously flow across the gate terminal of the LDO power transistor in the balanced state, introducing unintended errors into the entire system. Furthermore, it can be seen that the current Ic1 will change with... I1 changes, The larger I1 is, the larger Ic1 is. The smaller I1 is, the smaller Ic1 is. Ic1 changes with V. FB The lower the process, the stronger the adjustment ability, as V... FB As the current gradually increases, the regulating ability gradually weakens. This dynamic regulating ability is more effective than directly applying a fixed current.

[0055] When the load suddenly changes from heavy load to light load, and the LDO output voltage Vout becomes overvoltage, V FB If I increases, then I1 will decrease. I1, I1=gm1 V FB , V FB For V FB The amount of voltage increase. When I1 decreases. If I1, then I7 will decrease by e. I1, when e When I1 is greater than the sum of the currents flowing through M14 and M15, the sum of the currents flowing through M14 and M15 is the third current threshold Ith3. That is, when I8 is greater than I9, the output B of the overvoltage current comparator circuit 140 will become a high-level signal, corresponding to a change in the output voltage Vout. FB The change in elevation is greater than V2_R=I th3 / (gm1 e) When B is a high-level signal, M22 is closed; when I1 decreases... The decrease in I1 and I10 is f When I1 is in equilibrium, I10 equals the current flowing through M19, and at this time I11 equals the decrease in I10 by f. I1;I11'=g I11, Ic2=h I11', where g and h are the corresponding mirror ratios, and combining all the formulas above, we get Ic2=f g h I1. If the LDO's power transistor is a P-type MOSFET, it will pull the gate high, weakening the power transistor's capability. If the LDO's power transistor is an N-type MOSFET, it will pull the gate low, weakening the power transistor's capability. When e When I1 decreases to less than the current flowing through M14, the current value flowing through M14 becomes the fourth current threshold Ith4. Point B will then return to a low-level signal, corresponding to a change in the output voltage Vout. FB The increase gradually decreases to less than V2_F=I th4 / (gm1 At time e), B becomes a low-level signal, M22 is turned off, and Ic2=0. Similarly... V2_R and The size of V2_F can be set reasonably according to system requirements. In practical applications, it can be determined first based on the needs. V2_R and The value of V2_F is then used to further determine I based on gm1 and e. th3 and I th4 Value. It can be seen that Ic2 only has current when B is a high-level signal, i.e., V. FB The increase reached Current will only flow after V2_R, such as Figure 10 As shown. Without this judgment switch, when mismatches occur in the entire system, I10 might be less than the current flowing through M19 in the balanced state. Then, I11 will have current, resulting in a current Ic2 continuously flowing across the gate terminal of the LDO power transistor in the balanced state. This will introduce unintended errors into the entire system. Furthermore, it can be seen that the current Ic2 will change with... I1 changes, The larger I1 is, the larger Ic2 is. The smaller I1 is, the smaller Ic2 is. Ic2 increases with V. FB The stronger the adjustment ability during the rising process, the better as V... FB As the current gradually decreases, the regulating capability gradually weakens. This dynamic regulating capability is more effective than directly applying a fixed current.

[0056] Furthermore, such as Figure 11 As shown, the undervoltage compensation circuit 130 also includes a third compensation output module 132 corresponding to each stage of amplifiers (A1~An) after the error amplifier EA. Each third compensation output module 132 corresponds to one stage of amplifier, and each third compensation output module 132 has the same structure as the first compensation output module 131. The output of each third compensation output module 132 is coupled to the output terminal of an amplifier. Figure 12As shown, the overvoltage compensation circuit 150 also includes a fourth compensation output module 152 corresponding to each stage of the amplifier after the error amplifier EA. Each fourth compensation output module 152 corresponds to a stage amplifier. Each fourth compensation output module 152 has the same structure as the second compensation output module 151. The output of each fourth compensation output module 152 is coupled to the output terminal of an amplifier. Figure 11 and Figure 12 The structure is suitable for Figure 13 LDOs also include multi-stage amplifier structures. Figure 13 If there is an n-stage amplifier, then Figure 11 and Figure 12 There are n third compensation output modules 132 and n fourth compensation output modules 152, resulting in n third compensation currents Ic3 and n fourth compensation currents Ic4. The third compensation output module 132 has the same structure and connection as the first compensation output module 131. The third compensation output module 132 is only used to obtain a compensation current with a different value than the first compensation current Ic1 (i.e., the ratio of Ic3 to I6' is different from the ratio of Ic1 to I6') to provide to the output terminals of different stages of amplifiers, because the compensation current required at the output terminals of different stages of amplifiers is usually different. Similarly, the fourth compensation output module 152 has the same structure and connection as the second compensation output module 151. The fourth compensation output module 152 is only used to obtain a compensation current with a different value than the second compensation current Ic2 (i.e., the ratio of Ic4 to I11' is different from the ratio of Ic2 to I11') to provide to the output terminals of different stages of amplifiers. It should be noted that... Figure 13 The diagram shows the case where the power transistor M0 is an N-type MOSFET. Of course, in practical applications, it also applies to the case where the power transistor M0 is a P-type MOSFET. Figure 11-13 The corresponding implementation can improve the transient response of the LDO by increasing the slew rate of each amplifier stage.

[0057] In summary, the transient response enhancement circuit applied to LDOs according to the embodiments of this disclosure can effectively improve transient response capability.

[0058] Furthermore, this disclosure also provides a low-dropout linear regulator, which includes a transient response enhancement circuit for an LDO according to any one of the foregoing embodiments. Therefore, the low-dropout linear regulator in this disclosure has better transient response capability. Corresponding to the transient response enhancement circuit in the foregoing embodiments, the low-dropout linear regulator in this embodiment can be... Figure 1 or Figure 5 The circuit structure shown in the diagram can also be Figure 13 The circuit structure is shown in the figure.

[0059] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0060] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0061] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A transient response improvement circuit for LDOs, characterized in that, The transient response enhancement circuit includes: a differential comparator circuit, an undervoltage current comparator circuit, an undervoltage compensation circuit, an overvoltage current comparator circuit, and an overvoltage compensation circuit. The differential comparator circuit is configured to compare two voltage signals, a reference voltage and a feedback voltage, and convert the two voltage signals into two current signals. The current signal corresponding to the feedback voltage is a first current, and the current signal corresponding to the reference voltage is a second current. The reference voltage is the input reference voltage of the error amplifier in the low-dropout linear regulator, and the feedback voltage is the feedback voltage of the output voltage of the low-dropout linear regulator. The undervoltage current comparison circuit is configured to generate a third current positively correlated with the first current, and to compare the magnitudes of the third current and the fourth current via a Schmitt trigger. After the output voltage becomes undervoltage, when the increase in the third current is greater than a first current threshold, a high-level signal is output, and when the increase in the third current is less than a second current threshold, a low-level signal is output. The first current threshold is the steady-state difference between the fourth current and the third current, and the second current threshold is less than the first current threshold. The undervoltage compensation circuit is configured to generate a fifth current positively correlated with the first current and a sixth current positively correlated with the change of the first current, and to control the input of a first compensation current to the output of the error amplifier according to the level signal output by the undervoltage current comparison circuit. The first compensation current is positively correlated with the mirror current of the sixth current. The overvoltage current comparison circuit is configured to generate a seventh current positively correlated with the first current, an eighth current equal to the steady-state value of the seventh current, and to compare the magnitudes of the eighth current and the ninth current via a Schmitt trigger. After the output voltage becomes overvoltage, when the drop in the seventh current is greater than a third current threshold, a high-level signal is output, and when the drop in the seventh current is less than a fourth current threshold, a low-level signal is output. The ninth current is the sum of the seventh current and the third current threshold, and the fourth current threshold is less than the third current threshold. The overvoltage compensation circuit is configured to generate a tenth current positively correlated with the first current and an eleventh current positively correlated with the change of the first current, and to control the input of a second compensation current to the output of the error amplifier according to the level signal output by the overvoltage current comparison circuit. The second compensation current is positively correlated with the mirror current of the eleventh current.

2. The transient response improvement circuit for LDOs according to claim 1, characterized in that, The undervoltage current comparison circuit includes: first to fifth transistors and a first Schmitt trigger. The control electrode of the first transistor is coupled to the differential comparator circuit. The first transistor is configured to mirror the first current to generate the third current. The first electrode of the first transistor is coupled to the ground terminal, and the second electrode of the first transistor is coupled to the input terminal of the first Schmitt trigger. The control terminals of the second, third, and fourth transistors are all coupled to the differential comparator circuit. The second, third, and fourth transistors generate three currents according to the current source in the differential comparator circuit. The first terminals of the second, third, and fourth transistors are all coupled to the power supply voltage. The second terminals of the second and third transistors are all coupled to the input terminal of the first Schmitt trigger. The second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor. The control terminal of the fifth transistor is coupled to the output terminal of the first Schmitt trigger. The second terminal of the fifth transistor is coupled to the input terminal of the first Schmitt trigger. The sum of the three currents is the fourth current. The output of the first Schmitt trigger is also coupled to the undervoltage compensation circuit as the output of the undervoltage current comparison circuit.

3. The transient response improvement circuit for LDOs according to claim 2, characterized in that, The undervoltage compensation circuit includes: transistors six to eleven and a first compensation output module. The control electrode of the sixth transistor is coupled to the differential comparator circuit. The sixth transistor is configured to mirror the first current to generate the fifth current. The first electrode of the sixth transistor is coupled to the ground terminal, and the second electrode of the sixth transistor is coupled to the second electrode of the seventh transistor. The control electrode of the seventh transistor is coupled to the differential comparator circuit. The seventh transistor generates current according to the current source in the differential comparator circuit. The first electrode of the seventh transistor is coupled to the power supply voltage. The control terminals of the eighth and ninth transistors are both coupled to the second terminal of the seventh transistor. The first terminals of the eighth and ninth transistors are both coupled to the power supply voltage. The second terminal of the eighth transistor is coupled to the control terminal of the eighth transistor. The second terminal of the ninth transistor is coupled to the second terminal of the tenth transistor. The current flowing through the eighth transistor is the sixth current, and the current flowing through the ninth transistor is the mirror current of the sixth current. The control electrode of the tenth transistor is coupled to the level signal output by the undervoltage current comparator circuit, the first electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor and the second electrode of the eleventh transistor, and the first electrode of the eleventh transistor is coupled to the ground terminal. The first compensation output module is configured to output the first compensation current based on the mirror current of the sixth current.

4. The transient response improvement circuit for LDOs according to claim 3, characterized in that, The overvoltage current comparison circuit includes: transistors twelve to seventeen, a second Schmitt trigger, an inverter, and a first current source. The control electrode of the twelfth transistor is coupled to the differential comparator circuit. The twelfth transistor is configured to mirror the first current to generate the seventh current. The first electrode of the twelfth transistor is coupled to the ground terminal, and the second electrode of the twelfth transistor is coupled to the input terminal of the second Schmitt trigger. The control electrode of the thirteenth transistor is coupled to the differential comparator circuit. The thirteenth transistor generates the eighth current according to the current source in the differential comparator circuit. The first electrode of the thirteenth transistor is coupled to the power supply voltage, and the second electrode of the thirteenth transistor is coupled to the input terminal of the second Schmitt trigger. The control terminals of the fourteenth, fifteenth, and sixteenth transistors are all coupled to the second terminal of the sixteenth transistor and the first current source. The first terminals of the fourteenth, fifteenth, and sixteenth transistors are all coupled to ground. The second terminal of the fourteenth transistor is coupled to the input terminal of the second Schmitt trigger. The second terminal of the fifteenth transistor is coupled to the first terminal of the seventeenth transistor. The second terminal of the seventeenth transistor is coupled to the input terminal of the second Schmitt trigger, and the control terminal of the seventeenth transistor is coupled to the output terminal of the second Schmitt trigger. The output of the second Schmitt trigger is also coupled to the input of the inverter, and the output of the inverter is coupled to the overvoltage compensation circuit as the output of the overvoltage current comparison circuit. The ninth current is the sum of the current flowing through the twelfth transistor, the current flowing through the fourteenth transistor, and the current flowing through the fifteenth transistor.

5. The transient response improvement circuit for LDOs according to claim 4, characterized in that, The overvoltage compensation circuit includes: transistors eighteen to twenty-three and a second compensation output module. The control electrode of the eighteenth transistor is coupled to the differential comparator circuit. The eighteenth transistor is configured to mirror the first current to generate the tenth current. The first electrode of the eighteenth transistor is coupled to the ground terminal, and the second electrode of the eighteenth transistor is coupled to the second electrode of the nineteenth transistor. The control electrode of the nineteenth transistor is coupled to the differential comparator circuit. The nineteenth transistor generates current according to the current source in the differential comparator circuit. The first electrode of the nineteenth transistor is coupled to the power supply voltage. The control terminals of the 20th and 21st transistors are both coupled to the second terminal of the 18th transistor. The first terminals of the 20th and 21st transistors are both coupled to the ground terminal. The second terminal of the 20th transistor is coupled to the control terminal of the 20th transistor. The second terminal of the 21st transistor is coupled to the first terminal of the 22nd transistor. The current flowing through the 20th transistor is the 11th current. The current flowing through the 21st transistor is the mirror current of the 11th current. The control electrode of the 22nd transistor is coupled to the level signal output by the overvoltage current comparison circuit, the second electrode of the 22nd transistor is coupled to the control electrode of the 23rd transistor and the second electrode of the 23rd transistor, and the first electrode of the 23rd transistor is coupled to the ground terminal; The second compensation output module is configured to output the second compensation current based on the mirror current of the eleventh current.

6. The transient response improvement circuit for LDOs according to claim 5, characterized in that, The first compensation output module includes: a twenty-fourth transistor or a twenty-fifth transistor. Wherein, the control electrode of the 24th transistor is coupled to the control electrode of the 11th transistor, the first electrode of the 24th transistor is coupled to the ground terminal, and the second electrode of the 24th transistor outputs the first compensation current. The control electrode of the 25th transistor is coupled to the control electrode of the 9th transistor, the first electrode of the 25th transistor is coupled to the power supply voltage, and the second electrode of the 25th transistor outputs the first compensation current.

7. The transient response improvement circuit for LDOs according to claim 6, characterized in that, The second compensation output module includes: a twenty-sixth transistor or a twenty-seventh transistor. In this configuration, the control electrode of the 26th transistor is coupled to the control electrode of the 23rd transistor, the first electrode of the 26th transistor is coupled to the power supply voltage, and the second electrode of the 26th transistor outputs the second compensation current. The control electrode of the 27th transistor is coupled to the control electrode of the 21st transistor, the first electrode of the 27th transistor is coupled to the ground terminal, and the second electrode of the 27th transistor outputs the second compensation current.

8. The transient response improvement circuit for LDOs according to claim 1, characterized in that, The differential comparator circuit includes: transistors 28 to 40, a second current source, a first resistor, and an input stage module. In this configuration, the first terminals of the 28th and 29th transistors are both coupled to the power supply voltage. The control terminal of the 28th transistor is coupled to the control terminal of the 29th transistor, the second terminal of the 28th transistor, and the first terminal of the 30th transistor. The second terminal of the 29th transistor is coupled to one end of the first resistor. The second terminal of the 30th transistor is coupled to the second current source and the control terminal of the 30th transistor. The other end of the first resistor is coupled to the second terminal of the thirty-first transistor and the control terminal of the thirty-second transistor, respectively. The control terminal of the thirty-first transistor is coupled to one end of the first resistor, the first terminal of the thirty-first transistor is coupled to the second terminal of the thirty-second transistor, and the first terminal of the thirty-second transistor is coupled to the ground terminal. The control terminal of the 33rd transistor is coupled to the control terminal of the 29th transistor. The first terminal of the 33rd transistor is coupled to the power supply voltage. The second terminal of the 33rd transistor is coupled to the first terminal of the 34th transistor. The control terminal of the 34th transistor is coupled to the control terminal of the 30th transistor. The second terminal of the 34th transistor is coupled to the second terminal of the 35th transistor, the control terminal of the 36th transistor, and the control terminal of the 37th transistor. The control terminal of the 35th transistor is coupled to the control terminal of the 31st transistor. The first terminal of the 35th transistor is coupled to the second terminal of the 36th transistor. The first terminals of the 36th and 37th transistors are... All are coupled to the ground terminal. The second terminal of the thirty-seventh transistor is coupled to the first terminal of the thirty-eighth transistor. The control terminal of the thirty-eighth transistor is coupled to the control terminal of the thirty-fifth transistor. The second terminal of the thirty-eighth transistor is coupled to the second terminal of the thirty-ninth transistor. The control terminal of the thirty-ninth transistor is coupled to the control terminal of the thirty-fourth transistor. The first terminal of the thirty-ninth transistor is coupled to the second terminal of the fortieth transistor. The control terminal of the fortieth transistor is coupled to the control terminal of the thirty-third transistor. The first terminal of the fortieth transistor is coupled to the power supply voltage. The current flowing through the thirty-sixth transistor is the first current, and the current flowing through the thirty-seventh transistor is the second current. The input stage module includes transistors 41 to 43, wherein the control electrode of transistor 41 is coupled to the control electrode of transistor 29, the first electrode of transistor 41 is coupled to a power supply voltage, the second electrode of transistor 41 is coupled to the first electrodes of transistors 42 and 43, respectively, the control electrode of transistor 42 is coupled to the feedback voltage, the control electrode of transistor 43 is coupled to the reference voltage, the second electrode of transistor 42 is coupled to the second electrode of transistor 36, and the second electrode of transistor 43 is coupled to the second electrode of transistor 37; or... The input stage module includes transistors 44 to 47, wherein the control electrode of transistor 44 is coupled to the control electrode of transistor 32, the first electrode of transistor 44 is coupled to ground, the second electrode of transistor 44 is coupled to the first electrode of transistor 45, the control electrode of transistor 45 is coupled to the control electrode of transistor 31, the second electrode of transistor 45 is coupled to the first electrodes of transistors 46 and 47, the control electrode of transistor 46 is coupled to the feedback voltage, the control electrode of transistor 47 is coupled to the reference voltage, the second electrode of transistor 46 is coupled to the second electrode of transistor 33, and the second electrode of transistor 47 is coupled to the second electrode of transistor 40.

9. The transient response improvement circuit for LDOs according to claim 7, characterized in that, The undervoltage compensation circuit also includes a third compensation output module corresponding to each stage of the amplifier after the error amplifier. Each third compensation output module corresponds to a stage of the amplifier. Each third compensation output module has the same structure as the first compensation output module. The output of each third compensation output module is coupled to the output terminal of an amplifier. The overvoltage compensation circuit also includes a fourth compensation output module corresponding to each stage of the amplifier after the error amplifier. Each fourth compensation output module corresponds to a stage of the amplifier. Each fourth compensation output module has the same structure as the second compensation output module. The output of each fourth compensation output module is coupled to the output terminal of an amplifier.

10. A low-dropout linear regulator, characterized in that, The low-dropout linear regulator includes a transient response enhancement circuit for an LDO according to any one of claims 1 to 9.

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