Fast response linear voltage regulator without continuous time high-precision error amplifier

Abstract

The invention discloses a quick response linear voltage regulator without a continuous time high-precision error amplifier. The linear voltage regulator comprises a first output stage circuit used for generating a first output voltage according to a first control voltage; and a correction circuit which is enabled in a first correction period after the linear voltage regulator is started. In a first correction period, the correction circuit is used for generating a first control voltage according to an output related signal and a reference voltage, and the output related signal is related to a first output voltage. The first output stage circuit and the correction circuit form a first control loop, and the first control loop enters an open loop state after the first correction period ends. The first output stage circuit comprises a second control loop used for adjusting the first output voltage in a closed loop mode according to the change of the first control voltage and the first output voltage during the operation period after the first correction period.

Description

Technical Field

[0001] This invention relates to a linear regulator, and more particularly to a fast-response linear regulator that does not require a continuous-time high-precision error amplifier. Background Technology

[0002] Figure 1 A schematic diagram of a prior art linear regulator 1001 is shown. The linear regulator 1001 includes an error amplifier 900 and an output stage circuit 910. This prior art linear regulator 1001 includes a feedback tracking loop and a fast tracking loop. The feedback tracking loop adjusts the output voltage level of an output voltage Vregout based on a feedback voltage Vfb and a reference voltage Vref. The fast tracking loop is used to respond to fast load transients on the output voltage Vregout. In this prior art, both the feedback tracking loop and the fast tracking loop adjust the output voltage Vregout in a closed-loop manner.

[0003] like Figure 1 As shown, a power transistor Mpp in the output stage circuit 910 generates an output voltage Vregout based on a drive voltage Vpg. A current-guided control transistor Mset is controlled by a control voltage Vset generated by the error amplifier 900 to guide and regulate a first bias current Ibb1 and a second bias current Ibb2 in a main bias current Ibb.

[0004] From another perspective, in this prior art, the feedback tracking loop (i.e., error amplifier 900) is used to respond to errors in the output voltage Vregout at DC and low frequencies, providing high-precision regulation. Simultaneously, the fast tracking loop (i.e., output stage circuit 910) is used to respond to transients in the output voltage Vregout at high frequencies. It should be noted that both the feedback tracking loop and the fast tracking loop operate continuously in a closed-loop manner.

[0005] like Figure 1 The disadvantage of this prior art is that the error amplifier 900 in the linear regulator 1001 must operate continuously in a closed-loop manner. Although this configuration can provide fast response and high accuracy, the design of the amplifier and resistors R1 and R2 results in higher cost and increased power consumption.

[0006] In view of this, the present invention addresses the shortcomings of the prior art by proposing an innovative linear regulator that eliminates the need for an error amplifier, or more broadly, eliminates the need for a continuously operating high-precision feedback loop to regulate the output voltage. This method achieves the effects of reducing cost and power consumption. Summary of the Invention

[0007] From one perspective, the present invention provides a linear regulator comprising: a first output stage circuit for generating a first output voltage based on a first control voltage; and a correction circuit enabled during a first correction period after the linear regulator is started, wherein during the first correction period, the correction circuit generates the first control voltage based on an output correlation signal and a reference voltage, and the output correlation signal is correlated with the first output voltage; wherein the first output stage circuit and the correction circuit form a first control loop, the first control loop entering an open-loop state after the first correction period ends; wherein the first output stage circuit includes a second control loop for adjusting the first output voltage in a closed-loop manner during an operation period following the first correction period, based on changes in the first control voltage and the first output voltage.

[0008] In one embodiment, the correction circuit is further configured to store the first control voltage after the first correction period ends; wherein after the correction circuit stores the first control voltage, a portion of the sub-circuit of the correction circuit is disabled, thereby entering the open-loop state.

[0009] In one embodiment, the linear regulator further includes: a sensing circuit for generating an output correlation signal based on the first output voltage during the first calibration period; wherein the calibration circuit includes: a comparator for generating a comparison signal based on a comparison of the output correlation signal and the reference voltage during the first calibration period; and a control circuit for generating the first control voltage based on the comparison signal during the first calibration period; wherein after the calibration circuit stores the first control voltage, the sensing circuit is disabled and / or the comparator is disabled.

[0010] In one embodiment, the control circuit includes: an adjustment circuit for generating an adjustment signal based on the comparison signal during the first correction period, and for storing the adjustment signal after the first correction period ends; and a voltage generation circuit for generating the first control voltage based on the adjustment signal.

[0011] In one embodiment, the correction circuit corrects and generates the first control voltage according to a linear search or a binary search, such that the difference between the level of the output correlation signal and the level of the reference voltage is less than a first threshold, thereby making the difference between the level of the first output voltage and the level of a target voltage less than a second threshold.

[0012] In one embodiment, the first output stage circuit includes: a control terminal for receiving the first control voltage; an adjustment output terminal for generating the first output voltage; a bias current source for generating a main bias current at a bias node, wherein the main bias current includes a first bias current and a second bias current; and a first current branch and a second current branch, wherein the first current branch and the second current branch are coupled to the bias node, wherein the first bias current and the second bias current flow through the first current branch and the second current branch, respectively; wherein the first current branch is used to generate a drive voltage based on the first bias current; wherein the second current branch is used to guide the regulation of the second bias current to guide the regulation of the first bias current based on a voltage difference between the first output voltage and the first control voltage, and the second current branch is used to adjust the first output voltage based on the drive voltage and the second bias current.

[0013] In one embodiment, the first current branch includes: a bias load transistor and a common gate transistor, connected in series between an input power supply and the bias node, for operating on a drive node to generate the drive voltage according to the first bias current, wherein the gates of the bias load transistor and the common gate transistor are biased by a first bias voltage and a second bias voltage, respectively; wherein the second current branch includes: a power transistor and a current-directed regulating transistor, connected in series between the input power supply and the bias node, and coupled to the regulating output terminal, wherein the drive voltage and the first control voltage are used to control the gates of the power transistor and the current-directed regulating transistor to generate the first output voltage.

[0014] In one embodiment, the first output stage circuit includes an overshoot suppression circuit, wherein the overshoot suppression circuit includes: a first overshoot suppression transistor and a suppression resistor, connected in series to the regulated output terminal and configured as a source follower, wherein the gate and drain of the first overshoot suppression transistor are respectively coupled to the bias node and the regulated output terminal; and a second overshoot suppression transistor, coupled between the regulated output terminal and a ground potential, wherein the gate of the second overshoot suppression transistor is coupled to an output of the source follower; wherein when an overshoot occurs in the first output voltage, the first overshoot suppression transistor and the second overshoot suppression transistor are turned on, thereby suppressing the overshoot.

[0015] In one embodiment, the linear regulator further includes: a plurality of output stage circuits, including at least the first output stage circuit and a second output stage circuit; wherein the second output stage circuit is configured to generate a second output voltage according to a second control voltage; wherein the correction circuit is further configured to enable a second correction period after the first correction period, wherein during the second correction period, the correction circuit is configured to generate the second control voltage according to the output correlation signal and the reference voltage, and the output correlation signal is related to the second output voltage; wherein the second output stage circuit and the correction circuit form a third control loop, wherein the third control loop enters an open-loop state after the second correction period ends; wherein the second output stage circuit includes a fourth control loop, configured to adjust the second output voltage in a closed-loop manner according to the changes in the second control voltage and the second output voltage during the operation period after the second correction period.

[0016] In one embodiment, the correction circuit is further configured to store the second control voltage after the second correction period ends; wherein after the correction circuit stores the second control voltage, a portion of the sub-circuit of the correction circuit is disabled, thereby entering the open-loop state.

[0017] In one embodiment, the sensing circuit is further configured to generate the output correlation signal based on the second output voltage during the second calibration period; wherein the control circuit is further configured to generate the second control voltage based on the comparison signal; wherein after the calibration circuit stores the second control voltage, the sensing circuit is disabled and / or the comparator is disabled.

[0018] In one embodiment, each of the first output stage circuit and the second output stage circuit includes: a control terminal and an adjustment output terminal; a bias current source for generating a main bias current at a bias node, wherein the main bias current includes a first bias current and a second bias current; and a first current branch and a second current branch, wherein the first current branch and the second current branch are coupled to the bias node, wherein the first bias current and the second bias current flow through the first current branch and the second current branch, respectively; wherein the first current branch is used to generate a drive voltage according to the first bias current; wherein the second current branch is used to conduct... The second bias current is steered to guide the regulation of the first bias current based on a voltage difference between the regulated output voltage at the regulated output terminal and the control voltage received via the control terminal, and the second current branch is used to regulate the regulated output voltage based on the drive voltage and the second bias current; wherein the control voltage of the first output stage circuit and the control voltage of the second output stage circuit correspond to the first control voltage and the second control voltage, respectively, and the regulated output voltage of the first output stage circuit and the regulated output voltage of the second output stage circuit correspond to the first output voltage and the second output voltage, respectively.

[0019] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0020] Figure 1 A schematic diagram of a linear regulator in the prior art is shown.

[0021] Figure 2 A block diagram of one embodiment of the linear regulator of the present invention is shown.

[0022] Figure 3 A schematic diagram of one embodiment of the linear regulator of the present invention is shown.

[0023] Figure 4A A schematic diagram of a specific embodiment of the output stage circuit of the linear regulator of the present invention is shown.

[0024] Figure 4B A schematic diagram of a specific embodiment of the output stage circuit of the linear regulator of the present invention is shown.

[0025] Figure 5 A schematic diagram of a specific embodiment of the output stage circuit of the linear regulator of the present invention with an overshoot suppression circuit is shown.

[0026] Figure 6 A block diagram of one embodiment of the linear regulator of the present invention is shown.

[0027] Figure 7 A block diagram showing an embodiment of the control circuit of the linear regulator of the present invention is provided.

[0028] Figure 8 A block diagram showing an embodiment of the control circuit of the linear regulator of the present invention is provided.

[0029] Figure 9 A schematic diagram of a specific embodiment of the present invention is shown.

[0030] Figure 10 A schematic diagram of a specific embodiment of the control circuit of the linear regulator of the present invention is shown.

[0031] Figure 11 A schematic diagram of a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is shown.

[0032] Figure 12 A schematic diagram of a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is shown.

[0033] Figure 13 A schematic diagram of a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is shown.

[0034] Explanation of symbols in the diagram

[0035] 10: Sensing Circuit

[0036] 20: Comparator

[0037] 21: Bias Current Source

[0038] 30: Programmable Current Source

[0039] 40: Sub-digital-to-analog converter

[0040] 50: Amplifier

[0041] 71, 72: Selection circuit

[0042] 100, 101, 110: Correction circuit

[0043] 201, 202, 210: Output stage circuits

[0044] 220A, 220B: Output stage circuit

[0045] 222: Second current branch

[0046] 230: Output stage circuit

[0047] 300, 310, 320, 330, 340: Control circuit

[0048] 400: Overshoot suppression circuit

[0049] 500: Adjustment circuit

[0050] 601, 602, 610, 620, 630, 640, 650: Digital-to-Analog Converters

[0051] 900: Error Amplifier

[0052] 910: Output stage circuit

[0053] 1001, 1002, 1003, 1006: Linear regulators

[0054] Cmp: Comparison signal

[0055] I1~I3: Current source

[0056] Ibb: Main bias current

[0057] Ibb1: First bias current

[0058] Ibb2: Second bias current

[0059] IL1, IL2: Load

[0060] Im1, Im2: Current

[0061] Iset: Current

[0062] M1, M2: PMOS transistors

[0063] Mns, Mpp, Mset, Mcg, Mld, Msk: Transistors

[0064] Ndr: Driver Node

[0065] Nng: Bias Node

[0066] Pi: Control terminal

[0067] Po: Adjust the output terminal

[0068] R1, R2: Resistors

[0069] Rs1, Rs2, Rs3: Resistors

[0070] Rld: Bias load resistor

[0071] Rsr: Overshoot suppression resistor

[0072] Sadj1, Sadj2: Adjusting signals

[0073] SW1, SW2, SW3: Switches

[0074] Vadj: Adjust voltage

[0075] Vbg: Bandgap voltage

[0076] Vcg: Bias voltage

[0077] Vdiv: Output related signals

[0078] Vfb: Feedback voltage

[0079] VIN: Input voltage

[0080] Vpg: Drive voltage

[0081] Vref: Reference voltage

[0082] Vregout: Output voltage

[0083] VRI: Control Voltage

[0084] VRO: Regulated Output Voltage

[0085] Vro1: First output voltage

[0086] Vro2: Second output voltage

[0087] Vset: Control voltage

[0088] Vset1: First control voltage

[0089] Vset2: First control voltage Detailed Implementation

[0090] The accompanying drawings in this invention are illustrative and are primarily intended to show the coupling relationships between circuits and the relationships between signal waveforms. The circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application.

[0091] Figure 2 A block diagram showing a linear regulator 1002 according to an embodiment of the present invention. In one embodiment, as... Figure 2 As shown, the linear regulator 1002 includes an output stage circuit 201 and a correction circuit 100. The output stage circuit 201 generates a first output voltage Vro1 based on a first control voltage Vset1. The correction circuit 100 is enabled during a first correction period after the linear regulator 1002 is started.

[0092] In one embodiment, during the first correction period, the correction circuit 100 generates a first control voltage Vset1 based on the output correlation signal Vdiv and the reference voltage Vref. In this embodiment, the output correlation signal Vdiv is correlated with the first output voltage Vro1 during the first correction period. In one embodiment, the output stage circuit 201 and the correction circuit 100 form a first control loop.

[0093] In one embodiment, the correction circuit 100 is further configured to store the first control voltage Vset1 after the first correction period ends. After the correction circuit 100 stores the first control voltage Vset1, a portion of the correction circuit 100 is disabled, causing the first control loop to enter an open-loop state.

[0094] Figure 3 A schematic diagram of a linear regulator 1003 according to an embodiment of the present invention is shown. In one embodiment, the linear regulator 1003 further includes a sensing circuit 10. The sensing circuit 10 is used to generate an output correlation signal Vdiv based on a first output voltage Vro1 during a first correction period. In this embodiment, the sensing circuit 10 includes resistors R1 and R2 for dividing the first output voltage Vro1 to generate the output correlation signal Vdiv. In another embodiment, the sensing circuit 10 may be omitted; in other words, the output correlation signal Vdiv may be directly connected to the first output voltage Vro1, thereby giving the linear regulator 1003 a feedback gain of 1.

[0095] In one embodiment, the correction circuit 110 includes a comparator 20 and a control circuit 300. In one embodiment, the comparator 20 is configured to generate a comparison signal Cmp during a first correction period based on a comparison between an output correlation signal Vdiv and a reference voltage Vref. The control circuit 300 is configured to generate a first control voltage Vset1 during the first correction period based on the comparison signal Cmp. In one embodiment, the sensing circuit 10 and / or the comparator 20 are disabled after the correction circuit 110 stores the first control voltage Vset1.

[0096] like Figure 3 As shown, in one embodiment, the output stage circuit 210 includes a second control loop for adjusting the first output voltage Vro1 in a closed-loop manner according to the first control voltage Vset1 during operation after the first correction period, particularly in response to transients in the first output voltage Vro1. In other words, the second control loop can be considered a fast tracking loop. Details of the second control loop will be described in the following embodiments.

[0097] In one specific embodiment, during the first correction period, the correction circuit 110 iteratively corrects and generates a first control voltage Vset1 according to a linear search method or a binary search method until the difference between the level of the output correlation signal Vdiv and the level of the reference voltage Vref is less than a first threshold (i.e., the output correlation signal Vdiv is sufficiently close to the reference voltage Vref). This ensures that the difference between the level of the first output voltage Vro1 and the level of the target voltage is less than a second threshold (i.e., the first output voltage Vro1 is sufficiently close to the target voltage, meeting a predetermined requirement). Subsequently, the correction circuit 110 stores the first control voltage Vset1 after the first correction period ends.

[0098] It should be noted that, since the linear regulator of the present invention does not require a high-precision error amplifier that needs to operate continuously to achieve high-precision regulation as described in the prior art, cost and power consumption can be reduced. More specifically, according to the present invention, a portion of the correction circuit is prevented from entering an open-loop state during operation, thereby achieving low cost and low power consumption.

[0099] Figure 4A A schematic diagram of a specific embodiment of the output stage circuit of the linear regulator of the present invention is shown. In one embodiment, Figure 3 The topology of the output stage circuit 210 in the middle and Figure 4A The output stage circuit 220A shown is identical and corresponding. In one embodiment, the output stage circuit 220A includes a power transistor Mpp, a current-directed control transistor Mset, a common-gate transistor Mcg, a bias load transistor Mild, and a bias current source 21.

[0100] In one embodiment, bias current source 21 is used to generate a main bias current Ibb at bias node Nng. Bias load transistor Mld and common gate transistor Mcg are connected in series between input voltage VIN and bias node Nng, forming a first current branch 221. Power transistor Mpp and current-directed control transistor Mset are connected in series between input voltage VIN and bias node Nng, forming a second current branch 222, wherein power transistor Mpp and current-directed control transistor Mset are coupled to the regulating output terminal Po.

[0101] In one embodiment, the gate of the bias load transistor Mld is coupled to a fixed voltage, such as... Figure 4AThe figure shows the ground potential. The gate of the common-gate transistor Mcg is biased by a bias voltage Vcg. In one embodiment, the bias load transistor Mld and the common-gate transistor Mcg are used to generate a drive voltage Vpg based on a first bias current Ibb1 of the main bias current Ibb. This drive voltage Vpg is generated at the drive node Ndr where the bias load transistor Mld and the common-gate transistor Mcg are coupled to each other. It should be noted that the first bias current Ibb1 of the main bias current Ibb flows through the first current branch 221.

[0102] In this embodiment, the power transistor Mpp is configured as an inverting amplifier stage (i.e., its drain is coupled to the regulated output terminal Po), controlled by the drive voltage Vpg, while the current-directed regulating transistor Mset is configured as a source follower stage (i.e., its source is coupled to the regulated output terminal Po), controlled by the control voltage VRI received through the control terminal Pi of the output stage circuit 220A. The power transistor Mpp and the current-directed regulating transistor Mset are used to generate the regulated output voltage VRO at the regulated output terminal Po of the output stage circuit 220A. The second bias current Ibb2 of the main bias current Ibb flows through the aforementioned second current branch 222.

[0103] The gate-source voltage of the current-directed control transistor Mset (i.e., the voltage difference between the control voltage VRI and the regulated output voltage VRO) controls the current level of the second bias current Ibb2. Since the sum of the second bias current Ibb2 and the first bias current Ibb1 equals the main bias current Ibb, which has a fixed value, the first bias current Ibb1 also changes with the second bias current Ibb2. For example, when the voltage difference between the control voltage VRI and the regulated output voltage VRO decreases (e.g., due to a drop in the regulated output voltage VRO), the second bias current Ibb2 decreases accordingly, while the first bias current Ibb1 increases. In this case, the drive voltage Vpg decreases as the first bias current Ibb1 increases, causing the power transistor Mpp to conduct more (i.e., with lower on-resistance), thus boosting the regulated output voltage VRO. In other words, the output stage circuit 220A adjusts the regulated output voltage VRO to the level of the control voltage VRI after source-gate voltage shift via the current-directed control transistor Mset using negative feedback. From one perspective, the output stage circuit can be considered a closed-loop circuit.

[0104] Figure 4B This diagram shows a specific embodiment of the output stage circuit 220B in the linear regulator of the present invention. The output stage circuit 220B and... Figure 4A The output stage circuit 220A is similar. In this embodiment, the bias load device of the output stage circuit 220B is a bias load resistor Rld, and all the above-described functions remain the same in this embodiment.

[0105] It should be noted that, Figure 4A and 4B The control voltage VRI and the regulated output voltage VRO in the figure correspond to respectively Figure 3 The first control voltage Vset1 and the first output voltage Vro1.

[0106] Figure 5 This diagram illustrates a specific embodiment of the output stage circuit 230 of the linear regulator of the present invention, which includes an overshoot suppression circuit 400. In one embodiment, the output stage circuit 230 further includes the overshoot suppression circuit 400 for mitigating overshoot at the regulator output. In this embodiment, the overshoot suppression circuit 400 includes a first overshoot suppression transistor Mns, an overshoot suppression resistor Rsr, and a second overshoot suppression transistor Msk. The first overshoot suppression transistor Mns and the overshoot suppression resistor Rsr are connected in series and coupled between the regulated output terminal Po and ground, configured as a source follower. More specifically, the gate and drain of the first overshoot suppression transistor Mns are coupled to the bias node Nng and the regulated output terminal Po, respectively. The second overshoot suppression transistor Msk is coupled between the regulated output terminal Po and ground. More specifically, the gate of the second overshoot suppression transistor Msk is coupled to the output of the source follower. When an overshoot occurs at the regulated output voltage VRO, the current-directing control transistor Msk directs the second bias current Ibb2 to increase, and the voltage at the bias node Nng rises accordingly. Therefore, the first overshoot suppression transistor Mns and the second overshoot suppression transistor Msk are turned on, thereby pulling down the regulated output voltage VRO and suppressing the overshoot of the regulated output voltage VRO.

[0107] Figure 6 A block diagram showing one embodiment of the linear regulator of the present invention is displayed. In one embodiment, the linear regulator of the present invention may support multiple outputs. Figure 6 As shown, in one embodiment, the linear regulator 1006 may include multiple output stage circuits, such as at least two output stage circuits. In one specific embodiment, the multiple output stage circuits include output stage circuit 201 and output stage circuit 202. In one embodiment, all the above-described functions of output stage circuit 201 remain the same. In one embodiment, output stage circuit 202 is used to generate a second output voltage Vro2 according to a second control voltage Vset2. It should be noted that the second output voltage Vro2 may be equal to or different from the first output voltage Vro1.

[0108] In one embodiment, the correction circuit 101 is further configured to enable a second correction period (e.g., immediately following the first correction period). During the second correction period, the correction circuit 101 generates a second control voltage Vset2 based on the output correlation signal Vdiv and the reference voltage Vref. In this embodiment, the output correlation signal Vdiv is correlated with the second output voltage Vro2 during the second correction period. In one embodiment, the output stage circuit 202 and the correction circuit 101 form a third control loop. The third control loop enters an open-loop state after the second correction period ends.

[0109] In one embodiment, the output stage circuit 202 includes a fourth control loop for adjusting the second output voltage Vro2 in a closed-loop manner during operation following the second correction period, based on changes (including transients) in the second control voltage Vset2 and the second output voltage Vro2. Figure 6 The topologies of output stage circuits 201 and 202 in the circuit are similar to those in the circuit. Figure 4A The output stage circuit shown is the same as and corresponds to 220A.

[0110] It should be noted that, in this embodiment, the sensing circuit 10 is used to generate an output correlation signal Vdiv based on the output voltages Vro1 and Vro2 during the first correction period and the second correction period, respectively. In other words, the output correlation signal Vdiv is correlated with the output voltage Vro1 during the first correction period and with the output voltage Vro2 during the second correction period. In this embodiment, the correction circuit 101 is used to sequentially generate a first control voltage Vset1 during the first correction period and a second control voltage Vset2 during the second correction period, and store the second control voltage Vset2 after the second correction period ends. Subsequently, during operation, at least a portion of the correction circuit 101 is disabled.

[0111] It should also be noted that output stage circuits 201 and 202 are used to generate a first output voltage Vro1 and a second output voltage Vro2 based on a first control voltage Vset1 and a second control voltage Vset2, respectively. In this embodiment, output voltages Vro1 and Vro2 are used to drive loads IL1 and IL2, respectively. Other details of the linear regulator 1006 can be derived from the above embodiment.

[0112] Figure 7 A block diagram showing an embodiment of the control circuit of the linear regulator of the present invention. In one embodiment, Figure 3 The control circuit 300 in the middle can be configured as follows: Figure 7The control circuit 310 is described above. In one embodiment, the control circuit 310 includes an adjustment circuit 500 and a voltage generation circuit. In this embodiment, the voltage generation circuit is configured as a digital-to-analog converter (DAC) 601. The adjustment circuit 500 is used to generate an adjustment signal Sadj1 based on a comparison signal Cmp during a first correction period. The adjustment circuit 500 is further used to store the adjustment signal Sadj1 after the first correction period ends, thereby storing a first control voltage Vset1. The DAC 601 is used to generate the first control voltage Vset1 based on the adjustment signal Sadj1.

[0113] Figure 8 A block diagram showing an embodiment of the control circuit of the linear regulator of the present invention. Figure 8 The control circuit 320 in the middle is Figure 6 An embodiment of the control circuit for the center correction circuit 101. Control circuit 320 and... Figure 7 The control circuit 310 is similar to that in this embodiment. In this embodiment, the voltage generation circuit further includes at least one other DAC 602. DAC 602 is used to generate a second control voltage Vset2 based on the adjustment signal Sadj2 during the second correction. In this embodiment, the other functions of DAC 602 are the same as those of DAC 601.

[0114] It should be noted that, in Figure 7 and Figure 8 In one embodiment, the adjustment signal Sadj1 and / or the adjustment signal Sadj2 are generated based on the comparison signal Cmp, thereby correcting the corresponding first control voltage Vset1 and / or second control voltage Vset2.

[0115] Figure 9 A schematic diagram showing a specific embodiment of the control circuit (330) of the linear regulator of the present invention is shown. Figure 9 The DAC 610 in the middle is Figure 7 DAC 601 or Figure 8 A specific embodiment of one of the DACs is described. In one embodiment, the DAC 610 includes a programmable current source 30 and a resistor Rs1. In this embodiment, the programmable current source 30 is used to generate a current Iset according to an adjustment signal Sadj1. The current Iset and the resistor Rs1 are used to generate a first control voltage Vset1. In this embodiment, the adjustment signal Sadj1 is an adjustment signal corresponding to the digital domain.

[0116] Figure 10 A schematic diagram showing a specific embodiment of the control circuit (340) of the linear regulator of the present invention is shown. Figure 10 The DAC 620 in the middle is Figure 7 DAC 601 or Figure 8A specific embodiment of one of the DACs is described. In one embodiment, DAC 620 includes a sub-digital-to-analog converter (sub-DAC) 40, a PMOS transistor M1, and a resistor Rs2. In this embodiment, the sub-digital-to-analog converter 40 is used to generate an adjustment voltage Vadj based on an adjustment signal Sadj1. The PMOS transistor M1 is used to generate a current Im1 based on the adjustment voltage Vadj. The current Im1 and the resistor Rs2 are used to generate a first control voltage Vset1.

[0117] Figure 11 A schematic diagram showing a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is provided. In one embodiment, the voltage generation circuit is configured as a DAC 630. Figure 11 The DAC 630 in the middle is Figure 7 One specific embodiment of DAC 601. In one embodiment, DAC 630 includes amplifier 50, PMOS transistor M2, selection circuitry 71, and a series of resistors as a voltage divider. In this embodiment, the output of amplifier 50 is used to control PMOS transistor M2 to generate a current Im2 according to, for example, a bandgap voltage Vbg. Current Im2, along with multiple resistors (i.e., a resistor string), is used to generate multiple divided voltages. Selection circuitry 71 selects one of the divided voltages according to an adjustment signal Sadj1 to generate a first control voltage Vset1.

[0118] Figure 12 A schematic diagram showing a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is provided. In one embodiment, the voltage generation circuit is configured as a DAC 640. Figure 12 The DAC 640 in the middle is Figure 8 One embodiment of the DAC in the example. DAC640 and Figure 11 Similar to DAC 630 in this embodiment. In this embodiment, DAC 640 further includes at least another selection circuit 72. Selection circuit 72 selects one of the voltage dividers based on the adjustment signal Sadj2 to generate a second control voltage Vset2. In this embodiment, the other functions of selection circuit 72 remain unchanged.

[0119] Figure 13 A schematic diagram showing a specific embodiment of the voltage generation circuit of the linear regulator of the present invention is provided. In one embodiment, the voltage generation circuit is configured as a DAC 650. Figure 13 The DAC 650 in the middle is Figure 7 DAC 601 or Figure 8This is a specific embodiment of one of the DACs. In one embodiment, the DAC 650 includes multiple current sources (e.g., current sources I1~I3), a corresponding number of switches (e.g., switches SW1~SW3), and a resistor Rs3. In this embodiment, the current sources I1~I3 are connected in series with the switches SW1~SW3, and then further connected in series with the resistor Rs3. The switches SW1~SW3 are controlled by an adjustment signal Sadj1, such that the switches SW1~SW3 and the resistor Rs3 are used to generate a first control voltage Vset1. In one embodiment, the levels of the current sources can be arranged in a binary weighted manner.

[0120] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A linear regulator, comprising: A first output stage circuit for generating a first output voltage based on a first control voltage; and A calibration circuit is enabled during a first calibration period after the linear regulator is started, wherein during the first calibration period, the calibration circuit is configured to generate a first control voltage based on an output correlation signal and a reference voltage, and the output correlation signal is correlated with the first output voltage. The first output stage circuit and the correction circuit form a first control loop, and the first control loop enters an open loop state after the first correction period ends. The first output stage circuit includes a second control loop for adjusting the first output voltage in a closed-loop manner during an operation period following the first correction period, based on the changes in the first control voltage and the first output voltage.

2. The linear regulator as described in claim 1, wherein, The correction circuit is also used to store the first control voltage after the first correction period ends; wherein after the correction circuit stores the first control voltage, a portion of the sub-circuit of the correction circuit is disabled, thereby entering the open loop state.

3. The linear regulator as described in claim 2, wherein, The correction circuit includes: A comparator, used during the first correction period, to generate a comparison signal based on a comparison between the output correlation signal and the reference voltage; and A control circuit is used to generate the first control voltage based on the comparison signal during the first correction period; The comparator is disabled after the correction circuit stores the first control voltage.

4. The linear regulator as described in claim 3, wherein, Also includes: A sensing circuit is used to generate the output correlation signal based on the first output voltage during the first calibration period; The sensing circuit is disabled after the correction circuit stores the first control voltage.

5. The linear regulator as described in claim 3, wherein, The control circuit includes: An adjustment circuit is configured to generate an adjustment signal based on the comparison signal during the first calibration period, and to store the adjustment signal after the first calibration period ends; and A voltage generating circuit is used to generate the first control voltage according to the adjustment signal.

6. The linear regulator as described in claim 2, wherein, The correction circuit corrects and generates the first control voltage according to a linear search method or a binary search method, so that the difference between the level of the output correlation signal and the level of the reference voltage is less than a first threshold, thereby making the difference between the level of the first output voltage and the level of a target voltage less than a second threshold.

7. The linear regulator as described in claim 2, wherein, The first output stage circuit includes: A control terminal is used to receive the first control voltage; One output terminal is adjusted to generate the first output voltage; A bias current source for generating a primary bias current at a bias node, wherein the primary bias current includes a first bias current and a second bias current; and A first current branch and a second current branch, wherein the first current branch and the second current branch are coupled to the bias node, wherein the first bias current and the second bias current flow through the first current branch and the second current branch, respectively. The first current branch is used to generate a driving voltage based on the first bias current; The second current branch is used to guide and regulate the second bias current, so as to guide and regulate the first bias current according to a voltage difference between the first output voltage and the first control voltage, and the second current branch is used to adjust the first output voltage according to the drive voltage and the second bias current.

8. The linear regulator as described in claim 7, in, The first current branch includes: A bias load transistor and a common gate transistor are connected in series between an input power supply and the bias node to operate on a drive node to generate the drive voltage according to the first bias current, wherein the gates of the bias load transistor and the common gate transistor are biased by a first bias voltage and a second bias voltage, respectively. The second current branch includes: A power transistor and a current-directed regulating transistor are connected in series between the input power supply and the bias node, and are coupled to each other at the regulating output terminal, wherein the driving voltage and the first control voltage are used to control the gates of the power transistor and the current-directed regulating transistor to generate the first output voltage.

9. The linear regulator as claimed in claim 7, wherein, The first output stage circuit includes an overshoot suppression circuit, wherein the overshoot suppression circuit includes: A first overshoot suppression transistor and a suppression resistor are connected in series to the regulating output terminal and configured as a source follower, wherein the gate and drain of the first overshoot suppression transistor are respectively coupled to the bias node and the regulating output terminal; and A second overshoot suppression transistor is coupled between the regulating output terminal and a ground potential, wherein the gate of the second overshoot suppression transistor is coupled to an output of the source follower; When an overshoot occurs in the first output voltage, the first overshoot suppression transistor and the second overshoot suppression transistor are turned on, thereby suppressing the overshoot.

10. The linear regulator as claimed in claim 1, wherein, Also includes: Multiple output stage circuits, including at least the first output stage circuit and a second output stage circuit; The second output stage circuit is used to generate a second output voltage according to a second control voltage; The correction circuit is also configured to enable a second correction period following the first correction period, wherein during the second correction period, the correction circuit is configured to generate the second control voltage based on the output correlation signal and the reference voltage, and the output correlation signal is related to the second output voltage. The second output stage circuit and the correction circuit form a third control loop, wherein the third control loop enters an open loop state after the second correction period ends. The second output stage circuit includes a fourth control loop, which is used to adjust the second output voltage in a closed-loop manner according to the changes in the second control voltage and the second output voltage during the operation period after the second correction period.

11. The linear regulator of claim 10, wherein, The correction circuit is also used to store the second control voltage after the second correction period ends; wherein after the correction circuit stores the second control voltage, a portion of the sub-circuit of the correction circuit is disabled, thereby entering the open loop state.

12. The linear regulator of claim 11, wherein, The correction circuit includes: A comparator is configured to generate a comparison signal during the first correction period or the second correction period based on a comparison between the output correlation signal and the reference voltage; and A control circuit is used to generate the first control voltage based on the comparison signal during the first correction period, or to generate the second control voltage based on the comparison signal during the second correction period; The comparator is disabled after the correction circuit stores the second control voltage.

13. The linear regulator of claim 12, wherein, Also includes: A sensing circuit is configured to generate the output correlation signal based on the first output voltage during the first correction period, and to generate the output correlation signal based on the second output voltage during the second correction period; The sensing circuit is disabled after the correction circuit stores the second control voltage.

14. The linear regulator of claim 10, wherein, Each of the first output stage circuit and the second output stage circuit includes: One control terminal and one adjustable output terminal; A bias current source for generating a primary bias current at a bias node, wherein the primary bias current includes a first bias current and a second bias current; and A first current branch and a second current branch, wherein the first current branch and the second current branch are coupled to the bias node, wherein the first bias current and the second bias current flow through the first current branch and the second current branch, respectively. The first current branch is used to generate a driving voltage based on the first bias current; The second current branch is used to guide and regulate the second bias current so as to guide and regulate the first bias current according to a voltage difference between the regulated output voltage at the regulated output terminal and the control voltage received via the control terminal, and the second current branch is used to regulate the regulated output voltage according to the drive voltage and the second bias current. The control voltage of the first output stage circuit and the control voltage of the second output stage circuit correspond to the first control voltage and the second control voltage, respectively, and the regulated output voltage of the first output stage circuit and the regulated output voltage of the second output stage circuit correspond to the first output voltage and the second output voltage, respectively.

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