Low dropout regulator, serializer and deserializer

Abstract

A serializer, a deserializer, a second transistor, a first transistor, a first resistor and a second resistor are connected in series, a first reference voltage is accessed to a first error amplifier, the inverted input end of the first error amplifier is connected between the two resistors, and the inverted input end of the first error amplifier is connected between the two resistors. The output end of the first error amplifier is connected with the third electrode of the first transistor; the acquisition end of the gate voltage correction module is connected with the second electrode of the second transistor; the output end of the gate voltage correction module is connected with the third electrode of the second transistor; the gate voltage correction module adjusts a second driving voltage output to the third pole of the second transistor according to the second pole end voltage of the second transistor. After the second driving voltage is adjusted, the change of the second extreme voltage caused by the change of the output current can be eliminated, so that the second extreme voltage is kept stable, the second transistor is controlled to work in a saturation region, and the power supply rejection ratio improving capability of the second transistor is ensured.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a low-dropout linear regulator, a serializer, and a deserializer. Background Technology

[0002] In high-speed interconnect chip applications, in order to improve the speed, the signal amplitude is getting lower and lower, and the signal is more sensitive to noise or power fluctuations. The chip power supply needs to be handled better, and high-performance low dropout linear regulators (hereinafter referred to as LDOs) have become an indispensable core module for high-speed interconnect chips.

[0003] Conventional LDOs are only good at suppressing low-frequency power supply noise. For high-speed applications, the high-frequency power rejection ratio (PSR) is difficult to meet the application requirements. Improving the high-frequency power rejection ratio has become a problem of concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a low-dropout linear regulator, a serializer, and a deserializer to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a low dropout linear regulator, the low dropout linear regulator comprising: a first error amplifier, a first transistor, a second transistor, a first resistor, a second resistor, and a gate voltage correction module; The first terminal of the second transistor is connected to a power source, the second terminal of the second transistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded. The non-inverting input of the first error amplifier is used to connect to the first reference voltage, the inverting input of the first error amplifier is connected between the first resistor and the second resistor, and the output of the first error amplifier is connected to the third terminal of the first transistor. The acquisition terminal of the gate voltage correction module is connected to the second stage of the second transistor, and the output terminal of the gate voltage correction module is connected to the third stage of the second transistor. A terminal is led out from the second pole of the first transistor to serve as the output terminal of the low-dropout linear regulator. The gate voltage correction module adjusts the second driving voltage it outputs to the third terminal of the second transistor according to the second terminal voltage of the second transistor.

[0006] The second driving voltage is dynamically adjusted according to the second terminal voltage of the second transistor. After the second driving voltage is adjusted, the change in the second terminal voltage caused by the change in output current can be eliminated, thereby keeping the second terminal voltage stable and controlling the second transistor to work in the saturation region, so as to ensure that the second transistor improves the power supply rejection ratio.

[0007] Optionally, the gate voltage correction module is used to increase the second driving voltage output to the third terminal of the second transistor when the voltage at the second terminal of the second transistor decreases; When the voltage at the second terminal of the second transistor increases, the second driving voltage output to the third terminal of the second transistor is reduced.

[0008] The second driving voltage is reverse-regulated relative to the second terminal voltage of the second transistor, so that the second terminal voltage of the second transistor follows the change, thereby eliminating the change in the second terminal voltage caused by the change in output current.

[0009] Optionally, the gate voltage correction module includes a second error amplifier, the inverting input terminal of the second error amplifier serving as the acquisition terminal of the gate voltage correction module and connected to the second terminal of the second transistor, the non-inverting input terminal of the second error amplifier being used to connect to a second reference voltage, and the output terminal of the second error amplifier serving as the output terminal of the gate voltage correction module and connected to the third terminal of the second transistor.

[0010] The driving voltage is regulated by an error amplifier to ensure the stability of the second terminal voltage of the second transistor M2 and to ensure that it operates in the saturation region.

[0011] Optionally, the gate voltage correction module further includes a comparison unit, which includes a third transistor and a pull-down current source; The first terminal of the third transistor is connected to the power supply, the second terminal of the third transistor is connected to one end of the pull-down current source, and the other end of the pull-down current source is grounded. The second terminal of the third transistor is connected to the non-inverting input of the second error amplifier.

[0012] This method yields a stable second reference voltage while avoiding the introduction of high-power devices.

[0013] Secondly, embodiments of the present invention provide a deserializer, which includes the aforementioned low-dropout linear regulator.

[0014] Thirdly, embodiments of the present invention provide a serializer, the serializer including the aforementioned low-dropout linear regulator.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of a low-dropout linear regulator provided in an embodiment of the present invention.

[0018] Figure 2 This is a second schematic diagram of the low-dropout linear regulator provided in an embodiment of the present invention.

[0019] Figure 3 This is the third schematic diagram of the low-dropout linear regulator provided in the embodiments of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Please refer to Figure 1 , Figure 1 This is one of the structural schematic diagrams of a low-dropout linear regulator provided in an embodiment of the present invention. The low-dropout linear regulator includes: a first error amplifier U1, a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, and a gate voltage correction module.

[0025] The first terminal of the second transistor M2 is connected to the power supply Vdd. The second terminal of the second transistor M2 is connected to the first terminal of the first transistor M1. The second terminal of the first transistor M1 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the second resistor R2. The other end of the second resistor R2 is grounded.

[0026] In the embodiments of the present invention, the transistor can be an NMOS transistor. When the transistor is an NMOS transistor, the first electrode of the transistor is the drain of the NMOS transistor, the second electrode of the transistor is the source of the NMOS transistor, and the third electrode of the transistor is the gate of the NMOS transistor.

[0027] The non-inverting input of the first error amplifier U1 is used to connect to the first reference voltage Vref, the inverting input of the first error amplifier U1 is connected between the first resistor R1 and the second resistor R2, and the output of the first error amplifier U1 is connected to the third terminal of the first transistor M1.

[0028] The acquisition terminal of the gate voltage correction module is connected to the second stage of the second transistor M2, and the output terminal of the gate voltage correction module is connected to the third stage of the second transistor M2.

[0029] A terminal is led out from the second pole of the first transistor M1 as the output terminal of the low dropout linear regulator, which is used to connect to the back-end load, which can be the clock module in the serializer or deserializer.

[0030] The gate voltage correction module adjusts the second drive voltage VB it outputs to the third terminal of the second transistor M2 according to the second terminal voltage VS of the second transistor M2.

[0031] The first error amplifier U1 is used to output a first driving voltage to the third terminal of the first transistor M1 based on the feedback voltage connected to its inverting input terminal and the first reference voltage, so as to keep the feedback voltage stable, specifically, to keep it within the fluctuation range corresponding to the first reference voltage, allowing small fluctuations.

[0032] It should be understood that the feedback voltage remains stable, that is, the current flowing through the second resistor R2 remains stable, that is, the second terminal voltage of the first transistor M1 remains stable. Even if the magnitude of the output current Iout of the low dropout linear regulator changes, the second terminal voltage of the first transistor M1 remains stable under the regulation of the first error amplifier U1, which will cause the second terminal voltage VS of the second transistor M2 to change.

[0033] When the gate voltage correction module is not set and the second driving voltage VB connected to the third terminal of the second transistor M2 is a fixed voltage, if the voltage at the second terminal of the second transistor M2 changes, it may cause the second transistor M2 to operate in the non-saturation region, which will greatly affect its ability to improve the power supply rejection ratio in a high-frequency environment.

[0034] For example, when Iout is a large current, the second driving voltage VB and the second terminal voltage VS of the second transistor M2 are normal operating voltages. However, when Iout is switched to a small current, the second terminal voltage VS of the second transistor M2 will become higher, the Vds voltage of the second transistor M2 will decrease, and the second transistor M2 will enter the linear region. The second transistor M2 will then be unable to improve the power supply rejection ratio (PSR).

[0035] Specifically, as Iout decreases, with the current flowing through the second resistor R2 remaining constant, the current flowing through the source of the second transistor M2 decreases. When the power supply Vdd and the second driving voltage VB are fixed voltages, only the voltage VS at the second terminal of the second transistor M2 can become high.

[0036] In this embodiment of the invention, a gate voltage adjustment module is provided to dynamically adjust the second driving voltage VB of the second transistor M2 according to the second terminal voltage VS. After the second driving voltage VB is adjusted, the change of the second terminal voltage VS caused by the change of Iout can be eliminated, thereby keeping the second terminal voltage VS stable, so as to control the second transistor M2 to work in the saturation region and ensure that the second transistor M2 can improve the power supply rejection ratio (PSR).

[0037] In one alternative implementation, the gate voltage correction module is used to increase the second drive voltage VB output to the third terminal of the second transistor M2 when the second terminal voltage VS of the second transistor M2 decreases.

[0038] When the voltage VS at the second terminal of the second transistor M2 increases, the second driving voltage VB output to the third terminal of the second transistor M2 decreases.

[0039] Building upon the preceding text, regarding the stability of the second terminal voltage of the second transistor M2, ensuring its operation in the saturation region, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 2 , Figure 2 This is a second schematic diagram of the low-dropout linear regulator provided in an embodiment of the present invention.

[0040] The gate voltage correction module includes a second error amplifier U2. The inverting input of the second error amplifier U2 serves as the acquisition terminal of the gate voltage correction module and is connected to the second terminal of the second transistor M2. The non-inverting input of the second error amplifier U2 is used to connect to the second reference voltage VSC. The output of the second error amplifier U2 serves as the output of the gate voltage correction module and is connected to the third terminal of the second transistor M2.

[0041] The second error amplifier U2 is used to output a second driving voltage to the third terminal of the second transistor M2 based on the second terminal voltage VS of the second transistor M2 connected to its inverting input terminal and the second reference voltage VSc, so as to keep the second terminal voltage VS stable.

[0042] Please continue to refer to this. Figure 2 The gate voltage correction module also includes a reference unit, which includes a third transistor M3 and a pull-down current source Iss.

[0043] The first terminal of the third transistor M3 is connected to the power supply Vdd, the second terminal of the third transistor M3 is connected to one end of the pull-down current source, and the other end of the pull-down current source is grounded. The second terminal of the third transistor M3 is connected to the non-inverting input of the second error amplifier U2 to provide a second reference voltage to the second error amplifier U2.

[0044] Of course, the reference unit can also use a voltage divider resistor to perform a fixed voltage division, thereby providing a stable second reference voltage VSc to the second error amplifier. Compared to voltage division via resistors, in this application... Figure 2 The structure shown consumes less power. Furthermore, Figure 2 The second reference voltage VSc generated by the structure shown can follow the threshold voltage Vth of the third transistor M3. The second transistor M2 and the third transistor M3 use the same type of device. The second reference voltage VSc can follow the threshold voltage Vth of the second transistor M2, which is more robust.

[0045] Please refer to Figure 3 , Figure 3 This is a third schematic diagram of the low-dropout linear regulator provided in an embodiment of the present invention. In an optional embodiment, the control unit further includes a fourth transistor M4, the first terminal of which is connected to the second terminal of the third transistor M3, the second terminal of which is connected to one end of a pull-down current source, and the fourth transistor M4 is connected in series between the third transistor M3 and the pull-down current source.

[0046] The fourth transistor, M4, can be used to stabilize the pull-down current source Iss, making its fluctuations smaller.

[0047] The gate of the fourth transistor M4 is connected to the gate of the first transistor M1.

[0048] Optionally, the fourth transistor M4 is of the same type as the first transistor M1, and the third transistor M3 is of the same type as the second transistor M2.

[0049] The second transistor M2 and the third transistor M3 have the same size ratio, which ensures that the threshold voltage Vth of the second transistor M2 and the third transistor M3 are consistent with the changes in process and temperature, resulting in better robustness and avoiding changes caused by the influence of process and temperature.

[0050] Of course, the size ratio of the first transistor M1 to the fourth transistor M4 can also be the same, with similar effects.

[0051] Optionally, the low-dropout linear regulator also includes a charge pump connected to the power supply terminal of the first error amplifier U1.

[0052] Due to the application of high-speed deserializers and serializers, the power supply Vdd is generally low. At the same time, low dropout linear regulators with NMOS transistor outputs have better high-frequency PSR performance. Therefore, the amplifier power supply needs a charge pump to boost the voltage.

[0053] This invention also provides a deserializer, which includes the aforementioned low-dropout linear regulator.

[0054] This invention also provides a serializer, which includes the low dropout linear regulator described above.

[0055] Specifically, the low-dropout linear regulator is used to power the clock modules in the serializer and deserializer.

[0056] In summary, the low-dropout linear regulator, serializer, and deserializer provided in this embodiment of the invention involve a second transistor, a first transistor, a first resistor, and a second resistor connected in series. A first error amplifier is connected to a first reference voltage, with its inverting input connected between two resistors, and its output connected to the third terminal of the first transistor. The gate voltage correction module's acquisition terminal is connected to the second stage of the second transistor, and its output terminal is connected to the third terminal of the second transistor. The gate voltage correction module adjusts its second driving voltage output to the third terminal of the second transistor based on the second terminal voltage of the second transistor. By dynamically adjusting the second driving voltage based on the second terminal voltage of the second transistor, the changes in the second terminal voltage caused by variations in the output current can be eliminated, thereby stabilizing the second terminal voltage and controlling the second transistor to operate in the saturation region, thus ensuring the second transistor's improved power supply rejection ratio.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0058] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A low-dropout linear regulator, characterized in that, The low-dropout linear regulator includes: a first error amplifier, a first transistor, a second transistor, a first resistor, a second resistor, and a gate voltage correction module; The first terminal of the second transistor is connected to a power source, the second terminal of the second transistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded. The non-inverting input of the first error amplifier is used to connect to the first reference voltage, the inverting input of the first error amplifier is connected between the first resistor and the second resistor, and the output of the first error amplifier is connected to the third terminal of the first transistor. The acquisition terminal of the gate voltage correction module is connected to the second stage of the second transistor, and the output terminal of the gate voltage correction module is connected to the third stage of the second transistor. A terminal is led out from the second pole of the first transistor to serve as the output terminal of the low-dropout linear regulator. The gate voltage correction module adjusts the second driving voltage it outputs to the third terminal of the second transistor according to the second terminal voltage of the second transistor.

2. The low-dropout linear regulator as described in claim 1, characterized in that, The first error amplifier is used to output a first drive voltage to the third terminal of the first transistor based on the feedback voltage connected to its inverting input terminal and the first reference voltage, so as to keep the feedback voltage stable.

3. The low-dropout linear regulator as described in claim 1, characterized in that, The gate voltage correction module is used to increase the second driving voltage output to the third terminal of the second transistor when the voltage at the second terminal of the second transistor decreases; When the voltage at the second terminal of the second transistor increases, the second driving voltage output to the third terminal of the second transistor is reduced.

4. The low-dropout linear regulator as described in any one of claims 1-3, characterized in that, The gate voltage correction module includes a second error amplifier. The inverting input of the second error amplifier serves as the acquisition terminal of the gate voltage correction module and is connected to the second terminal of the second transistor. The non-inverting input of the second error amplifier is used to connect to a second reference voltage. The output of the second error amplifier serves as the output terminal of the gate voltage correction module and is connected to the third terminal of the second transistor.

5. The low-dropout linear regulator as described in claim 4, characterized in that, The gate voltage correction module also includes a comparison unit, which includes a third transistor and a pull-down current source; The first terminal of the third transistor is connected to the power supply, the second terminal of the third transistor is connected to one end of the pull-down current source, and the other end of the pull-down current source is grounded. The second terminal of the third transistor is connected to the non-inverting input of the second error amplifier.

6. The low-dropout linear regulator as described in claim 5, characterized in that, The control unit further includes a fourth transistor, the first terminal of which is connected to the second terminal of the third transistor, and the second terminal of the fourth transistor is connected to one end of the pull-down current source; The gate of the fourth transistor is connected to the gate of the first transistor.

7. The low-dropout linear regulator as described in claim 6, characterized in that, The fourth transistor is of the same type as the first transistor, and the third transistor is of the same type as the second transistor.

8. The low-dropout linear regulator as described in claim 1, characterized in that, The low-dropout linear regulator also includes a charge pump, which is connected to the power supply terminal of the first error amplifier.

9. A deserializer, characterized in that, The deserializer includes the low-dropout linear regulator according to any one of claims 1-8.

10. A serializer, characterized in that, The serializer includes the low-dropout linear regulator according to any one of claims 1-8.

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