Soft start system and control method suitable for low dropout linear regulator

Abstract

The application discloses a soft start system and control method suitable for a low dropout linear regulator. The soft start system comprises a ramp voltage generation module for generating a ramp voltage Vramp with a slow ramp-up; a voltage selection module for selecting a minimum value Vmin from the ramp voltage Vramp or Vref and outputting; a voltage clamping module for temporarily clamping the output voltage of the comparison module in the initial stage of power supply power-on, limiting the input voltage of the power stage through a buffer stage, thereby suppressing the sharp peak current; a comparison module for comparing the minimum value Vmin and a feedback voltage Vfb, and adjusting the current of the power stage according to the comparison result; and a buffer stage module for providing a low-impedance output voltage Vg_power. The application can reduce the average current in the start-up process, suppress the short-time sharp peak current appearing on the power tube, protect the LDO and the load circuit from the electromagnetic interference problem caused by the sharp peak current, and reduce the risk of circuit burning.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and relates to a linear regulator, and more particularly to a soft-start system and control method suitable for low dropout linear regulators. Background Technology

[0002] Low dropout linear regulators (LDOs) are widely used in mobile electronic devices and the Internet of Things (IoT) due to their advantages such as low noise, low cost, and simple circuit structure. Traditional LDOs have an off-chip capacitor on the output side, typically in the microfarad range, to help stabilize the loop and provide good load transient characteristics.

[0003] LDOs with external capacitors can experience large current spikes on their power transistors during startup without proper handling, potentially damaging the chip. Chinese patent CN104331112A proposes a soft-start circuit, the block diagram of which is shown below. Figure 1 As shown in the diagram, this circuit primarily reduces the average current of the power transistor by controlling the LDO's reference voltage to rise slowly, thereby increasing the LDO's startup time.

[0004] However, in practical applications, the output of the error amplifier (EA) is usually connected to a buffer stage first, and then to the power stage circuit, such as... Figure 2 As shown. The buffer circuit has a very small input capacitance, which, together with the impedance at the output of EA, forms a high-frequency pole, which can optimize the loop stability of the LDO and improve the loop unity-gain bandwidth (GBW). Due to the circuit structure characteristics, at the initial stage of power-on, the gate voltage Vbn of MOSFETs 203 and 204 rises earlier than the gate voltage Vg_p of MOSFETs 207 and 208.

[0005] Therefore, in the very short initial startup period, the drain current of transistor 204 is larger than that of transistor 208, drawing current from the input capacitance of the buffer. Since the input capacitance of the buffer is very small, the input voltage of the buffer experiences a brief drop. Typically, a PMOS transistor is used as the power stage, and this drop in the buffer input voltage is transmitted to the power stage, causing a decrease in the gate voltage of the PMOS transistor, resulting in a short-term large current I_peak, as illustrated in the waveform diagram below. Figure 3 As shown. Figure 1 The circuit in the paper only solves the problem of excessive average current during startup, but it cannot solve the problem of peak current.

[0006] In view of this, there is an urgent need to design a new boot method in order to overcome at least some of the aforementioned defects of the existing boot methods. Summary of the Invention

[0007] This invention provides a soft-start system and control method suitable for low dropout linear regulators, which can reduce the average current during the startup process, suppress short-term peak currents on the power transistor, protect the LDO and its load circuit from electromagnetic interference caused by peak currents, and reduce the risk of circuit burnout.

[0008] To solve the above-mentioned technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0009] A soft-start system suitable for low-dropout linear regulators, the soft-start system comprising:

[0010] The ramp voltage generation module is used to generate a ramp voltage Vramp that rises slowly.

[0011] A voltage selection module, whose input is connected to the output of the ramp voltage generation module, is used to select the minimum value Vmin between the ramp voltage Vramp and the reference voltage Vref, and then output it.

[0012] The voltage clamping module is used to temporarily clamp the output voltage of the comparator module during the initial stage of power-on, thereby limiting the input voltage of the power stage through the buffer stage and suppressing peak current.

[0013] The comparison module has its input terminals connected to the output terminals of the voltage selection module, the voltage clamping module, and the feedback voltage Vfb generated by detecting the voltage at the output terminal of the voltage regulator, respectively. It is used to compare the minimum value Vmin with the feedback voltage Vfb and adjust the current of the power stage according to the comparison result.

[0014] A buffer stage module, whose input is connected to the output of the comparator module, is used to provide a low-impedance output voltage Vg_power.

[0015] In one embodiment of the present invention, the ramp voltage generating module includes a current source, a first current mirror, a second current mirror, and a first capacitor;

[0016] The source of the first current mirror is connected to the source of the second current mirror, and the drain of the first current mirror is connected to the gate of the first current mirror, the gate of the second current mirror, and the input terminal of the current source, respectively.

[0017] The drain of the second current mirror is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is grounded, and the output terminal of the current source is grounded.

[0018] The ramp rate of the voltage Vramp is determined by the capacitance C1 of the first capacitor and the charging current I. C1 The relationship between Vramp and charging time t is determined as follows:

[0019]

[0020] When Vramp equals the reference voltage Vref, the LDO's output voltage reaches the set value, and the LDO's startup process ends. Therefore, the LDO's startup time t... st for:

[0021]

[0022] Let the output voltage of the LDO be Vout, and the load capacitance of the LDO be C. load During the LDO output setup process, the average current I of the power transistor... avg for:

[0023]

[0024] In one embodiment of the present invention, the voltage selection module includes a first transistor and a second transistor;

[0025] The voltage selection module is a minimum selection circuit, and the output voltage of the voltage selection module will be used as the input of the comparison module; the voltage selection module is independent of the comparison module, or the voltage selection module is embedded in the comparison module as a component.

[0026] In one embodiment of the present invention, the voltage clamping module includes a current source, a switch, and a transistor; the drain of the transistor is connected to the gate of the transistor and the first terminal of the switch, the second terminal of the switch is connected to the input terminal of the current source, and the output terminal of the current source is connected to a single pulse signal V_pulse.

[0027] The single-pulse signal V_pulse originates from the EN signal of the LDO circuit, and the pulse width is t. w Adjust according to the current and device parameters of EA to ensure that when the V_pulse signal disappears, the gate voltage Vg_p of the transistor in EA has reached a stable value.

[0028] The clamping voltage output is connected to the output Vout_EA of EA; if the current of the current source is set to be much greater than the DC current of transistor 208 in EA, then when V_pulse is high voltage, the value of Vout_EA is mainly determined by the voltage clamping module.

[0029] When V_pulse is a high voltage, the current of the power stage is denoted as I. vpulse ;

[0030] To suppress the generation of peak currents, the following relationship exists:

[0031] I vpulse >I avg

[0032] To prevent the voltage clamping module from introducing additional LDO output voltage overshoot, another relationship also needs to be satisfied:

[0033]

[0034] In one embodiment of the present invention, the comparison module includes an error amplifier EA; the error amplifier EA has three input terminals, including a third transistor, a first transistor, and a second transistor;

[0035] The minimum value Vmin of the reference voltage Vref and Vramp is selected by the first transistor and the second transistor; the error amplifier EA compares the magnitudes of Vmin and Vfb and outputs the comparison result to the buffer stage.

[0036] In one embodiment of the present invention, the buffer stage module includes a PMOS transistor and a current source; the output terminal of the current source is connected to the source of the PMOS transistor; the PMOS transistor is a source follower, and the current source 702 provides DC bias to the PMOS.

[0037] As one embodiment of the present invention, the startup process includes three stages;

[0038] Phase 1: from t0 to t1; the voltage clamping circuit is in operation. During this phase, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design ensures that the rise rate of Vramp is less than the rise rate of the feedback voltage Vfb.

[0039] Second stage: Time period from t1 to t2; At time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace the reference voltage Vref and act on the loop. Since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise until time t2, when Vramp catches up with Vfb.

[0040] The third stage: from t2 to t3; during this stage, the LDO loop operates, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg. At time t3, Vramp reaches the reference voltage Vref. After this point, the voltage selection circuit causes the LDO loop to be controlled by the reference voltage Vref, and the LDO's output voltage reaches a stable value. After time t3, Vramp continues to rise until it reaches the supply voltage.

[0041] According to another aspect of the present invention, the following technical solution is adopted: a soft-start control method suitable for low-dropout linear regulators, the soft-start control method comprising:

[0042] This generates a ramp voltage Vramp that rises slowly.

[0043] Select the minimum value Vmin from the ramp voltage Vramp or the reference voltage Vref, and output it;

[0044] During the initial power-on phase, the output voltage of the comparator module is temporarily clamped, and the input voltage of the power stage is limited by the buffer stage, thereby suppressing peak current.

[0045] The comparison module compares the minimum value Vmin with the feedback voltage Vfb, and adjusts the current of the power stage based on the comparison result;

[0046] The output voltage Vg_power with low impedance is provided based on the output of the comparator module.

[0047] As one embodiment of the present invention, the soft-start control method includes:

[0048] In the first stage: from t0 to t1; the voltage clamping circuit is in operation. During this stage, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design makes the rise rate of Vramp less than the rise rate of the feedback voltage Vfb.

[0049] In the second stage: the time period from t1 to t2; at time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace the reference voltage Vref and act on the loop; since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise; until time t2, Vramp catches up with Vfb;

[0050] In the third stage: from t2 to t3; during this stage, the LDO loop operates, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg. At time t3, Vramp reaches the reference voltage Vref. After this point, the voltage selection circuit causes the LDO loop to be controlled by the reference voltage Vref, and the LDO's output voltage reaches a stable value. After time t3, Vramp continues to rise until it reaches the supply voltage.

[0051] The beneficial effects of this invention are as follows: The soft-start system and control method proposed in this invention, which are suitable for low dropout linear regulators, can reduce the average current during the startup process, while suppressing the short-term peak current that appears on the power transistor, protecting the LDO and its load circuit from electromagnetic interference caused by peak current, and reducing the risk of circuit burnout. Attached Figure Description

[0052] Figure 1 A schematic diagram of the composition of an existing LDO soft-start system.

[0053] Figure 2 A schematic diagram of a typical LDO circuit with soft-start capability.

[0054] Figure 3 A schematic diagram of the existing peak current generation mechanism.

[0055] Figure 4 A schematic diagram of the composition of an LDO soft-start system in one embodiment of the present invention.

[0056] Figure 5 A schematic diagram of a ramp voltage generation circuit in one embodiment of the present invention.

[0057] Figure 6 A circuit diagram of the voltage clamping circuit in an embodiment of the present invention.

[0058] Figure 7 A circuit diagram of the buffer stage circuit in an embodiment of the present invention.

[0059] Figure 8 A waveform diagram of a key node during the LDO startup process in this embodiment of the invention. Detailed Implementation

[0060] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0061] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0062] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Substitution of identical or similar prior art methods with some technical features in the embodiments is also within the scope of the description and protection of this invention.

[0063] The steps described in the various embodiments in the specification are for illustrative purposes only, and the implementation of this application is not limited by the order of the steps.

[0064] The term "connection" in the specification includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through circuits or components such as switches or follower circuits.

[0065] This invention discloses a soft-start system suitable for low-dropout linear regulators. Figure 4 A schematic diagram of the LDO soft-start system in one embodiment of the present invention; please refer to [link / reference]. Figure 4 The soft-start system includes: a ramp voltage generation module 1, a voltage selection module 2, a voltage clamping module 3, a comparison module 4, and a buffer stage module 5.

[0066] The ramp voltage generation module 1 is used to generate a ramp voltage Vramp that rises slowly.

[0067] The input terminal of the voltage selection module 2 is connected to the output terminal of the ramp voltage generation module 1 to select the minimum value Vmin between the ramp voltage Vramp and the reference voltage Vref, and then output it.

[0068] The voltage clamping module 3 is used to temporarily clamp the output voltage of the comparator module during the initial stage of power-on, thereby limiting the input voltage of the power stage through the buffer stage and suppressing peak current.

[0069] The input terminal of the comparison module 4 is connected to the output terminal of the voltage selection module 2, the output terminal of the voltage clamping module 3, and the feedback voltage Vfb generated by detecting the voltage at the output terminal of the voltage regulator, respectively, to compare the minimum value Vmin and the feedback voltage Vfb, and adjust the current of the power stage according to the comparison result.

[0070] The input terminal of the buffer stage module 5 is connected to the output terminal of the comparison module 4 to provide a low-impedance output voltage Vg_power.

[0071] Figure 5 A circuit diagram of the ramp voltage generation circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 5In one embodiment of the present invention, the ramp voltage generating module includes a current source 501, a first current mirror 502, a second current mirror 503, and a first capacitor 504.

[0072] The source of the first current mirror 502 is connected to the source of the second current mirror 503, and the drain of the first current mirror 502 is connected to the gate of the first current mirror 502, the gate of the second current mirror 503, and the input terminal of the current source 501.

[0073] The drain of the second current mirror 503 is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is grounded, and the output terminal of the current source 501 is grounded.

[0074] The ramp rate of the voltage Vramp is determined by the capacitance C1 of the first capacitor and the charging current I. C1 The relationship between Vramp and charging time t is determined as follows:

[0075] When Vramp equals Vref, the LDO's output voltage reaches the set value, and the LDO's startup process ends. Therefore, the LDO's startup time t... st for:

[0076] Let the output voltage of the LDO be Vout, and the load capacitance of the LDO be C. load During the LDO output setup process, the average current I of the power transistor... avg for:

[0077] Please see Figure 2 In one embodiment of the present invention, the voltage selection module includes a first transistor 202 and a second transistor 209. The voltage selection module is a minimum selection circuit, and the output voltage of the voltage selection module is used as the input of the comparison module; the voltage selection module is independent of the comparison module, or the voltage selection module is embedded in the comparison module as a component.

[0078] Figure 6 A circuit diagram of the voltage clamping circuit in this embodiment of the invention; please refer to... Figure 6 In one embodiment of the present invention, the voltage clamping module includes a current source 601, a switch 602, and a transistor 603; the drain of the transistor 603 is connected to the gate of the transistor 603 and the first terminal of the switch 602, the second terminal of the switch 602 is connected to the input terminal of the current source 601, and the output terminal of the current source 601 is connected to a single pulse signal V_pulse.

[0079] The single-pulse signal V_pulse originates from the EN signal of the LDO circuit, and the pulse width is t. wAdjusted according to the current and device parameters of EA, to ensure that when the V_pulse signal disappears, the gate voltage Vg_p of transistor 208 in EA has reached a stable value.

[0080] The clamping voltage output is connected to the output Vout_EA of EA; if the current of current source 601 is set to be much greater than the DC current of transistor 208 in EA, then when V_pulse is high voltage, the value of Vout_EA is mainly determined by the voltage clamping module.

[0081] When V_pulse is a high voltage, the current of the power stage is denoted as I. vpulse ;

[0082] To suppress the generation of peak currents, the following relationship exists:

[0083] I vpulse >I avg

[0084] To prevent the voltage clamping module from introducing additional LDO output voltage overshoot, another relationship also needs to be satisfied:

[0085]

[0086] Please see Figure 2 In one embodiment of the present invention, the comparison module includes an error amplifier EA; the error amplifier EA has three input terminals, including a third transistor 201, a first transistor 202, and a second transistor 209. The first transistor 202 and the second transistor 209 select the minimum value Vmin of Vref and Vramp; the error amplifier EA compares the magnitudes of Vmin and Vfb and outputs the comparison result to the buffer stage.

[0087] Figure 7 A circuit diagram of the buffer stage circuit in this embodiment of the invention; please refer to... Figure 7 In one embodiment of the present invention, the buffer stage module includes a PMOS transistor 701 and a current source 702; the output terminal of the current source 702 is connected to the source of the PMOS transistor 701; the PMOS transistor 701 is a source follower, and the current source 702 provides DC bias to the PMOS transistor.

[0088] Figure 8 Waveform diagrams of key nodes during the LDO startup process in this embodiment of the invention; please refer to... Figure 8 In one embodiment of the present invention, the startup process includes three stages;

[0089] Phase 1: from t0 to t1; the voltage clamping circuit is in operation. During this phase, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design ensures that the rise rate of Vramp is less than the rise rate of the feedback voltage Vfb.

[0090] Second stage: Time period from t1 to t2; At time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace Vref and act on the loop. Since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise until time t2, when Vramp catches up with Vfb.

[0091] The third stage: from t2 to t3; during this stage, the LDO loop operates, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg. At time t3, Vramp reaches Vref. After this point, the voltage selection circuit causes the LDO loop to be controlled by the reference voltage Vref, and the LDO's output voltage reaches a stable value. After time t3, Vramp continues to rise until it reaches the supply voltage.

[0092] This invention also discloses a soft-start control method suitable for low-dropout linear regulators, the soft-start control method comprising:

[0093] This generates a ramp voltage Vramp that rises slowly.

[0094] Select the minimum value Vmin from the ramp voltage Vramp or Vref, and output it;

[0095] During the initial power-on phase, the output voltage of the comparator module is temporarily clamped, and the input voltage of the power stage is limited by the buffer stage, thereby suppressing peak current.

[0096] The comparison module compares the minimum value Vmin with the feedback voltage Vfb, and adjusts the current of the power stage based on the comparison result;

[0097] The output voltage Vg_power with low impedance is provided based on the output of the comparator module.

[0098] In one embodiment of the present invention, the soft-start control method includes:

[0099] In the first stage: from t0 to t1; the voltage clamping circuit is in operation. During this stage, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design makes the rise rate of Vramp less than the rise rate of the feedback voltage Vfb.

[0100] In the second stage: the time period from t1 to t2; at time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace Vref and act on the loop; since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise; until time t2, Vramp catches up with Vfb.

[0101] In the third stage: from t2 to t3; during this stage, the LDO loop operates, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg. At time t3, Vramp reaches Vref. After this point, the voltage selection circuit causes the LDO loop to be controlled by the reference voltage Vref, and the LDO's output voltage reaches a stable value. After time t3, Vramp continues to rise until it reaches the supply voltage.

[0102] In summary, the soft-start system and control method proposed in this invention, applicable to low-dropout linear regulators, can reduce the average current during startup, suppress short-term peak currents on the power transistor, protect the LDO and its load circuit from electromagnetic interference caused by peak currents, and reduce the risk of circuit burnout.

[0103] It should be noted that this application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium; for example, RAM memory, magnetic or optical drives, floppy disks, and similar devices. In addition, some steps or functions of this application can be implemented in hardware; for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. Effects or advantages involved in the embodiments may not be apparent due to various factors, and the description of effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be apparent to those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A soft-start system suitable for low-dropout linear regulators, characterized in that, The soft-start system includes: The ramp voltage generation module is used to generate a ramp voltage Vramp that rises slowly. A voltage selection module, whose input is connected to the output of the ramp voltage generation module, is used to select the minimum value Vmin between the ramp voltage Vramp and the reference voltage Vref, and then output it. The voltage clamping module is used to temporarily clamp the output voltage of the comparator module during the initial stage of power-on, thereby limiting the input voltage of the power stage through the buffer stage and suppressing peak current. The comparison module has its input terminals connected to the output terminals of the voltage selection module, the voltage clamping module, and the feedback voltage Vfb generated by detecting the voltage at the output terminal of the voltage regulator, respectively. It is used to compare the minimum value Vmin with the feedback voltage Vfb and adjust the current of the power stage according to the comparison result. A buffer stage module, whose input is connected to the output of the comparator module, is used to provide a low-impedance output voltage Vg_power; The voltage clamping module includes a current source, a switch, and a transistor; the drain of the transistor is connected to the gate of the transistor and the first terminal of the switch, the second terminal of the switch is connected to the input terminal of the current source, and the output terminal of the current source is connected to a single pulse signal V_pulse. The single-pulse signal V_pulse originates from the EN signal of the LDO circuit, and the pulse width is... Adjust according to the current and device parameters of EA to ensure that when the V_pulse signal disappears, the gate voltage Vg_p of the transistor in EA has reached a stable value. The clamping voltage output is connected to the output Vout_EA of EA; if the current of the current source is set to be much greater than the DC current of transistor 208 in EA, then when V_pulse is high voltage, the value of Vout_EA is determined by the voltage clamping module. When V_pulse is a high voltage, the current of the power stage is denoted as... ; To suppress the generation of peak currents, the following relationship exists: ; The average current of the power transistor; To prevent the voltage clamping module from introducing additional LDO output voltage overshoot, another relationship also needs to be satisfied: ; The startup process consists of three phases; Phase 1: from t0 to t1; the voltage clamping circuit is in operation. During this phase, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design ensures that the rise rate of Vramp is less than the rise rate of the feedback voltage Vfb. Second stage: Time period from t1 to t2; At time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace Vref and act on the loop. Since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise until time t2, when Vramp catches up with Vfb. The third stage: from t2 to t3; during this stage, the LDO loop takes effect, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg; at time t3, Vramp reaches Vref. After this point, the voltage selection circuit makes the LDO loop controlled by the reference voltage Vref, and the output voltage of the LDO reaches a stable value; after time t3, Vramp continues to rise until the power supply voltage.

2. The soft-start system for low-dropout linear regulators according to claim 1, characterized in that: The ramp voltage generation module includes a current source, a current mirror, and a first capacitor; the current mirror includes a fourth transistor and a fifth transistor. The source of the fourth transistor is connected to the source of the fifth transistor, and the drain of the fourth transistor is connected to the gate of the fourth transistor, the gate of the fifth transistor, and the input terminal of the current source, respectively. The drain of the fifth transistor is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is grounded, and the output terminal of the current source is grounded. The ramp rate of the voltage Vramp is determined by the capacitance C1 of the first capacitor and the charging current. The relationship between Vramp and charging time t is determined as follows: ； When Vramp equals Vref, the LDO's output voltage reaches the set value, and the LDO's startup process ends; therefore, the LDO's startup time... for: ； Let the output voltage of the LDO be Vout, and the load capacitance of the LDO be... During the LDO output setup process, the average current of the power transistor... for: 。 3. The soft-start system for low-dropout linear regulators according to claim 1, characterized in that: The voltage selection module includes a first transistor and a second transistor; The voltage selection module is a minimum selection circuit, and the output voltage of the voltage selection module will be used as the input of the comparison module; the voltage selection module is independent of the comparison module, or the voltage selection module is embedded in the comparison module as a component.

4. The soft-start system for low-dropout linear regulators according to claim 1, characterized in that: The comparison module includes an error amplifier EA; the error amplifier EA has three input terminals, including a third transistor, a first transistor, and a second transistor. The minimum value Vmin of Vref and Vramp is selected by the first transistor and the second transistor; the error amplifier EA compares the magnitudes of Vmin and Vfb and outputs the comparison result to the buffer stage.

5. The soft-start system for low-dropout linear regulators according to claim 1, characterized in that: The buffer stage module includes a PMOS transistor and a current source; the output terminal of the current source is connected to the source of the PMOS transistor; the PMOS transistor is a source follower, and the current source provides DC bias to the PMOS transistor.

6. A soft-start control method for a soft-start system suitable for a low-dropout linear regulator, as described in any one of claims 1 to 5, characterized in that, The soft-start control method includes: This generates a ramp voltage Vramp that rises slowly. Select the minimum value Vmin from the ramp voltage Vramp or the reference voltage Vref, and output it; During the initial power-on phase, the output voltage of the comparator module is temporarily clamped, and the input voltage of the power stage is limited by the buffer stage, thereby suppressing peak current. The comparison module compares the minimum value Vmin with the feedback voltage Vfb, and adjusts the current of the power stage based on the comparison result; The output voltage Vg_power with low impedance is provided based on the output of the comparator module; The soft-start control method includes: In the first stage: the time period from t0 to t1; the voltage clamping circuit is in operation. During this stage, the current on the LDO power transistor is determined by the clamping circuit, which is I_vpulse. The ramp voltage generation circuit is also powered on at time t0, and the ramp voltage Vramp begins to slowly rise. The circuit design makes the rise rate of Vramp less than the rise rate of the feedback voltage Vfb. In the second stage: the time period from t1 to t2; at time t1, the voltage clamping circuit's V_pulse changes from high to low. At this time, the clamping circuit no longer affects the LDO loop, and the voltage selection circuit causes Vramp to replace the reference voltage Vref and act on the loop; since Vramp is less than Vfb at this moment, the loop will adjust the gate voltage Vg_power of the power transistor, causing the power transistor to turn off, and the output voltage Vout and feedback voltage Vfb stop rising; however, Vramp continues to rise; until time t2, Vramp catches up with Vfb; In the third stage: from t2 to t3; during this stage, the LDO loop operates, adjusting the power transistor current according to the value of Vramp. The current in this stage is determined by the rise rate of Vramp, which is I_avg. At time t3, Vramp reaches the reference voltage Vref. After this point, the voltage selection circuit makes the LDO loop controlled by the reference voltage Vref, and the output voltage of the LDO reaches a stable value. After time t3, Vramp continues to rise until the power supply voltage is reached.

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