Display substrate, operating method thereof, and display device

Abstract

The embodiments of the present disclosure provide a display substrate, a method for operating the same, and a display device. The display substrate includes multiple pixel drive circuits and multiple light-emitting elements connected to the multiple pixel drive circuits, the multiple pixel drive circuits being configured to drive the multiple light-emitting elements to emit light, and at least one pixel drive circuit including a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a drive subcircuit, and a light-emitting subcircuit. The technical solution provided by the embodiments of the present disclosure improves the defect of grayscale display unevenness (mura) of the display substrate in the prior art.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a display substrate and a working method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] At least one embodiment of the present disclosure provides a display substrate, a working method thereof, and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate comprising a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit comprises a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a driving subcircuit, and a light-emitting subcircuit;

[0006] The first reset sub-circuit is connected to the initial signal line, the second node, and the first scanning signal line, respectively, and is configured to write the initial signal of the initial signal line into the second node under the control of the first scanning signal line;

[0007] The compensation sub-circuit is connected to the first power line, the first scan signal line, the first node, the second node, and the third node, respectively, and is configured to provide the signal of the third node to the first node under the control of the first scan signal line. The time for providing the signal of the third node to the first node during the threshold compensation stage is adjustable until the signal of the first node meets the threshold condition;

[0008] The writing sub-circuit is connected to the fourth scan signal line, the data signal line and the first node respectively, and is configured to write the data signal of the data signal line into the first node under the control of the fourth scan signal line; and to couple the signal of the first node to the second node during the data writing phase so that the signal of the second node meets the threshold condition;

[0009] the second reset sub-circuit being connected to the initial signal line, the second scanning signal line, and the first electrode of the light-emitting element, respectively, and being configured to write the initial signal of the initial signal line into the first electrode of the light-emitting element under the control of the second scanning signal line, and to write the initial signal of the initial signal line into the third node during the threshold compensation phase;

[0010] The driving sub-circuit is connected to the second node, the third node, and the fourth node respectively, and is configured to provide a driving current to the fourth node according to the signals of the second node and the third node;

[0011] The light-emitting sub-circuit is respectively connected to the first power line, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first pole of the light-emitting element, and is configured to write the signal of the first power line into the third node under the control of the first light-emitting signal line, and write the signal of the fourth node into the first pole of the light-emitting element under the control of the second light-emitting signal line.

[0012] In an exemplary embodiment, the time for providing the signal of the third node to the first node during the threshold compensation phase is 2H to 100H, where H is the scanning time of one row of sub-pixels.

[0013] In an exemplary embodiment, the compensation subcircuit includes a second transistor, a first capacitor, and a second capacitor;

[0014] The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node;

[0015] The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node;

[0016] The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the second node.

[0017] In an exemplary embodiment, the write sub-circuit includes an eighth transistor;

[0018] A control electrode of the eighth transistor is connected to the fourth scan signal line, a first electrode of the eighth transistor is connected to the data signal line, and a second electrode of the eighth transistor is connected to the first node.

[0019] In an exemplary embodiment, the second reset sub-circuit includes a seventh transistor;

[0020] The control electrode of the seventh transistor is connected to the second scanning signal line, the first electrode of the seventh transistor is connected to the initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element.

[0021] In an exemplary embodiment, the light emitting sub-circuit includes a fifth transistor and a sixth transistor;

[0022] The control electrode of the fifth transistor is connected to the first light emitting signal line, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the third node;

[0023] The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element.

[0024] In an exemplary embodiment, the first reset subcircuit includes a first transistor;

[0025] The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the second node.

[0026] In an exemplary embodiment, the driving sub-circuit includes a third transistor;

[0027] The control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the fourth node.

[0028] In an exemplary embodiment, a reference voltage providing subcircuit is further included;

[0029] The reference voltage providing subcircuit is connected to the reference voltage signal line, the third scanning signal line and the third node respectively, and is configured to write the reference voltage signal of the reference voltage signal line into the third node under the control of the third scanning signal line.

[0030] In an exemplary embodiment, the reference voltage providing subcircuit includes a fourth transistor;

[0031] A control electrode of the fourth transistor is connected to the third scanning signal line, a first electrode of the fourth transistor is connected to a reference voltage signal line, and a second electrode of the fourth transistor is connected to the third node.

[0032] In an exemplary embodiment, the first reset subcircuit includes a first transistor; the compensation subcircuit includes a second transistor, a first capacitor, and a second capacitor; the driving subcircuit includes a third transistor; the reference voltage providing subcircuit includes a fourth transistor; the light emitting subcircuit includes a fifth transistor and a sixth transistor; the second reset subcircuit includes a seventh transistor; and the writing subcircuit includes an eighth transistor.

[0033] The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the second node;

[0034] The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node;

[0035] The control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the fourth node;

[0036] The control electrode of the fourth transistor is connected to the third scanning signal line, the first electrode of the fourth transistor is connected to the reference voltage signal line, and the second electrode of the fourth transistor is connected to the third node;

[0037] The control electrode of the fifth transistor is connected to the first light emitting signal line, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the third node;

[0038] The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element;

[0039] The control electrode of the seventh transistor is connected to the second scanning signal line, the first electrode of the seventh transistor is connected to the initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element;

[0040] The control electrode of the eighth transistor is connected to the fourth scan signal line, the first electrode of the eighth transistor is connected to the data signal line, and the second electrode of the eighth transistor is connected to the first node;

[0041] The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node;

[0042] The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the second node.

[0043] In an exemplary embodiment, the first to second transistors and the eighth transistor are oxide transistors, and the third to seventh transistors are low-temperature polysilicon transistors.

[0044] In an exemplary embodiment, the second reset sub-circuit is configured to write the initial signal of the initial signal line into the fifth node during the threshold compensation phase under the control of the second scan signal line;

[0045] The light emitting sub-circuit is further configured to provide the initial signal of the fifth node to the fourth node under the control of the second light emitting signal line;

[0046] The driving sub-circuit is further configured to write the initial signal of the fourth node into the third node under the control of the second node.

[0047] In a second aspect, an embodiment of the present disclosure further provides a method for operating a display substrate, the display substrate comprising a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, the plurality of pixel driving circuits being configured to drive the plurality of light-emitting elements to emit light, at least one pixel driving circuit comprising a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a driving subcircuit, and a light-emitting subcircuit, the method comprising:

[0048] Under the control of the first scanning signal line, the first reset sub-circuit writes the initial signal of the initial signal line into the second node;

[0049] Under the control of the first scan signal line, the compensation subcircuit provides the signal of the third node to the first node. The time for providing the signal of the third node to the first node during the threshold compensation phase is adjustable until the signal of the first node meets the threshold condition.

[0050] Under the control of the fourth scan signal line, the write sub-circuit writes the data signal of the data signal line into the first node; in the data write phase, the signal of the first node is coupled to the second node so that the signal of the second node meets the threshold condition;

[0051] Under the control of the second scanning signal line, the second reset subcircuit writes the initial signal of the initial signal line into the first electrode of the light-emitting element, and writes the initial signal of the initial signal line into the third node during the threshold compensation phase;

[0052] The driving sub-circuit provides a driving current to the fourth node according to the signals of the second node and the third node;

[0053] Under the control of the first light-emitting signal line, the light-emitting sub-circuit writes the signal of the first power line into the third node, and under the control of the second light-emitting control line, the light-emitting sub-circuit writes the signal of the fourth node into the first pole of the light-emitting element.

[0054] In an exemplary embodiment, the method further comprises:

[0055] Under the control of the third scanning signal line, the reference voltage supply sub-circuit writes the reference voltage signal of the reference voltage signal line into the third node.

[0056] In an exemplary embodiment, the time for providing the signal of the third node to the first node during the threshold compensation phase is 2H to 100H, where H is the scanning time of one row of sub-pixels.

[0057] In an exemplary embodiment, the method further comprises:

[0058] Under the control of the second scanning signal line, the second reset sub-circuit writes the initial signal of the initial signal line into the fifth node during the threshold compensation phase;

[0059] Under the control of the second light-emitting signal line, the light-emitting sub-circuit provides the initial signal of the fifth node to the fourth node;

[0060] Under the control of the second node, the driving sub-circuit writes the initial signal of the fourth node into the third node.

[0061] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0062] The display substrate, working method thereof, and display device provided in this embodiment include multiple pixel driving circuits in the display substrate, at least one pixel driving circuit writes the initial signal of the initial signal line to the third node through the second reset sub-circuit in the threshold compensation stage, the time for providing the signal of the third node to the first node in the threshold compensation stage is adjustable until the signal of the first node can meet the threshold condition, and the signal of the first node is coupled to the second node in the data writing stage so that the signal of the second node meets the threshold condition, thereby using the initial signal of the initial signal line to compensate for the threshold voltage, and the time for providing the signal of the third node to the first node in the threshold compensation stage is adjustable, which can improve the defect of uneven grayscale display in the display substrate.

[0063] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0065] Figure 1 Shown is a schematic structural diagram of a display device;

[0066] Figure 2 Shown is a schematic diagram of a planar structure of a display substrate;

[0067] Figure 3 Shown is a schematic diagram of a cross-sectional structure of a display substrate;

[0068] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0069] Figure 5 Shown is a working timing diagram of a pixel driving circuit;

[0070] Figure 6a FIG2 is a schematic structural diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0071] Figure 6b FIG. 1 is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0072] Figure 7 FIG2 is a working timing diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0073] Figure 8 FIG. 1 is a working timing diagram of a display substrate provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0075] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.

[0076] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0077] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0078] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0079] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0080] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0081] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0082] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0083] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0084] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0085] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values within the range of process and measurement errors.

[0086] Figure 1The figure shows a schematic structural diagram of a display device. The display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values and control signals received from a timing controller. For example, the data signal driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan signal driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission signal driver can generate emission signals to be supplied to emission signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting signal driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate emission signals in a manner such that emission stop signals provided in the form of off-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal. o may be a natural number.

[0087] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, a display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and the light-emitting signal lines and output corresponding currents to the light-emitting devices. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the currents output by the pixel driving circuits of their respective subpixels.

[0088] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the sub-pixels in the pixel unit may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure.

[0089] Figure 3 This is a schematic diagram of the cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a base 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the base 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this disclosure.

[0090] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0091] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0092] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 4 Figure 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0093] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0094] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0095] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initialization signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0096] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0097] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0098] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0099] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0100] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initialization signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0101] In an exemplary embodiment, the second electrode of the light-emitting device is connected to a second power line VSS. The signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same as the first scan signal line S1 in the pixel driving circuit of the previous display row. This can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0102] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0103] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0104] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0105] Figure 5 This is a working timing diagram of a pixel driving circuit. Figure 4 The operation process of the exemplary pixel driving circuit illustrates an exemplary embodiment. Figure 4 The pixel driving circuit includes 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0106] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0107] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the initialization signal line INIT is supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0108] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initialization signal line INIT is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing the initialization and ensuring that the OLED does not emit light. The signal of the second scanning signal line S2 is a high-level signal, turning off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0109] In the third phase A3, referred to as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the OLED to emit light.

[0110] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0111] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0112] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0113] The leakage current of IGZO (Indium Gallium Zinc Oxide) TFT (Thin Film Transistor) is much smaller than that of LTPS (Low Temperature Poly-Silicon) TFT. The power consumption of the display is divided into driving power and luminous power. LTPO (Low Temperature Polycrystalline Oxide) technology converts some LTPS transistors into oxide transistors, which reduces the leakage current and allows the capacitor voltage (charge) to be maintained for one second to drive 1Hz. Due to the large leakage current of LTPS, even driving static pixels requires 60Hz, otherwise the brightness will be greatly reduced. LTPO technology can solve this problem to a certain extent. In related technologies, display substrates prepared using LTPO technology often have the defect of uneven display (mura) of each grayscale due to insufficient threshold voltage compensation.

[0114] The present disclosure provides a display substrate, which may include a plurality of pixel driving circuits and a plurality of light-emitting elements OLED respectively connected to the plurality of pixel driving circuits. The plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements OLED to emit light. Figure 6a As shown, at least one pixel driving circuit may include a first reset subcircuit 101, a compensation subcircuit 102, a writing subcircuit 103, a second reset subcircuit 104, a driving subcircuit 105 and a light emitting subcircuit 106;

[0115] The first reset sub-circuit 101 is connected to the initial signal line Vinit, the second node N2, and the first scanning signal line S1, and is configured to write the initial signal of the initial signal line Vinit into the second node N2 under the control of the first scanning signal line S1;

[0116] The compensation sub-circuit 102 is connected to the first power line VDD, the first scan signal line S1, the first node N1, the second node N2, and the third node N3, respectively. The compensation sub-circuit 102 is configured to provide a signal of the third node N3 to the first node N1 under the control of the first scan signal line S1. The timing of providing the signal of the third node N3 to the first node N1 during the threshold compensation phase is adjustable until the signal of the first node N1 meets the threshold condition.

[0117] The writing sub-circuit 103 is connected to the fourth scan signal line S4, the data signal line data, and the first node N1, respectively, and is configured to write the data signal of the data signal line data into the first node N1 under the control of the fourth scan signal line S4; and to couple the signal of the first node N1 to the second node N2 during the data writing phase so that the signal of the second node N2 meets the threshold condition;

[0118] The second reset sub-circuit 104 is connected to the initial signal line Vinit, the second scan signal line S2, and the first electrode of the light-emitting element OLED, respectively, and is configured to write the initial signal of the initial signal line Vinit into the first electrode of the light-emitting element OLED under the control of the second scan signal line S2, and write the initial signal of the initial signal line Vinit into the third node N3 during the threshold compensation phase;

[0119] The driving sub-circuit 105 is connected to the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to provide a driving current to the fourth node N4 according to the signals of the second node N2 and the third node N3;

[0120] The light-emitting sub-circuit 106 is respectively connected to the first power line VDD, the third node N3, the fourth node N4, the first light-emitting signal line EM1, the second light-emitting signal line EM2, and the first electrode of the light-emitting element OLED. It is configured to write the signal of the first power line VDD into the third node N3 under the control of the first light-emitting signal line, and to write the signal of the fourth node N4 into the first electrode of the light-emitting element OLED under the control of the second light-emitting signal line EM2.

[0121] The display substrate provided by the embodiment of the present disclosure includes multiple pixel driving circuits. At least one pixel driving circuit writes the initial signal of the initial signal line Vinit to the third node N3 through the second reset sub-circuit 104 during the threshold compensation stage. The time for providing the signal of the third node N3 to the first node N1 during the threshold compensation stage is adjustable until the signal of the first node N1 can meet the threshold condition. During the data writing stage, the signal of the first node N1 is coupled to the second node N2 so that the signal of the second node N2 meets the threshold condition. This realizes compensation of the threshold voltage using the initial signal of the initial signal line Vinit, and the time for providing the signal of the third node N3 to the first node N1 during the threshold compensation stage is adjustable. This can improve the defect of grayscale display unevenness (mura) in the display substrate.

[0122] In an exemplary embodiment, the time for providing the signal of the third node N3 to the first node N1 during the threshold compensation phase is 2 hours to 100 hours, where H is the scanning time for a row of sub-pixels. Because the time for providing the signal of the third node N3 to the first node N1 during the threshold compensation phase can be adjusted according to actual needs, there is sufficient time to compensate the threshold voltage of the driving transistor (T3) using the signal of the initial signal line Vinit, thereby significantly improving the display unevenness (mura) defect of multiple grayscales in the display substrate and avoiding the problem of mura existing in each grayscale due to insufficient threshold voltage compensation time.

[0123] In an exemplary embodiment, Figure 6b As shown, the compensation sub-circuit 102 may include a second transistor T2, a first capacitor C1, and a second capacitor C2;

[0124] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3;

[0125] A first plate of the first capacitor C1 is connected to the first power line VDD, and a second plate of the first capacitor C1 is connected to the first node N1;

[0126] A first plate of the second capacitor C2 is connected to the first node N1 , and a second plate of the second capacitor C2 is connected to the second node N2 .

[0127] In an exemplary embodiment, Figure 6b As shown, the writing sub-circuit 103 may include an eighth transistor T8;

[0128] A control electrode of the eighth transistor T8 is connected to the fourth scan signal line S4 , a first electrode of the eighth transistor T8 is connected to the data signal line data, and a second electrode of the eighth transistor T8 is connected to the first node N1 .

[0129] In an exemplary embodiment, Figure 6b As shown, the second reset sub-circuit 104 may include a seventh transistor T7;

[0130] A control electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element OLED.

[0131] In an exemplary embodiment, Figure 6b As shown, the light emitting sub-circuit 106 may include a fifth transistor T5 and a sixth transistor T6;

[0132] The control electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3;

[0133] A control electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2 , a first electrode of the sixth transistor T6 is connected to the fourth node N4 , and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element OLED.

[0134] In an exemplary embodiment, Figure 6b As shown, the first reset sub-circuit 101 may include a first transistor T1;

[0135] A control electrode of the first transistor T1 is connected to the first scan signal line S1 , a first electrode of the first transistor T1 is connected to the initial signal line Vinit, and a second electrode of the first transistor T1 is connected to the second node N2 .

[0136] In an exemplary embodiment, Figure 6b As shown, the driving sub-circuit 105 may include a third transistor T3;

[0137] A control electrode of the third transistor T3 is connected to the second node N2 , a first electrode of the third transistor T3 is connected to the third node N3 , and a second electrode of the third transistor T3 is connected to the fourth node N4 .

[0138] In an exemplary embodiment, Figure 6b As shown, the pixel driving circuit may further include a reference voltage providing subcircuit 107;

[0139] like Figure 6a and Figure 6b As shown, the reference voltage providing sub-circuit 107 is connected to the reference voltage signal line, the third scanning signal line S3, and the third node N3 respectively, and is configured to write the reference voltage signal of the reference voltage signal line into the third node N3 under the control of the third scanning signal line S3.

[0140] In an exemplary embodiment, Figure 6b As shown, the reference voltage providing sub-circuit 107 may include a fourth transistor T4;

[0141] A control electrode of the fourth transistor T4 is connected to the third scan signal line S3 , a first electrode of the fourth transistor T4 is connected to the reference voltage signal line, and a second electrode of the fourth transistor T4 is connected to the third node N3 .

[0142] In an exemplary embodiment, Figure 6bAs shown, the first reset subcircuit 101 includes a first transistor T1; the compensation subcircuit 102 includes a second transistor T2, a first capacitor C1 and a second capacitor C2; the driving subcircuit 105 includes a third transistor T3; the reference voltage providing subcircuit 107 includes a fourth transistor T4; the light emitting subcircuit 106 includes a fifth transistor T5 and a sixth transistor T6; the second reset subcircuit 104 includes a seventh transistor T7; and the writing subcircuit 103 includes an eighth transistor T8.

[0143] The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode of the first transistor T1 is connected to the second node N2;

[0144] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3;

[0145] The control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the fourth node N4;

[0146] The control electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the reference voltage signal line, and the second electrode of the fourth transistor T4 is connected to the third node N3;

[0147] The control electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the third node N3;

[0148] The control electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the fourth node N4, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element OLED;

[0149] The control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element OLED;

[0150] The control electrode of the eighth transistor T8 is connected to the fourth scan signal line S4, the first electrode of the eighth transistor T8 is connected to the data signal line data, and the second electrode of the eighth transistor T8 is connected to the first node N1;

[0151] A first plate of the first capacitor C1 is connected to the first power line VDD, and a second plate of the first capacitor C1 is connected to the first node N1;

[0152] A first plate of the second capacitor C2 is connected to the first node N1 , and a second plate of the second capacitor C2 is connected to the second node N2 .

[0153] In example embodiments, the first to second transistors T1 to T2 and the eighth transistor T8 may be oxide transistors, and the third to seventh transistors T3 to T7 may be low-temperature polysilicon transistors.

[0154] In an exemplary embodiment, Figures 6a to 6b As shown, the second reset sub-circuit 104 is configured to write the initial signal of the initial signal line Vinit into the fifth node N5 under the control of the second scan signal line S2 during the threshold compensation phase;

[0155] The light emitting sub-circuit 106 is further configured to provide the initial signal of the fifth node N5 to the fourth node N4 under the control of the second light emitting signal line EM2;

[0156] The driving sub-circuit 105 is further configured to write the initial signal of the fourth node N4 into the third node N3 under the control of the second node N2.

[0157] The following describes a pixel driving circuit provided by an exemplary embodiment through the working process of the pixel driving circuit.

[0158] Figure 6b An equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment is shown in FIG. Figure 7 and Figure 8 FIG1 is a working timing diagram of a display substrate provided by an exemplary embodiment. Figure 6b As shown, an exemplary embodiment of a pixel drive circuit may include: 8 switching transistors (T1 to T8), 2 capacitor units (C1 and C2), the pixel drive circuit may be connected to 11 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a data signal line data, a reference voltage signal line vref, a first light emitting signal line EM1, a second light emitting signal line EM2, an initial signal line Vinit, a first power line VDD, and a second power line VSS), the first transistor T1, the second transistor T2, and the eighth transistor T8 may be N-type oxide transistors, and the third transistor T3 to the seventh transistor T7 may be P-type low-temperature polysilicon transistors. Figure 7 and 8 As shown, the working process of the display substrate provided by an exemplary embodiment may include a refresh phase ( Figure 7 shown) and the holding phase ( Figure 8 As shown), Figure 7 As shown, the refresh phase may include the first phase M11 to the fourth phase M14:

[0159] The first stage M11 can be called the reset stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scanning signal line S1, and the second scanning signal line S2 are at high levels, and the signals of the third scanning signal line S3 and the fourth scanning signal line S4 are at low levels. Since the first scan signal line S1 is at a high level, the first transistor T1 and the second transistor T2 are turned on, and the initial voltage vinit output by the initial signal line Vinit is provided to the second node N2 through the first transistor T1. The second node N2 is at a low level (the initial voltage vinit output by the initial signal line Vinit), initializing (resetting) the second capacitor C2 and clearing the original charge in the second capacitor C2. Since the signal of the second scan signal line S2 is at a high level, the seventh transistor T7 is turned off, and the signal of the initial signal line Vinit cannot be provided to the fifth node N5 through the seventh transistor T7. The fifth node N5 maintains the level of the previous frame. Since the signal of the third scan signal line S3 is at a low level, the fourth transistor T4 is turned on, and the reference voltage Vref output by the reference voltage signal line vref is written into the third node N3 through the fourth transistor T4. The potential of the third node N3 is the reference voltage Vref. Since the second transistor T2 is turned on, the potential of the third node N3 is written to the first node N1 via the second transistor T2, and the potential of the first node N1 is Vref; since the signal of the fourth scan signal line S4 is at a low level, the eighth transistor T8 is turned off, and the data voltage output by the data signal line data cannot be written to the first node N1 via the eighth transistor T8; since the second node N2 is at a low level, the third transistor T3 is turned on, and the potential Vref of the third node N3 is written to the fourth node N4 via the third transistor T3, and the potential of the fourth node N4 is the reference voltage Vref; since the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are at a high level, the fifth transistor T5 and the sixth transistor T6 are both turned off, and the signal of the first power line VDD cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3, and the sixth transistor T6. In this stage, the OLED does not emit light.

[0160] The second stage M12 can be called the threshold compensation stage, the signals of the first light-emitting signal line EM1, the first scanning signal line S1, and the third scanning signal line S3 are high level, and the signals of the second light-emitting signal line EM2, the second scanning signal line S2, and the fourth scanning signal line S4 are low level. Since the signal of the first scan signal line S1 is at a high level, the first transistor T1 and the second transistor T2 are turned on, the initial voltage output by the initial signal line Vinit is provided to the second node N2 through the first transistor T1, the second node N2 is at a low level (the initial voltage vinit output by the initial signal line Vinit), and the third transistor N3 is turned on; since the signal of the second scan signal line S2 is at a low level, the seventh transistor T7 is turned on, the signal of the initial signal line Vinit is provided to the fifth node N5 through the seventh transistor T7, and the potential of the fifth node N5 is the initial voltage vinit output by the initial signal line Vinit; since the signal of the third scan signal line S3 is at a high level, the fourth transistor T4 is turned off, and the signal of the reference voltage signal line vref cannot be written into the third node N3 through the fourth transistor T4; since the signal of the fourth scan signal line S4 is at a low level, the eighth transistor T8 is turned off, and the signal of the data signal line data cannot be written into the first node N1 through the eighth transistor T8; since the signal of the first light-emitting signal line EM1 is at a high level, the fifth transistor T5 is turned off, and the The signal of the power line VDD cannot be written to the third node N3 via the fifth transistor T5. Since the signal of the second light-emitting signal line EM2 is at a low level, the sixth transistor T6 is turned on, and the potential vinit of the fifth node N5 is written to the fourth node N4 via the sixth transistor T6. The potential of the fourth node N4 is the initial voltage vinit output by the initial signal line Vinit. Since the second transistor T2 and the third transistor T3 are turned on, the potential of the fourth node N4 is transmitted to the first node N1 via the third transistor T3 and the second transistor T2, and the difference between the initial voltage vinit output by the initial signal line Vinit and the threshold voltage vth of the third transistor T3 is charged into the first capacitor C1 and the second capacitor C2. The potentials of the first plate of the first capacitor C1, the second plate of the second capacitor C2, the first node N1, and the third node N3 are vinit-vth. Since the fifth transistor T5 is turned off, the signal of the first power line VDD cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3, and the sixth transistor T6. Therefore, the OLED does not emit light in this stage.

[0161] The third phase M13 can be called the data writing phase. The signals of the first light-emitting signal line EM1, the second scanning signal line S2, the third scanning signal line S3, and the fourth scanning signal line S4 are at a high level, and the signals of the second light-emitting signal line EM2 and the first scanning signal line S1 are at a low level. Since the signal of the first scanning signal line S1 is at a low level, the first transistor T1 and the second transistor T2 are turned off, and the signal of the initial signal line Vinit cannot be written to the second node N2 via the first transistor T1. Since the signal of the second scanning signal line S2 is at a high level, the seventh transistor T7 is turned off, and the signal of the initial signal line Vinit cannot be provided to the fifth node N5 via the seventh transistor T7. The fifth node N5 maintains the potential vinit of the previous frame. Since the signal of the third scanning signal line S3 is at a high level, the fourth transistor T4 is turned off, and the signal of the reference voltage signal line vref cannot be written to the third node N3 via the fourth transistor T4. Since the signal of the fourth scanning signal line S4 is at a high level, the eighth transistor T8 is turned on, and the data voltage Vdata output by the data signal line data is written to the first node N3 via the eighth transistor T8. 1. The potential of the first node N1 changes from vinit-vth to the data voltage Vdata. The potential change of the first node N1 is Vdata-(vinit-vth). According to the law of conservation of charge, the potential of the second node N2 changes to vinit+Vdata-(vinit-vth), that is, Vdata+vth. Because the signal of the first light-emitting signal line EM1 is at a high level, the fifth transistor T5 is turned off. The signal of the first power line VDD cannot be written to the third node N3 via the fifth transistor T5. The third node N3 can maintain the potential vinit-vth of the previous frame. Because the signal of the second light-emitting signal line EM2 is at a low level, the sixth transistor T6 is turned on. The potential of the fifth node N5 is transmitted to the fourth node N4 via the sixth transistor T6. The potential of the fourth node N4 is vinit. Because the fifth transistor T5 is turned off, the signal of the first power line VDD cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3, and the sixth transistor T6. During this stage, the OLED does not emit light.

[0162] The fourth stage M14 can be called the light-emitting stage. The signals of the second scanning signal line S2 and the third scanning signal line S3 are at a high level, and the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first scanning signal line S1, and the fourth scanning signal line S4 are at a low level. Since the signal of the first scanning signal line S1 is at a low level, the first transistor T1 and the second transistor T2 are disconnected, and the signal of the initial signal line Vinit cannot be written into the second node N2 via the first transistor T1. Since the voltage across the second capacitor C does not produce a sudden change, the second node N2 maintains the potential Vdata+vth of the previous frame. Since the signal of the second scanning signal line S2 is at a high level, the seventh transistor T7 is disconnected, and the signal of the initial signal line Vinit cannot be provided to the fifth node N5 via the seventh transistor T7. Since the signal of the third scanning signal line S3 is at a high level, the fourth transistor T4 is disconnected, and the signal of the reference voltage signal line vref cannot be written into the third node N3 via the fourth transistor T4. Since the signal of the fourth scanning signal line S4 is at a low level, the eighth transistor T 8 is disconnected, and the data voltage Vdata output by the data signal line data cannot be written into the first node N1 through the eighth transistor T8. Since the voltages across the first capacitor C1 and the second capacitor C2 do not suddenly change, the first node N1 maintains the potential Vdata of the previous frame. Since the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power supply voltage Vdd output by the first power line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light. The potential of the third node N3 is Vdd, and the potentials of the fourth node N4 and the fifth node N5 are both the voltage Anode that drives the first electrode of the OLED.

[0163] like Figure 8 As shown, the holding phase may include a first phase M21 to a third phase M23:

[0164] In the three stages from the first stage M21 to the third stage M23, the signals of the first scan signal line S1 and the fourth scan signal line S4 are all low, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off; because the first transistor T1 is turned off, the signal of the initial signal line Vinit cannot be written into the second node N2 via the first transistor T1, and the second node N2 maintains the potential Vdata+vth of the previous frame. Because the second transistor T2 is turned off, the potential of the third node N3 cannot be written into the first node N1 via the second transistor T2. Because the eighth transistor T8 is turned off, the data voltage Vdata output by the data signal line data cannot be written into the first node N1 via the eighth transistor T8. Since the voltage across the first capacitor C1 and the second capacitor C2 does not produce a sudden change, the potential of the first node N1 maintains the potential of the previous frame (data voltage Vdata). The following details the working process of the first transistor T1 to the eighth transistor T8, the first capacitor C1 and the second capacitor C2 under the drive of the signals output by the second scan signal line S2, the third scan signal line S3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2:

[0165] The first stage M21 can be called a reset stage, in which the signals of the first light emitting signal line EM1, the second light emitting signal line EM2, and the second scanning signal line S2 are at a high level, and the signal of the third scanning signal line S3 is at a low level. Since the second scan signal line S2 is at a high level, the seventh transistor T7 is turned off, and the initial voltage vinit output by the initial signal line Vinit cannot be provided to the fifth node N5 through the seventh transistor T7, and the fifth node N5 maintains the potential of the previous frame; since the signal of the third scan signal line S3 is at a low level, the fourth transistor T4 is turned on, and the reference voltage Vref output by the reference voltage signal line vref is written into the third node N3 via the fourth transistor T4, and the potential of the third node N3 is the reference voltage Vref; since the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are at a high level, the fifth transistor T5 and the sixth transistor T6 are both turned off, and the signal of the first power line VDD cannot provide a driving voltage to the first electrode of the OLED via the fifth transistor T5, the third transistor T3, and the sixth transistor T6. In this stage, the OLED does not emit light. Since the third transistor T3 is turned on, the potential Vref of the third node N3 is written into the fourth node N4 via the third transistor T3, and the potential of the fourth node N4 is the reference voltage Vref.

[0166] The second stage M22 can be called the anode reset stage, the signals of the first light emitting signal line EM1, the second light emitting signal line EM2, and the third scanning signal line S3 are at high level, and the signal of the second scanning signal line S2 is at low level. Since the second scan signal line S2 is at a low level, the seventh transistor T7 is turned on, and the initial voltage vinit output by the initial signal line Vinit is provided to the fifth node N5 through the seventh transistor T7. The potential of the fifth node N5 is low (the initial voltage vinit output by the initial signal line Vinit), which can ensure that the OLED does not emit light; since the signal of the third scan signal line S3 is at a high level, the fourth transistor T4 is disconnected, and the reference voltage Vref output by the reference voltage signal line vref cannot be written to the third node N3 through the fourth transistor T4, and the potential of the third node N3 can maintain the previous frame level (reference voltage Vref); since the signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are at a high level, the fifth transistor T5 and the sixth transistor T6 are both disconnected, and the signal of the first power line VDD cannot provide a driving voltage to the first electrode of the OLED through the fifth transistor T5, the third transistor T3, and the sixth transistor T6. At this stage, the OLED does not emit light.

[0167] The third phase M23 is also known as the light-emitting phase. The signals on the first and second light-emitting signal lines EM1 and EM2 are at a low level, while the signals on the second and third scan signal lines S2 and S3 are at a high level. Because the second scan signal line S2 is at a high level, the seventh transistor T7 is off, and the initial voltage vinit output by the initial signal line Vinit cannot be supplied to the fifth node N5 via the seventh transistor T7. Because the signal on the third scan signal line S3 is at a high level, the fourth transistor T4 is off, and the reference voltage Vref output by the reference voltage signal line vref cannot be written to the third node N3 via the fourth transistor T4. Because the signals on the first and second light-emitting signal lines EM1 and EM2 are at a low level, the fifth and sixth transistors T5 and T6 are both on. The signal on the first power line VDD provides a driving voltage to the first electrode of the OLED via the fifth, third, and sixth transistors T5, T3, and T6, driving the OLED to emit light. The potential of the third node N3 is Vdd, and the potentials of the fourth and fifth nodes N4 and N5 are both the voltage Anode that drives the first electrode of the OLED.

[0168] In the embodiment of the present disclosure, Figure 7 and Figure 8 As shown, the second scanning signal line S2 is refreshed periodically. On the one hand, the signal of the initial signal line Vinit can be used to periodically initialize the first electrode of the OLED (i.e., the fifth node N5), which can avoid the voltage left over from the previous frame at the fifth node N5 affecting the current driving current and improve the display effect.

[0169] In the embodiment of the present disclosure, Figure 7 and Figure 8 As shown, the relationship between the refresh frame and the hold frame can be 1:1, that is, one refresh frame corresponds to one hold frame; or, one refresh frame can correspond to multiple hold frames, that is, one Figure 7 The refresh frames shown in Figure 8 The holding frame shown in FIG. 1 , one refresh frame corresponds to multiple holding frames, which can reduce the refresh frequency and the power consumption of the pixel driving circuit. In the embodiment of the present disclosure, as shown in FIG. Figure 8 As shown, in the frame holding stage, the first scan signal line S1 and the fourth scan signal line S4 are not refreshed, and the second scan signal line S2 and the third scan signal line S3 are refreshed, so that low power consumption display can be achieved.

[0170] In the embodiments of the present disclosure, Figure 7 As shown, the duration of the first stage M11 (reset stage) can be 1H to 2H, and the duration of the second stage M12 (threshold compensation stage) can be 2H to 100H. In the embodiment of the present disclosure, the duration of the threshold compensation stage can be appropriately adjusted to improve the defect of uneven display (mura) of multiple grayscales, thereby improving the display effect of the display substrate. In the embodiment of the present disclosure, Figure 7 and Figure 8 The 1H shown in the figure may represent the scanning time of a row of sub-pixels, or 1H may be understood as the time it takes for the display panel to scan a row of pixels when displaying a frame of picture.

[0171] The present disclosure also provides an operating method for a display substrate, wherein the display substrate includes a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit includes a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a driving subcircuit, and a light-emitting subcircuit. The operating method for the display substrate includes:

[0172] Under the control of the first scanning signal line, the first reset sub-circuit writes the initial signal of the initial signal line into the second node;

[0173] Under the control of the first scan signal line, the compensation subcircuit provides the signal of the third node to the first node. The time for providing the signal of the third node to the first node during the threshold compensation phase is adjustable until the signal of the first node meets the threshold condition.

[0174] Under the control of the fourth scan signal line, the write sub-circuit writes the data signal of the data signal line into the first node; in the data write phase, the signal of the first node is coupled to the second node so that the signal of the second node meets the threshold condition;

[0175] Under the control of the second scanning signal line, the second reset subcircuit writes the initial signal of the initial signal line into the first electrode of the light-emitting element, and writes the initial signal of the initial signal line into the third node during the threshold compensation phase;

[0176] The driving sub-circuit provides a driving current to the fourth node according to the signals of the second node and the third node;

[0177] Under the control of the first light-emitting signal line, the light-emitting sub-circuit writes the signal of the first power line into the third node, and under the control of the first light-emitting signal line, the light-emitting sub-circuit writes the signal of the fourth node into the first pole of the light-emitting element.

[0178] In an exemplary embodiment, the method further comprises:

[0179] Under the control of the third scanning signal line, the reference voltage supply sub-circuit writes the reference voltage signal of the reference voltage signal line into the third node.

[0180] In an exemplary embodiment, the time for providing the signal of the third node to the first node in the threshold compensation stage is 2H to 100H, where H is the scanning time of one row of sub-pixels.

[0181] In an exemplary embodiment, the method may further include:

[0182] Under the control of the second scanning signal line, the second reset sub-circuit writes the initial signal of the initial signal line into the fifth node during the threshold compensation phase;

[0183] Under the control of the second light-emitting signal line, the light-emitting sub-circuit provides the initial signal of the fifth node to the fourth node;

[0184] Under the control of the second node, the driving sub-circuit writes the initial signal of the fourth node into the third node.

[0185] The display substrate, working method thereof, and display device provided in this embodiment include multiple pixel driving circuits in the display substrate, at least one pixel driving circuit writes the initial signal of the initial signal line to the third node through the second reset sub-circuit in the threshold compensation stage, the time for providing the signal of the third node to the first node in the threshold compensation stage is adjustable until the signal of the first node can meet the threshold condition, and the signal of the first node is coupled to the second node in the data writing stage so that the signal of the second node meets the threshold condition, thereby using the initial signal of the initial signal line to compensate for the threshold voltage, and the time for providing the signal of the third node to the first node in the threshold compensation stage is adjustable, which can improve the defect of uneven grayscale display in the display substrate.

[0186] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: The device comprises a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one pixel driving circuit comprises a first reset subcircuit, a compensation subcircuit, a writing subcircuit, a second reset subcircuit, a driving subcircuit, and a light-emitting subcircuit; the driving subcircuit comprises a driving transistor; The first reset sub-circuit is connected to the initial signal line, the second node, and the first scanning signal line, respectively, and is configured to write the initial signal of the initial signal line into the second node under the control of the first scanning signal line; The compensation sub-circuit is connected to the first power line, the first scan signal line, the first node, the second node, and the third node, respectively, and is configured to provide the signal of the third node to the first node under the control of the first scan signal line. The time for providing the signal of the third node to the first node during the threshold compensation stage is adjustable until the signal of the first node meets the threshold condition; The writing sub-circuit is connected to the fourth scanning signal line, the data signal line and the first node respectively, and is configured to write the data signal of the data signal line into the first node under the control of the fourth scanning signal line; and coupling the signal of the first node to the second node during the data writing phase so that the signal of the second node satisfies a threshold condition; The second reset sub-circuit is connected to the initial signal line, the second scanning signal line, and the first electrode of the light-emitting element, respectively, and is configured to write the initial signal of the initial signal line into the first electrode of the light-emitting element under the control of the second scanning signal line, and write the initial signal of the initial signal line into the third node via the light-emitting sub-circuit and the driving sub-circuit during the threshold compensation stage, and provide the potential of the third node to the first node via the compensation sub-circuit, so as to charge the difference between the initial voltage output by the initial signal line and the threshold voltage of the driving transistor into the first node; The driving sub-circuit is connected to the second node, the third node, and the fourth node respectively, and is configured to provide a driving current to the fourth node according to the signals of the second node and the third node; The light-emitting sub-circuit is respectively connected to the first power line, the third node, the fourth node, the first light-emitting signal line, the second light-emitting signal line and the first pole of the light-emitting element, and is configured to write the signal of the first power line into the third node under the control of the first light-emitting signal line, and write the signal of the fourth node into the first pole of the light-emitting element under the control of the second light-emitting signal line.

2. The display substrate according to claim 1, wherein: The time for providing the signal of the third node to the first node in the threshold compensation stage is 2H to 100H, where H is the scanning time of a row of sub-pixels.

3. The display substrate according to claim 1, wherein The compensation subcircuit includes a second transistor, a first capacitor and a second capacitor; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node; The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node; The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the second node.

4. The display substrate according to claim 1, wherein The write sub-circuit includes an eighth transistor; A control electrode of the eighth transistor is connected to the fourth scan signal line, a first electrode of the eighth transistor is connected to the data signal line, and a second electrode of the eighth transistor is connected to the first node.

5. The display substrate according to claim 1, wherein The second reset sub-circuit includes a seventh transistor; The control electrode of the seventh transistor is connected to the second scanning signal line, the first electrode of the seventh transistor is connected to the initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element.

6. The display substrate according to claim 1, wherein: The light emitting sub-circuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is connected to the first light emitting signal line, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the third node; The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element.

7. The display substrate according to claim 1, wherein: The first reset sub-circuit includes a first transistor; The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the second node.

8. The display substrate according to claim 1, wherein: The transistor included in the driving sub-circuit is a third transistor; The control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the fourth node.

9. The display substrate according to claim 1, wherein: Also included is a reference voltage providing subcircuit; The reference voltage providing subcircuit is connected to the reference voltage signal line, the third scanning signal line and the third node respectively, and is configured to write the reference voltage signal of the reference voltage signal line into the third node under the control of the third scanning signal line.

10. The display substrate according to claim 9, wherein: The reference voltage providing subcircuit includes a fourth transistor; A control electrode of the fourth transistor is connected to the third scanning signal line, a first electrode of the fourth transistor is connected to a reference voltage signal line, and a second electrode of the fourth transistor is connected to the third node.

11. The display substrate according to claim 9, wherein The first reset subcircuit includes a first transistor; the compensation subcircuit includes a second transistor, a first capacitor, and a second capacitor; the driving subcircuit includes a third transistor; the reference voltage providing subcircuit includes a fourth transistor; the light emitting subcircuit includes a fifth transistor and a sixth transistor; the second reset subcircuit includes a seventh transistor; and the writing subcircuit includes an eighth transistor. The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the initial signal line, and the second electrode of the first transistor is connected to the second node; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node; The control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the fourth node; The control electrode of the fourth transistor is connected to the third scanning signal line, the first electrode of the fourth transistor is connected to the reference voltage signal line, and the second electrode of the fourth transistor is connected to the third node; The control electrode of the fifth transistor is connected to the first light emitting signal line, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the third node; The control electrode of the sixth transistor is connected to the second light emitting signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the first electrode of the light emitting element; The control electrode of the seventh transistor is connected to the second scanning signal line, the first electrode of the seventh transistor is connected to the initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting element; The control electrode of the eighth transistor is connected to the fourth scan signal line, the first electrode of the eighth transistor is connected to the data signal line, and the second electrode of the eighth transistor is connected to the first node; The first plate of the first capacitor is connected to the first power line, and the second plate of the first capacitor is connected to the first node; The first plate of the second capacitor is connected to the first node, and the second plate of the second capacitor is connected to the second node.

12. The display substrate according to claim 11, wherein: The first transistor, the second transistor and the eighth transistor are oxide transistors, and the third transistor to the seventh transistor are low-temperature polysilicon transistors.

13. The display substrate according to claim 1, wherein The second reset sub-circuit is configured to write the initial signal of the initial signal line into the fifth node during the threshold compensation phase under the control of the second scan signal line; The light emitting sub-circuit is further configured to provide the initial signal of the fifth node to the fourth node under the control of the second light emitting signal line; The driving sub-circuit is further configured to write the initial signal of the fourth node into the third node under the control of the second node.

14. A method for operating a display substrate, characterized in that: The display substrate includes a plurality of pixel driving circuits and a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits, the plurality of pixel driving circuits being configured to drive the plurality of light-emitting elements to emit light, at least one pixel driving circuit including a first reset subcircuit, a compensation subcircuit, a write subcircuit, a second reset subcircuit, a driving subcircuit, and a light-emitting subcircuit, the driving subcircuit including a driving transistor; and an operating method of the display substrate including: Under the control of the first scanning signal line, the first reset sub-circuit writes the initial signal of the initial signal line into the second node; Under the control of the first scan signal line, the compensation subcircuit provides the signal of the third node to the first node. The time for providing the signal of the third node to the first node during the threshold compensation phase is adjustable until the signal of the first node meets the threshold condition. Under the control of the fourth scan signal line, the write sub-circuit writes the data signal of the data signal line into the first node; in the data write phase, the signal of the first node is coupled to the second node so that the signal of the second node meets the threshold condition; Under the control of the second scanning signal line, the second reset sub-circuit writes the initial signal of the initial signal line into the first electrode of the light-emitting element, and in the threshold compensation stage, writes the initial signal of the initial signal line into the third node via the light-emitting sub-circuit and the driving sub-circuit, and provides the potential of the third node to the first node via the compensation sub-circuit, and charges the difference between the initial voltage output by the initial signal line and the threshold voltage of the driving transistor into the first node; The driving sub-circuit provides a driving current to the fourth node according to the signals of the second node and the third node; Under the control of the first light-emitting signal line, the light-emitting sub-circuit writes the signal of the first power line into the third node, and under the control of the second light-emitting control line, the light-emitting sub-circuit writes the signal of the fourth node into the first pole of the light-emitting element.

15. The working method according to claim 14, characterized in that: Also includes: Under the control of the third scanning signal line, the reference voltage supply sub-circuit writes the reference voltage signal of the reference voltage signal line into the third node.

16. The working method according to claim 14 or 15, characterized in that: The time for providing the signal of the third node to the first node in the threshold compensation stage is 2H to 100H, where H is the scanning time of a row of sub-pixels.

17. The working method according to claim 14 or 15, characterized in that: Also includes: Under the control of the second scanning signal line, the second reset sub-circuit writes the initial signal of the initial signal line into the fifth node during the threshold compensation phase; Under the control of the second light-emitting signal line, the light-emitting sub-circuit provides the initial signal of the fifth node to the fourth node; Under the control of the second node, the driving sub-circuit writes the initial signal of the fourth node into the third node.

18. A display device, characterized in that: The device comprises a plurality of light-emitting elements and a plurality of display substrates according to any one of claims 1 to 13.

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