Semiconductor structure, method and apparatus for detecting a semiconductor structure

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a detection method and device of the semiconductor structure. A plurality of independent connection holes are arranged in a semiconductor structure to be detected, so as to obtain a detection image of the semiconductor structure to be detected, and then determine whether non-conductive substances are left in the connection holes in the semiconductor structure to be detected according to image characteristic values of positions of the connection holes in the detection image.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor structures, methods and apparatus for detecting semiconductor structures. Background Technology

[0002] With the continuous development of semiconductor and storage technologies, electronic devices are constantly moving towards miniaturization and integration. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] In current DRAM mass production and R&D processes, interconnects are typically used to connect different components that need to transmit signals. In practical applications, if non-conductive material remains at the bottom of the interconnect, it can lead to electrical open circuit failure. However, with the shrinking critical dimension (CD) and increasing aspect ratio of interconnects, traditional optical inspection can no longer detect the bottom of the interconnect, thus failing to detect defects such as the presence of non-conductive material at the bottom of the interconnect. Summary of the Invention

[0004] The semiconductor structure, semiconductor structure detection method, and apparatus provided in this disclosure are used to solve the problem that the prior art cannot detect whether there are non-conductive substances remaining at the bottom of the connection hole.

[0005] In a first aspect, embodiments of this disclosure provide a method for detecting semiconductor structures, including:

[0006] Acquire a detection image of the semiconductor structure to be detected; wherein, the multiple connection holes in the semiconductor structure to be detected are independent of each other;

[0007] Based on the image feature values ​​of the location of the connecting hole in the detection image, it is determined whether there is any non-conductive material remaining in the connecting hole of the semiconductor structure to be detected.

[0008] Based on this implementation method, by setting multiple independent connection holes in the semiconductor structure to be tested, a detection image of the semiconductor structure to be tested is obtained, and then the image feature value of the location of the connection hole in the detection image is used to determine whether there is any non-conductive material remaining in the connection hole of the semiconductor structure to be tested.

[0009] In some possible implementations, the connection hole includes a target connection hole;

[0010] The step of determining whether non-conductive material remains inside the connection hole in the semiconductor structure to be detected based on the image feature value of the location of the connection hole in the detection image includes:

[0011] Obtain a reference image of the reference semiconductor structure;

[0012] By comparing the image feature values ​​of the target connection hole location in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure, it is determined whether there is any non-conductive material remaining in the target connection hole in the semiconductor structure to be detected.

[0013] In some possible implementations, the image feature values ​​include grayscale values; the step of comparing the image feature values ​​of the target connection hole location in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure to determine whether there is residual non-conductive material in the target connection hole in the semiconductor structure to be detected includes:

[0014] Determine the grayscale difference between the grayscale values ​​of the target connection hole at the same location in the detected image and the reference image;

[0015] Determine whether the grayscale difference is greater than a set threshold;

[0016] If so, it is determined that non-conductive material remains inside the target connection hole;

[0017] If not, then it is determined that no non-conductive material remains in the target connection hole.

[0018] In some possible implementations, the image feature values ​​include the signal-to-noise ratio; the step of comparing the image feature values ​​of the target connection hole location in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure to determine whether there is residual non-conductive material in the target connection hole in the semiconductor structure to be detected includes:

[0019] Determine the signal-to-noise ratio difference between the signal-to-noise ratios of the target connecting holes at the same location in the detected image and the reference image;

[0020] Determine whether the signal-to-noise ratio difference is greater than a set threshold;

[0021] If so, it is determined that non-conductive material remains inside the target connection hole;

[0022] If not, then it is determined that no non-conductive material remains in the target connection hole.

[0023] In some possible implementations, the connection hole includes target connection holes and reference connection holes at different locations;

[0024] Based on the image feature values ​​of the location of the connecting hole in the detection image, determine whether there is any residual non-conductive material inside the connecting hole in the semiconductor structure to be detected, including:

[0025] By comparing the image feature values ​​of the target connection hole location and the reference connection hole location in the detection image, it is determined whether there is any non-conductive material remaining in the target connection hole in the semiconductor structure to be detected.

[0026] In some possible implementations, the image feature values ​​include grayscale values;

[0027] The step of comparing the image feature values ​​of the target connection hole location and the reference connection hole location in the detection image to determine whether there is residual non-conductive material in the target connection hole in the semiconductor structure to be detected includes:

[0028] Determine the first gray value of the target connection hole in the detection image and the second gray value of the reference connection hole in the detection image;

[0029] Determine whether the first grayscale value is greater than the second grayscale value;

[0030] If so, it is determined that non-conductive material remains inside the target connection hole;

[0031] If not, then it is determined that no non-conductive material remains in the target connection hole.

[0032] In some possible implementations, the semiconductor structure to be tested includes a first region and a second region; the first region has a plurality of independent interconnecting holes, and the second region has a plurality of interconnecting interconnecting holes.

[0033] The acquisition of the detection image of the semiconductor structure to be detected includes:

[0034] An image of the first region of the semiconductor structure to be tested is obtained using a scanning electron microscope and is used as the test image.

[0035] In some possible implementations, obtaining the reference image of the reference semiconductor structure includes:

[0036] An image of the region in the reference semiconductor structure where multiple interconnect holes are formed is obtained using a scanning electron microscope and is used as the reference image.

[0037] In some possible implementations, prior to acquiring the detection image of the semiconductor structure to be detected, the method further includes:

[0038] A dielectric layer is formed on a semiconductor substrate on which semiconductor elements are formed; the semiconductor substrate includes a first region and a second region;

[0039] The dielectric layer is etched to form multiple independent openings to be detected in the dielectric layer corresponding to the first region, and multiple interconnected target openings are formed in the dielectric layer corresponding to the second region.

[0040] Using the dielectric layer as a mask, the semiconductor substrate is etched to form a contact hole to be tested that communicates with the opening to be tested, and a target contact hole that communicates with the target opening; wherein, the opening to be tested and the contact hole to be tested that communicate with each other constitute a connection hole in the first region, and the target opening and the target contact hole that communicate with each other constitute a connection hole in the second region.

[0041] In some possible implementations, the etching of the dielectric layer forms a plurality of independent openings to be detected in the dielectric layer corresponding to the first region, and a plurality of interconnected target openings in the dielectric layer corresponding to the second region, including:

[0042] A first mask layer is formed on the dielectric layer, the first mask layer comprising a plurality of first patterns arranged in an array;

[0043] A second mask layer is formed on the first mask layer, the second mask layer comprising a plurality of second patterns arranged in an array;

[0044] Using the first mask layer and the second mask layer as masks, the dielectric layer is etched to form multiple independent openings to be detected in the dielectric layer corresponding to the first region, and multiple interconnected target openings are formed in the dielectric layer corresponding to the second region.

[0045] In the first region, the edges of the first projection of the first pattern on the semiconductor substrate and the second projection of the second pattern on the semiconductor substrate are in contact with or partially overlap each other; in the second region, there is a gap between the edges of the first projection of the first pattern on the semiconductor substrate and the second projection of the second pattern on the semiconductor substrate.

[0046] In some possible implementations, the contact hole is a bit line contact hole, and the semiconductor element includes a transistor drain region;

[0047] After determining that no non-conductive material remains in the connection holes of the semiconductor structure to be tested, the method further includes:

[0048] Remove the dielectric layer and fill the bit line contact hole with a conductive contact structure;

[0049] A bit line material layer is deposited on the semiconductor substrate;

[0050] The bit line material layer is etched to form a bit line, which is electrically connected to the transistor drain region of the semiconductor substrate through the conductive contact structure.

[0051] In some possible implementations, after forming the connection hole, the method further includes:

[0052] A conductive structure is filled into each of the connection holes;

[0053] After acquiring the detection image of the semiconductor structure to be detected, the conductive structure is removed.

[0054] Secondly, embodiments of this disclosure also provide a semiconductor structure detection device, including:

[0055] The acquisition unit is configured to acquire a detection image of a semiconductor structure to be detected; wherein, the plurality of connection holes in the semiconductor structure to be detected are independent of each other;

[0056] The determining unit is configured to determine whether there is any non-conductive material remaining in the connecting hole of the semiconductor structure to be detected, based on the image feature value of the location of the connecting hole in the detection image.

[0057] Based on the above embodiments, since multiple independent connection holes are provided in the semiconductor structure to be tested, the detection device acquires a detection image of the semiconductor structure to be tested, and then determines whether there is any non-conductive material remaining in the connection holes of the semiconductor structure to be tested based on the image feature values ​​of the location of the connection holes in the detection image.

[0058] Thirdly, embodiments of this disclosure also provide a semiconductor structure, including:

[0059] A semiconductor substrate, wherein semiconductor elements and contact holes to be detected are formed in the semiconductor substrate;

[0060] A dielectric layer is located on the semiconductor substrate, and the dielectric layer includes a plurality of independent openings to be detected; the openings to be detected and the contact holes to be detected are connected and together form a connection hole.

[0061] Based on the above embodiments, since multiple independent connection holes are provided in the semiconductor structure to be tested, during the test, by acquiring the test image of the semiconductor structure to be tested, and then determining whether there is any non-conductive material remaining in the connection holes of the semiconductor structure to be tested based on the image feature value of the location of the connection holes in the test image.

[0062] In some possible implementations, the semiconductor substrate includes a first region and a second region, with the opening to be detected and the contact hole to be detected located in the first region;

[0063] The dielectric layer also covers the second region;

[0064] The dielectric layer corresponding to the first region includes: a plurality of dielectric patterns that are in contact with or partially overlap each other, wherein an opening to be detected is formed between the dielectric patterns, and the opening to be detected is connected to the opening to be detected;

[0065] The dielectric layer corresponding to the second region includes: a plurality of independent dielectric patterns, wherein a target opening is formed between the dielectric patterns, and the target opening is connected to the target opening. Attached Figure Description

[0066] Figure 1 Here are some flowcharts of the semiconductor structure detection method in the embodiments of this disclosure;

[0067] Figure 2 These are some top view structural schematic diagrams of the semiconductor structures in the embodiments of this disclosure;

[0068] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the semiconductor structure along the AA' direction.

[0069] Figure 4 This is a schematic diagram of the detection image in an embodiment of this disclosure;

[0070] Figure 5 These are some top view structural schematic diagrams of the reference semiconductor structure in the embodiments of this disclosure;

[0071] Figure 6 This is a schematic diagram of a reference image in an embodiment of this disclosure;

[0072] Figure 7 Here are some further flowcharts of the semiconductor structure detection method in the embodiments of this disclosure;

[0073] Figure 8 Here are some further flowcharts of the semiconductor structure detection method in the embodiments of this disclosure;

[0074] Figure 9 Here are some further flowcharts of the semiconductor structure detection method in the embodiments of this disclosure;

[0075] Figure 10 These are some structural schematic diagrams of the semiconductor structure detection device in the embodiments of this disclosure. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0077] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0078] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0079] With the continuous development of semiconductor and memory technologies, electronic devices are increasingly miniaturized and integrated. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read / write speeds. DRAM typically consists of multiple memory cells, each usually including a transistor and a capacitor. The capacitor stores data, and the transistor controls the reading and writing of data in the capacitor. In practical applications, the transistor's gate is connected to the word line, its drain to the bit line, and its source to the capacitor. The voltage signal on the word line controls the transistor's on / off state, thereby allowing data to be read from or written to the capacitor via the bit line.

[0080] During DRAM mass production and R&D, interconnects are typically formed to allow for electrical connections between different components. In practical applications, if non-conductive material remains at the bottom of the interconnect, it can lead to electrical breakage. However, with the shrinking critical dimension (CD) and increasing aspect ratio of interconnects, traditional optical inspection can no longer detect the bottom of the interconnect, thus failing to detect defects such as the presence of non-conductive material at the bottom.

[0081] This disclosure provides a method for detecting semiconductor structures. By setting multiple independent connection holes in the semiconductor structure to be detected, a detection image of the semiconductor structure to be detected is obtained. Then, based on the image feature values ​​of the location of the connection holes in the detection image, it is determined whether there are residual non-conductive substances in the connection holes of the semiconductor structure to be detected.

[0082] like Figure 1 As shown, embodiments of this disclosure provide a method for detecting semiconductor structures, including:

[0083] S10. Obtain a detection image of the semiconductor structure to be detected. The multiple connection holes in the semiconductor structure to be detected are independent of each other.

[0084] In some examples of this disclosure, before step S10, the process further includes: forming a semiconductor structure to be detected.

[0085] For example, forming the semiconductor structure to be tested may include the following steps:

[0086] First, combined Figure 2 and Figure 3 As shown, the semiconductor substrate includes a first region B1 and a second region B2, in which semiconductor elements (e.g., source and drain regions of a transistor) are formed respectively. A dielectric layer 12 is formed on the semiconductor substrate in which the semiconductor elements are formed.

[0087] For example, the manufacturing process of DRAM may include steps such as material deposition, etching, and cleaning. Combined with... Figure 2 and Figure 3 As shown, a shallow trench isolation region is formed on a semiconductor substrate (e.g., a silicon-based wafer) to define the active region, and silicon oxide is filled in the shallow trench isolation region. Word line trenches are then etched into the semiconductor substrate, passing through the active region and the silicon oxide in the shallow trench isolation region. A gate oxide layer is then formed on the surface of the word line trenches. Buried word lines 11 are then formed in the word line trenches. A silicon nitride film is then deposited over the entire surface of the semiconductor substrate. A dielectric layer 12 is then deposited on the silicon nitride film.

[0088] Optionally, the material of the dielectric layer includes, but is not limited to, silicon oxide.

[0089] Alternatively, the deposition process may include, but is not limited to, physical vapor deposition, chemical vapor deposition, and molecular beam epitaxy.

[0090] Optionally, the first region may include, but is not limited to, a test region, a virtual region, or a cutting channel region.

[0091] Optionally, the second region may include, but is not limited to, the chip region, such as the storage region of the chip region.

[0092] Afterwards, combined Figure 2 and Figure 3 As shown, wet etching or dry etching is used to etch the dielectric layer 12, forming multiple independent detection openings 15' in the dielectric layer 12 corresponding to the first region B1. The independent detection openings 15' are sealed by the remaining dielectric layers 12 / 122' / 121'. Multiple interconnected target openings 15 are formed in the dielectric layer corresponding to the second region. The remaining dielectric layers 12 / 122 / 121 around the interconnected target openings 15 contain multiple spaced patterns.

[0093] For example, etching the dielectric layer may include: first, forming a first mask layer on the dielectric layer, the first mask layer including a plurality of arrayed first patterns (the first patterns corresponding to dielectric layer pattern 121' in a first region B1 and corresponding to dielectric layer pattern 121 in a second region B2). Then, forming a second mask layer on the first mask layer, the second mask layer including a plurality of arrayed second patterns (the second patterns corresponding to dielectric layer pattern 122' in a first region B1 and corresponding to dielectric layer pattern 122 in a second region B2). Then, using the first and second mask layers as masks, etching the dielectric layer to form dielectric layer patterns 121' and 122' in the first region B1 and dielectric layer patterns 121 and 122 in the second region B2, so as to form a plurality of independent detection openings 15' in the dielectric layer 12 corresponding to the first region B1 and a plurality of interconnected target openings 15 in the dielectric layer 12 corresponding to the second region B2. In the first region B1, the edges of the first projection of the first pattern (such as dielectric layer pattern 121') on the semiconductor substrate 10 and the second projection of the second pattern (such as dielectric layer pattern 122') on the semiconductor substrate 10 are in contact with or partially overlap each other. For example, the first or second pattern is arranged in a square arrangement, or the first and second patterns together are arranged in a hexagonal close-packed arrangement, so that the multiple openings 15' to be detected are independent of each other. In the second region B2, there is a gap between the edges of the first projection of the first pattern (such as dielectric layer pattern 121) on the semiconductor substrate 10 and the second projection of the second pattern (such as dielectric layer pattern 122) on the semiconductor substrate 10, so that the multiple target openings 15 are interconnected.

[0094] Of course, etching the dielectric layer may also include: first, forming a third mask layer on the dielectric layer, wherein the first mask layer includes multiple arrayed third patterns (the third patterns correspond to dielectric layer pattern 121' in the first region B1, dielectric layer pattern 121 in the second region B2, and dielectric layer pattern 122' in the first region B1 and dielectric layer pattern 122 in the second region B2). Then, using the third mask layer as a mask, the dielectric layer is etched to form dielectric layer patterns 121' and 122' in the first region B1 and dielectric layer patterns 121 and 122 in the second region B2, so as to form multiple independent detection openings 15' in the dielectric layer 12 corresponding to the first region B1 and multiple interconnected target openings 15 in the dielectric layer 12 corresponding to the second region B2. In the first region B1, the edges of the first projection of the third pattern (such as dielectric layer pattern 121') onto the semiconductor substrate 10 and the second projection of the third pattern (such as dielectric layer pattern 122') onto the semiconductor substrate 10 are in contact with or partially overlap each other, so that the plurality of detection openings 15' are independent of each other. In the second region B2, there is a gap between the edges of the first projection of the third pattern (such as dielectric layer pattern 121) onto the semiconductor substrate 10 and the second projection of the third pattern (such as dielectric layer pattern 122) onto the semiconductor substrate 10, so that the plurality of target openings 15 are interconnected.

[0095] Afterwards, combined Figure 2 and Figure 3 As shown, using the dielectric layer 12 as a mask, the semiconductor substrate 10 is etched to form a contact hole 16' that communicates with the opening 15' to be detected, and a target contact hole 16 that communicates with the target opening 15. This allows the independent openings 15' and contact holes 16' to form connection holes in the first region B1, and the interconnected target openings 15 and target contact holes 16 to form connection holes in the second region B2. Figure 2 The dashed lines in the diagram represent the bit lines that will be formed. Since the bit lines have not yet been formed, dashed lines are used instead. Using independent detection openings 15' and contact holes 16' to form independent connecting holes in the first region B1 can achieve better detection results. Using interconnected target openings 15' and target contact holes 16' to form interconnected connecting holes in the second region B2 can ensure that the size of the subsequently formed contact structure is large enough.

[0096] In some examples, a semiconductor substrate with interconnecting holes can be used as the semiconductor structure to be inspected, placed in an image acquisition device, and an inspection image of the semiconductor structure to be inspected can be acquired. Optionally, an image of a first region of the semiconductor structure to be inspected can be acquired as the inspection image. Exemplarily, the image acquisition device may include a scanning electron microscope, so that an image of the first region of the semiconductor structure to be inspected can be acquired using the scanning electron microscope as the inspection image. Optionally, as... Figure 4 The detection image JSB1 shown contains specific connecting holes a11 to a45.

[0097] It should be noted that, Figure 4 The detection image shown is for illustrative purposes only. In practical applications, the actual SEM image can be used as the detection image.

[0098] In other examples, after forming the vias, the process may further include filling each via with a conductive structure. Then, the conductive substrate filled with the conductive structure is placed in an image acquisition device as the semiconductor structure to be tested, and a test image of the semiconductor structure to be tested is acquired. Optionally, an image of a second region of the semiconductor structure to be tested can be acquired as the test image. Exemplarily, the image acquisition device may include a scanning electron microscope, which can be used to acquire an image of the second region of the semiconductor structure to be tested as the test image. Subsequently, to avoid the influence of the conductive structure on subsequent processes, after acquiring the test image of the semiconductor structure to be tested, wet etching or dry etching may be used to remove the conductive structure. Optionally, the material of the conductive structure may include, but is not limited to, polysilicon (Poly) or metallic materials (such as W). Since the substrate material exposed by the vias may be silicon, the conductivity of the via region can be enhanced by filling with a conductive structure, increasing the generation of secondary electrons, thereby increasing the contrast between the locations of vias with non-conductive materials and those without in the test image.

[0099] For the detection image, the size (or critical size) of the pattern after etching the dielectric layer is increased, forming independent interconnect holes. Then, the semiconductor structure is placed in a scanning electron microscope. Because the size (or critical size) of the pattern is increased, its aspect ratio is lower than before, and the voltage contrast (VC) signal can be enhanced, making it easier to detect the VC signal. Therefore, the interconnect holes displayed in the detection image are relatively more accurate.

[0100] S20. Based on the image feature values ​​of the location of the connecting hole in the detection image, determine whether there is any residual non-conductive material inside the connecting hole in the semiconductor structure to be detected. For example, after step S20, the method further includes: removing the dielectric layer and filling the bit line contact hole with a conductive contact structure; depositing a bit line material layer on the semiconductor substrate; etching the bit line material layer to form a bit line, the bit line being electrically connected to the transistor drain region of the semiconductor substrate through the conductive contact structure. This makes the contact hole a bit line contact hole, and the semiconductor element includes a transistor drain region.

[0101] In some examples, the connection hole may include a target connection hole. The target connection hole may be one or more in the first region. Step S20 may include the following steps:

[0102] First, a reference image of the reference semiconductor structure is acquired. This reference image can be predetermined as a baseline. It is an image of the side of the reference semiconductor structure where multiple interconnects are formed, and these interconnects are independent of each other.

[0103] In some examples, forming a reference semiconductor structure may include the following steps:

[0104] First, combined Figure 6 As shown, a reference dielectric layer is formed on a reference semiconductor substrate on which semiconductor elements are formed. Exemplarily, a shallow trench isolation region is formed on the reference semiconductor substrate (e.g., a silicon-based wafer) 10 to define an active region, and silicon oxide is filled in the shallow trench isolation region. Word line trenches are then etched into the reference semiconductor substrate, passing through the active region and the silicon oxide in the shallow trench isolation region. A gate oxide layer is then formed on the surface of the word line trenches. Buried word lines are then formed in the word line trenches. A silicon nitride film is then deposited over the entire surface of the reference semiconductor substrate. A dielectric layer is then deposited on the silicon nitride film.

[0105] Optionally, the material of the dielectric layer includes, but is not limited to, silicon oxide.

[0106] Alternatively, the deposition process may include, but is not limited to, physical vapor deposition, chemical vapor deposition, and molecular beam epitaxy.

[0107] Afterwards, combined Figure 5 As shown, wet etching or dry etching is used to etch the reference dielectric layer, forming reference dielectric layer patterns 121” and 122”, thereby creating multiple independent reference openings 15” in the reference dielectric layer. Figure 5 The dashed lines in the diagram represent the position lines that will be formed at this point. Since the position lines have not yet been formed, dashed lines are used instead.

[0108] Afterwards, combined Figure 5As shown, using the reference dielectric layer as a mask, the reference semiconductor substrate is etched to form a reference contact hole that communicates with the reference opening 15”. This allows the interconnected reference opening 15” and the reference contact hole to form a connection hole in the reference semiconductor substrate.

[0109] In some examples, a reference semiconductor substrate with interconnecting vias can be used as a reference semiconductor structure, placed in an image acquisition device, and an image of the reference semiconductor structure can be acquired as a reference image. Exemplarily, the image acquisition device may include a scanning electron microscope, allowing the acquisition of an image of the reference semiconductor structure as a reference image. Optionally, such as... Figure 6 The reference image RF shown contains specific connection holes b11 to b45.

[0110] It should be noted that, Figure 6 The reference image shown is for illustrative purposes only. In practical applications, the actual SEM image can be used as the reference image.

[0111] For the reference image, the size (or critical size) of the pattern after etching the reference dielectric layer is increased, forming independent interconnects. This reference semiconductor structure is then placed in a scanning electron microscope. Because the size (or critical size) of the pattern is increased, its aspect ratio is lower than before, and the voltage contrast (VC) signal can be enhanced, making it easier to detect. Therefore, the interconnects shown in the reference image are relatively more accurate. By comparing the detected image with the reference image, the accuracy of the comparison results can be further improved.

[0112] Next, the image feature values ​​of the target connection hole location in the detected image of the semiconductor structure under test and the reference image of the reference semiconductor structure are compared to determine whether there is residual non-conductive material inside the target connection hole in the semiconductor structure under test. This allows for the determination of whether there is residual non-conductive material inside the target opening in the semiconductor structure under test based on the image feature values ​​of the target connection hole at the same location in the detected image and the pre-determined reference image. That is, if a significant difference is found in the image feature values ​​of the target connection hole at the same location in the detected image and the reference image, it can be considered a defect with residual non-conductive material. Conversely, if no significant difference is found, it can be considered that there is no defect with residual non-conductive material or that the residual non-conductive material has no adverse effect on subsequent processes, and the defect can be ignored.

[0113] In some examples, if a non-conductive material remains in a connection hole, the resistance of that connection hole will increase, resulting in fewer secondary electrons received by the hole. Consequently, the brightness of that connection hole in the detection image will be darker than that of a connection hole at the same location in the reference image, thus detecting the presence of a defect caused by residual non-conductive material. For example, image feature values ​​may include gray levels. Figure 7 As shown, determining whether non-conductive material remains within a target opening in a semiconductor structure to be tested can include the following steps:

[0114] S211. Determine the grayscale difference between the grayscale values ​​of the target connecting hole at the same location in the detection image and the reference image.

[0115] For example, combined Figure 4 and Figure 6 As shown, connection holes a11 and b11 are target connection holes at the same position in the detection image JSB1 and the reference image RF, respectively. The gray value difference Ga11-Gb11 between the gray value Ga11 of connection hole a11 and the gray value Gb11 of connection hole b11 can be obtained.

[0116] And since the connecting holes a12 and b12 are target connecting holes at the same position in the detection image JSB1 and the reference image RF respectively, the gray value difference Ga12-Gb12 between the gray value Ga12 of connecting hole a12 and the gray value Gb12 of connecting hole b12 can be obtained.

[0117] The same principle applies to the others, and so on, so I will not go into details here.

[0118] S212. Determine whether the grayscale difference is greater than the set threshold. If yes, proceed to step S213. If no, proceed to step S214.

[0119] For example, the threshold value can be determined empirically. Of course, in practical applications, the threshold value can be determined according to the needs of the actual application, and this is not limited here.

[0120] S213. Determine if there is any non-conductive material remaining in the target connection hole.

[0121] For example, if the grayscale difference Ga12-Gb12 is greater than a set threshold, it can be determined that there is residual non-conductive material in the connection hole a12, that is, the connection hole a12 has a defect of residual non-conductive material.

[0122] For example, the non-conductive material may include, but is not limited to, a dielectric layer and / or a silicon nitride film layer.

[0123] S214. Ensure that no non-conductive material remains inside the target connection hole.

[0124] For example, if the grayscale difference Ga11-Gb11 is not greater than a set threshold, it can be determined that no non-conductive material remains in the connection hole a11, that is, the connection hole a11 does not have the defect of residual non-conductive material. In other words, it can be said that there is absolutely no residual non-conductive material in the connection hole a11, or that the residual non-conductive material does not have an adverse effect on the performance of the semiconductor structure prepared later, and the defect can be ignored.

[0125] In other examples, if non-conductive material remains in a connection hole, the resistance of that connection hole will increase, resulting in fewer secondary electrons received by the hole. This makes the signal-to-noise ratio (SNR) of that connection hole in the detection image stronger than that of a connection hole at the same location in the reference image, thus detecting the defect of residual non-conductive material. For example, image feature values ​​may include the signal-to-noise ratio. Figure 8 As shown, determining whether non-conductive material remains within a target opening in a semiconductor structure to be tested can include the following steps:

[0126] S221. Determine the signal-to-noise ratio difference between the signal-to-noise ratios of the target connecting holes at the same location in the detection image and the reference image.

[0127] For example, combined Figure 4 and Figure 6 As shown, connection holes a11 and b11 are target connection holes at the same location in the detection image JSB1 and the reference image RF, respectively. The signal-to-noise ratio difference Xa11-Xb11 between connection hole a11 and connection hole b11 can be obtained.

[0128] And since the connection holes a12 and b12 are target connection holes at the same position in the detection image JSB1 and the reference image RF respectively, the signal-to-noise ratio difference Xa12-Xb12 between the signal-to-noise ratio Xa12 of connection hole a12 and the signal-to-noise ratio Xb12 of connection hole b12 can be obtained.

[0129] The same principle applies to the others, and so on, so I will not go into details here.

[0130] S222. Determine whether the signal-to-noise ratio difference is greater than a set threshold. If yes, proceed to step S223. If no, proceed to step S224.

[0131] For example, the threshold value can be determined empirically. Of course, in practical applications, the threshold value can be determined according to the needs of the actual application, and this is not limited here.

[0132] S223. Determine if there is any non-conductive material remaining in the target connection hole.

[0133] For example, if the signal-to-noise ratio difference Xa12-Xb12 is greater than a set threshold, it can be determined that there is residual non-conductive material in the connection hole a12, that is, the connection hole a12 has a defect of residual non-conductive material.

[0134] S224. Ensure that no non-conductive material remains inside the target connection hole.

[0135] For example, if the signal-to-noise ratio difference Xa11-Xb11 is not greater than a set threshold, it can be determined that no non-conductive material remains in the connection hole a11, that is, the connection hole a11 does not have the defect of residual non-conductive material. In other words, it can be said that there is absolutely no residual non-conductive material in the connection hole a11, or that the residual non-conductive material does not have an adverse effect on the performance of the semiconductor structure prepared later, and the defect can be ignored.

[0136] In some other examples, the connection holes in the detection image may include target connection holes and reference connection holes at different locations. That is, one or more are selected from the detection image as target connection holes, and the remaining one or more are selected as reference connection holes. Then step S20 may include: comparing the image feature values ​​of the target connection hole location and the reference connection hole location in the detection image to determine whether there is residual non-conductive material in the target connection hole of the semiconductor structure to be detected. In this way, the process of determining whether there is residual non-conductive material in the target connection hole of the semiconductor structure to be detected can be achieved by comparing only the image feature values ​​of the connection holes in the detection image.

[0137] like Figure 9 As shown, comparing the image feature values ​​of the target connection hole location and the reference connection hole location in the detection image to determine whether non-conductive material remains in the target connection hole in the semiconductor structure to be detected can include the following steps:

[0138] S231. Determine the first gray value of the target connection hole in the detection image and the second gray value of the reference connection hole in the detection image.

[0139] For example, combined Figure 4 As shown, connection hole a11 is the target connection hole in the detection image, and its grayscale value Ga11 can be obtained. Connection hole a13 is the reference connection hole in the detection image, and its grayscale value Ga13 can be obtained. Therefore, grayscale value Ga11 can be used as the first grayscale value, and grayscale value Ga13 can be used as the second grayscale value.

[0140] The same principle applies to the others, and so on, so I will not go into details here.

[0141] S232. Determine whether the first grayscale value is greater than the second grayscale value. If yes, proceed to step S233. If no, proceed to step S234.

[0142] S233, determine that there is residual non-conductive material inside the target connection hole.

[0143] For example, if the gray value Ga11 is greater than the gray value Ga13, it can be determined that there is residual non-conductive material in the contact hole a11, that is, the contact hole a11 has a defect of residual non-conductive material.

[0144] S224, ensure that no non-conductive material remains inside the target connection hole.

[0145] For example, if the grayscale value Ga11 is not greater than the grayscale value Ga13, it can be determined that there is no residual non-conductive material in the contact hole a11, that is, the contact hole a11 does not have the defect of residual non-conductive material. Alternatively, it can be said that there is absolutely no residual non-conductive material in the contact hole a11, or that the residual non-conductive material does not have an adverse effect on the performance of the semiconductor structure prepared later, and the defect can be ignored.

[0146] This disclosure also provides a semiconductor structure detection device, such as... Figure 10 As shown, it may include:

[0147] Acquisition unit 01 is configured to acquire a detection image of a semiconductor structure to be detected; wherein, multiple connection holes in the semiconductor structure to be detected are independent of each other;

[0148] The determining unit 02 is configured to determine whether there is any non-conductive material remaining in the connecting hole of the semiconductor structure to be detected based on the image feature value of the location of the connecting hole in the detection image.

[0149] It should be noted that the working principle and specific implementation method of the semiconductor structure detection device are the same as those of the semiconductor structure detection method in the above embodiments. Therefore, the working method of the semiconductor structure detection device can be implemented by referring to the specific implementation method of the semiconductor structure detection method in the above embodiments, and will not be repeated here.

[0150] In some examples, the acquisition unit and the determination unit may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0151] This disclosure also provides a semiconductor structure, which can be described above, and... Figure 2 and Figure 3 The structure shown is exemplary. The semiconductor structure includes: a semiconductor substrate in which semiconductor elements and contact holes to be detected are formed; and a dielectric layer located on the semiconductor substrate, the dielectric layer including a plurality of independent openings to be detected; the openings to be detected and the contact holes to be detected are connected and together constitute a connection hole.

[0152] For example, refer to Figure 2 and Figure 3 As shown, the semiconductor substrate includes a first region and a second region, with the opening to be detected and the contact hole to be detected located in the first region. A dielectric layer also covers the second region. The dielectric layer corresponding to the first region includes: multiple dielectric patterns that are in contact with or partially overlap each other, forming the opening to be detected between the dielectric patterns, and the openings to be detected communicating with each other. The dielectric layer corresponding to the second region includes: multiple independent dielectric patterns, forming the target opening between the dielectric patterns, and the target openings communicating with each other.

[0153] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0155] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0156] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0157] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0158] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A method of detecting a semiconductor structure, characterized by, The application relates to a method for detecting whether non-conductive substances remain in connection holes of a semiconductor structure. The method comprises the following steps: obtaining an image in a first region of the semiconductor structure to be detected as a detection image, so as to obtain a detection image of the semiconductor structure to be detected; wherein the semiconductor structure to be detected comprises a first region and a second region, the first region has a plurality of mutually independent connection holes, the second region has a plurality of mutually connected connection holes, and the plurality of connection holes in the semiconductor structure to be detected are mutually independent; 2. The method of detecting a semiconductor structure according to claim 1, wherein determining whether non-conductive substances remain in the connection holes in the semiconductor structure to be detected according to image feature values of positions of the connection holes in the detection image. The connection holes comprise target connection holes; The method further comprises the following steps: obtaining a reference image of a reference semiconductor structure; 3. The method of detecting a semiconductor structure according to claim 2, wherein comparing image feature values of positions of the target connection holes in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure, so as to determine whether non-conductive substances remain in the target connection holes in the semiconductor structure to be detected. The image feature values comprise gray values; the comparison of the image feature values of the positions of the target connection holes in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure, so as to determine whether non-conductive substances remain in the target connection holes in the semiconductor structure to be detected, comprises the following steps: determining a gray value difference between the gray values of the target connection holes at the same positions in the detection image and the reference image; judging whether the gray value difference is greater than a set threshold value; if yes, it is determined that non-conductive substances remain in the target connection holes; 4. The method of claim 2, wherein the semiconductor structure is a semiconductor-on- insulator structure. if no, it is determined that non-conductive substances do not remain in the target connection holes. The image feature values comprise signal-to-noise ratios; the comparison of the image feature values of the positions of the target connection holes in the detection image of the semiconductor structure to be detected and the reference image of the reference semiconductor structure, so as to determine whether non-conductive substances remain in the target connection holes in the semiconductor structure to be detected, comprises the following steps: determining a signal-to-noise ratio difference between the signal-to-noise ratios of the target connection holes at the same positions in the detection image and the reference image; judging whether the signal-to-noise ratio difference is greater than a set threshold value; if yes, it is determined that non-conductive substances remain in the target connection holes; 5. The method of claim 1, wherein if no, it is determined that non-conductive substances do not remain in the target connection holes. The connection holes comprise target connection holes and reference connection holes at different positions; The method further comprises the following steps:

6. The method of detecting a semiconductor structure according to claim 5, wherein comparing image feature values of positions of the target connection holes in the detection image and image feature values of positions of the reference connection holes, so as to determine whether non-conductive substances remain in the target connection holes in the semiconductor structure to be detected. The image feature values comprise gray values; The comparing the image feature value of the position where the target connection hole is located in the detection image and the image feature value of the position where the reference connection hole is located determines whether the target connection hole in the semiconductor structure to be detected has residual non-conductive substance, comprising: determining a first gray value of the position where the target connection hole is located in the detection image, and a second gray value of the position where the reference connection hole is located in the detection image; determining whether the first gray value is greater than the second gray value; if yes, it is determined that the target connection hole has residual non-conductive substance; if no, it is determined that the target connection hole has no residual non-conductive substance.

7. The method of detecting a semiconductor structure according to any one of claims 2 to 4, wherein The reference image of the reference semiconductor structure is obtained, comprising: using a scanning electron microscope to obtain an image of a region in the reference semiconductor structure where a plurality of connection holes are formed as the reference image.

8. The method of detecting a semiconductor structure according to any one of claims 1 to 6, wherein Before the detection image of the semiconductor structure to be detected is obtained, further comprising: forming a dielectric layer on a semiconductor substrate where semiconductor elements are formed; the semiconductor substrate comprises a first region and a second region; etching the dielectric layer to form a plurality of mutually independent detection openings in the dielectric layer corresponding to the first region, and a plurality of mutually connected target openings in the dielectric layer corresponding to the second region; using the dielectric layer as a mask, etching the semiconductor substrate to form a detection contact hole connected with the detection opening, and a target contact hole connected with the target opening; wherein the mutually connected detection opening and the detection contact hole constitute the connection hole in the first region, and the mutually connected target opening and the target contact hole constitute the connection hole in the second region.

9. The method of detecting a semiconductor structure according to claim 8, wherein, The etching of the dielectric layer to form a plurality of mutually independent detection openings in the dielectric layer corresponding to the first region, and a plurality of mutually connected target openings in the dielectric layer corresponding to the second region, comprises: forming a first mask layer on the dielectric layer, the first mask layer comprising a plurality of first patterns arranged in an array; forming a second mask layer on the first mask layer, the second mask layer comprising a plurality of second patterns arranged in an array; using the first mask layer and the second mask layer as a mask, etching the dielectric layer to form a plurality of mutually independent detection openings in the dielectric layer corresponding to the first region, and a plurality of mutually connected target openings in the dielectric layer corresponding to the second region; wherein, in the first region, the first projection of the first pattern on the semiconductor substrate and the second projection of the second pattern on the semiconductor substrate are in edge contact or partially overlap; in the second region, the first projection of the first pattern on the semiconductor substrate and the second projection of the second pattern on the semiconductor substrate have a gap therebetween.

10. The method of claim 8, wherein the method further comprises: The contact hole is a bit line contact hole, and the semiconductor element comprises a transistor drain region; After the determination that the connection hole in the semiconductor structure to be detected has no residual non-conductive substance, further comprising: removing the dielectric layer and filling a conductive contact structure in the bit line contact hole; depositing a bit line material layer on the semiconductor substrate; The bit line material layer is etched to form a bit line, which is electrically connected with the transistor drain region of the semiconductor substrate through the conductive contact structure.

11. The method of claim 8, wherein the semiconductor structure is a semiconductor-on- insulator structure. After forming the connection hole, further comprising: filling a conductive structure in each of the connection holes; After obtaining the detection image of the semiconductor structure to be detected, the conductive structure is removed.

12. An apparatus for detecting a semiconductor structure, characterized by Comprising: An acquisition unit is configured to obtain an image in a first region of a semiconductor structure to be detected as a detection image by using a scanning electron microscope, so as to obtain a detection image of the semiconductor structure to be detected; wherein the semiconductor structure to be detected comprises a first region and a second region, the first region has a plurality of mutually independent connection holes, the second region has a plurality of mutually connected connection holes, and the plurality of connection holes in the semiconductor structure to be detected are mutually independent; A determination unit is configured to determine whether there is non-conductive substance remaining in the connection hole in the semiconductor structure to be detected according to the image feature value of the position where the connection hole is located in the detection image.

13. A semiconductor structure, characterized by Comprising: A semiconductor substrate, wherein a semiconductor element and a contact hole to be detected are formed in the semiconductor substrate, the semiconductor substrate comprises a first region and a second region, and the opening to be detected and the contact hole to be detected are located in the first region; A dielectric layer on the semiconductor substrate, wherein the dielectric layer comprises a plurality of mutually independent openings to be detected; the opening to be detected and the contact hole to be detected are connected and jointly constitute a connection hole; The dielectric layer also covers the second region; The dielectric layer corresponding to the first region comprises a plurality of mutually contacting or partially overlapping dielectric patterns, the openings to be detected are formed between the dielectric patterns, and the openings to be detected are connected with the openings to be detected; The dielectric layer corresponding to the second region comprises a plurality of mutually independent dielectric patterns, target openings are formed between the dielectric patterns, and the target openings are connected with the target openings.

Images