Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first bottom electrode with a first feature size and a second bottom electrode with a second feature size, and the first feature size is greater than the second feature size; a first resistive switching layer and a second resistive switching layer; a first top electrode with a third feature size and a second top electrode with a fourth feature size, and the third feature size is greater than the fourth feature size; wherein a vertical projection of the first bottom electrode and a vertical projection of the first top electrode at least partially overlap to form a first overlapping area, and the first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping area constitute an erasable memristor; a vertical projection of the second bottom electrode and a vertical projection of the second top electrode at least partially overlap to form a second overlapping area, and the second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping area constitute a non-erasable memristor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Memristors, as a novel type of nonlinear electronic device, possess characteristics such as a simple metal-insulator-metal structure, high scalability, and non-volatile storage, making them one of the core components for overcoming Moore's Law bottlenecks and realizing high-performance, low-power hardware platforms. However, existing memristor arrays are mostly single-function, possessing only erasable or non-erasable characteristics. If a memristor array needs to simultaneously achieve both functions, multiple chips must be fabricated using different processes and then packaged and integrated. This leads to increased fabrication costs, reduced integration density, and introduces interconnection losses between chips, ultimately affecting the overall device performance.

[0003] Furthermore, since the erasable / non-erasable functional differentiation of existing memristor arrays is mostly achieved by changing the material system, electrode structure, or functional layer thickness, multiple film deposition, masking, and etching processes are required. The process steps are cumbersome, and the process compatibility of different functional devices is poor, making it difficult to achieve high-density integration on a single chip. This severely limits the industrial application of memristors in hierarchical data storage and multifunctional integrated circuits. Summary of the Invention

[0004] In view of this, the present application provides a semiconductor structure and a method for preparing the same to solve at least one problem existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a semiconductor structure, including: The substrate has erasable device regions and non-erasable device regions; At least one first bottom electrode with a first feature size is located in the erasable device region, and at least one second bottom electrode with a second feature size is located in the non-erasable device region, wherein the first feature size is larger than the second feature size; The first resistive switching layer and the second resistive switching layer are respectively located on the first bottom electrode and the second bottom electrode; At least one first top electrode having a third characteristic dimension and at least one second top electrode having a fourth characteristic dimension, wherein the third characteristic dimension is larger than the fourth characteristic dimension; wherein, The first top electrode is located on the first resistive switching layer, and on the plane where the substrate is located, the vertical projection of the first bottom electrode and the vertical projection of the first top electrode at least partially overlap to form one or more first overlapping regions. The first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping region constitute an erasable memristor. The second top electrode is located on the second resistive switching layer, and on the plane where the substrate is located, the vertical projection of the second bottom electrode and the vertical projection of the second top electrode at least partially overlap to form one or more second overlapping regions. The second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping region constitute a non-erasable memristor.

[0006] In conjunction with the first aspect of this application, in an optional embodiment, the first feature size and the third feature size are both greater than or equal to 100 μm; the second feature size and the fourth feature size are both less than or equal to 30 μm.

[0007] In conjunction with a first aspect of this application, in an alternative embodiment, the first feature size is equal to the third feature size, and the second feature size is equal to the fourth feature size.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, the erasable device region includes at least one erasable device array, one of the erasable device arrays including four first bottom electrodes and four first top electrodes, and the four first bottom electrodes and the four first top electrodes partially overlap on the vertical projection of the substrate, forming sixteen first overlapping regions; the sixteen first overlapping regions are arranged in rows along a first direction and in columns along a second direction, forming a 4-row 4-column rectangular array; the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction is perpendicular to the second direction; The non-erasable device region includes at least one non-erasable device array, and one of the non-erasable device arrays includes one second bottom electrode and ten second top electrodes; one second bottom electrode and ten second top electrodes overlap the vertical projection portion on the plane where the substrate is located to form ten second overlapping regions; the ten second overlapping regions are arranged in rows along the first direction and in columns along the second direction to form a rectangular array of 1 row and 10 columns.

[0009] In conjunction with the first aspect of this application, in an optional embodiment, the materials of the first resistive switching layer and the second resistive switching layer are aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, both the first resistive switching layer and the second resistive switching layer are made of aluminum nitride; the aluminum content in the aluminum nitride is in the range of 51% to 55%.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, both the first resistive switching layer and the second resistive switching layer are made of aluminum nitride; the thickness of the aluminum nitride is 10 nm to 30 nm.

[0012] In conjunction with a first aspect of this application, in an optional embodiment, the erasable memristor has a low-resistance state and a high-resistance state, wherein the ratio of the turn-off resistance of the high-resistance state to the on-resistance of the low-resistance state is greater than or equal to 10. 5 The duration of the low-resistivity state is greater than or equal to 10. 4 s.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, both the erasable memristor and the non-erasable memristor are unipolar memristors; the erasable memristor and the non-erasable memristor share a single-voltage drive circuit.

[0014] Secondly, embodiments of this application provide a method for fabricating a semiconductor structure, including: A substrate is provided, the substrate having an erasable device region and a non-erasable device region; At least one first bottom electrode having a first feature size and at least one second bottom electrode having a second feature size are formed on the substrate; wherein the first bottom electrode is located in an erasable device region and the second bottom electrode is located in the non-erasable device region; the first feature size is larger than the second feature size; A first resistive switching layer and a second resistive switching layer are formed on the first bottom electrode and the second bottom electrode, respectively; At least one first top electrode having a third characteristic dimension and at least one second top electrode having a fourth characteristic dimension are formed, wherein the third characteristic dimension is larger than the fourth characteristic dimension; wherein, The first top electrode is located on the first resistive switching layer, and on the plane where the substrate is located, the vertical projection of the first bottom electrode and the vertical projection of the first top electrode at least partially overlap to form one or more first overlapping regions. The first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping region constitute an erasable memristor. The second top electrode is located on the second resistive switching layer, and on the plane where the substrate is located, the vertical projection of the second bottom electrode and the vertical projection of the second top electrode at least partially overlap to form one or more second overlapping regions. The second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping region constitute a non-erasable memristor.

[0015] Compared with existing technologies, this application has the following advantages: The semiconductor structure and its fabrication method provided in the embodiments of this application can achieve functional differentiation of devices of different sizes by only differentiating the feature dimensions of the top and bottom electrodes of the device. This allows for high-density integration of erasable and non-erasable memristors on a single chip. Thus, it solves the problems of existing memristor arrays, such as single function, cumbersome multi-functional integration fabrication processes, poor process compatibility, and high cost.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a top view of the semiconductor structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of an erasable memristor array provided in an embodiment of this application; Figure 3 Electron micrograph of an erasable memristor array provided in an embodiment of this application; Figure 4 A top view of the non-erasable memristor array provided in an embodiment of this application; Figure 5 Pulse response diagram of an erasable memristor array provided in an embodiment of this application; Figure 6 Pulse response diagram of a non-erasable memristor array provided in an embodiment of this application; Figure 7 This is a test diagram of the multi-resistivity retention time of an erasable memristor array provided in an embodiment of this application; Figure 8 A characteristic curve of the average resistance of the erasable memristor array provided in the embodiments of this application as a function of the limiting current; Figure 9 Cycle-Set test diagram of an erasable memristor array provided in an embodiment of this application; Figure 10 Cycle-Reset test diagram of an erasable memristor array provided in an embodiment of this application; Figure 11 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment; Figures 12 to 14 This is a schematic diagram of the structure of the erasable memristor array provided in the embodiments of this application during the fabrication process. Detailed Implementation

[0018] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0019] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0020] In the accompanying drawings, for clarity, the dimensions of the structures and their relative dimensions may be exaggerated. The same reference numerals denote the same structural features throughout.

[0021] When structures are referred to as being "on," "adjacent to," "connected to," or "coupled to" other structures, they may be directly on, adjacent to, connected to, or coupled to other structures, or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other structures, there are no intervening structures. Although the terms first, second, third, etc., may be used to describe structures or parts, these terms are only used to distinguish one structure or part from another. Therefore, without departing from the teachings of this application, the first structure or part discussed below may be referred to as the second structure or part. And the discussion of the second structure or part does not imply that the first structure or part necessarily exists in this application.

[0022] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated feature but do not exclude the presence or addition of one or more other features. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0025] This application provides a semiconductor structure. Figure 1 This is a top view of the semiconductor structure provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of an erasable memristor array provided in an embodiment of this application; Figure 3Electron micrograph of an erasable memristor array provided in an embodiment of this application; Figure 4 This is a top view schematic diagram of the non-erasable memristor array provided in an embodiment of this application. Figures 1 to 4 As shown, the semiconductor structure includes: The substrate 100 has an erasable device region 101 and a non-erasable device region 102; At least one first bottom electrode 201 with a first feature size is located in the erasable device region 101 and at least one second bottom electrode 301 with a second feature size is located in the non-erasable device region 102, wherein the first feature size is larger than the second feature size; The first resistive switching layer 202 and the second resistive switching layer 302 are respectively located on the first bottom electrode 201 and the second bottom electrode 301; At least one first top electrode 203 having a third characteristic dimension and at least one second top electrode 303 having a fourth characteristic dimension, wherein the third characteristic dimension is larger than the fourth characteristic dimension; wherein, The first top electrode 203 is located on the first resistive switching layer 202, and on the plane of the substrate 100, the vertical projections of the first bottom electrode 201 and the first top electrode 203 at least partially overlap to form one or more first overlapping regions a. The first bottom electrode 201, the first resistive switching layer 202 and the first top electrode 203 located in the same first overlapping region a constitute an erasable memristor 200. The second top electrode 303 is located on the second resistive switching layer 302, and on the plane of the substrate 100, the vertical projections of the second bottom electrode 301 and the second top electrode 303 at least partially overlap to form one or more second overlapping regions b. The second bottom electrode 301, the second resistive switching layer 302 and the second top electrode 303 located in the same second overlapping region b constitute a non-erasable memristor 300.

[0026] It is understood that in the semiconductor structure provided in this application embodiment, the first feature size of the first bottom electrode 201 is larger than the second feature size of the second bottom electrode 301, and the third feature size of the first top electrode 203 is larger than the fourth feature size of the second top electrode 303. Based on the above feature sizes, the first bottom electrode 201, the first resistive switching layer 202, and the first top electrode 203 located in the same first overlapping region a constitute a large-size device (also known as a "large-size memristor cell"), while the second bottom electrode 301, the second resistive switching layer 302, and the second top electrode 303 located in the same second overlapping region b constitute a small-size device (also known as a "small-size memristor cell").

[0027] Furthermore, there are significant differences in the internal electric fields of large-size and small-size devices. Specifically, the large-size device has a uniform internal electric field distribution and moderate current density. During the reset process, the Joule heat generated inside the device can diffuse smoothly, thereby achieving controllable melting of the conductive channel and allowing the device to stably return to a high-resistivity state, thus realizing the erasable function. Therefore, the large-size device is an erasable memristor 200. On the other hand, the small-size device has a concentrated internal electric field and a significantly higher current density than the large-size device. During the reset process, the small-size device will generate a strong arc remelting effect, causing the conductive channel to be rapidly rebuilt after melting, making it impossible to return to the high-resistivity state. Ultimately, it can only maintain a low-resistivity state, thus realizing the non-erasable function. Therefore, the small-size device is a non-erasable memristor 300.

[0028] In summary, the embodiments of this application can achieve functional differentiation of devices of different sizes simply by differentiating the feature dimensions of the bottom electrode and top electrode, thereby enabling high-density integration of erasable and non-erasable memristors on a single chip. This solves the problems of existing memristor arrays, such as limited functionality, cumbersome multi-functional integration fabrication processes, poor process compatibility, and high costs.

[0029] It should be noted that in the field of integrated circuits, feature size refers to the smallest dimension in a semiconductor device. In the embodiments of this application, for any single electrode, its feature size is defined as: the lateral dimension of the electrode measured in the plane of the substrate along a direction perpendicular to the electrode's own extension direction. The electrode can be any one of the first bottom electrode 201, the second bottom electrode 301, the first top electrode 203, and the second top electrode 303. The first bottom electrode 201 and the second bottom electrode 301 are collectively referred to as bottom electrodes, and the first top electrode 203 and the second top electrode 303 are collectively referred to as top electrodes.

[0030] In some embodiments, please refer to Figure 1 The substrate 100 may be a semiconductor substrate; specifically, the substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. In the embodiments of this application, the substrate 100 is a single-crystal silicon substrate with a (100) crystal orientation.

[0031] It should be noted that the surface of substrate 100 is defined as the plane in which substrate 100 is located, and the direction perpendicular to the plane in which substrate 100 is located is the thickness direction of substrate 100. The first direction and the second direction are perpendicular to the thickness direction of substrate 100, and the first direction intersects the second direction. In the embodiments of this application, the first direction is perpendicular to the second direction.

[0032] It should also be noted that erasable device region 101 and non-erasable device region 102 refer to two functional partitions formed by virtual functional area division on the surface of substrate 100. Erasable device region 101 corresponds to the area where one or more erasable memristors 200 are located; erasable device region 101 can be referred to as the "erasable region" or "erasable memristor array region." Non-erasable device region 102 corresponds to the area where one or more non-erasable memristors 300 are located; non-erasable device region 102 can be referred to as the "non-erasable region" or "non-erasable memristor array region." Erasable device region 101 and non-erasable device region 102 are only used to define the layout range of different functional devices.

[0033] In some embodiments, please refer to Figure 1 The erasable device region 101 includes at least one erasable memristor array 401. An erasable memristor array 401 includes a plurality of erasable memristors 200 arranged in a first direction (row direction) and a second direction (column direction). Furthermore, the non-erasable device region 102 includes at least one non-erasable memristor array 402. A non-erasable memristor array 402 includes a plurality of non-erasable memristors 300 arranged in a first direction (row direction) and a second direction (column direction).

[0034] In some embodiments, in an erasable memristor array 401, there are multiple first bottom electrodes 201 and multiple first top electrodes 203, and the multiple first bottom electrodes 201 and multiple first top electrodes 203 are all strip-shaped. The multiple first bottom electrodes 201 extend in the erasable device region 101 along a first direction and are spaced apart along a second direction; the multiple first top electrodes 203 extend in the erasable device region 101 along the second direction and are spaced apart along the first direction.

[0035] Thus, in an erasable memristor array 401, a first bottom electrode 201 can serve as the common bottom electrode of multiple erasable memristors 200 located in the same row; a first top electrode 203 can serve as the common top electrode of multiple erasable memristors 200 located in the same column.

[0036] In some embodiments, in a non-erasable memristor array 402, there are multiple second bottom electrodes 301 and multiple top electrodes 303, and the multiple second bottom electrodes 301 and multiple second top electrodes 303 are strip-shaped. The multiple second bottom electrodes 301 extend in the non-erasable device region 102 along a first direction and are spaced apart along a second direction; the multiple second top electrodes 303 extend in the non-erasable device region 102 along the second direction and are spaced apart along the first direction.

[0037] Thus, in a non-erasable memristor array 402, a second bottom electrode 301 can serve as the common bottom electrode of multiple non-erasable memristors 300 located in the same row; a second top electrode 303 can serve as the common top electrode of multiple non-erasable memristors 300 located in the same column.

[0038] It should be noted that the number of the first bottom electrode 201 and the first top electrode 203 located in an erasable memristor array 401 is not necessarily multiple. Similarly, the number of the second bottom electrode 301 and the second top electrode 303 located in a non-erasable memristor array 402 is not necessarily multiple. The number of each electrode can be designed according to the actual application requirements, and this application does not impose a unique limitation on this.

[0039] In the embodiments of this application, please refer to Figure 2 and Figure 4 Each erasable device array 401 in the erasable device region 101 includes four first bottom electrodes 201 and four first top electrodes 203. The vertical projections of the four first bottom electrodes 201 and the four first top electrodes 203 on the plane of the substrate 100 overlap to form sixteen first overlapping regions a. The sixteen first overlapping regions a are arranged in rows along a first direction and in columns along a second direction to form a rectangular array of 4 rows and 4 columns. Each non-erasable device array 402 in the non-erasable device region 102 includes one second bottom electrode 301 and ten second top electrodes 303. The vertical projections of the one second bottom electrode 301 and the ten second top electrodes 303 on the plane of the substrate 100 overlap to form ten second overlapping regions b. The ten second overlapping regions b are arranged in rows along a first direction and in columns along a second direction to form a rectangular array of 1 row and 10 columns.

[0040] In some embodiments, please refer to Figure 2 and Figure 4 The ratio of the first characteristic dimension of the first bottom electrode 201 to the second characteristic dimension of the second bottom electrode 301 is the first ratio, and the ratio of the third characteristic dimension of the first top electrode 203 to the fourth characteristic dimension of the second top electrode 303 is the second ratio. Both the first ratio and the second ratio are greater than or equal to 10:3; specifically, the first ratio and the second ratio can be 10:3, 4:1, 5:1, 10:1, 20:1, etc. Here, the first characteristic dimension is the dimension of the first bottom electrode 201 along the second direction; the second characteristic dimension is the dimension of the second bottom electrode 301 along the second direction; the third characteristic dimension is the dimension of the first top electrode 203 along the first direction; and the fourth characteristic dimension is the dimension of the second top electrode 303 along the first direction.

[0041] Understandably, limiting both the first and second ratios to no less than 10:3 can further ensure the full realization of functional differentiation for devices of different sizes.

[0042] In some embodiments, the first feature size and the third feature size are both greater than or equal to 100 μm; the second feature size and the fourth feature size are both less than or equal to 30 μm.

[0043] Understandably, by limiting the first and third feature dimensions to both greater than or equal to 100 μm, it is beneficial to further improve the uniformity of the electric field distribution and the appropriate current density within the erasable memristor 200; by limiting the second bottom electrode 301 and the fourth feature dimension to both less than or equal to 30 μm, the electric field within the non-erasable memristor 300 can be highly concentrated and the current density can be sharply increased. In this way, the complete functional differentiation between the erasable memristor 200 and the non-erasable memristor 300 can be ensured.

[0044] In some embodiments, the first and third feature dimensions can be 100μm to 200μm; the second and fourth feature dimensions can be 3μm to 30μm. This ensures complete functional differentiation between devices of different sizes while avoiding excessive area occupation by large-size devices, thus improving device integration. For example, the first and third feature dimensions can be 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, etc.; the second and fourth feature dimensions can be 3μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, etc.

[0045] In some embodiments, the first feature size is equal to the third feature size, and the second feature size is equal to the fourth feature size. For example, the first and third feature sizes are both 100 μm, and the second and fourth feature sizes are both 30 μm.

[0046] In some embodiments, the materials for both the bottom electrode and the top electrode can be active metals such as aluminum (Al), copper (Cu), and silver (Ag). The thickness of both the bottom electrode and the top electrode is 100 nm.

[0047] In some embodiments, the bottom electrode and the top electrode are each provided with electrode leads 400 at opposite ends along their corresponding extension directions, which are used for electrical connection with peripheral driving circuits. It is understood that since both the bottom electrode and the top electrode are strip-shaped, providing electrode leads 400 only at opposite ends along their corresponding extension directions allows for unified addressing and signal transmission of multiple corresponding devices. This is beneficial for improving the integration density of the erasable memristor array 401 and the non-erasable memristor array 402.

[0048] In some embodiments, please refer to Figure 2 and Figure 4The materials of the first resistive switching layer 202 and the second resistive switching layer 302 can be wide bandgap semiconductor materials such as aluminum nitride (AlN), gallium nitride (GaN) or aluminum gallium nitride (AlGaN).

[0049] In this embodiment, the first resistive switching layer 202 and the second resistive switching layer 302 are made of aluminum nitride, and the erasable memristor 200 and the non-erasable memristor 300 are aluminum nitride-based memristors. As an ultra-wide bandgap semiconductor material, aluminum nitride possesses excellent physical and chemical properties, making it an ideal candidate material for the functional layer of memristors.

[0050] In some embodiments, aluminum nitride is (100) preferred oriented, which allows for tight bonding with the bottom electrode without interface separation, thereby effectively ensuring the structural stability and electrical performance of the device. The overall band gap of aluminum nitride ranges from 5.7 eV to 6.1 eV, for example, 5.77 eV. The aluminum content in aluminum nitride is in the range of 51% to 55%. Compared with standard stoichiometric aluminum nitride, this composition of aluminum nitride can induce the formation of a large number of nitrogen vacancy defects at the electrode-resistive switching layer interface; nitrogen vacancies can serve as charge transport sites, effectively reducing the formation barrier of conductive channels and facilitating the rapid formation of continuous conductive filaments.

[0051] In some embodiments, when the materials of the first resistive switching layer 202 and the second resistive switching layer 302 are aluminum nitride, the thickness of the first resistive switching layer 202 and the second resistive switching layer 302 can be 10nm to 30nm, specifically, for example, 10nm, 15nm, 20nm, 25nm, 30nm, etc. In the embodiments of this application, the thickness of the first resistive switching layer 202 and the second resistive switching layer 302 is 22nm.

[0052] In some embodiments, both the erasable memristor 200 and the non-erasable memristor 300 are unipolar memristors. The erasable memristor 200 and the non-erasable memristor 300 may share a single voltage drive circuit (also known as a "unidirectional voltage drive circuit").

[0053] Understandably, existing memristor research largely focuses on bipolar memristors that require bidirectional voltage to achieve resistive switching. Integrating different types of memristors to simultaneously achieve both erasable and non-erasable functions would lead to complex external drive circuit design and increased power consumption. In this application, the erasable memristor array 401 and the non-erasable memristor array 402 share a unidirectional voltage drive circuit, which can significantly reduce the complexity of the external drive circuit design and power consumption.

[0054] In some embodiments, the erasable memristor 200 has a low-resistance state and a high-resistance state, wherein the ratio of the turn-off resistance of the high-resistance state to the on-resistance state is greater than or equal to 10. 5 The low-resistivity state is maintained for a duration of 10 seconds or more. 4The erasable memristor 200 achieves more than 80 stable non-volatile cycle switching.

[0055] In some embodiments, the erasable memristor 200 is in a current-limiting current (I CC Under a unidirectional positive voltage of 1mA, the Forming (initialization), Set (write), and Reset processes can be achieved. The non-erasable memristor 300 does not require a Forming process; under a unidirectional positive voltage, only the Set process can be achieved, and the Reset process cannot. This is because the electric field inside the small-sized device is significantly concentrated, making the carrier transport path more determined. Therefore, the Set operation can be performed directly without pre-building a channel through high-voltage Forming.

[0056] It should be noted that the performance and related parameters of the erasable memristor 200 and the non-erasable memristor 300 mentioned above were obtained by conducting electrical performance tests and analyses on the memristor array using a Keithley 4200A-SCS semiconductor parameter analyzer and probe station. The test environment was room temperature and normal pressure. Below, in conjunction with... Figures 5 to 7 Analyze the test results.

[0057] Figure 5 Pulse response diagram of an erasable memristor array provided in an embodiment of this application; Figure 6 The pulse response diagram of the non-erasable memristor array provided in the embodiments of this application; wherein, Figure 5 and Figure 6 The horizontal axis represents time, and the vertical axes represent the device's input voltage and response current, respectively.

[0058] like Figure 5 As shown, for the erasable memristor array 401, the same unidirectional voltage pulse is used to implement read, write, and reset operations. The write pulse is 4V (current limited to 1mA), the erase pulse is 2V (current unlimited), and the read pulse is 0.5V. Under pulse drive, the device can achieve stable resistance state switching. After writing, the low-resistance state resistance is <100Ω, and after erasing, the high-resistance state resistance returns to 10Ω. 7 Ω level, turn-off / on resistance ratio >10 5 Furthermore, the resistive state showed no significant drift after multiple pulse read / write operations, demonstrating excellent pulse programmable and non-volatile storage characteristics.

[0059] like Figure 6As shown, for the non-erasable memristor array 402, no forming process is required. Using the same unidirectional voltage pulse as the erasable memristor array 401, the write pulse is 4V (current limit 1mA) and the read pulse is 0.5V, which can achieve stable writing. After writing, the low-resistance state resistance is <100Ω. When a 2V erase pulse (with the same parameters as the erasable memristor array 401) is applied, the resistance does not rise significantly and always remains in a low-resistance state, with no erasure effect. During the pulse test, the low-resistance state remains stable without drift attenuation, demonstrating excellent pulse programmable and non-erasable storage characteristics.

[0060] As can be seen, both the erasable memristor array 401 and the non-erasable memristor array 402 can be driven by the same unidirectional voltage pulse source. The pulse parameters are highly matched, and they can share the same peripheral pulse drive circuit. There is no need for polarity switching, which can greatly simplify the peripheral circuit design of the memristor array and reduce circuit power consumption and integration difficulty.

[0061] Figure 7 This is a test diagram of the multi-resistivity retention time of an erasable memristor array provided in an embodiment of this application; Figure 8 The graph shows the characteristic curve of the average resistance of the erasable memristor array provided in the embodiments of this application as a function of the limiting current. Figure 7 and Figure 8 As shown, I is controlled by gradient CC The current was increased from 200μA to 1mA, and the resistance hold-up time and resistance stability of the erasable memristor array 401 in the high resistance state (HRS) and low resistance state (LRS) were tested under different current limiting conditions: when the current limiting current I... CC At a current limit of 200 μA, the device can maintain a low-resistance state, but a spontaneous resistance jump occurs at 222 s, exhibiting low-resistance fatigue characteristics. When the current limit is gradually increased to 1 mA, the device's low-resistance state holding time reaches 10 ms. 4 The resistance is above 10 s, and there is no significant drift in the resistance value throughout the entire range, with the high resistance state stably maintained at 10. 7 With resistance at the Ω level, it exhibits excellent resistance state retention characteristics. Therefore, the erasable memristor array 401 can achieve at least 8 stable resistance states, corresponding to the storage of >3 bits of data, which is beneficial for applications in high-density storage, neuromorphic computing, and other fields.

[0062] Figure 9 Cycle-Set test diagram of an erasable memristor array provided in an embodiment of this application; Figure 10 This is a cycle-reset test diagram of an erasable memristor array provided in an embodiment of this application. Figure 9 and Figure 10As shown, the erasable memristor array 401 can stably achieve repeated switching of the resistance state, with clear distinction between high and low resistance states and small resistance state fluctuations. It can achieve more than 80 stable non-volatile cycle switching and has good cycle durability and erasable and rewritable characteristics.

[0063] This application also provides a method for fabricating a semiconductor structure. Figure 11 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in this application embodiment. Please refer to... Figure 11 Methods for fabricating semiconductor structures include: Step S101: Provide a substrate having an erasable device region and a non-erasable device region; Step S102: Form at least one first bottom electrode having a first feature size and at least one second bottom electrode having a second feature size on the substrate; wherein the first bottom electrode is located in an erasable device region and the second bottom electrode is located in a non-erasable device region; the first feature size is larger than the second feature size; Step S103: A first resistive switching layer and a second resistive switching layer are formed on the first bottom electrode and the second bottom electrode, respectively. Step S104: Form at least one first top electrode having a third feature size and at least one second top electrode having a fourth feature size, wherein the third feature size is larger than the fourth feature size; wherein the first top electrode is located on the first resistive switching layer, and on the plane of the substrate, the vertical projection of the first bottom electrode and the vertical projection of the first top electrode at least partially overlap to form one or more first overlapping regions, and the first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping region constitute an erasable memristor; the second top electrode is located on the second resistive switching layer, and on the plane of the substrate, the vertical projection of the second bottom electrode and the vertical projection of the second top electrode at least partially overlap to form one or more second overlapping regions, and the second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping region constitute a non-erasable memristor.

[0064] It is understood that in the semiconductor structure fabrication method provided in this application embodiment, the first feature size of the first bottom electrode is larger than the second feature size of the second bottom electrode, and the third feature size of the first top electrode is larger than the fourth feature size of the second top electrode. Based on the above feature sizes, the first bottom electrode, the first resistive switching layer, and the first top electrode located in the same first overlapping region constitute a large-size device (also known as a "large-size memristor cell"), while the second bottom electrode, the second resistive switching layer, and the second top electrode located in the same second overlapping region constitute a small-size device (also known as a "small-size memristor cell").

[0065] Furthermore, there are significant differences in the internal electric fields between large-size and small-size devices. Specifically, the large-size device has a uniform internal electric field distribution and moderate current density. During the reset process, the Joule heat generated inside the device can diffuse smoothly, thereby achieving controllable melting of the conductive channel and allowing the device to stably return to a high-resistivity state, thus realizing the erasable function. Therefore, the large-size device is an erasable memristor. On the other hand, the small-size device has a concentrated internal electric field and a significantly higher current density than the large-size device. During the reset process, the small-size device will generate a strong arc remelting effect, causing the conductive channel to melt and rebuild rapidly, making it impossible to return to the high-resistivity state. Ultimately, it can only maintain a low-resistivity state, thus realizing the non-erasable function. Therefore, the small-size device is a non-erasable memristor.

[0066] In summary, the embodiments of this application can achieve functional differentiation of devices of different sizes simply by differentiating the feature dimensions of the bottom electrode and top electrode, thereby enabling high-density integration of erasable and non-erasable memristors on a single chip. This solves the problems of existing memristor arrays, such as limited functionality, cumbersome multi-functional integration fabrication processes, poor process compatibility, and high costs.

[0067] It should also be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0068] Figures 12 to 14 This is a schematic diagram illustrating the fabrication process of the erasable memristor array provided in this embodiment of the application. It should be noted that... Figures 12 to 14 The fabrication process of the erasable memristor located in the erasable device region is only schematically shown. Those skilled in the art will clearly understand that the non-erasable device and the erasable device are fabricated simultaneously on the same substrate, and the functional layers and electrode structures of both are formed simultaneously with the same process steps. The fabrication process, process parameters and structural forming methods are completely consistent. Therefore, the fabrication process of the non-erasable memristor located in the non-erasable device region is not shown in the figure.

[0069] Below, in conjunction with Figure 1 , Figure 2 , Figure 4 ,as well as Figures 12 to 14 The preparation method of the semiconductor structure provided in the embodiments of this application and its beneficial effects are further described in detail.

[0070] First, please refer to Figure 1In step S101, a substrate 100 is provided, the substrate 100 having an erasable device region 101 and a non-erasable device region 102.

[0071] In some embodiments, please refer to Figure 1 The substrate 100 may be a semiconductor substrate; specifically, the substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. In the embodiments of this application, the substrate 100 is a single-crystal silicon substrate with a (100) crystal orientation.

[0072] In some embodiments, after providing the substrate 100, the substrate 100 can be pretreated. The specific steps may include: first, cleaning the surface of the substrate 100 sequentially with acetone, isopropanol, and deionized water to remove surface defects such as organic contaminants and particulate impurities attached to the surface of the substrate 100, and ensuring the cleanliness of the substrate 100 surface; then, drying the residual moisture on the surface of the substrate 100 with high-purity nitrogen gas with a purity of not less than 99.999%; and finally, placing the dried substrate 100 in the magnetron sputtering chamber for subsequent deposition (DEP) processes.

[0073] Then, please refer to Figure 2 , Figure 4 and Figure 12 In step S102, at least one first bottom electrode 201 having a first feature size and at least one second bottom electrode 301 having a second feature size are formed on the substrate 100; wherein the first bottom electrode 201 is located in the erasable device region 101, and the second bottom electrode 301 is located in the erasable device region 101 and the non-erasable device region 102, respectively; the first feature size is larger than the second feature size.

[0074] In some embodiments, the specific steps of forming at least one first bottom electrode 201 having a first feature size and at least one second bottom electrode 301 having a second feature size on the substrate 100 may include: first, forming a photoresist layer on the substrate 100 and patterning the photoresist layer to form at least one first opening having a first exposure size and at least one second opening having a second exposure size in the photoresist layer, the first opening and the second opening exposing portions of the erasable device region 101 and the non-erasable device region 102 of the substrate 100, respectively, and the first exposure size being larger than the second exposure size; then, depositing bottom electrode material on the substrate 100, the bottom electrode material filling the first opening and the second opening and covering the top surface of the remaining photoresist layer; finally, using a lift-off process to remove the remaining photoresist layer and the bottom electrode material located on the top surface of the photoresist layer, the remaining bottom electrode material filling the first opening and the second opening forming the first bottom electrode 201 having the first feature size and the second bottom electrode 301 having the second feature size, respectively. The first bottom electrode 201 and the second bottom electrode 301 serve as the bottom electrodes of the subsequently formed erasable memristor and non-erasable memristor, respectively; the feature size of the first bottom electrode 201 and the second bottom electrode 301 is determined by the exposure size of the first opening and the second opening.

[0075] For example, the specific steps for forming a photoresist layer on substrate 100 and exposing and developing the photoresist layer include: spin-coating AZ5214 photoresist onto the surface of substrate 100; after spin-coating, pre-baking the photoresist on a hot plate to form a photoresist layer; then, sequentially exposing, developing, and fixing the photoresist layer to obtain a photoresist layer (also known as a "photoresist mask") that matches the target bottom electrode pattern; finally, drying with high-purity nitrogen to obtain a photoresist layer with a thickness of 1.5 μm, uniform film without pinholes, neat edges, and no etching or residual photoresist problems. Specifically, the spin-coating speed is 4000 r / min, and the spin-coating time is 30 s; the pre-baking temperature is 100℃, and the pre-baking time is 90 s; the exposure treatment is achieved through ultraviolet lithography with an exposure dose of 150 mJ / cm². 2 The developing and fixing processes were performed using developer and deionized water, respectively. The developing time was 60 seconds and the fixing time was 30 seconds.

[0076] It should be noted that the exposure mask used to expose the photoresist layer can be a customized mask. The pattern structure, size specifications and arrangement of the exposure mask can be designed and adjusted according to the actual device fabrication requirements, structural design and process compatibility requirements.

[0077] For example, the specific steps for depositing the bottom electrode material on the substrate 100 include: using a high-purity Al target with a purity of 99.99% as the sputtering target, using a patterned photoresist layer as a mask, and depositing an Al thin film using DC magnetron sputtering. During the sputtering process, the deposition temperature is room temperature (RT), the deposition power is 100W~150W, and the deposition time is 15min~20min; the reaction gas is argon, the argon flow rate is 20sccm~30sccm; and the sputtering pressure is 1mTorr~10mTorr, for example, 0.5Pa. Here, the sputtering pressure of the Al thin film is controlled at 1mTorr~10mTorr, which allows the Al atoms to have a suitable mean free path and deposition kinetic energy, which is conducive to forming a dense Al thin film with a (111) preferred orientation. The uniformity of the film is less than 5%, and there are no structural defects such as pinholes and cracks.

[0078] The specific principle of depositing Al thin films using DC magnetron sputtering is as follows: high-purity Al is used as the target material, and ionization is performed under the action of an electric field to generate argon ions (Ar). + High-energy argon ions bombard the Al target, causing Al atoms to be sputtered and released; the Al atoms migrate to the surface of the substrate 100 and are deposited.

[0079] Exemplarily, the step of stripping the remaining photoresist layer and the bottom electrode material on the top surface of the photoresist layer includes: immersing the substrate 100 with the deposited Al thin film in an acetone stripper solution at a constant temperature, and using the swelling effect of the stripper solution to strip the photoresist and the Al thin film attached to the photoresist surface. After stripping, the substrate 100 can be ultrasonically cleaned with deionized water to remove residual stripper solution and Al particles, and then dried with high-purity nitrogen gas. The immersion temperature is 60℃~80℃, the immersion time is 10min~20min; the ultrasonic cleaning power is 200W, and the ultrasonic cleaning time is 5min.

[0080] In some embodiments, there are multiple first bottom electrodes 201 and multiple second bottom electrodes 301; both the first bottom electrodes 201 and the second bottom electrodes 301 are strip-shaped. The multiple first bottom electrodes 201 and the multiple second bottom electrodes 301 extend along a first direction and are arranged at intervals along a second direction.

[0081] In some embodiments, please refer to Figure 2 and Figure 4 The ratio of the first characteristic dimension of the first bottom electrode 201 to the second characteristic dimension of the second bottom electrode 301 is the first ratio value, which is greater than or equal to 10:3, and can specifically be 10:3, 4:1, 5:1, 10:1, 20:1, etc.

[0082] In some embodiments, the first feature size is greater than or equal to 100 μm; the second feature size is less than or equal to 30 μm. In the embodiments of this application, the first feature size can be 100 μm to 200 μm; the second feature size can be 3 μm to 30 μm. For example, the first feature size can be 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, etc.; the second feature size can be 3 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc.

[0083] In some embodiments, the thickness of both the first bottom electrode 201 and the second bottom electrode 301 can be 100 nm.

[0084] In some embodiments, the first bottom electrode 201 and the second bottom electrode 301 are provided with electrode lead-out terminals 400 at their opposite ends along the first direction, which are used to electrically connect with the peripheral driving circuit.

[0085] Next, please refer to Figure 2 , Figure 4 and Figure 13 In step S103, a first resistive switching layer 202 and a second resistive switching layer 302 are formed on the first bottom electrode 201 and the second bottom electrode 301, respectively.

[0086] In some embodiments, the specific steps for forming the first resistive switching layer 202 and the second resistive switching layer 302 include: transferring the substrate 100 on which the first bottom electrode 201 and the second bottom electrode 301 are formed from the magnetron sputtering chamber to the plasma enhanced-atomic layer deposition (PEALD) chamber, and depositing a resistive switching material on the first bottom electrode 201 and the second bottom electrode 301 using the PEALD process to form a resistive switching material layer. The resistive switching material can be a wide bandgap semiconductor such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN); wherein the portion of the resistive switching material layer located on the first bottom electrode 201 constitutes the first resistive switching layer 202, and the portion of the resistive switching material layer located on the second bottom electrode 301 constitutes the second resistive switching layer 302.

[0087] For example, the specific steps for depositing resistive switching materials include: first, evacuating the PEALD chamber to control the chamber vacuum level to ≤1×10⁻⁶. -3After maintaining this vacuum level for 30 minutes, the PEALD deposition process was initiated. During PEALD deposition, trimethylaluminum (TMA) with a purity ≥99.999% was used as the aluminum source precursor, and ammonia (NH3) with a purity ≥99.999% was used as the nitrogen source precursor. The radio frequency power was controlled at 100W~300W during deposition, specifically 100W, 150W, 200W, 250W, and 300W. Based on the above precursor and radio frequency power parameters, a cycle mode of "introducing TMA—purge—introducing NH3—purge" was adopted to deposit aluminum nitride layer by layer.

[0088] The specific parameters for the above deposition process are set as follows: TMA precursor flow rate is 10 sccm~50 sccm, TMA precursor pulse time is 0.1s~0.3s, and purging time after pulse is 5s~15s (e.g., 10s); NH3 reactive gas flow rate is 50 sccm~200 sccm, NH3 reactive gas pulse time is 1s~3s, and purging time after pulse is 10s~20s (e.g., 15s); the TMA to NH3 flow rate ratio is controlled at 1:4~1:10, the reaction chamber temperature is 250℃~350℃ (e.g., 300℃), and the deposition cycle number is controlled at 150~200 times.

[0089] In some embodiments, after AlN deposition is completed, the chamber heating device is turned off, allowing the substrate 100 to cool naturally to room temperature with the chamber. Since AlN is prepared by PEALD deposition, no additional annealing treatment is required, which effectively simplifies the overall preparation process and reduces process complexity and manufacturing costs.

[0090] In some embodiments, aluminum nitride is (100) preferred orientation; the overall band gap of aluminum nitride ranges from 5.7 eV to 6.1 eV. The Al content in AlN is controlled within the range of 51% to 55%.

[0091] In some embodiments, the thickness of the first resistive switching layer 202 and the second resistive switching layer 302 can be 10nm to 30nm, specifically, for example, 10nm, 15nm, 20nm, 25nm, 30nm, etc. In this embodiment, the thickness of the first resistive switching layer 202 and the second resistive switching layer 302 is 22nm.

[0092] Finally, please refer to Figure 2 , Figure 4 and Figure 14Step S104 is executed to form at least one first top electrode 203 having a third feature size and at least one second top electrode 303 having a fourth feature size, wherein the third feature size is larger than the fourth feature size; wherein the first top electrode 203 is located on the first resistive switching layer 202, and on the plane of the substrate 100, the vertical projections of the first bottom electrode 201 and the first top electrode 203 at least partially overlap to form one or more first overlapping regions a, wherein the first bottom electrode 201, the first resistive switching layer 202 and the first top electrode 203 located in the same first overlapping region a constitute an erasable memristor 200; the second top electrode 303 is located on the second resistive switching layer 302, and on the plane of the substrate 100, the vertical projections of the second bottom electrode 301 and the second top electrode 303 at least partially overlap to form one or more second overlapping regions b, wherein the second bottom electrode 301, the second resistive switching layer 302 and the second top electrode 303 located in the same second overlapping region b constitute an erasable memristor 300.

[0093] It should be noted that in this embodiment, the top electrode is formed using the same process as the bottom electrode. Its specific fabrication process, material selection, parameter settings, and operational requirements are all consistent with the bottom electrode's fabrication process, and will not be repeated here. It should also be noted that in this embodiment, the first bottom electrode 201 and the second bottom electrode 301 are formed simultaneously, and the first top electrode 203 and the second top electrode 303 are formed simultaneously. This simplifies the overall fabrication process of the semiconductor structure.

[0094] In some embodiments, there are multiple first top electrodes 203 and multiple second top electrodes 303; both the first top electrodes 203 and the second top electrodes 303 are strip-shaped. The multiple first top electrodes 203 and the multiple second top electrodes 303 extend along a second direction and are arranged at intervals along a first direction.

[0095] In some embodiments, please refer to Figure 2 and Figure 4 The ratio of the third characteristic dimension of the first top electrode 203 to the fourth characteristic dimension of the second top electrode 303 is the second ratio, which is greater than or equal to 10:3, and can be 10:3, 4:1, 5:1, 10:1, 20:1, etc.

[0096] In some embodiments, the third feature size is greater than or equal to 100 μm; the fourth feature size is less than or equal to 30 μm. In the embodiments of this application, the third feature size can be 100 μm to 200 μm; the fourth feature size can be 3 μm to 30 μm. For example, the third feature size can be 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, etc.; the fourth feature size can be 3 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc.

[0097] In some embodiments, the first feature size is equal to the third feature size, and the second feature size is equal to the fourth feature size. For example, the first and third feature sizes are both 100 μm, and the second and fourth feature sizes are both 30 μm.

[0098] In some embodiments, the thickness of both the first top electrode 203 and the second top electrode 303 can be 100 nm.

[0099] In some embodiments, the first top electrode 203 and the second top electrode 303 are provided with electrode lead-out terminals 400 at their opposite ends along the first direction, which are used to electrically connect with the peripheral driving circuit.

[0100] In some embodiments, the prepared semiconductor structure can be post-processed and tested: the prepared semiconductor structure is cleaned with deionized water, dried with nitrogen, and its electrical performance is tested using a probe station and a semiconductor parameter analyzer to complete device screening.

[0101] Tests have shown that the erasable memristor 200 has a low-resistance state and a high-resistance state, and the ratio of its high-resistance turn-off resistance to its low-resistance on-resistance state is greater than or equal to 10. 5 The low-resistivity state is maintained for a duration of 10 seconds or more. 4 The erasable memristor 200 achieves more than 80 stable non-volatile cycle switching.

[0102] Erasable memristor 200 in current-limiting current (I CC Under a unidirectional positive voltage of 1mA, the Forming (initialization), Set (write), and Reset processes can be implemented. The non-erasable memristor 300 does not require a Forming process; under a unidirectional positive voltage, only the Set process can be implemented, and the Reset process cannot be implemented.

[0103] In summary, this application provides a monolithically integrated erasable / non-erasable AlN-based memristor array structure and its fabrication method, enabling the integrated fabrication of erasable and non-erasable memristors on a single chip, simplifying process steps and improving integration density. Furthermore, this fabrication method is compatible with CMOS processes, which helps simplify peripheral circuit design, improves integration density, and is suitable for high-density storage, neuromorphic computing, and other scenarios.

[0104] It should be noted that the semiconductor structure embodiments and the semiconductor structure fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the semiconductor structure provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the semiconductor structure provided in the embodiments of this application is not limited to the semiconductor structure fabrication method provided in the embodiments of this application, and any semiconductor structure prepared by the fabrication method that can form the semiconductor structure provided in the embodiments of this application is within the scope of protection of this application.

[0105] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: The substrate has erasable device regions and non-erasable device regions; At least one first bottom electrode with a first feature size is located in the erasable device region, and at least one second bottom electrode with a second feature size is located in the non-erasable device region, wherein the first feature size is larger than the second feature size; The first resistive switching layer and the second resistive switching layer are respectively located on the first bottom electrode and the second bottom electrode; At least one first top electrode having a third characteristic dimension and at least one second top electrode having a fourth characteristic dimension, wherein the third characteristic dimension is larger than the fourth characteristic dimension; wherein, The first top electrode is located on the first resistive switching layer, and on the plane where the substrate is located, the vertical projection of the first bottom electrode and the vertical projection of the first top electrode at least partially overlap to form one or more first overlapping regions. The first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping region constitute an erasable memristor. The second top electrode is located on the second resistive switching layer, and on the plane where the substrate is located, the vertical projection of the second bottom electrode and the vertical projection of the second top electrode at least partially overlap to form one or more second overlapping regions. The second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping region constitute a non-erasable memristor.

2. The semiconductor structure according to claim 1, characterized in that, The first feature size and the third feature size are both greater than or equal to 100 μm; the second feature size and the fourth feature size are both less than or equal to 30 μm.

3. The semiconductor structure according to claim 2, characterized in that, The first feature size is equal to the third feature size, and the second feature size is equal to the fourth feature size.

4. The semiconductor structure according to claim 1, characterized in that, The erasable device area includes at least one erasable device array. Each erasable device array includes four first bottom electrodes and four first top electrodes. The four first bottom electrodes and the four first top electrodes partially overlap on the vertical projection of the substrate, forming sixteen first overlapping regions. The sixteen first overlapping regions are arranged in rows along a first direction and in columns along a second direction, forming a 4-row, 4-column rectangular array. The first direction and the second direction are perpendicular to the thickness direction of the substrate, and the first direction is perpendicular to the second direction. The non-erasable device region includes at least one non-erasable device array, and one of the non-erasable device arrays includes one second bottom electrode and ten second top electrodes; One second bottom electrode and ten second top electrodes overlap in the vertical projection portion on the plane where the substrate is located, forming ten second overlapping regions; the ten second overlapping regions are arranged in rows along the first direction and in columns along the second direction, forming a rectangular array of 1 row and 10 columns.

5. The semiconductor structure according to claim 1, characterized in that, The materials of the first resistive switching layer and the second resistive switching layer are aluminum nitride, gallium nitride, or aluminum gallium nitride.

6. The semiconductor structure according to claim 5, characterized in that, Both the first resistive switching layer and the second resistive switching layer are made of aluminum nitride; the aluminum content in the aluminum nitride is in the range of 51% to 55%.

7. The semiconductor structure according to claim 5, characterized in that, The first resistive switching layer and the second resistive switching layer are both made of aluminum nitride; the thickness of the aluminum nitride is 10nm~30nm.

8. The semiconductor structure according to claim 1, characterized in that, The erasable memristor has a low-resistance state and a high-resistance state, wherein the ratio of the turn-off resistance of the high-resistance state to the on-resistance resistance of the low-resistance state is greater than or equal to 10. 5 The duration of the low-resistivity state is greater than or equal to 10. 4 s.

9. The semiconductor structure according to claim 1, characterized in that, Both the erasable memristor and the non-erasable memristor are unipolar memristors; the erasable memristor and the non-erasable memristor share a single-voltage drive circuit.

10. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate having an erasable device region and a non-erasable device region; At least one first bottom electrode having a first feature size and at least one second bottom electrode having a second feature size are formed on the substrate; wherein the first bottom electrode is located in an erasable device region and the second bottom electrode is located in the non-erasable device region; the first feature size is larger than the second feature size; A first resistive switching layer and a second resistive switching layer are formed on the first bottom electrode and the second bottom electrode, respectively; At least one first top electrode having a third characteristic dimension and at least one second top electrode having a fourth characteristic dimension are formed, wherein the third characteristic dimension is larger than the fourth characteristic dimension; wherein, The first top electrode is located on the first resistive switching layer, and on the plane where the substrate is located, the vertical projection of the first bottom electrode and the vertical projection of the first top electrode at least partially overlap to form one or more first overlapping regions. The first bottom electrode, the first resistive switching layer and the first top electrode located in the same first overlapping region constitute an erasable memristor. The second top electrode is located on the second resistive switching layer, and on the plane where the substrate is located, the vertical projection of the second bottom electrode and the vertical projection of the second top electrode at least partially overlap to form one or more second overlapping regions. The second bottom electrode, the second resistive switching layer and the second top electrode located in the same second overlapping region constitute a non-erasable memristor.

Images