Method and apparatus for monitoring defects in semiconductor structures
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-13
- Publication Date
- 2026-07-07
AI Technical Summary
Existing semiconductor capacitor defect monitoring equipment is ineffective at detecting residues at the bottom of capacitors, resulting in low detection efficiency and easy damage to capacitors, thus increasing detection costs.
By obtaining the overlay accuracy offset between the capacitor pillar and the support structure and the etching opening size of the etched film, their correspondence is determined. Based on this relationship, structural defects in the semiconductor manufacturing process are monitored, the overlay accuracy offset is controlled within the set range, the etching opening size is ensured to be normal, and the bottom residue is removed.
It improves the effectiveness of semiconductor structural defect monitoring, reduces product waste, avoids residues caused by etching solution not being able to enter the bottom of the capacitor, and enhances the reliability and efficiency of detection.
Smart Images
Figure CN115472519B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for monitoring semiconductor structural defects. Background Technology
[0002] DRAM (Dynamic Random Access Memory) capacitors have a high aspect ratio during manufacturing, making them prone to leaving residues on the bottom that can affect their final storage performance. However, due to the high aspect ratio and the fact that these residues are typically located on the bottom of the capacitor, existing defect monitoring equipment struggles to detect them directly. Currently, screening is primarily done through electrical testing or polishing followed by optical microscopy, which is inefficient and can easily cause irreversible damage to the capacitor, increasing testing costs.
[0003] Therefore, the current defect monitoring effect of capacitors is poor. Summary of the Invention
[0004] This disclosure provides a method, apparatus, storage medium, and electronic device for monitoring semiconductor structural defects, thereby improving the defect monitoring effect of capacitors.
[0005] In a first aspect, one embodiment of this disclosure provides a method for monitoring defects in a semiconductor structure, the semiconductor structure including a front layer structure and a current layer structure; wherein the front layer structure includes at least: a capacitor pillar, a support structure for supporting the capacitor pillar, and a dielectric film layer; the current layer structure includes at least: an etched film layer; the method includes:
[0006] Obtain the overlay accuracy offset between the capacitor column and the support structure;
[0007] Obtain the size of the etching opening in the etched film;
[0008] Determine the correspondence between the overlay accuracy offset and the etching opening size;
[0009] Structural defects in the semiconductor manufacturing process are monitored based on the correspondence relationship.
[0010] In one optional embodiment of this disclosure, obtaining the overlay accuracy offset between the capacitor post and the support structure includes at least:
[0011] Obtain the first optical scan image of the front layer structure;
[0012] In the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the support structure and the capacitor pillar.
[0013] In one optional embodiment of this disclosure, the support structure includes a first support structure located at the top of the capacitor post and a second support structure located on the body of the capacitor post; in the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the support structure and the capacitor post, including:
[0014] In the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the second support structure and the capacitor column.
[0015] In an optional embodiment of this disclosure, in the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the support structure and the capacitor pillar, including:
[0016] In the first optical scanning image, the horizontal overlay accuracy offset along the axial direction of the support structure and the longitudinal overlay accuracy offset along the radial direction of the support structure are calculated based on the first structural parameters of the support structure and the capacitor column, respectively.
[0017] The horizontal and vertical overprinting accuracy offsets are weighted and calculated to obtain the overprinting accuracy offset.
[0018] In one optional embodiment of this disclosure, the first weighting coefficient of the horizontal overlay accuracy offset is greater than the second weighting coefficient of the vertical overlay accuracy offset.
[0019] In an optional embodiment of this disclosure, in the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the support structure and the capacitor pillar, including:
[0020] In the first optical scanning image, the horizontal overlay accuracy offset along the axial direction of the support structure is calculated based on the first structural parameters of the support structure and the capacitor column, respectively.
[0021] The horizontal overlay accuracy offset is determined as the overlay accuracy offset.
[0022] In one optional embodiment of this disclosure, obtaining the etching opening size of the etched film layer includes:
[0023] Obtain the second optical scan image of the front layer structure;
[0024] In the second optical scan image, the size of the etching opening in the etched film is calculated based on the second structural parameters of the etched film.
[0025] In one optional embodiment of this disclosure, there are multiple quantities of film stress, overlay accuracy offset, and etching opening size. Determining the correspondence between the overlay accuracy offset and the etching opening size includes:
[0026] Data fitting is performed on multiple overlay accuracy offsets and multiple etching opening sizes to generate a fitting function for the overlay accuracy offsets and etching opening sizes, thus obtaining the corresponding relationship.
[0027] In one optional embodiment of this disclosure, the offset of each etching precision and the size of each etching opening are determined repeatedly for the same location point in the semiconductor structure.
[0028] In one optional embodiment of this disclosure, monitoring structural defects in the semiconductor manufacturing process based on correspondence includes:
[0029] Obtain the current overlay accuracy offset of the current structure of the semiconductor under test;
[0030] The target etching opening size range corresponding to the semiconductor under test is determined based on the correspondence and the current overlay accuracy offset.
[0031] Defect monitoring of the semiconductor under test is performed based on the size range of the target etching opening.
[0032] In an optional embodiment of this disclosure, the semiconductor structure defect monitoring method further includes:
[0033] If the overlay accuracy offset is greater than the preset offset, the film stress of the dielectric film layer will be reduced.
[0034] Re-determine the current etching opening size of the semiconductor under test until the current etching opening size is within the range of the target etching opening size.
[0035] In an optional embodiment of this disclosure, the semiconductor structure defect monitoring method further includes:
[0036] If the overlay accuracy offset is greater than the preset offset, the film stress at the edge of the dielectric film will be reduced.
[0037] In one optional embodiment of this disclosure, determining the target etching opening size range corresponding to the semiconductor under test based on the correspondence and the current overlay accuracy offset includes:
[0038] If the overlay accuracy offset is greater than the preset offset, the opening size of the etched film is increased to obtain the target etch opening size range; wherein, the target etch opening size range is determined based on the overlay accuracy offset and the corresponding relationship.
[0039] In one optional embodiment of this disclosure, the semiconductor structure is a capacitor.
[0040] Secondly, one embodiment of this disclosure provides a semiconductor structure defect monitoring device, wherein the semiconductor structure includes a front layer structure and a current layer structure; wherein the front layer structure includes at least: a capacitor pillar, a support structure for supporting the capacitor pillar, and a dielectric film layer; the current layer structure includes at least: an etched film layer; the semiconductor structure defect monitoring device includes:
[0041] The first acquisition module is used to acquire the overlay accuracy offset between the capacitor column and the support structure.
[0042] The second acquisition module is used to acquire the size of the etching opening in the etched film layer;
[0043] The determination module is used to determine the correspondence between the overlay accuracy offset and the etching opening size;
[0044] The monitoring module is used to monitor structural defects in the semiconductor manufacturing process based on the correspondence relationship.
[0045] The technical solution disclosed herein has the following beneficial effects:
[0046] This embodiment first obtains the overlay accuracy offset between the capacitor pillar and the support structure, and the etching opening size of the etched film layer. Then, it determines the correspondence between the overlay accuracy offset and the etching opening size. In actual manufacturing, it is only necessary to monitor structural defects in the semiconductor manufacturing process based on this correspondence. That is, by controlling the overlay accuracy offset of the previous structure within a set range, the etching opening size of the current structure is ensured to be within the normal range. This allows the etching solution to flow normally into the bottom of the capacitor through the etching opening of the film layer to remove bottom residues to the greatest extent. In other words, by controlling the earlier process nodes, the structural defects of subsequent process nodes are reduced without causing excessive product waste. This solves the technical problem of poor defect monitoring effect in capacitors and achieves the technical effect of improving the monitoring effect of semiconductor structural defects.
[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0049] Figure 1(a) shows a schematic diagram of the capacitor fabrication process in a semiconductor structural defect monitoring method according to this exemplary embodiment;
[0050] Figure 1(b) shows a schematic diagram of the capacitor fabrication process in a semiconductor structural defect monitoring method according to this exemplary embodiment;
[0051] Figure 1(c) shows a schematic diagram of the capacitor fabrication process in a semiconductor structural defect monitoring method according to this exemplary embodiment;
[0052] Figure 1(d) shows a schematic diagram of the capacitor fabrication process in a semiconductor structural defect monitoring method according to this exemplary embodiment;
[0053] Figure 2 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0054] Figure 3 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0055] Figure 4 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0056] Figure 5 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0057] Figure 6 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0058] Figure 7 This diagram illustrates a flowchart of a semiconductor structure defect monitoring method according to this exemplary embodiment;
[0059] Figure 8 This diagram illustrates the film curvature test data at different process nodes in a semiconductor structural defect monitoring method according to this exemplary embodiment.
[0060] Figure 9 This diagram illustrates a film stress test in a semiconductor structure defect monitoring method according to an exemplary embodiment of the present invention.
[0061] Figure 10 This diagram illustrates a film stress test in a semiconductor structure defect monitoring method according to an exemplary embodiment of the present invention.
[0062] Figure 11 This diagram illustrates a semiconductor structural defect monitoring device according to an exemplary embodiment. Detailed Implementation
[0063] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0064] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0065] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0066] In related technologies, DRAM capacitors have a high aspect ratio during manufacturing, which easily leads to residues at the bottom of the capacitor, affecting its final storage performance. However, due to the high aspect ratio and the fact that these residues are typically located at the bottom, existing defect monitoring equipment struggles to detect them directly. Currently, screening is mainly done through electrical testing or polishing followed by optical microscopy, which is inefficient and can easily cause irreversible damage to the capacitor, increasing testing costs. Therefore, current defect monitoring for capacitors is ineffective.
[0067] In view of the above problems, this disclosure provides a semiconductor structural defect monitoring method to improve the defect monitoring effect of capacitors. The following is a brief introduction to the application environment of the semiconductor structural defect monitoring method provided in this disclosure:
[0068] The manufacturing process of capacitors is generally fixed. A complete process includes multiple process nodes, such as deposition, etching, and cleaning. Please refer to [link to relevant documentation]. Figure 1(a)-Figure 1(d) Figure 1 is a schematic diagram of the capacitor fabrication process, including a substrate 110, various film layers 120, capacitor pillars 130, capacitor leads 140, and a support structure 150 for the capacitor pillars 130. During the fabrication process, as shown in Figure 1(a), the capacitor structure is completed after one deposition. However, due to the influence of the evaporation rate and concentration during the deposition process, the stress on the surface of the film layer 120 is uneven. Once the stress is different, the capacitor pillars 130 and the support structure 150 used to fix the capacitor pillars 130 will tilt. As shown in Figure 1(b), the etching process node is performed based on Figure 1(a). Photoresist 160 is spin-coated onto the surface of the film layer 120 using a masking method. However, the capacitor pillars 130 are tilted, which causes the photoresist 160 used to etch the substrate 110 to not flow completely along the gaps between the capacitor pillars 130 and the gaps between the capacitor pillars 130 and the support structure 150 to flow to the bottom. This results in the situation shown in Figure 1(c) and Figure 1(d) where the substrate 110 cannot be completely cleaned. Meanwhile, please refer to Figure 1(c). Due to the influence of the overlay accuracy during the etching process, the size of the etching opening 170 of the film layer 120 is not the same. If the opening 170 is small, the same situation as above will also affect the removal of the photoresist from the substrate 110.
[0069] Semiconductor structures include front-layer structures and current-layer structures; wherein, the front-layer structure refers to the site structure for depositing capacitor pillars and supporting structures for supporting capacitor pillars, and includes at least: capacitor pillars, supporting structures for supporting capacitor pillars and dielectric film layers; the current-layer structure refers to the site structure for obtaining etched film layers based on the front-layer structure, and the current-layer structure includes at least etched film layers.
[0070] The following example illustrates how the semiconductor structural defect monitoring method is applied to the control device to monitor process defects in capacitor manufacturing. It should be noted that the control device can be a management terminal or a user terminal for on-site personnel. The control device can be a server, computer, personal laptop, wearable device, etc. This disclosure does not impose any limitations and the appropriate device can be selected based on the specific circumstances. Please refer to... Figure 2 The semiconductor structural defect monitoring method provided in this disclosure includes the following steps 201-204:
[0071] Step 201: Obtain the overlay accuracy offset between the capacitor column and the support structure.
[0072] The overlay accuracy offset refers to the deviation between the actual position of the capacitor post and the support structure after overlay and the preset position. This deviation can easily lead to an excessively small etching opening or an uneven film surface. In this embodiment, the overlay accuracy offset can be characterized by a first offset of the capacitor post relative to a first preset position, or by a second offset of the support structure relative to a second preset position. It should be explained that the first preset position refers to the pre-set target position of the etched capacitor post, and the second preset position refers to the pre-set target position of the etched support structure.
[0073] Step 202: Obtain the size of the etching opening in the etched film.
[0074] Etching openings in a film layer refer to channels created on the surface of the film layer using photoresist or similar materials to introduce etching solutions. During the etching process, the etching solution flows through these openings into the bottom of the capacitor to remove any residue. If the etching openings are too small, the etching effect will be directly affected.
[0075] Step 203: Determine the correspondence between the overlay accuracy offset and the etching opening size.
[0076] The overlay accuracy offset directly affects the size of the etching opening. A smaller overlay accuracy offset results in a larger etching opening and better removal of bottom residues; conversely, a larger overlay accuracy offset results in a smaller etching opening, leading to poorer removal of bottom residues and more severe structural defects. It should be noted that the embodiments in this disclosure determine the correspondence between the overlay accuracy offset and the etching opening size based on the same batch or model of semiconductors; that is, for the same batch or model of semiconductors, the specific numerical value of the etching opening size corresponding to the overlay accuracy offset.
[0077] Step 204: Monitor structural defects in the semiconductor manufacturing process based on the correspondence relationship.
[0078] Once this correspondence is obtained, for the semiconductor to be monitored, it is only necessary to adjust the overlay accuracy offset in the previous layer structure to the set standard range to ensure that the size of the opening in the current layer structure is within the normal range. This allows the etching solution to flow normally into the bottom of the capacitor through the etching opening of the film layer in the subsequent etching process, so as to remove the bottom residue to the greatest extent. This achieves the purpose of controlling structural defects in subsequent nodes by controlling the previous node.
[0079] This embodiment first obtains the overlay accuracy offset between the capacitor pillar and the support structure, and the etching opening size of the etched film layer. Then, it determines the correspondence between the overlay accuracy offset and the etching opening size. In actual manufacturing, it is only necessary to monitor structural defects in the semiconductor manufacturing process based on this correspondence. That is, by controlling the overlay accuracy offset of the previous structure within a set range, the etching opening size of the current structure is ensured to be within the normal range. This allows the etching solution to flow normally into the bottom of the capacitor through the etching opening of the film layer to remove bottom residues to the greatest extent. In other words, by controlling the earlier process nodes, the structural defects of subsequent process nodes are reduced without causing excessive product waste. This solves the technical problem of poor defect monitoring effect in capacitors and achieves the technical effect of improving the monitoring effect of semiconductor structural defects.
[0080] Please see Figure 3 In an optional embodiment of this disclosure, step 201, obtaining the overlay accuracy offset between the capacitor post and the support structure, includes at least the following steps 301-302:
[0081] Step 301: Obtain the first optical scan image of the front layer structure.
[0082] The first optical scan image can be an image containing parameters of the support structure and capacitor pillars in the front layer structure, obtained through any optical detection method, such as electron microscopy.
[0083] Step 302: In the first optical scan image, calculate the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor column.
[0084] First structural parameters of the support structure and capacitor column are extracted from the first optical scan image, such as length, width, thickness, and the angle between them relative to the horizontal position or the angle between the capacitor column and the support structure. Then, the overlay accuracy offset of the support structure relative to the first preset position or the overlay accuracy offset of the capacitor column relative to the second preset position in the front layer structure is calculated based on the first structural parameters.
[0085] In this embodiment, the first optical scan image of the front layer structure is obtained first. Then, based on the first structural parameters of the support structure and the capacitor pillar in the first optical scan image, the overlay accuracy offset is calculated. That is, the overlay accuracy offset is determined by the optical scan image of the actual semiconductor structure. Combined with actual production, the reliability is higher.
[0086] In an optional embodiment of this disclosure, multiple support structures are generally provided to improve the stability of the capacitor post, such as a first support structure located at the top of the capacitor post and a second support structure located on the body of the capacitor post; step 302 above, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor post in the first optical scan image, includes the following steps:
[0087] In the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the second support structure and the capacitor column.
[0088] In semiconductor structures, as depth increases—that is, as the etching solution extends from the semiconductor surface to the bottom—its fluidity decreases. The internal structure of the semiconductor has a greater impact than the surface structure. Therefore, in this embodiment, the overlay accuracy offset is calculated based on the second support structure located at the capacitor pillar body and the first structural parameters of the capacitor pillar. As long as this overlay accuracy offset ensures that the obtained etching opening size is within a preset etching opening size, the etching opening size corresponding to the first support structure will also necessarily be within the range of that preset etching opening size. Therefore, this embodiment does not require calculating a corresponding overlay accuracy offset for each support structure; it only needs to calculate one overlay accuracy offset based on the second support structure located at the capacitor pillar body to achieve the purpose of controlling the etching opening size. This significantly reduces the computational load while ensuring control of the etching opening size, further improving the monitoring efficiency of the semiconductor structure defect monitoring method of this embodiment.
[0089] Please see Figure 4 In an optional embodiment of this disclosure, step 302, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor pillar in the first optical scan image, includes the following steps 401-402:
[0090] Step 401: In the first optical scan image, calculate the horizontal overlay accuracy offset along the axial direction of the support structure and the longitudinal overlay accuracy offset along the radial direction of the support structure based on the first structural parameters of the support structure and the capacitor column.
[0091] Step 402: Perform a weighted calculation on the horizontal overlay accuracy offset and the vertical overlay accuracy offset to obtain the overlay accuracy offset.
[0092] Overlay refers to the process of transferring a mask pattern on a photomask onto a wafer through a series of steps such as alignment and exposure. Due to errors in alignment accuracy, exposure dosage, and mask position offset, a certain overlay error is inevitable. This overlay error includes horizontal overlay accuracy offset along the semiconductor surface extension direction and vertical overlay accuracy offset along the semiconductor structure depth direction. Finally, different weighting coefficients are assigned to the horizontal and vertical overlay accuracy offsets according to the actual situation. The resulting overlay accuracy offset is closer to the actual value and has higher reliability. This can further improve the reliability of the correspondence between the overlay accuracy offset and the film etching opening, thereby improving the monitoring effect of the semiconductor structure defect monitoring method of this embodiment.
[0093] In one optional embodiment of this disclosure, the first weighting coefficient of the horizontal overlay accuracy offset is greater than the second weighting coefficient of the vertical overlay accuracy offset.
[0094] Extensive experiments have shown that the horizontal overlay accuracy offset has a greater impact on the size of the etching opening and the stress of the film layer than the vertical overlay accuracy offset. Therefore, in this embodiment, the first weighting coefficient of the horizontal overlay accuracy offset is greater than the second weighting coefficient of the vertical overlay accuracy offset, thereby increasing the proportion of the horizontal overlay accuracy offset in the overlay accuracy offset, minimizing the possibility of structural defects, and thus improving the monitoring effect of the semiconductor structural defect monitoring method in this embodiment.
[0095] Please see Figure 5 In an optional embodiment of this disclosure, step 302, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor pillar in the first optical scan image, includes the following steps 501-502:
[0096] Step 501: In the first optical scan image, calculate the horizontal overlay accuracy offset along the axial direction of the support structure based on the first structural parameters of the support structure and the capacitor column.
[0097] Step 502: Determine the horizontal overlay accuracy offset as the overlay accuracy offset.
[0098] Numerous experiments have shown that the horizontal overlay accuracy offset has a greater impact on the size of the etching opening and the stress of the film layer than the vertical overlay. Therefore, in this embodiment, the horizontal overlay accuracy offset is directly used as the overlay accuracy offset for monitoring structural defects, eliminating the need to calculate the bus overlay accuracy offset. This greatly reduces the amount of testing and calculation, minimizes the possibility of structural defects, and improves the monitoring effect of the semiconductor structural defect monitoring method of this embodiment.
[0099] Please see Figure 6In an optional embodiment of this disclosure, step 202, obtaining the etching opening size of the etched film layer, includes the following steps 601-602:
[0100] Step 601: Obtain the second optical scan image of the front layer structure.
[0101] Step 602: In the second optical scan image, calculate the etching opening size of the etching film based on the second structural parameters of the etching film.
[0102] The second structural parameters of the etched film layer, such as length, width, thickness, and via size, are extracted from the second optical scan image. Then, the overlay accuracy offset of the etched opening size of the etched film layer in the previous structure relative to the second preset position is calculated based on the second structural parameters.
[0103] In this embodiment, the first optical scan image of the front layer structure is obtained first. Then, based on the first structural parameters of the support structure and the capacitor pillar in the first optical scan image, the overlay accuracy offset is calculated. That is, the overlay accuracy offset is determined by the optical scan image of the actual semiconductor structure. Combined with actual production, the reliability is higher.
[0104] In an optional embodiment of this disclosure, there are multiple film stresses, overlay accuracy offsets, and etching opening sizes. Step 203, determining the correspondence between the overlay accuracy offsets and etching opening sizes, includes the following steps:
[0105] Data fitting is performed on multiple overlay accuracy offsets and multiple etching opening sizes to generate a fitting function for the overlay accuracy offsets and etching opening sizes, thus obtaining the corresponding relationship.
[0106] This embodiment of the invention uses data fitting based on the overlay accuracy offset and the size of multiple etching openings corresponding to multiple semiconductor structures of the same batch or model to obtain a fitting function for the overlay accuracy offset and the size of the etching opening. This fitting function is used as the representation of the correspondence. In subsequent monitoring, only the overlay accuracy offset obtained from the previous layer needs to be input into the fitting function to output the size of the etching opening that can be used for normal etching, which is more convenient, simple, and more efficient.
[0107] In one optional embodiment of this disclosure, the overlay accuracy offset and the size of each etching opening are determined repeatedly for the same location point in the semiconductor structure. Repeated testing for the same location point or repeated testing for the same location point of multiple semiconductor structures of the same batch or model makes the obtained multiple overlay accuracy offsets and etching opening sizes more reliable, thereby improving the reliability of the semiconductor structure defect monitoring method of this disclosure embodiment.
[0108] Please see Figure 7In an optional embodiment of this disclosure, step 204, monitoring structural defects in the semiconductor manufacturing process based on the correspondence relationship, includes the following steps 701-703:
[0109] Step 701: Obtain the current overlay accuracy offset of the current structure of the semiconductor under test;
[0110] Step 702: Determine the target etching opening size range corresponding to the semiconductor under test based on the correspondence and the current overlay accuracy offset;
[0111] Step 703: Monitor defects in the semiconductor under test based on the target etching opening size range.
[0112] In actual production, it is only necessary to obtain the current overlay accuracy offset of the current structure, and then determine the target etching opening size range corresponding to the current overlay accuracy offset according to the corresponding relationship. In the current process node, it is only necessary to adjust the opening size of the dielectric film layer to the range of the target etching opening size to ensure that the etching solution can smoothly enter the bottom during the etching process, remove the residue, and thus reduce the structural defects of the semiconductor.
[0113] In one optional embodiment of this disclosure, the above method for defect monitoring of the semiconductor under test based on the target etching opening size range may include the following two cases:
[0114] In the first case, if the overlay accuracy offset is greater than the preset offset, the film stress of the dielectric film is reduced, and the current etching opening size of the semiconductor under test is re-determined until the current etching opening size is within the range of the target etching opening size.
[0115] Stress is one of the important factors affecting the flatness of the film layer. The flatness of the film layer directly affects the overlay accuracy offset between the capacitor pillar and the support structure used to support the capacitor pillar. The greater the stress value, the greater the overlay accuracy offset, and the more serious the defects caused. Therefore, in the embodiments of this disclosure, the film stress of the dielectric film layer is reduced when the overlay accuracy offset is greater than the preset offset. By adjusting the film stress, the etching opening size of the dielectric film layer is increased until the opening size of the dielectric film layer is adjusted to within the range of the target etching opening size. This ensures that the etching solution can smoothly enter the bottom during the etching process, remove the residue, and thus reduce the structural defects of the semiconductor.
[0116] In the second case, if the overlay accuracy offset is greater than the preset offset, the opening size of the etched film is increased to obtain the target etch opening size range.
[0117] The target etching opening size range is determined based on the overlay accuracy offset and its corresponding relationship. This embodiment directly increases the opening size of the etched film layer, making the actual opening larger than a pre-set opening size. In other words, by increasing the etching opening in the current structure, structural defects caused by overlay in the previous layer are adjusted, preventing the etching solution from failing to penetrate to the bottom during the next process node, thus avoiding the continued formation of residues.
[0118] In one optional embodiment of this disclosure, reducing the film stress of the dielectric film in the above steps can directly reduce the film stress at the edge of the dielectric film.
[0119] Please see Figure 8 This is a set of stress test data from actual production. The horizontal axis represents different process nodes, and the vertical axis represents the curvature of the wafer film surface. A value greater than 0 indicates downward curvature (e.g., ...). Figure 9 The compressive stress in 9(a) and 9(b) is less than 0, indicating upward bending. Figure 10 The tensile stresses in 10(a) and 10(b) are considered. Figures 8-10 It is clearly shown that the stress mainly occurs at the edge of the dielectric film. Therefore, the embodiments of this disclosure directly adjust the size of the etching opening by adjusting the film stress at the edge, which is more convenient than adjusting the entire film.
[0120] In one optional embodiment of this disclosure, the semiconductor structure is a capacitor. By monitoring the structural defects in the capacitor manufacturing process through the correspondence between the overlay accuracy offset and the size of the etching opening in the capacitor, waste of the product can be avoided.
[0121] Please see Figure 11 This disclosure provides a semiconductor structure defect monitoring device 1100, wherein the semiconductor structure includes a front layer structure and a current layer structure; wherein the front layer structure includes at least: capacitor pillars, a support structure for supporting the capacitor pillars, and a dielectric film layer; the current layer structure includes at least: an etched film layer; the semiconductor structure defect monitoring device 1100 includes:
[0122] The first acquisition module 1110 is used to acquire the overlay accuracy offset between the capacitor column and the support structure.
[0123] The second acquisition module 1120 is used to acquire the size of the etching opening in the etched film layer;
[0124] The determination module 1130 is used to determine the correspondence between the overlay accuracy offset and the etching opening size;
[0125] The monitoring module 1140 is used to monitor structural defects in the semiconductor manufacturing process based on the correspondence relationship.
[0126] The semiconductor structural defect monitoring device 1100 first acquires the overlay accuracy offset between the capacitor pillar and the support structure through the first acquisition module 1110, and acquires the etching opening size of the etch film layer through the second acquisition module 1120. Then, the determination module 1130 determines the correspondence between the overlay accuracy offset and the etching opening size. In the actual process, the monitoring module 1140 only needs to monitor the structural defects in the semiconductor production process based on this correspondence. That is, by controlling the overlay accuracy offset of the previous structure within a set range, the etching opening size of the current structure is ensured to be within the normal range. This allows the etching solution to flow normally into the bottom of the capacitor through the etching opening of the film layer to remove the bottom residue to the greatest extent. In other words, by controlling the earlier process nodes, the device aims to reduce the structural defects of the subsequent process nodes, while also avoiding excessive product waste. This solves the technical problem of poor defect monitoring effect of capacitors and achieves the technical effect of improving the monitoring effect of semiconductor structural defects.
[0127] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to exemplary embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.
[0128] Those skilled in the art will understand that various aspects of this disclosure can be implemented as systems, methods, or program products. Therefore, various aspects of this disclosure can be embodied in entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.” Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0129] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A method for monitoring semiconductor structural defects, characterized in that, The semiconductor structure includes a front layer structure and a current layer structure; wherein, the front layer structure includes at least: capacitor pillars, a support structure for supporting the capacitor pillars, and a dielectric film layer; the current layer structure includes at least: an etched film layer; the method includes: Obtain the overlay accuracy offset between the capacitor post and the support structure; Obtain the size of the etching opening in the etched film; Determine the correspondence between the overlay accuracy offset and the etching opening size; Based on the aforementioned correspondence, structural defects in the semiconductor manufacturing process are monitored.
2. The semiconductor structural defect monitoring method according to claim 1, characterized in that, The step of obtaining the overlay accuracy offset between the capacitor post and the support structure includes at least: Obtain the first optical scan image of the front layer structure; In the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the support structure and the capacitor column.
3. The semiconductor structural defect monitoring method according to claim 2, characterized in that, The support structure includes a first support structure located at the top of the capacitor column and a second support structure located on the body of the capacitor column; In the first optical scan image, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor post includes: In the first optical scan image, the overlay accuracy offset is calculated based on the first structural parameters of the second support structure and the capacitor column.
4. The semiconductor structural defect monitoring method according to claim 3, characterized in that, In the first optical scan image, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor post includes: In the first optical scanning image, the horizontal overlay accuracy offset along the axial direction of the support structure and the longitudinal overlay accuracy offset along the radial direction of the support structure are calculated based on the first structural parameters of the support structure and the capacitor column, respectively. The horizontal overprinting accuracy offset and the vertical overprinting accuracy offset are weighted and calculated to obtain the overprinting accuracy offset.
5. The semiconductor structural defect monitoring method according to claim 4, characterized in that, The first weighting coefficient of the horizontal overlay accuracy offset is greater than the second weighting coefficient of the vertical overlay accuracy offset.
6. The semiconductor structural defect monitoring method according to claim 3, characterized in that, In the first optical scan image, calculating the overlay accuracy offset based on the first structural parameters of the support structure and the capacitor post includes: In the first optical scanning image, the horizontal overlay accuracy offset along the axial direction of the support structure is calculated based on the first structural parameters of the support structure and the capacitor column, respectively. The horizontal overlay accuracy offset is determined as the overlay accuracy offset.
7. The semiconductor structural defect monitoring method according to claim 1, characterized in that, Obtaining the etching opening size of the etched film layer includes: Obtain the second optical scan image of the front layer structure; In the second optical scan image, the size of the etching opening in the etched film is calculated based on the second structural parameters of the etched film.
8. The semiconductor structural defect monitoring method according to claim 1, characterized in that, The number of the dielectric film stress, the number of the overlay accuracy offset, and the number of the etching opening sizes are all multiple. Determining the correspondence between the overlay accuracy offset and the etching opening size includes: Data fitting is performed on multiple overlay accuracy offsets and multiple etching opening sizes to generate a fitting function for the overlay accuracy offsets and etching opening sizes, thereby obtaining the corresponding relationship.
9. The semiconductor structure defect monitoring method according to claim 8, characterized in that, The overlay accuracy offset and the etching opening size are all determined repeatedly for the same location point in the semiconductor structure.
10. The semiconductor structure defect monitoring method according to claim 1, characterized in that, The monitoring of structural defects in the semiconductor manufacturing process based on the aforementioned correspondence includes: Obtain the current overlay accuracy offset of the current structure of the semiconductor under test; The target etching opening size range corresponding to the semiconductor under test is determined based on the correspondence and the current overlay accuracy offset. Defect monitoring is performed on the semiconductor under test based on the target etching opening size range.
11. The semiconductor structure defect monitoring method according to claim 10, characterized in that, The method further includes: If the overlay accuracy offset is greater than the preset offset, then the film stress of the dielectric film layer is reduced. The current etching aperture size of the semiconductor under test is redefined until the current etching aperture size is within the range of the target etching aperture size.
12. The semiconductor structure defect monitoring method according to claim 11, characterized in that, The method further includes: If the overlay accuracy offset is greater than the preset offset, then the film stress at the edge of the dielectric film layer is reduced.
13. The semiconductor structural defect monitoring method according to claim 10, characterized in that, The step of determining the target etching opening size range corresponding to the semiconductor under test based on the correspondence and the current overlay accuracy offset includes: If the overlay accuracy offset is greater than the preset offset, the opening size of the etched film is increased to obtain the target etch opening size range; wherein, the target etch opening size range is determined based on the overlay accuracy offset and the corresponding relationship.
14. The semiconductor structural defect monitoring method according to claim 1, characterized in that, The semiconductor structure is a capacitor.
15. A semiconductor structural defect monitoring device, characterized in that, The semiconductor structure includes a front layer structure and a current layer structure; wherein, the front layer structure includes at least: capacitor pillars, a support structure for supporting the capacitor pillars, and a dielectric film layer; the current layer structure includes at least: an etched film layer; the device includes: The first acquisition module is used to acquire the overlay accuracy offset between the capacitor column and the support structure; The second acquisition module is used to acquire the size of the etching opening in the etched film layer; A determining module is used to determine the correspondence between the overlay accuracy offset and the etching opening size; The monitoring module is used to monitor structural defects in the semiconductor manufacturing process based on the aforementioned correspondence.