Method of improving ac performance of pmos devices
By leaving a low-k dielectric layer in the PMOS device, the parasitic capacitance problem between the source/drain and the gate is solved, thus improving the AC performance of the device.
Patent Information
- Application Number
- CN202310166357.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-24
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2043-02-24
AI Technical Summary
In PMOS devices, the SiN between the source/drain terminals and the gate is difficult to remove, resulting in a large parasitic capacitance that affects AC performance.
By leaving a low-k dielectric layer in the gap between the source/drain and the gate, the dielectric constant is reduced. Excess sidewalls are removed using wet etching technology to form a low-k dielectric layer to reduce parasitic capacitance.
This reduces the parasitic capacitance between the source/drain terminals and the gate, thus improving the AC performance of the PMOS device.
Smart Images
Figure CN116130419B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, in particular to a method for improving AC performance of PMOS device. BACKGROUND
[0002] In the design and production process of a device, parasitic capacitance will inevitably be introduced, which will affect the AC performance of the device. With the continuous shrinking of the technology node, the defects and effects caused by parasitic capacitance are becoming more and more obvious. How to effectively control and reduce parasitic capacitance is a problem that cannot be ignored and needs to be solved urgently.
[0003] After the growth of SiGe at the source and drain end of the PMOS in the traditional process, the hard mask plate SiN will be removed. Due to the structural characteristics, SiN cannot be easily removed between the source and drain end and the gate, and will not be removed. As we all know, the dielectric constant of SIN is relatively high ~ 8C2 / (N*M2), which will inevitably generate a large parasitic capacitance between the source and drain end and the gate.
[0004] To solve the above problems, a new method for improving the AC performance of PMOS device is needed. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving the AC performance of PMOS device, which is used to solve the problem that after the growth of SiGe at the source and drain end of the PMOS in the prior art, the hard mask plate SiN will be removed. Due to the structural characteristics, SiN cannot be easily removed between the source and drain end and the gate, which will generate a large parasitic capacitance between the source and drain end and the gate.
[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a method for improving the AC performance of PMOS device, comprising:
[0007] Step one, providing a substrate, an STI is formed on the substrate to define an active area, a PMOS structure and an NMOS structure are formed on the active area, a protective layer is formed on the area outside the PMOS structure on the substrate, the PMOS structure is composed of a gate structure and epitaxial layers located on both sides of the gate structure, the gate structure is composed of a stack and first and second side walls located on the sidewalls of the stack in sequence;
[0008] Step two, etching the second side wall so that the second side wall outside the gap between the epitaxial layer and the gate structure is removed, and then etching to remove the remaining second side wall;
[0009] Step three, forming a low-K dielectric layer on the substrate to cover the remaining stack, first side wall and epitaxial layer;
[0010] Step four, etching the low K dielectric layer so that the epitaxial layer and the low K dielectric layer in the gap between the gate structure remain.
[0011] Preferably, the substrate in step one is a silicon substrate.
[0012] Preferably, the material of the first side wall in step one is SiCN.
[0013] Preferably, the material of the second side wall in step one is silicon nitride.
[0014] Preferably, the stack in step one is composed of a first gate oxide layer, a high K dielectric layer, a spacer layer, a gate polysilicon layer, a gate nitride layer, and a second gate oxide layer from bottom to top.
[0015] Preferably, the etching method in step two is wet etching.
[0016] Preferably, the K value of the low K dielectric layer in step three is < 8C2 / (N*M2).
[0017] Preferably, the thickness of the low K dielectric layer in step three is at least more than half of the gap width.
[0018] Preferably, the thickness of the low K dielectric layer in step three is 50 to 80 angstroms.
[0019] Preferably, the etching method in step four is wet etching.
[0020] As mentioned above, the method for improving the AC performance of PMOS devices of the present application has the following beneficial effects:
[0021] The present application keeps the low K dielectric layer in the gap between the source / drain and the gate in a residual manner. Since the dielectric constant of the low K dielectric layer material is low, the parasitic capacitance between the source / drain and the gate is reduced, and the AC performance of the PMOS device is improved. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 The figure shows the process flow diagram of the present application;
[0023] Figure 2 The figure shows the PMOS structure diagram of the present application;
[0024] Figure 3 The figure shows the first etching of the second side wall of the present application;
[0025] Figure 4 The figure shows the second etching of the second side wall of the present application;
[0026] Figure 5 The figure shows the formation of the low K dielectric layer of the present application;
[0027] Figure 6 The figure shows the schematic diagram of the etching low-K dielectric layer of the present application. DETAILED DESCRIPTION
[0028] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure, or can be learned by practice of the application. The advantages and benefits of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. Various modifications and changes can be made thereto without departing from the spirit and scope of the application.
[0029] Referring to Figure 1 The present application provides a method for improving the AC performance of PMOS device, comprising:
[0030] Step one, referring to Figure 2 A substrate 101 is provided, and an STI 102 is formed on the substrate 101 to define an active region. A PMOS structure and an NMOS structure are formed on the active region. A protective layer is formed on the substrate 101 outside the PMOS structure. The PMOS structure is composed of a gate structure and epitaxial layers 106 on both sides of the gate structure. The gate structure is composed of a stack 103 and first and second sidewalls on the sidewalls of the stack 103 in sequence. The epitaxial layer 106 formed in the PMOS is usually a germanium-silicon epitaxial layer 106, and the epitaxial layer formed in the NMOS is a pure silicon epitaxial layer.
[0031] The PMOS structure and the NMOS structure are formed on the active region. Before the second sidewall 105 in the PMOS structure is formed, a protective layer material layer covering the PMOS structure and the NMOS structure is formed on the substrate 101. Then a photoresist layer covering the protective layer material layer is formed. The photoresist layer is opened in the area of the PMOS structure. Then the exposed protective layer material layer is etched by a dry etching method to form the second sidewall 105 on the first sidewall 104. The protective layer on the substrate 101 outside the PMOS structure is retained.
[0032] In the embodiment of the present application, the substrate 101 in step one is a silicon substrate 101.
[0033] In the embodiment of the present application, the material of the first sidewall 104 in step one is SiCN. Carbon-doped silicon nitride is weaker in etching degree than silicon nitride in wet cleaning.
[0034] In the embodiment of the present application, the material of the second sidewall 105 in step one is silicon nitride.
[0035] In the embodiment of the present application, the stack 103 in step one is composed of, from bottom to top, a first gate oxide layer, a high-K dielectric layer, an isolation layer, a gate polysilicon layer, a gate nitride layer, and a second gate oxide layer. The materials of the first and second gate oxide layers can be silicon dioxide, the material of the high-K dielectric layer can be HfO, and the material of the gate nitride layer can be silicon nitride.
[0036] In step two, the second side wall 105 is etched so that the second side wall 105 outside the gap between the epitaxial layer 106 and the gate structure (between the source-drain region and the gate structure) is removed, forming a structure as shown in FIG. 2B. Figure 3 Then the remaining second side wall 105 is etched away, forming a structure as shown in FIG. 2C. Figure 4
[0037] In the embodiment of the present application, the etching method in step two is wet etching. After most of the second side wall 105 is removed by wet etching, the second side wall 105 still remains in the gap, affecting the parasitic capacitance between the source-drain end and the gate structure.
[0038] In step three, a low-K dielectric layer 107 is formed on the substrate 101 to cover the remaining stack 103, the first side wall 104, and the epitaxial layer 106, forming a structure as shown in FIG. 2D. Figure 5
[0039] In the embodiment of the present application, the material of the low-K dielectric layer 107 in step three has a K value < 8C2 / (N*M2), for example, SiCOH, which can be formed by a chemical vapor deposition method.
[0040] In the embodiment of the present application, to ensure that the gap is filled with the low-K dielectric layer 107, the thickness of the low-K dielectric layer 107 in step three is at least more than half the width of the gap.
[0041] In the embodiment of the present application, the thickness of the low-K dielectric layer 107 in step three is 50 to 80 angstroms.
[0042] In step four, the low-K dielectric layer 107 is etched so that the low-K dielectric layer 107 in the gap between the epitaxial layer 106 and the gate structure is retained, forming a structure as shown in FIG. 2E. Figure 6
[0043] In the embodiment of the present application, the etching method in step four is wet etching.
[0044] It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application, rather than the number, shape, and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of type, number, and proportion, and the layout pattern of the components can be more complex.
[0045] In summary, the low-K dielectric layer is reserved in the gap between the source-drain and the gate in a residual manner, the dielectric constant of the low-K dielectric layer is low, the parasitic capacitance between the source-drain and the gate is reduced, and the AC performance of the PMOS device is improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0046] The above embodiments only illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of improving AC performance of a PMOS device, characterized by, At least comprising: Step one, providing a substrate, the substrate is formed with STI to define active area, the active area is formed with PMOS structure and NMOS structure, the substrate is formed with protective layer outside the PMOS structure, the PMOS structure is composed of gate structure and epitaxial layer on both sides of the gate structure, the gate structure is composed of stack and first and second side walls on the sidewall of the stack in turn; Step two, etching the second side wall, so that the second side wall outside the gap between the epitaxial layer and the gate structure is removed, and then etching to remove the second side wall in the gap; Step three, forming low-K dielectric layer on the substrate covering the remaining stack, the first side wall and the epitaxial layer; Step four, etching the low-K dielectric layer, so that the low-K dielectric layer between the epitaxial layer sidewall and the first side wall is reserved.
2. The method of boosting PMOS device AC performance of claim 1, wherein: The substrate in step one is silicon substrate.
3. The method of boosting PMOS device AC performance of claim 1, wherein: The material of the first side wall in step one is SiCN.
4. The method of boosting PMOS device AC performance of claim 1, wherein: The material of the second side wall in step one is silicon nitride.
5. The method for boosting PMOS device AC performance of claim 1, wherein: The stack in step one is composed of first gate oxide layer, high-K dielectric layer, isolation layer, gate polysilicon layer, gate nitride layer and second gate oxide layer from bottom to top.
6. The method for boosting PMOS device AC performance of claim 1, wherein: The etching method in step two is wet etching.
7. The method for boosting PMOS device AC performance of claim 1, wherein: The K value of the low-K dielectric layer in step three is less than 8.
8. The method for boosting PMOS device AC performance of claim 1, wherein: The thickness of the low-K dielectric layer in step three is at least half of the gap width.
9. The method of boosting PMOS device AC performance of claim 8, wherein: The thickness of the low-K dielectric layer in step three is 50 to 80 angstrom.
10. The method for boosting PMOS device AC performance of claim 1, wherein: The etching method in step four is wet etching.
Citation Information
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