Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a hole region, a peripheral wiring region and a regular wiring region, and comprises a substrate, a first wire, a second wire and a first wire layer and a second wire layer formed on the substrate in sequence. The first wire comprises a first straight segment in the regular wiring region and a first curved segment in the peripheral wiring region, and the first curved segment is located in the first wire layer. The second wire comprises a second straight segment in the regular wiring region and a second curved segment in the peripheral wiring region, the second straight segment is the same as the extension direction of the first straight segment, and the second curved segment is located in the second wire layer. The orthographic projection of the shielding layer on the substrate at least partially overlaps the orthographic projection of the first curved segment on the substrate, and / or the orthographic projection of the shielding layer on the substrate at least partially overlaps the orthographic projection of the second curved segment on the substrate. The display panel provided by the application reduces the signal interference between the wires near the hole region of the display panel.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the performance requirements for display devices are getting higher and higher. In the punch screen technology, a hole region is formed in a display region by punching, and a photosensitive module is integrated below the hole region to achieve good work of the photosensitive module. However, the formation of the hole region makes part of the wiring need to bypass the hole region to form a winding, and the spacing between the windings is small, so that signal interference easily occurs between adjacent windings, thereby seriously affecting the display effect. SUMMARY

[0003] Embodiments of the present application provide a display panel and a display device, which reduce signal interference between wirings near a hole region of the display panel and improve the display quality of the display panel.

[0004] Embodiments of the first aspect of the present application provide a display panel, which comprises a hole region, a peripheral wiring region and a regular wiring region, the peripheral wiring region surrounds at least part of the hole region, and the regular wiring region surrounds at least part of the peripheral wiring region, and the display panel comprises:

[0005] a substrate;

[0006] a first wiring layer formed on the substrate;

[0007] a shielding layer formed on a side of the first wiring layer away from the substrate;

[0008] a second wiring layer formed on a side of the shielding layer away from the first wiring layer;

[0009] a first wiring comprising a first straight segment located in the regular wiring region and a first curved segment located in the peripheral wiring region, and the first curved segment is located in the first wiring layer;

[0010] a second wiring comprising a second straight segment located in the regular wiring region and a second curved segment located in the peripheral wiring region, and the second straight segment is in the same extension direction as the first straight segment, and the second curved segment is located in the second wiring layer;

[0011] wherein a normal projection of the shielding layer on the substrate at least partially overlaps a normal projection of the first curved segment on the substrate, and / or a normal projection of the shielding layer on the substrate at least partially overlaps a normal projection of the second curved segment on the substrate.

[0012] Embodiments of the second aspect of the present application also provide a display device comprising the display panel provided by the first aspect of the present application.

[0013] The display panel provided in the present application has a shielding layer arranged between the first wiring layer and the second wiring layer, the orthographic projection of the shielding layer on the substrate at least partially overlaps the orthographic projection of the first curve segment on the substrate, and / or the orthographic projection of the shielding layer on the substrate at least partially overlaps the orthographic projection of the second curve segment on the substrate, so that the coupling capacitance between the first curve segment and the second curve segment can be effectively reduced, the signal interference between the first curve segment and the second curve segment can be reduced, the phenomenon of display unevenness near the hole region can be improved, and the display quality can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0015] Figure 1 is a top view of a display panel provided by the prior art;

[0016] Figure 2 is a top view of a display panel provided by the present application;

[0017] Figure 3 is Figure 2 is a sectional view along Q-Q' in

[0018] Figure 4 is Figure 2 is a sectional view along N-N' in

[0019] Figure 5 is Figure 2 is another sectional view along Q-Q' in

[0020] Figure 6 is a top view of another display panel provided by the present application;

[0021] Figure 7 is Figure 6 is a sectional view along P-P' in

[0022] Figure 8 is Figure 6 is another sectional view along P-P' in

[0023] Figure 9 is Figure 2 is a partial enlarged view of the E area of

[0024] Figure 10 is Figure 2 is another partial enlarged view of the E area of

[0025] Figure 11 is Figure 6 is an enlarged view of region F in FIG. 1;

[0026] Figure 12 is Figure 11 is a sectional view along M-M' in FIG. 1;

[0027] Figure 13 is Figure 6 is another enlarged view of region F in FIG. 1;

[0028] Figure 14 is Figure 13 is a sectional view along A-A' in FIG. 1;

[0029] Figure 15 is a schematic view of a film layer structure of a display panel provided by an embodiment of the present application;

[0030] Figure 16 is a top view of another display panel provided by an embodiment of the present application;

[0031] Figure 17 is a schematic view of a film layer structure of another display panel provided by an embodiment of the present application;

[0032] Figure 18 is a schematic view of a film layer structure of another display panel provided by an embodiment of the present application;

[0033] Figure 19 is a top view of a display device provided by an embodiment of the present application.

[0034] In the drawings:

[0035] 1 - display panel; A1 - hole region; A2 - peripheral wiring region; A3 - general wiring region; 10 - substrate; 101 - inorganic material barrier layer; 102 - flexible organic material layer; 11 - first wiring layer; 111 - first wiring; 1111 - first straight segment; 1112 - first curved segment; 12 - shielding layer; 121 - first shielding unit; 122 - second shielding unit; 13 - second wiring layer; 131 - second wiring; 1311 - second straight segment; 1312 - second curved segment; 14 - insulating layer; 15 - planarization layer; 16 - first gap; 17 - second gap; 18 - semiconductor layer; 19 - first insulating layer; 20 - gate metal layer; 21 - second insulating layer; 22 - capacitor metal layer; 23 - third insulating layer; 24 - source-drain metal layer; 25 - fourth insulating layer; 26 - auxiliary metal layer; 27 - third wiring; 271 - straight portion; 272 - winding portion. DETAILED DESCRIPTION

[0036] Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application can be practiced without some or all of these specific details. The description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

[0037] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Also, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article or device. Without more limitations, the elements defined by the statement "comprise" do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0038] The inventors have found, as shown in Figure 1 , in the punched screen, the hole area HL of the display panel 01 is integrated with a photosensitive module, and the photosensitive module needs a good light transmission environment to realize high-quality work, so the hole area HL is required to have high light transmission rate to ensure the working performance of the photosensitive module. In the display panel 01, the traces 02 extending along the first direction x or the second direction y, when passing through the hole area HL, need to bypass the hole area HL to form a winding line, so as to avoid the traces 02 directly penetrating through the hole area HL and affecting the light transmission rate of the hole area HL. Since the hole area HL occupies a certain space, the distance between the adjacent winding lines becomes smaller after the traces 02 bypass the hole area HL, so that signal interference between the adjacent winding lines is prone to occur, thereby seriously affecting the display effect. Based on the research on the above problems, the inventors provide a display panel and a display device to reduce the signal interference between the traces near the hole area of the display panel, thereby improving the display quality of the display panel.

[0039] In order to better understand the present application, the following will be combined with Figures 2 to 19 The display panel and the display device according to the embodiments of the present application are described in detail.

[0040] Please refer to Figures 2 to 4 , Figure 2 is a top view of a display panel provided by the embodiments of the present application; Figure 3 is Figure 2 a cross-sectional view along Q-Q' in FIG. 1; Figure 4 is Figure 2 a cross-sectional view along N-N' in FIG. 1.

[0041] The display panel 1 provided by the embodiment of the present application includes a hole region A1, a peripheral wiring region A2 surrounding at least part of the hole region A1, and a regular wiring region A3 surrounding at least part of the peripheral wiring region A2. The display panel 1 includes a substrate 10, a first wiring layer 11, a shielding layer 12, a second wiring layer 13, a first wiring 111, and a second wiring 131. The first wiring layer 11 is formed on the substrate 10. The shielding layer 12 is formed on a side of the first wiring layer 11 away from the substrate 10. The second wiring layer 13 is formed on a side of the shielding layer 12 away from the first wiring layer 11. The first wiring 111 includes a first straight segment 1111 located in the regular wiring region A3 and a first curved segment 1112 located in the peripheral wiring region A2, and the first curved segment 1112 is located in the first wiring layer 11. The second wiring 131 includes a second straight segment 1311 located in the regular wiring region A3 and a second curved segment 1312 located in the peripheral wiring region A2, and the second straight segment 1311 is in the same extension direction as the first straight segment 1111, and the second curved segment 1312 is located in the second wiring layer 13. The orthogonal projection of the shielding layer 12 on the substrate 10 at least partially overlaps the orthogonal projection of the first curved segment 1112 on the substrate 10, and / or the orthogonal projection of the shielding layer 12 on the substrate 10 at least partially overlaps the orthogonal projection of the second curved segment 1312 on the substrate 10.

[0042] In the display panel 1 provided by the present application, the hole region A1 can provide sufficient light for the photosensitive element to ensure normal operation of the photosensitive element. The hole region A1 is not provided with a sub-pixel, and the wiring extending along the row and column direction needs to bypass the hole region A1 in the hole region A1, so that the part of the wiring near the hole region A1 extends along a curve, avoiding the wiring passing through the hole region A1 to affect the light transmittance of the hole region A1. Therefore, the peripheral wiring region A2 is formed around the hole region A1 to accommodate the wiring that bends to avoid the hole region A1. The regular wiring region A3 is formed around the peripheral wiring region A2, and the remaining wiring that is not affected by the hole region A1 and the part of the wiring extending along a straight line are located in the regular wiring region A3.

[0043] The wiring includes but is not limited to a data line, a scan line, a reset signal line, a power signal line, etc., which are not particularly limited by the present application.

[0044] The substrate 10 can be transparent, translucent or opaque, which is not particularly limited by the present application. The substrate 10 can be a flexible substrate 10, and the specific material can be polyimide. Figure 5 As shown in FIG. 1, the substrate 10 can be a composite substrate 10 including a flexible organic material layer 102 and an inorganic material barrier layer 101 arranged in layers.

[0045] In the above embodiments, the insulating layer 14 is arranged between the first wiring layer 11 and the shielding layer 12 and between the shielding layer 12 and the second wiring layer 13, so as to insulate the adjacent layers. The second wiring layer 13 can further be provided with a planarization layer 15, which is not particularly limited in the present application.

[0046] The display panel 1 provided in the present application comprises a substrate 10 and a first wiring layer 11, a shielding layer 12 and a second wiring layer 13 formed on the substrate 10, which are sequentially stacked in a direction away from the substrate 10. The display panel 1 further comprises a first wiring 111 and a second wiring 131. The first wiring 111 comprises a first straight segment 1111 and a first curved segment 1112, the first curved segment 1112 is arranged around the hole region A1 and is located in the peripheral wiring region A2 and in the first wiring layer 11; the first straight segment 1111 is located in the regular wiring region A3. The second wiring 131 comprises a second straight segment 1311 and a second curved segment 1312, the second curved segment 1312 is arranged around the hole region A1 and is located in the peripheral wiring region A2 and in the second wiring layer 13; the second straight segment 1311 is located in the regular wiring region A3 and has the same extension direction as the first straight segment 1111. The first straight segment 1111 and the first curved segment 1112 can be located in the same layer or different layers, and the second straight segment 1311 and the second curved segment 1312 can be located in the same layer or different layers, which are not particularly limited in the present application. The first wiring 111 and the second wiring 131 can be the same kind of signal lines, the first curved segment 1112 in the first wiring 111 and the second curved segment 1312 in the second wiring 131 are arranged in different wiring layers, and the first curved segment 1112 and the second curved segment 1312 are stacked in a direction away from the substrate 10, so as to arrange the wiring in double-layer wiring layers (i.e. the first wiring layer 11 and the second wiring layer 13), which improves the wiring space, so as to reduce the distance between the adjacent first curved segments 1112 or the adjacent second curved segments 1312, thereby reducing the width of the peripheral wiring region A2.

[0047] In the display panel 1 provided in the present application, the shielding layer 12 is arranged between the first wiring layer 11 and the second wiring layer 13, the orthogonal projection of the shielding layer 12 on the substrate 10 at least partially overlaps the orthogonal projection of the first curved segment 1112 on the substrate 10, and / or the orthogonal projection of the shielding layer 12 on the substrate 10 at least partially overlaps the orthogonal projection of the second curved segment 1312 on the substrate 10, so as to effectively reduce the coupling capacitance between the first curved segment 1112 and the second curved segment 1312, thereby reducing the signal interference between the first curved segment 1112 and the second curved segment 1312, so as to improve the display unevenness near the hole region A1 and improve the display quality.

[0048] In a feasible embodiment, as shown in Figure 5 the present application, the first curved segment 1112 and the second curved segment 1312 are arranged in different layers.Figure 5 yes Figure 2 Another cross-sectional view along Q-Q'. At least a portion of the first curve segment 1112 corresponds one-to-one with the second curve segment 1312, and in each pair of one-to-one corresponding first curve segment 1112 and second curve segment 1312, the orthographic projection of the second curve segment 1312 on the first trace layer 11 is located within the first curve segment 1112.

[0049] In the above embodiment, at least a portion of the first curve segment 1112 and the second curve segment 1312 are configured to correspond one-to-one, and the orthogonal projection of the second curve segment 1312 on the first wiring layer 11 is located within the first curve segment 1112, thereby effectively utilizing the space of the peripheral wiring area A2. At the same time, the first curve segment 1112 in the first wiring layer 11 and the second curve segment 1312 in the second wiring layer 13 are configured to correspond one-to-one and be directly opposite each other in the direction perpendicular to the substrate 10, thereby allowing the first curve segment 1112 and the second curve segment 1312 to occupy a narrower peripheral wiring area A2, which helps to achieve the narrowing design of the peripheral wiring area A2.

[0050] In another feasible implementation, such as Figure 6 and Figure 7 As shown, Figure 6 This is a top view of another display panel provided in an embodiment of this application; Figure 7 yes Figure 6 A cross-sectional view along line P-P'. Adjacent first curve segments 1112 have a first gap 16, and adjacent second curve segments 1312 have a second gap 17. The orthographic projection of the first curve segment 1112 onto the second routing layer 13 covers the second gap 17, and the orthographic projection of the second curve segment 1312 onto the first routing layer 11 covers the first gap 16. That is, the first curve segment 1112 within the first routing layer 11 and the second curve segment 1312 within the second routing layer 13 are staggered. This arrangement increases the oblique distance between the first curve segment 1112 and the second curve segment 1312, thereby reducing mutual interference.

[0051] In one feasible implementation, the signals in different first curve segments 1112 are the same, the signals in different second curve segments 1312 are the same, and the signals in the first curve segment 1112 and the second curve segment 1312 are different.

[0052] In the above embodiment, the signals in different first curve segments 1112 are set to be the same, so that the mutual interference between adjacent first curve segments 1112 can be reduced without adding the shielding layer 12 between the adjacent first curve segments 1112; the signals in different second curve segments 1312 are set to be the same, so that the mutual interference between adjacent second curve segments 1312 can be reduced without adding the shielding layer 12 between the adjacent second curve segments 1312. The signals in the first curve segments 1112 and the second curve segments 1312 are different, and the shielding layer 12 is arranged between the first curve segments 1112 and the second curve segments 1312, so that the mutual interference between the different signals in the first curve segments 1112 and the second curve segments 1312 can be reduced.

[0053] In a feasible embodiment, the first wiring layer 11 can be arranged in the display panel 1 as a whole layer, that is, part of the first wiring layer 11 is arranged in the peripheral wiring area A2 and part of the first wiring layer 11 is arranged in the regular wiring area A3; or the first wiring layer 11 can be arranged only in the peripheral wiring area A2, which is not particularly limited in the present application. Meanwhile, the second wiring layer 13 can be arranged in the display panel 1 as a whole layer, that is, part of the second wiring layer 13 is arranged in the peripheral wiring area A2 and part of the second wiring layer 13 is arranged in the regular wiring area A3; or the second wiring layer 13 can be arranged only in the peripheral wiring area A2, which is not particularly limited in the present application.

[0054] In a feasible embodiment, as shown in FIG. 13, Figure 8 Figure 8 is Figure 6 another cross-sectional view along P-P' in FIG. 12; the shielding layer 12 is arranged in the peripheral wiring area A2, and the shielding layer 12 is arranged as a whole layer and continuously.

[0055] In the above embodiment, the shielding layer 12 is arranged as a whole layer and continuously in the peripheral wiring area A2, so that the manufacturing process can be simplified, and the oblique capacitive coupling between the first curve segments 1112 and the second curve segments 1312 can be reduced, and the signal shielding effect between the first curve segments 1112 and the second curve segments 1312 can be further improved.

[0056] In a feasible embodiment, as shown in FIG. 13, Figure 7 the shielding layer 12 is patterned, so that the area of the shielding layer 12 which is not covered by the second curve segments 1312 of the second wiring layer 13 forms a hollow part, so that the problem that the part of the shielding layer 12 which is not covered by the second curve segments 1312 is easy to reflect light when the display panel 1 is in a dark state can be improved, and the use experience of the display panel 1 can be further improved.

[0057] ​In an embodiment, the patterned shielding layer 12 comprises a plurality of first shielding units 121 arranged around the hole region A1 and sequentially nested, the first shielding units 121 are in a closed ring structure, and the orthographic projection of each first shielding unit 121 on the first wiring layer 11 covers two first curve segments 1112 located on both sides of the hole region A1. Alternatively, as shown in Figure 9 , Figure 9 is Figure 2 a partial enlarged view of the E region, the orthographic projection of each first shielding unit 121 on the second wiring layer 13 covers two second curve segments 1312 located on both sides of the hole region A1.

[0058] In the above embodiment, by patterning the shielding layer 12, the functional part of the shielding function is retained, and the non-functional part is removed. While ensuring the shielding effect of the first curve segment 1112 and the second curve segment 1312, the reflection of light is reduced, and the problem of brightening around the hole region A1 caused by the reflection of the shielding layer 12 is improved. After the shielding layer 12 is designed as a plurality of first shielding units 121, the first shielding unit 121 can correspond to two first curve segments 1112 or two second curve segments 1312 in the circumferential direction of the hole region A1, and the first shielding unit 121 is in a circular ring shape, which is convenient for preparation.

[0059] In another embodiment, the patterned shielding layer 12 comprises a plurality of second shielding units 122 arranged around the hole region A1 and sequentially arranged, the orthographic projection of each second shielding unit 122 on the first wiring layer 11 coincides with a first curve segment 1112, or as shown in Figure 10 , Figure 10 is Figure 2 another partial enlarged view of the E region, the orthographic projection of each second shielding unit 122 on the second wiring layer 13 coincides with a second curve segment 1312

[0060] In the above embodiment, the shielding layer 12 is designed as a plurality of second shielding units 122, and the second shielding unit 122 corresponds to a first curve segment 1112 or a second curve segment 1312, that is, the second shielding unit 122 is less than half a circle around the hole region A1, so that the area of the non-functional part between adjacent second shielding units 122 in the direction around the hole region A1 can be reduced, thereby further reducing the reflection of external light.

[0061] In an embodiment, the shielding layer 12 is connected to the fixed potential end.

[0062] In the present application, the fixed potential end refers to an electrical potential end where the electrical signal does not change, that is, the electrical signal is fixed.

[0063] Connecting the shielding layer 12 to the fixed potential end can effectively reduce the capacitive coupling between the adjacent first curved segment 1112 and the second curved segment 1312.

[0064] In an implementation, the fixed potential end includes one of a power voltage signal end and a reference voltage signal end.

[0065] There are various signal lines in the display panel 1, and each signal line is connected to a set potential end. The signal line in which the electrical signal does not change includes a power signal line, a reference voltage signal line, and the like. The potential end connected to the above two signal lines is a power voltage signal end and a reference voltage signal end. Therefore, the power voltage signal end and the reference voltage signal end can be reused as the fixed potential end electrically connected to the shielding layer 12, so as to simplify the wiring in the display panel 1.

[0066] In an implementation, the first straight segment 1111 and the second straight segment 1311 extend along the first direction x, and the first straight segment 1111 and the second straight segment 1311 are arranged in the same layer. The first curved segment 1112 and the second curved segment 1312 are arranged in different layers. As shown in Figure 11 and Figure 12 , Figure 11 is Figure 6 an enlarged view of the F region in Figure 12 is Figure 11 a sectional view along M-M' in Figure 13 and Figure 14 , Figure 13 is Figure 6 another enlarged view of the F region in Figure 14 is Figure 13 a sectional view along A-A' in

[0067] In the above embodiments, the first trace 111 and the second trace 131 share two layers of trace layers, i.e., the first trace layer 11 and the second trace layer 13. Specifically, the first straight segment 1111 is arranged in the same layer as one of the first curved segment 1112 and the second curved segment 1312. For example, the first straight segment 1111 is arranged in the same layer as the first curved segment 1112, and the first straight segment 1111 and the first curved segment 1112 can be directly connected (i.e., the first straight segment 1111 and the first curved segment 1112 are integrated). In this case, the second straight segment 1311 and the second curved segment 1312 are arranged in different layers, and the second straight segment 1311 and the second curved segment 1312 are connected by a via. Alternatively, the first straight segment 1111 is arranged in the same layer as the second curved segment 1312, i.e., the second straight segment 1311 and the second curved segment 1312 are arranged in the same layer and can be directly connected (i.e., the second straight segment 1311 and the second curved segment 1312 are integrated). In this case, the first straight segment 1111 and the first curved segment 1112 are arranged in different layers, and the first straight segment 1111 and the first curved segment 1112 are connected by a via.

[0068] Alternatively, the first straight segment 1111 and the first curved segment 1112 are arranged in different layers, and the first straight segment 1111 and the second curved segment 1312 are arranged in different layers. In this embodiment, the first straight segment 1111 and the second straight segment 1311 are arranged in the same layer, and the first straight segment 1111, the first curved segment 1112, and the second curved segment 1312 are arranged in different layers. In addition, the second straight segment 1311, the first curved segment 1112, and the second curved segment 1312 are arranged in different layers. In this case, the first trace 111 and the second trace 131 share three layers of trace layers. The first straight segment 1111 and the first curved segment 1112 are arranged in different layers and connected by a via, and the second straight segment 1311 and the second curved segment 1312 are arranged in different layers and connected by a via. The specific arrangement manner can be set according to the specific film layer structure of the display panel 1, which is not particularly limited in the present application.

[0069] In the display panel 1 provided in the present application, the specific arrangement manner of the first trace 111 and the second trace 131 can include the following manners:

[0070] In a feasible embodiment, as shown in Figure 15 , Figure 15 FIG. 1 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present application. The display panel 1 includes, in sequence from the direction away from the substrate 10, a semiconductor layer 18, a first insulating layer 19, a gate metal layer 20, a second insulating layer 21, a capacitor metal layer 22, a third insulating layer 23, and a source-drain metal layer 24.

[0071] The display panel 1 includes a driving circuit, which comprises transistors, capacitors, and other components. A semiconductor layer 18 forms the source, drain, and channel regions of the transistors. A gate metal layer 20 forms the gate of the transistor and the lower electrode of the capacitor; the gate metal layer 20 can be made of molybdenum. A first insulating layer 19 isolates the semiconductor layer 18 from the gate metal layer 20; the first insulating layer 19 can be made of silicon oxide. A capacitor metal layer 22 forms the upper electrode of the capacitor; the capacitor metal layer 22 can be made of molybdenum. A second insulating layer 21 isolates the capacitor metal layer 22 from the gate metal layer 20; the second insulating layer 21 can be made of silicon nitride. A source-drain metal layer 24 forms the source and drain electrodes of the transistors; the source-drain metal layer 24 can be made of molybdenum or stacked titanium, aluminum, or titanium. A third insulating layer 23 isolates the capacitor metal layer 22 from the source-drain metal layer 24; the third insulating layer 23 can be made of silicon oxide.

[0072] In the above embodiments, the first wiring layer 11 can be disposed on the same layer as the gate metal layer 20, the second wiring layer 13 can be disposed on the same layer as the source-drain metal layer 24, the first curved segment 1112 is located on the gate metal layer 20, the shielding layer 12 is located on the capacitor metal layer 22, and the second curved segment 1312 is located on the source-drain metal layer 24; the first straight segment 1111 is disposed on the same layer as the first curved segment 1112 or the second curved segment 1312, that is, the first straight segment 1111 is located on the gate metal layer 20 or the source-drain metal layer 24, and the second straight segment 1311 is located on the same layer as the first straight segment 1111.

[0073] In the above embodiment, the display panel 1 includes three metal layers stacked along the direction away from the substrate 10: a gate metal layer 20, a capacitor metal layer 22, and a source / drain metal layer 24. The first wiring layer 11 is disposed on the same layer as the gate metal layer 20, the shielding layer 12 is disposed on the same layer as the capacitor metal layer 22, and the second wiring layer 13 is disposed on the same layer as the source / drain metal layer 24.

[0074] In the above embodiments, such as Figure 16 As shown, the display panel 1 also includes a third trace 27, which includes a straight portion 271 located in the conventional wiring area A3 and a winding portion 272 located in the peripheral wiring area A2. The straight portion 271 extends along a second direction y, which intersects with the first direction x. The straight portion 271 and the winding portion 272 may be located on the same layer or on different layers, which is not particularly limited in this application. The third trace 27 is disposed on a different layer from the first trace 111 and the third trace 27 is disposed on a different layer from the second trace 131.

[0075] In the above embodiment, the third trace 27 is arranged in a layer different from the second trace 131 and the first trace 111. At this time, a third trace layer can be added to arrange the third trace 27. The third trace layer is arranged in a stack with the gate metal layer 20, the capacitor metal layer 22, and the source-drain metal layer 24. Specifically, the third trace layer 27 can be arranged above or below any one of the gate metal layer 20, the capacitor metal layer 22, and the source-drain metal layer 24. The present application does not make a special limitation.

[0076] In another possible implementation, as shown in Figure 17 Figure 17 FIG. 2 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present application. The display panel 1 further includes, in a direction away from the substrate 10, a semiconductor layer 18, a first insulating layer 19, a gate metal layer 20, a second insulating layer 21, a capacitor metal layer 22, a third insulating layer 23, a source-drain metal layer 24, a fourth insulating layer 25, and an auxiliary metal layer 26 arranged in a stack. The second curved segment 1312, the first straight segment 1111, and the second straight segment 1311 are located in the auxiliary metal layer 26. The second straight segment 1311 and the second curved segment 1312 are located in the same layer and are directly connected, i.e., the second trace 131 in Figure 17

[0077] In the above embodiment, the fourth insulating layer 25 can be made of polyimide or the like. The present application does not make a special limitation. The auxiliary metal layer 26 can be made of molybdenum or a stack of titanium, aluminum, and titanium.

[0078] In the above embodiment, the auxiliary metal layer 26 can further increase the wiring space. After the wiring space is increased, the distance between the traces in the same layer can be increased, and the mutual interference between adjacent traces can be reduced. Meanwhile, the increase of the wiring space can reduce the wiring difficulty and improve the production yield.

[0079] In the above embodiment, the display panel 1 includes, in a direction away from the substrate 10, four metal layers arranged in a stack, i.e., the gate metal layer 20, the capacitor metal layer 22, the source-drain metal layer 24, and the auxiliary metal layer 26. The second trace layer 13 can be arranged in the same layer as the auxiliary metal layer 26, i.e., the second curved segment 1312 is located in the auxiliary metal layer 26. The first straight segment 1111 and the second straight segment 1311 can be arranged in the same layer as the second curved segment 1312. At this time, the first curved segment 1112, the shielding layer 12, and the third trace 27 can occupy one of the gate metal layer 20, the capacitor metal layer 22, and the source-drain metal layer 24, respectively. The present application does not make a special limitation to the specific arrangement.

[0080] In another possible implementation, as shown in Figure 18 ​​As shown, the display panel 1 further comprises, in sequence from the direction away from the substrate 10, a semiconductor layer 18, a first insulating layer 19, a gate metal layer 20, a second insulating layer 21, a capacitor metal layer 22, a third insulating layer 23, a source-drain metal layer 24, a fourth insulating layer 25, and an auxiliary metal layer 26.

[0081] The first curve segment 1112 is located in the gate metal layer 20, the shielding layer 12 is located in the capacitor metal layer 22, and the second curve segment 1312 is located in the source-drain metal layer 24. The first straight line segment 1111 and the second straight line segment 1311 are both located in the auxiliary metal layer 26.

[0082] In the above embodiment, the first straight line segment 1111 and the second straight line segment 1311 are arranged in the same layer, and are arranged in different layers from the first curve segment 1112 and the second curve segment 1312. The first straight line segment 1111 and the first curve segment 1112 are connected by a via hole penetrating through the fourth insulating layer 25, the third insulating layer 23, and the second insulating layer 21. The second straight line segment 1311 and the second curve segment 1312 are connected by a via hole penetrating through the fourth insulating layer 25.

[0083] In the above embodiment, the third wire 27 is arranged in a different layer from the second wire 131 and the first wire 111. At this time, a third wire layer can be additionally provided to arrange the third wire 27. The third wire layer is stacked with the gate metal layer 20, the capacitor metal layer 22, the source-drain metal layer 24, and the auxiliary metal layer 26. Specifically, the third wire layer can be located above or below any one of the gate metal layer 20, the capacitor metal layer 22, the source-drain metal layer 24, and the auxiliary metal layer 26. The present application does not make special limitations.

[0084] In a feasible embodiment, the first wire 111 and the second wire 131 are data lines, and the third wire 27 is a scan line. Alternatively, the first wire 111 and the second wire 131 are scan lines, and the third wire 27 is a data line. The present application does not make special limitations.

[0085] In a feasible embodiment, the shielding layer 12 comprises, in sequence from the direction away from the substrate 10, a molybdenum material layer, a silicon dioxide material layer, and a silicon material layer.

[0086] In the above embodiment, when the shielding layer 12 is continuously disposed in the peripheral wiring area A2, a molybdenum material layer, a silicon dioxide material layer, and a silicon material layer can be stacked. The molybdenum material layer has high conductivity and is suitable as the main material of the shielding layer 12. The silicon material layer can include monocrystalline silicon and amorphous silicon. Monocrystalline silicon is grayish-black, and amorphous silicon is black, both exhibiting excellent light absorption capabilities. Therefore, placing the silicon material layer on the side of the molybdenum metal layer away from the substrate 10 can reduce the reflection of ambient light in the area of ​​the shielding layer 12 not blocked by the second curved portion, thereby reducing the probability of dark-state reflection near the hole area A1. Simultaneously, to avoid the poor electron transport capability of the surface silicon material layer affecting the shielding effect, a silicon dioxide material layer can be used as an insulating layer to prevent direct contact between the silicon material layer and the molybdenum metal layer, thus avoiding adverse effects on the transport capability of the molybdenum metal layer.

[0087] In the above embodiments, by setting the material of the shielding layer 12, the shielding layer 12 can reduce the reflection of light while ensuring a good shielding effect, thereby improving the dark state uniformity of the display panel 1.

[0088] This application also provides a display device 2, such as... Figure 19 As shown, Figure 19 This is a top view of a display device provided in an embodiment of this application. The display device 2 provided in this application includes any of the display panels 1 provided in the above embodiments of this application.

[0089] The display device 2 can be a mobile terminal such as a mobile phone or tablet, or a fixed terminal such as a monitor or television, or a wearable device such as a watch; this application does not impose any particular limitation. In this display device 2, signal interference near the display panel hole area A1 is greatly reduced, and the display effect is significantly improved, thereby greatly enhancing the user experience.

[0090] The embodiments described above are not exhaustive and do not limit the invention to specific examples. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, The display panel comprises a hole region, a peripheral wiring region surrounding at least part of the hole region, and a regular wiring region surrounding at least part of the peripheral wiring region, and comprises: a substrate; a first wiring layer formed on the substrate; a shielding layer formed on a side of the first wiring layer away from the substrate; a second wiring layer formed on a side of the shielding layer away from the first wiring layer; a first wiring comprising a first straight segment in the regular wiring region and a first curved segment in the peripheral wiring region, the first curved segment being located in the first wiring layer; a second wiring comprising a second straight segment in the regular wiring region and a second curved segment in the peripheral wiring region, the second straight segment being in the same extension direction as the first straight segment, and the second curved segment being located in the second wiring layer; wherein a projection of the shielding layer on the substrate at least partially overlaps a projection of the first curved segment on the substrate, and / or a projection of the shielding layer on the substrate at least partially overlaps a projection of the second curved segment on the substrate; the first wiring and the second wiring are the same type of signal line, the first straight segment and the second straight segment are arranged in the same layer, and the first curved segment and the second curved segment are arranged in different layers; the shielding layer comprises, in order from the direction away from the substrate, a molybdenum material layer, a silicon dioxide material layer, and a silicon material layer.

2. The display panel of claim 1, wherein, At least part of the first curved segment and the second curved segment correspond to each other, and in each pair of corresponding first curved segments and second curved segments, a projection of the second curved segment on the first wiring layer is located within the first curved segment.

3. The display panel of claim 1, wherein, Adjacent first curved segments have a first gap therebetween, and adjacent second curved segments have a second gap therebetween, a projection of the first curved segment on the second wiring layer covers the second gap, and a projection of the second curved segment on the first wiring layer covers the first gap.

4. The display panel of claim 1, wherein, Signals in different first curved segments are the same, signals in different second curved segments are the same, and signals in the first curved segment and the second curved segment are different.

5. The display panel of claim 1, wherein, The shielding layer is located in the peripheral wiring region, and the shielding layer is arranged continuously in the same layer.

6. The display panel of claim 1, wherein, The shielding layer comprises a plurality of first shielding units arranged in order and nested around the hole region, each first shielding unit has a projection on the first wiring layer covering two first curved segments located on both sides of the hole region, or each first shielding unit has a projection on the second wiring layer covering two second curved segments located on both sides of the hole region.

7. The display panel of claim 1, wherein, The shielding layer comprises a plurality of second shielding units arranged in order and partially around the hole region, a projection of each second shielding unit on the first wiring layer coincides with a first curved segment, or a projection of each second shielding unit on the second wiring layer coincides with a second curved segment.

8. The display panel of claim 1, wherein, The shielding layer is connected to a fixed potential terminal.

9. The display panel of claim 8, wherein, The fixed potential end comprises one of a power supply voltage signal end and a reference voltage signal end.

10. The display panel of claim 1, wherein, The first straight line segment and the second straight line segment extend in a first direction. The first straight line segment is arranged in the same layer as the first curved line segment or the second curved line segment, or the first straight line segment is arranged in a different layer from the first curved line segment and the first straight line segment is arranged in a different layer from the second curved line segment.

11. The display panel of claim 10, wherein, The display panel comprises, in sequence from the direction away from the substrate, a semiconductor layer, a first insulating layer, a gate metal layer, a second insulating layer, a capacitor metal layer, a third insulating layer, and a source-drain metal layer. The first curved line segment is located in the gate metal layer, the shielding layer is located in the capacitor metal layer, and the second curved line segment is located in the source-drain metal layer.

12. The display panel of claim 10, wherein, The display panel further comprises, in sequence from the direction away from the substrate, a semiconductor layer, a first insulating layer, a gate metal layer, a second insulating layer, a capacitor metal layer, a third insulating layer, a source-drain metal layer, a fourth insulating layer, and an auxiliary metal layer. The second curved line segment, the first straight line segment, and the second straight line segment are all located in the auxiliary metal layer.

13. The display panel of claim 10, wherein, The display panel further comprises, in sequence from the direction away from the substrate, a semiconductor layer, a first insulating layer, a gate metal layer, a second insulating layer, a capacitor metal layer, a third insulating layer, a source-drain metal layer, a fourth insulating layer, and an auxiliary metal layer. The first curved line segment is located in the gate metal layer, the shielding layer is located in the capacitor metal layer, and the second curved line segment is located in the source-drain metal layer.

14. The display panel of claim 10, wherein, The display panel further comprises a third trace, the third trace comprising a straight line portion located in the regular wiring area and a winding portion located in the peripheral wiring area, the straight line portion extending in a second direction, the second direction intersecting the first direction. The third trace is arranged in a different layer from the first trace and in a different layer from the second trace.

15. The display panel of claim 14, wherein, The first trace and the second trace are data lines, and the third trace is a scan line, or the first trace and the second trace are scan lines, and the third trace is a data line.

16. A display device comprising: The display panel comprises any one of the display panels according to claims 1-15.

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