A control board and test system

Abstract

The application provides a control board and a test system. The control board comprises a first debug access port (DAP) connector, a master control chip electrically connected with pins of the first DAP connector, wherein a target pin of the first DAP connector is electrically connected with a 10-pin DAP emulator through a first soldering mode of two resistors, and the target pin of the first DAP connector is electrically connected with a 20-pin joint test action group (JTAG) emulator through a second soldering mode of two resistors. The control board and the test system can realize compatible design of the DAP emulator and the JTAG emulator, meet the test requirements of project development, and solve the problem of adapting to different emulator interfaces.

Description

Technical Field

[0001] This invention relates to the field of simulator testing technology, and in particular to a control board and testing system. Background Technology

[0002] Typically, when designing circuit boards, the control board is designed to match the emulator port connectors according to the different emulator interfaces. If there are two types of emulators, two different control boards with different emulator ports need to be designed, which is costly and inflexible for testing. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a control board and a testing system that achieves DAP and JTAG compatibility design, meets the testing requirements of project development, and solves the problem of adapting to different simulator interfaces.

[0004] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0005] An embodiment of the present invention provides a control board, comprising:

[0006] First debug access port DAP connector;

[0007] The main control chip is electrically connected to the pins of the first DAP connector;

[0008] The target pin of the first DAP connector is electrically connected to the 10-pin DAP emulator via a first soldering method using two resistors.

[0009] The target pin of the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator via a second soldering method using two resistors.

[0010] Optionally, the test mode selection of the first DAP connector is to electrically connect the TMS pin to the main control chip;

[0011] The test clock input signal TCK pin of the first DAP connector is electrically connected to the main control chip;

[0012] The test data output TDO pin of the first DAP connector is electrically connected to the main control chip.

[0013] Optionally, the test mode selection pin of the first DAP connector is electrically connected to the main control chip and electrically connected to the power supply through the first pull-up resistor;

[0014] The test clock input signal TCK pin of the first DAP connector is electrically connected to the main control chip and grounded through a pull-down resistor;

[0015] The test data output TDO pin of the first DAP connector is electrically connected to the main control chip and electrically connected to the power supply through the second pull-up resistor. Data is output from the DAP connector through the test data output pin TDO.

[0016] Optionally, the target pin of the first DAP connector is electrically connected to the 10-pin DAP emulator via a first soldering method using two resistors, including:

[0017] When pin 9 of the first DAP connector is grounded through the first soldering resistor and the second soldering resistor is not soldered, the first DAP connector is electrically connected to the 10-pin DAP emulator.

[0018] Optionally, the target pin of the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator via a second soldering method using two resistors, including:

[0019] Pin 9 of the first DAP connector is electrically connected to the main control chip through the second soldering resistor. When the first soldering resistor is not soldered, the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator through the adapter board. Data is input to pin 9 through the test data input TDI pin of the 20-pin Joint Test Working Group JTAG emulator.

[0020] Optionally, the VREF pin of the first DAP connector is pulled up to the power supply;

[0021] The power supply is grounded through a filter capacitor;

[0022] Both the nReset pin and the nTRST pin of the first DAP connector are reset signal pins.

[0023] Optionally, the adapter board is provided with a 10-pin second debug access port (DAP) connector and a 20-pin joint test workgroup (JTAG) connector, wherein the signal pins of the second DAP connector and the 20-pin JTAG connector are connected to each other.

[0024] Optionally, the test mode selection TMS pin of the second DAP connector is connected to the test mode selection TMS pin of the 20-pin JTAG connector.

[0025] The test clock input signal TCK pin of the second DAP connector is connected to the test clock input signal TCK pin of the 20-pin JTAG connector.

[0026] Optionally, the test data input TDI pin of the second DAP connector is connected to the test data input TDI pin of the 20-pin JTAG connector;

[0027] The test data output TDO pin of the second DAP connector is connected to the test data output TDO pin of the 20-pin JTAG connector.

[0028] Optionally, the nTRST pin of the second DAP connector is connected to the TRST pin of the 20-pin JTAG connector;

[0029] The reference voltage Vref pin of the second DAP connector is connected to the reference voltage Vtref pin and the power supply pin of the 20-pin JTAG connector;

[0030] The RESET pin of the second DAP connector is connected to the RESET pin of the 20-pin JTAG connector;

[0031] The ground pin GND of the second DAP connector is connected to the ground pin GND of the 20-pin JTAG connector.

[0032] Embodiments of the present invention also provide a test system, including: a 10-pin DAP emulator, a 20-pin Joint Test Working Group (JTAG) emulator, and a control board as described above.

[0033] The above-described solution of the present invention has at least the following beneficial effects:

[0034] The above-described solution of the present invention utilizes a first debug access port (DAP) connector and a main control chip electrically connected to the pins of the first DAP connector. The target pins of the first DAP connector are electrically connected to a 10-pin DAP emulator via a first soldering method using two resistors. The target pins of the first DAP connector are also electrically connected to a 20-pin Joint Test Working Group (JTAG) emulator via a second soldering method using two resistors. This achieves a compatible design for both DAP and JTAG emulators on the control board, meeting the testing requirements of project development and reducing the development cycle and cost of a control board. By adopting a compatible design for both emulators, only a compatibility design needs to be implemented in the control board circuitry, adding an adapter board with a connector to adapt to different emulators, improving design convenience and increasing testing flexibility. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the control board provided in an embodiment of the present invention;

[0036] Figure 2 This is a JTAG standard pin diagram provided in an embodiment of the present invention;

[0037] Figure 3 This is a DAP pin diagram provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the adapter board provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of a control board compatibility scheme provided in an embodiment of the present invention. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] like Figure 1 As shown, an embodiment of the present invention provides a control board, comprising:

[0042] First debug access port DAP connector;

[0043] The main control chip is electrically connected to the pins of the first DAP connector, and the main control chip may be a microcontroller unit (MCU).

[0044] The target pin of the first DAP connector is electrically connected to the 10-pin DAP emulator via a first soldering method using two resistors.

[0045] The target pin of the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator via a second soldering method using two resistors.

[0046] In this embodiment, the first DAP (Debug Access Port) connector scheme is adopted in the PCB (Printed Circuit Board) layout of the control board. The design scheme with 10 pins greatly reduces the layout area. At the same time, by using different soldering methods for the first DAP connector and the two resistors, compatibility testing of the DAP emulator and the JTAG emulator can be achieved.

[0047] In an optional embodiment of the present invention, the test mode selection TMS pin of the first DAP connector is electrically connected to the main control chip.

[0048] The test clock input signal TCK pin of the first DAP connector is electrically connected to the main control chip;

[0049] The test data output TDO pin of the first DAP connector is electrically connected to the main control chip.

[0050] The test mode selection TMS pin of the first DAP connector is electrically connected to the main control chip and electrically connected to the power supply through the first pull-up resistor R1;

[0051] The test clock input signal TCK pin of the first DAP connector is electrically connected to the main control chip and grounded through pull-down resistor R5;

[0052] The test data output TDO pin of the first DAP connector is electrically connected to the main control chip and electrically connected to the power supply through the second pull-up resistor R4. Data is output from the DAP connector through the test data output pin TDO.

[0053] The target pin of the first DAP connector is electrically connected to the 10-pin DAP emulator via a first soldering method using two resistors, including:

[0054] When pin 9 of the first DAP connector is grounded through the first soldering resistor R9 and the second soldering resistor R7 is not soldered, the first DAP connector is electrically connected to the 10-pin DAP emulator.

[0055] The target pin of the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator via a second soldering method using two resistors, including:

[0056] Pin 9 of the first DAP connector is electrically connected to the main control chip through the second soldering resistor R7. When the first soldering resistor R9 is not soldered, the first DAP connector is electrically connected to the 20-pin Joint Test Working Group JTAG emulator through the adapter board. Data is input to pin 9 through the test data input TDI pin of the 20-pin Joint Test Working Group JTAG emulator.

[0057] In this embodiment of the present invention, the first DAP connector has 10 pins, namely:

[0058] Pin 1 VREF: Power input, connected to VDD power supply through pull-up resistor R8, C1 is the power supply filter capacitor;

[0059] Pin 2 TMS: Test mode selection signal, which passes through the first pull-up resistor R1 to the MCU chip for test mode selection;

[0060] 3-pin ground;

[0061] Pin 4 TCK: Test clock signal, which is connected to the MCU chip through pull-down resistor R5 and is the test clock input signal;

[0062] Pin 6 TDO: Test data output signal, which passes through the second pull-up resistor R4 to the MCU. The data is output from the DAP connector through the TDO pin.

[0063] 7-pin ground;

[0064] Pin 8 (nTRST) and pin 10 (nReset) are reset signals;

[0065] Pin 9 can be connected to TDI or GND. By selecting the appropriate resistors, DAP and JTAG compatibility can be achieved. Specifically, by selecting the soldering method of resistors R7 and R9, the control board can be compatible with both the DAP 10-pin emulator and the JTAG 20-pin emulator. TDI is the test data input, and data is input to this interface through the TDI pin.

[0066] The soldering methods for resistors R7 and R9 include:

[0067] First soldering method: Solder resistor R9, and do not solder resistor R7; in this case, pin 9 is connected to the GND pin through resistor R9. This solution can be directly adapted to a 10-pin DAP emulator.

[0068] The second soldering method involves soldering resistor R7, while leaving resistor R9 unsoldered. Pin 9 is connected to the MCU via resistor R7. Data is input to pin 9 via the TDI pin of the 20-pin Joint Test Working Group JTAG emulator. This solution can be adapted to the JTAG emulator using an external adapter board, thus enabling compatibility testing between the DAP emulator and the JTAG emulator.

[0069] It should be noted that the interface of the DAP emulator is the same as that of the first DAP connector, both conforming to the DAP standard interface.

[0070] like Figure 2 As shown, in an optional embodiment of the present invention, the 20-pin Joint Test Working Group JTAG emulator J1 has 20 pins, namely:

[0071] Pin 1 Vtref: Interface signal level reference voltage, usually directly connected to the power supply;

[0072] Pin 2 VDD: Power supply;

[0073] Pin 3 TRST (Test Reset Input): This is the test reset input pin; active low.

[0074] 4-pin ground;

[0075] Pin 5 TDI (Test Data Input): This is for inputting test data. Data is input to the JTAG interface through the TDI pin.

[0076] 6-pin ground;

[0077] 7-pin TMS (Test Mode Selector): Used to set the JTAG interface to a specific test mode;

[0078] 8-pin ground;

[0079] Pin 9 TCK (Test Clock): This is the test clock input.

[0080] Pin 10 is grounded; Pin 11 is NC and not connected.

[0081] 12-pin ground;

[0082] Pin 13 TDO (Test Data Output): This pin outputs test data from the JTAG interface.

[0083] 14-pin ground;

[0084] Pin 15 RESET: Target system reset signal;

[0085] 16-pin ground;

[0086] Pins 17 and 19 (NC): Not connected;

[0087] 18-pin ground;

[0088] 20-pin ground;

[0089] GND: Ground pin.

[0090] like Figure 3 The diagram shows the pinout of the DAP emulator interface, which can be connected to debuggers such as JTAG. The pinouts of the DAP emulator are as follows:

[0091] 2-pin TMS: Used to set the interface to a specific test mode, the same as the 7-pin TMS pin of JTAG;

[0092] Pin 4 TCK: This is the test clock input, the same as pin 9 TCK in JTAG;

[0093] 6-pin TDO: This is for test data output. Data is output from the interface through the TDO pin, which is the same as the 13-pin TDO of JTAG.

[0094] Pin 8 nTRST: Test reset, input pin, active low, same as pin 3 TRST of JTAG;

[0095] Pin 10 nRESET: Target system reset signal, same as pin 15 of JTAG;

[0096] Pin 1 Vref: Target board reference voltage, which is the same as the JTAG pin 1 Vtref and pin 2 VDD power supply;

[0097] Pin 9 can be connected to TDI or GND. By selecting the appropriate resistors, DAP and JTAG can be compatible. TDI: This is the test data input. Data is input to this interface through the TDI pin, which is the same as the TDI pin 5 of JTAG.

[0098] GND: Ground pin, the same as the GND pin of JTAG.

[0099] like Figure 4 As shown, in an optional embodiment of the present invention, the adapter board is provided with: a 10-pin second debug access port (DAP) connector and a 20-pin joint test workgroup (JTAG) connector, wherein the signal pins of the second DAP connector and the 20-pin JTAG connector are connected to each other.

[0100] Specifically, the test mode selection TMS pin of the second DAP connector is connected to the test mode selection TMS pin of the 20-pin JTAG connector;

[0101] The test clock input signal TCK pin of the second DAP connector is connected to the test clock input signal TCK pin of the 20-pin JTAG connector.

[0102] The test data input TDI pin of the second DAP connector is connected to the test data input TDI pin of the 20-pin JTAG connector;

[0103] The test data output TDO pin of the second DAP connector is connected to the test data output TDO pin of the 20-pin JTAG connector.

[0104] The nTRST pin of the second DAP connector is connected to the TRST pin of the 20-pin JTAG connector;

[0105] The reference voltage Vref pin of the second DAP connector is connected to the reference voltage Vtref pin and the VDD power supply pin of the 20-pin JTAG connector.

[0106] The RESET pin of the second DAP connector is connected to the RESET pin of the 20-pin JTAG connector;

[0107] The ground pin GND of the second DAP connector is connected to the ground pin GND of the 20-pin JTAG connector.

[0108] like Figure 5As shown, to adapt to the JTAG 20-pin emulator, an adapter board needs to be added between the emulator and the control board to convert between the first DAP connector and the JTAG emulator. The adapter board has a 10-pin second DAP connector and a 20-pin JTAG connector. The signals between the two connectors are connected by the same-name signal pins. The pins of the two connectors are connected one-to-one, and no additional components or circuits are required.

[0109] The embodiments of the present invention, by adding a DAP-to-JTAG adapter board to the first DAP connector of the control board as an interface conversion for JTAG emulators, achieve a high-density design scheme for the control board. This allows for flexible adaptation to both DAP and JTAG emulator schemes, achieving compatible applications of DAP and JTAG emulators, reducing the development cycle and cost of a control board, and improving testing flexibility. Simultaneously, by using a small-package DAP connector for the control board and a compatible design scheme for DAP pins, the layout density is increased, and design flexibility is enhanced.

[0110] Embodiments of the present invention also provide a test system, including: a 10-pin DAP emulator, a 20-pin Joint Test Working Group (JTAG) emulator, and a control board as described above. All implementations of the control board in the embodiments described above are applicable to this embodiment and can achieve the same technical effect.

[0111] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A control board, characterized by, Comprising: a first debug access port (DAP) connector; a master chip electrically connected to pins of the first DAP connector; wherein when a 9-pin of the first DAP connector is grounded through a first soldering resistor (R9) and a second soldering resistor (R7) is not soldered, the first DAP connector is electrically connected to a 10-pin DAP emulator; when the 9-pin of the first DAP connector is electrically connected to the master chip through the second soldering resistor (R7) and the first soldering resistor (R9) is not soldered, the first DAP connector is electrically connected to a 20-pin joint test action group (JTAG) emulator through an adapter board, and data is input to the 9-pin through a test data input (TDI) pin of the 20-pin JTAG emulator.

2. The control board of claim 1, wherein: a test mode select (TMS) pin of the first DAP connector is electrically connected to the master chip; a test clock input signal (TCK) pin of the first DAP connector is electrically connected to the master chip; a test data output (TDO) pin of the first DAP connector is electrically connected to the master chip.

3. The control board of claim 2, wherein: the test mode select (TMS) pin of the first DAP connector is electrically connected to the master chip and is electrically connected to a power supply through a first pull-up resistor (R1); the test clock input signal (TCK) pin of the first DAP connector is electrically connected to the master chip and is grounded through a pull-down resistor (R5); the test data output (TDO) pin of the first DAP connector is electrically connected to the master chip and is electrically connected to the power supply through a second pull-up resistor (R4), and data is output from the DAP connector through the test data output pin (TDO).

4. The control panel of claim 1, wherein, a VREF pin of the first DAP connector is pulled up to the power supply; the power supply is grounded through a filter capacitor (C1); the nReset pin and the nTRST pin of the first DAP connector are both reset signal pins.

5. The control panel of claim 1, wherein, the adapter board is provided with a 10-pin second debug access port (DAP) connector and a 20-pin joint test action group (JTAG) connector, and same-name signal pins of the second DAP connector and the 20-pin JTAG connector are connected.

6. The control board of claim 5, wherein: a test mode select (TMS) pin of the second DAP connector is connected to a test mode select (TMS) pin of the 20-pin JTAG connector; a test clock input signal (TCK) pin of the second DAP connector is connected to a test clock input signal (TCK) pin of the 20-pin JTAG connector.

7. The control board of claim 5, wherein: a test data input (TDI) pin of the second DAP connector is connected to a test data input (TDI) pin of the 20-pin JTAG connector; a test data output (TDO) pin of the second DAP connector is connected to a test data output (TDO) pin of the 20-pin JTAG connector.

8. The control board of claim 5, wherein: The nTRST pin of the second DAP connector is connected with the TRST pin of the 20-pin JTAG connector; The reference voltage Vref pin of the second DAP connector is connected with the reference voltage Vtref pin and the power supply pin of the 20-pin JTAG connector; The RESET pin of the second DAP connector is connected with the RESET pin of the 20-pin JTAG connector; The ground pins GND of the second DAP connector are respectively connected with the ground pins GND of the 20-pin JTAG connector.

9. A test system, characterized by Comprise: 10-pin DAP emulator, 20-pin Joint Test Action Group (JTAG) emulator and the control board according to any one of claims 1 to 8.

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