A method to improve the flash writing speed of C81 controller

Abstract

The present invention discloses a method for improving the flash writing speed of a C81 controller. The PC divides the data block A to be flashed into 252-byte frames and inserts a frame sequence before each frame of data to generate a new data block B. The PC transmits all the new data block B to the EPI, defines the data length of each frame transmitted by the EPI to the C81-ECU as 254, and then waits for the EPI's processing result. The EPI divides the new data block B into packets of 253 bytes per frame and automatically adds an SID before each frame of data packet to form a 254-byte data block C, which is transmitted to the C81-ECU. After receiving the data from the EPI, the C81-ECU returns a response to the EPI. After receiving the response from the C81-ECU, the EPI continues to send the next frame of data until all the data to be sent is transmitted. The PC periodically reads the EPI status until the EPI status indicates that all transmission is complete, and the entire transmission process ends. This method can save the 25ms of interaction time between the PC and the EPI when sending 254 bytes each time, thereby achieving the purpose of shortening the entire flash writing time.

Description

Technical Field

[0001] The present invention relates to the technical field of flashing equipment, and in particular to a method for improving the flashing speed of a C81 controller. Background Art

[0002] According to the production requirements of Quanchai engines, it is necessary to flash the data of C81-ECU. The flashing equipment mainly consists of three parts:

[0003] (1) PC: Human-computer interaction software, development of ISO14230 flashing protocol to implement data flashing of C81-ECU;

[0004] (2)EPI: This is a protocol converter that converts the application layer commands sent by the PC into CAN communication with the lower computer through the ISO15765 transmission protocol and assembles the data to send to the controller.

[0005] (3) C81-ECU: A Bosch engine controller for diesel engines;

[0006] The total amount of data flashed to the C81-ECU is 2572288 bytes. However, the flashing protocol defines that the length of each transmission data packet is less than or equal to 254 bytes (of which the SID occupies 1 byte and the frame sequence occupies 1 byte, and the actual maximum data transmitted per frame is 252 bytes). Therefore, the number of data transmissions is very large, and the time to flash the controller is very long, which may take up to 10 minutes.

[0007] Once engine production increases, the flashing cycle will not be able to meet the production cycle. The only solution is to reduce the flashing time of the C81-ECU or increase investment in new flashing equipment.

[0008] In the existing technology solution, during the data transmission phase when flashing the C81-ECU, the PC sends 254 bytes of data to the C81-ECU via the EPI per frame and waits for the controller's response. The total time for normal data exchange per frame is approximately 40ms, of which the interaction time between the PC and the EPI is approximately 25ms, and the time between the EPI and the C81-ECU is approximately 15ms. The disadvantages are as follows:

[0009] (1) The amount of data transmitted from the PC to the EPI in each frame is small, and the number of transmissions is large, resulting in a very long flashing time;

[0010] (2) The interaction time between the PC and EPI is long, occupying most of the interaction time per frame;

[0011] (3) The transmission frequency between the PC and EPI is high, and the flashing is unstable. Summary of the Invention

[0012] The present invention provides a method for improving the flash writing speed of a C81 controller to solve the problems mentioned in the background technology.

[0013] To achieve the above object, the technical solution adopted by the present invention is:

[0014] A method for improving the flash writing speed of a C81 controller comprises the following steps:

[0015] (1) The data block A to be written by the PC is divided into packets according to 252 bytes per frame. The frame sequence is added to the front of each frame of data to form a new data frame, which constitutes the new data block B;

[0016] (2) The PC transmits all new data blocks B to the EPI, defines the data length of each frame transmitted by the EPI to the C81-ECU as 254, and then waits for the processing result of the EPI;

[0017] (3) EPI divides the new data block B into packets of 253 bytes per frame and automatically adds the SID before each frame data packet, combining them into a 254-byte data block C for transmission to C81-ECU;

[0018] (4) After receiving the data from EPI, C81-ECU returns a response to EPI;

[0019] (5) After receiving the response from C81-ECU, EPI continues to send the next frame of data;

[0020] (6) EPI repeats steps 3-5 until all the data to be sent is transmitted;

[0021] (7) The PC reads the status of the EPI periodically until the EPI status shows that all transmissions are completed.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The method of the present invention can save the 25ms of interaction time between the PC and the EPI each time 254 bytes are sent, thereby shortening the entire flash writing time. Theoretically, the flash writing time is about half of the original time. In addition, the larger the amount of data, the greater the flash writing speed advantage.

[0024] Reduce the number of data transmissions between PC and EPI, making data transmission more stable;

[0025] Since EPI is a real-time operating system for single-chip microcomputers, a large amount of data is placed in EPI in advance, allowing EPI and C81-ECU to transmit and process data separately. This makes data transmission more secure and stable, and the timing more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A flowchart of the method of the present invention;

[0028] Figure 2 Schematic diagram of data flashing of the present invention. DETAILED DESCRIPTION

[0029] In order to make the technical means, creative features, purpose and efficacy of the present invention easier to understand, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain this description and are not intended to limit the present invention.

[0030] like Figure 1-2 , using 16128 bytes of data as the actual description, 16128 is 64 times 252 bytes

[0031] (1) The PC divides the 16128-byte data block A into 252-byte packets per frame. The frame sequence is added to the front of each frame to form a new data frame. 64 new data frames form a new data block B with a length of 16192. The original data block A counts from 0 to 16127, and the data block B counts from 0 to 16191. The structure is described as follows:

[0032] In the first frame, data blocks A[0] to A

[251] are inserted into the frame sequence and become new data blocks B[0] to B

[252] , where the value of B[0] is 1 (frame sequence), and B[1] to B

[252] correspond to the values ​​of data blocks A[0] to A

[251] ;

[0033] In the second frame, data blocks A

[252] to A

[503] are inserted into the frame sequence and become new data blocks B

[253] to B

[505] , where the value of B

[253] is 2 (frame sequence), and B

[254] to B

[505] correspond to the values ​​of data blocks A

[252] to A

[503] ;

[0034] In the third frame, data blocks A

[504] to A

[755] are inserted into the frame sequence and become new data blocks B

[506] to B

[758] , where the value of B

[506] is 3 (frame sequence), and B

[507] to B

[758] correspond to the values ​​of data blocks A

[504] to A

[755] ;

[0035] And so on;

[0036] In the nth frame, data blocks A[n*252] to A[n*252+251] are inserted into the frame sequence and become new data blocks B[n*253] to B[n*253+252], where the value of B[n*253] is n (frame sequence), and B[n*253+1] to B[n*253+252] correspond to the values ​​of data blocks A[n*252] to A[n*252+251];

[0037] In the last frame, data blocks A

[15876] to A

[16127] are inserted into the frame sequence and become new data blocks B

[15969] to B

[16127] , where the value of B

[15969] is 64 (frame sequence), and B

[15970] to B

[16191] correspond to the values ​​of data blocks A

[15876] to A

[16127] ;

[0038] (2) The PC transmits all new data blocks B to the EPI, and defines the data length of each frame transmitted by the EPI to the C81-ECU as 254 (SID + frame sequence + actual data), and then waits for the processing result of the EPI;

[0039] (3) EPI divides the new data block B into 253 packets per frame and automatically adds SID (0x36) before each frame data packet. The combined data block C is a 254-byte data block and transmitted to C81-ECU. The structure is as follows:

[0040] In the first frame, the data of C[0] is 0x36, the data of C[1] is B[0], the data of C[2] is B[1], the data of C[3] is B[2], and so on. The data of C[i] is B[i-1]. The corresponding value of the last data C

[253] of data block C is B

[252] .

[0041] In the second frame, the data of C[0] is 0x36, the data of C[1] is B

[253] , the data of C[2] is B

[254] , the data of C[3] is B

[255] , and so on. The data of C[i] is B[253+i-1]. The corresponding value of the last data C

[253] in data block C is B

[505] .

[0042] In the nth frame, the data of C[0] is 0x36, the data of C[1] is B[n*253], the data of C[2] is B[n*253+1], the data of C[3] is B[n*253+2], and so on. The data of C[i] is B[n*253+i-1]. The corresponding value of the last data C

[253] of data block C is B[n*253+252].

[0043] In the last frame, the data of C[0] is 0x36, the data of C[1] is B

[15969] , the data of C[2] is B

[15970] , the data of C[3] is B

[15971] , and so on. The data of C[i] is B[15969+i-1]. The corresponding value of the last data C

[253] of data block C is B

[16191] .

[0044] (4) After receiving the data from EPI, C81-ECU returns a response to EPI;

[0045] (5) After receiving the response from C81-ECU, EPI continues to send the next frame of data;

[0046] (6) EPI repeats steps 3-5 until all the data to be sent is transmitted;

[0047] (7) The PC reads the status of the EPI periodically until the EPI status shows that all transmissions are completed.

[0048] Terminology Notes:

[0049] (1) Service ID: Application layer protocol 0x36 service; referred to as SID;

[0050] (2) Frame sequence number: During data transmission, the sequence number of each frame of data starts from 0x01 to 0xFF, and then from 0x00 to 0xFF, referred to as the frame sequence;

[0051] (3) PC host software, referred to as PC;

[0052] (4)EPI protocol converter, short for Eureka protocal interface, referred to as EPI;

[0053] (5) C81 engine controller, referred to as C81-ECU;

[0054] (6) ISO14230 protocol: a CAN application layer protocol for automotive networks, referred to as the flash protocol below;

[0055] (7) ISO15765 protocol: a CAN transport layer protocol for automotive networks;

[0056] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above invention and description are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for improving the flash writing speed of a C81 controller, characterized by: The specific steps include: (1) The data block A to be written by the PC is divided into packets according to 252 bytes per frame. The frame sequence is added to the front of each frame of data to form a new data frame, which constitutes the new data block B; (2) The PC transmits all new data blocks B to the EPI protocol converter, defines the length of data transmitted by the EPI protocol converter to C81-ECU per frame as 254, and then waits for the processing result of the EPI protocol converter; (3) The EPI protocol converter divides the new data block B into packets of 253 bytes per frame and automatically adds a service ID before each frame of data packet, combining them into data blocks C with a data size of 254 bytes per frame and transmitting them to the C81-ECU; (4) After receiving the data from the EPI protocol converter, C81-ECU returns a response to the EPI protocol converter; (5) After receiving the response from C81-ECU, the EPI protocol converter continues to send the next frame of data; (6) The EPI protocol converter repeats steps 3-5 until all the data to be sent is transmitted; (7) The PC reads the status of the EPI protocol converter periodically until the status of the EPI protocol converter is "All transmissions completed" and the entire transmission process is completed.

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