A method for predicting RC interconnect delay based on graph neural networks

Abstract

This invention proposes a graph neural network-based method for predicting RC interconnect delays. Based on the SPEF parasitic parameter netlist, this method first searches for several RC paths using the DFS (DepthFirstSearch) algorithm, and then represents each RC path as a graph. Nodes in the RC path correspond to nodes in the graph, and the connections between nodes correspond to edges. Ground capacitance and coupling resistance are defined as node and edge attributes, respectively. The result is then obtained through delay inference using a graph convolutional neural network-based inference framework. This method consists of two parts: a SPEF parsing module and a graph neural network prediction module. Compared to using the Elmore and D2M models, using a suitable graph neural network to model the RC paths allows for faster and more accurate prediction of RC interconnect delays, earlier detection of timing violations, and shorter convergence time.

Description

Technical Field

[0001] This invention belongs to the field of chip interconnect delay prediction, and particularly relates to an RC interconnect delay prediction method based on graph neural networks. Background Technology

[0002] In traditional design flows, path delay calculations rely on precise models, but their efficiency becomes increasingly limited as circuit size increases. Furthermore, in advanced processes, wire delays account for a growing proportion of timing calculations, leading to longer and more frequent iterations in the design process. Traditional interconnect timing calculation methods include Wire-load Models and Elmore Delay. The accuracy of interconnect delay calculations is significantly affected by factors such as varying wire lengths, densities, distributions, equivalent models, and propagation methods. Using circuit simulation software like HSPICE for interconnect delay calculations incurs substantial time consumption. Summary of the Invention

[0003] The purpose of this invention is to provide a graph neural network-based method for predicting RC interconnect delay, so as to solve the technical problem of quickly and accurately predicting RC interconnect delay during the layout and routing stage.

[0004] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0005] A method for predicting RC interconnect delay based on graph neural networks, where the graph neural network is a graph convolutional network (GCN); RC interconnect delay refers to the delay of signal transmission between unit circuits, within modules, and between multi-chip components after integrated circuit placement and routing; the method includes the following steps:

[0006] S1: Based on the information in the netlist of the Standard Parasitic ExtractionFormat extracted after placement and routing, the RC path corresponding to the source point to the end point is found by using the Depth First Search principle. The graph topology information of the RC path to be predicted, as well as the feature information of nodes and edges, are constructed. The label value of the RC path delay is obtained by using HSPICE.

[0007] S2: The graph topology information, node and edge feature information, and label values ​​of each RC path in step S1 are used as input to the graph convolutional neural network. After training, the network will establish the connection between the graph representation information and delay information obtained from the RC path, which will be used as the parameters of the graph convolutional neural network model.

[0008] S3: The graph topology information, node and edge feature information generated in step S1, and the graph convolutional neural network model parameters trained in step S2 are used as inputs to the graph convolutional neural network to perform inference on RC interconnect delay.

[0009] Furthermore, step S1 specifically includes the following steps:

[0010] S11: Read the SPEF netlist, generate the corresponding RCT structure for each RC network in the SPEF file, and store it in the RCT_MAP structure;

[0011] S12: Traverse each RCT in the RCT_MAP structure, search for the RC path RC_Path from the source point to the end point using the DFS algorithm, and then expand it with one-hop nodes, storing the RC path information in the RC_Path structure; if the RCT has multiple ends, repeat the RC path search process.

[0012] S13: Convert each RC path into a directed cyclic graph (Graph) and generate the corresponding adjacency matrix; define the capacitance to ground as a node feature in the Graph, represent the coupling resistance as an edge feature in the Graph, and extract the port capacitance pin_cap from the cell library and accumulate it into the endpoint feature information to generate the corresponding feature matrix;

[0013] S14: Calculate the RC interconnection delay of the SPEF netlist using HSPICE, and use the delay information of each RC path as the label value for training the graph convolutional neural network.

[0014] S15: The adjacency matrix, feature matrix, and label value of each RC path are used as input information for training the graph convolutional neural network.

[0015] Furthermore, step S3 specifically includes the following steps:

[0016] S31: Use the adjacency matrix obtained in step S1 to represent graph topology information, and the feature matrix to represent node and edge information, as input to the graph neural network; the graph neural network architecture consists of a graph convolutional layer, a graph pooling layer, and a fully-connected layer.

[0017] S32: In the multi-layer graph convolutional layer, the first layer takes the graph data composed of the adjacency matrix and feature matrix as input, performs neighborhood aggregation and message passing, and calculates the new node embedding; from the second layer onwards, the output of each graph convolutional layer is the input of the next layer, and the output of the last graph convolutional layer is the final node embedding.

[0018] S33: Input the output of the last graph convolutional layer in step S32 into the graph pooling layer to downsample the RC path graph with the latest node embedding information and obtain a single vector to represent the overall graph features of the RC path.

[0019] S34: The output of the graph pooling layer is fed into the Fully-Connected Layer for dimensional transformation to obtain the delayed output of the RC path.

[0020] Furthermore, in step S3, the graph convolutional neural network uses main neighborhood aggregation graph convolution, which can accurately characterize the RC path delay data features.

[0021] The RC interconnect delay prediction method based on graph neural networks of the present invention has the following advantages:

[0022] 1. This invention proposes an intelligent timing RC interconnect delay prediction method based on graph convolutional neural networks. The SPEF netlist is simulated using the circuit analysis tool HSPICE to establish a sample dataset for training. Feature engineering is performed on the RC paths in the SPEF netlist, and the delay information of the RC paths is characterized using a graph neural network method.

[0023] 2. This invention uses a graph convolutional neural network method. By selecting an appropriate number of hidden layer channels and layers, a better model fitting effect and running speed can be obtained.

[0024] 3. This invention relates to modeling RC interconnects as graph structure data and using graph neural networks to directly model interconnect delays. This method has good interpretability.

[0025] Therefore, this invention can quickly and accurately predict RC interconnect delay, and has good practical application value. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the RC interconnect delay prediction framework of the present invention;

[0027] Figure 2 This is a flowchart of the SPEF parsing process of the present invention;

[0028] Figure 3 This is a schematic diagram of the main neighborhood aggregation graph convolution of the present invention;

[0029] Figure 4 This is a schematic diagram of the graph convolutional neural network model of the present invention. Detailed Implementation

[0030] To better understand the purpose, structure, and function of this invention, the following detailed description of an RC interconnect delay prediction method based on graph neural networks is provided in conjunction with the accompanying drawings.

[0031] This embodiment proposes an RC interconnect delay prediction method based on graph neural networks, which is specifically divided into the following steps:

[0032] S1: Based on the SPEF (Standard Parasitic Extraction Format) netlist information extracted after placement and routing, the RC path corresponding to the source point to the endpoint is found using the DFS (Depth First Search) principle. The graph topology information and node and edge feature information of the RC path to be predicted are constructed. The label value of the RC path delay is obtained through HSPICE.

[0033] S2: The graph topology information, node and edge feature information, and label values ​​of each RC path in step S1 are used as input to the graph convolutional neural network. After training, the network will establish the connection between the graph representation information and delay information obtained from the RC path, which will be used as the parameters of the graph convolutional neural network model.

[0034] S3: The graph topology information, node and edge feature information generated in step S1, and the graph convolutional neural network model parameters trained in step S2 are used as inputs to the graph convolutional neural network to perform inference on RC interconnect delay.

[0035] Step S1 specifically includes the following:

[0036] S11: Read the SPEF netlist, generate the corresponding RCT structure for each RC network in the SPEF file, and store it in the RCT_MAP structure;

[0037] S12: Traverse each RCT in the RCT_MAP structure, search for the RC path (RC_Path) from the source point to the endpoint using the DFS algorithm, and then expand it by one hop. Store the RC path information in the RC_Path structure. If an RCT has multiple endpoints, repeat the above process in S12.

[0038] S13: Convert each RC path into a directed cyclic graph (Graph) and generate the corresponding adjacency matrix; define the capacitance to ground as a node feature in the Graph, represent the coupling resistance as an edge feature in the Graph, and extract the port capacitance (pin_cap) from the cell library and add it to the endpoint feature information to generate the corresponding feature matrix;

[0039] S14: Calculate the RC interconnection delay of the SPEF netlist using HSPICE, and use the delay information of each RC path as the label value for training the graph convolutional neural network.

[0040] S15: The adjacency matrix, feature matrix, and label value of each RC path are used as input information for training the graph convolutional neural network;

[0041] Step S3 specifically includes the following:

[0042] S31: The adjacency matrix obtained in step S1, used to represent graph topology information, and the feature matrix used to represent node and edge information, are used as inputs to the graph neural network. The graph neural network architecture consists of graph convolutional layers, graph pooling layers, and fully-connected layers.

[0043] S32: In a multi-layer graph convolutional layer, the first layer takes graph data consisting of adjacency matrices and feature matrices as input, performs neighborhood aggregation and message passing, and calculates a new node embedding. Starting from the second layer, the output of each graph convolutional layer becomes the input of the next layer, and the output of the last graph convolutional layer yields the final node embedding.

[0044] S33: Input the output of the last graph convolutional layer in step S32 into the graph pooling layer to downsample the RC path graph with the latest node embedding information and obtain a single vector to represent the overall graph features of the RC path.

[0045] S34: The output of the graph pooling layer is fed into the fully-connected layer for dimensional transformation to obtain the delayed output of the RC path;

[0046] For example, the constructed graph convolutional neural network uses Principal Neighborhood Aggregated Graph Convolution (PNAConv), has 3 layers, 64 hidden neurons, uses Sum_nodes for graph pooling, has 3 fully connected layers for prediction, and has 1 dimension for both edge and node features. The mean absolute error (MAO) between the network's predictions and the actual values ​​is then calculated. The MAO is then minimized using the Adam adaptive moment estimation optimizer to optimize the model parameters. For example, the training parameters for the graph neural network are: training batch size of 128, initial learning rate of 0.001, the Adam optimizer, and the mean absolute error loss function.

[0047] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A method for RC interconnect delay prediction based on graph neural networks, characterized in that, The graph neural network is a graph convolutional neural network (GCN); the RC interconnection delay is a delay of a signal transmission carrier between unit circuits after layout and routing of an integrated circuit, within a module, and between multi-chip assemblies; and the method comprises the following steps: S1: according to standard parasitic exchange format (SPEF) netlist related information extracted after layout and routing, a RC path corresponding to a source point to an endpoint is found through a depth first search (DFS) principle, graph topology information of the RC path to be predicted and feature information of nodes and edges are constructed, and a label value of the RC path delay is obtained through HSPICE; S2: the graph topology information of each RC path, the feature information of nodes and edges, and the label value in the step S1 are taken as inputs of the graph convolutional neural network, the network establishes a connection between the graph representation information and the delay information obtained from the RC path after being trained, and the connection is taken as a graph convolutional neural network model parameter; S3: the graph topology information of the RC path to be predicted generated in the step S1, the feature information of nodes and edges, and the graph convolutional neural network model parameter trained in the step S2 are taken as inputs of the graph convolutional neural network, and inference of the RC interconnection delay is performed.

2. The RC interconnect delay prediction method based on graph neural network according to claim 1, characterized in that, The step S1 specifically comprises the following steps: S11: a SPEF netlist is read, a corresponding RCT structure is generated for each RC network in the SPEF file, and the RCT structure is stored in an RCT_MAP structure; S12: each RCT in the RCT_MAP structure is traversed, an RC path RC_Path from a source point to an endpoint is searched through a DFS algorithm, and a one-hop node is expanded, RC path information is stored in an RC_Path structure, and if the RCT has multiple endpoints, the RC path searching process is repeatedly performed; S13: each RC path is converted into a directed cyclic graph Graph, a corresponding adjacency matrix is generated, a ground capacitance is defined as a node feature in the Graph, a coupling resistance is represented as an edge feature in the Graph, and a port capacitance pin_cap is extracted from a cell library and added to endpoint feature information, and a corresponding feature matrix is generated; S14: RC interconnection delay calculation is performed on the SPEF netlist through HSPICE, and each RC path delay information obtained is taken as a label value for training of the graph convolutional neural network; S15: the adjacency matrix of each RC path, the feature matrix, and the label value are taken as input information for training of the graph convolutional neural network.

3. The RC interconnect delay prediction method based on graph neural network according to claim 2, characterized in that, The step S3 specifically comprises the following steps: S31: the adjacency matrix for representing the graph topology information and the feature matrix for representing the node and edge information obtained in the step S1 are taken as inputs of the graph neural network; the graph neural network architecture is composed of a graph convolutional layer, a graph pooling layer, and a fully-connected layer. S32: In the multi-layer graph convolutional layer, the first layer takes the graph data composed of the adjacency matrix and the feature matrix as input, performs neighborhood aggregation and message passing, and calculates new node embedding; starting from the second layer, the output of each layer of the graph convolutional layer is the input of the next layer, and the output of the last graph convolutional layer obtains the final node embedding; S33: The output of the last graph convolutional layer in step S32 is input into the graph pooling layer, the RC path graph with the latest node embedding information is down-sampled to obtain a single vector representing the overall graph features of the RC path; S34: The output of the graph pooling layer is input into the fully-connected layer to perform dimension transformation to obtain the delay output of the RC path.

4. The RC interconnect delay prediction method based on graph neural network according to claim 2, characterized in that, In step S3, the graph convolutional neural network adopts the main neighborhood aggregation graph convolution, which can accurately represent the delay data characteristics of the RC path.

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