Monitoring circuits, statistical methods, and memories

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a statistical method, and a memory, comprising: a plurality of storage cells, a plurality of comparators, and a plurality of counters, wherein each storage cell corresponds to a comparator and a counter; a storage judgment module, for receiving a currently enabled word line address, and comparing, based on the comparators corresponding to the storage cells that have stored the word line addresses, whether the word line addresses stored in the storage cells are the same as the enabled word line addresses; if there is a storage cell with the same address as the enabled word line address, the count value of the counter corresponding to the indicated storage cell is increased by one; if there is no storage cell with the same address as the enabled word line address, the enabled word line address is stored in a storage cell that has not written the word line address; and a processing output module, based on the comparison of the counter values, outputs the word line address stored in the storage cell corresponding to the counter with the largest value, so as to obtain the word line address that has been enabled the most times.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a statistical method, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) stores data in a one-transistor-one-memory cell structure (1T1C). The transistors are controlled by a word line (WL). When the WL is turned on, the charge in the memory cell is shared with the charge on the bit line (BL) to read data from or write data to the target memory cell.

[0003] However, frequent or long-term activation of the WL may cause charge loss in adjacent memory cells, which may result in errors in the data stored in the memory cells.

[0004] How to count the number of times WL is turned on to ensure the accuracy of the data stored in each storage unit is a counting problem that needs to be solved urgently. Summary of the Invention

[0005] An embodiment of the present disclosure provides a monitoring circuit to obtain the address of a word line that is turned on the most times.

[0006] An embodiment of the present disclosure provides a monitoring circuit, comprising: a plurality of storage cells, a plurality of comparators, and a plurality of counters, wherein each storage cell is used to store a word line address, and each storage cell corresponds to a comparator and a counter; a storage judgment module, used to receive a currently turned-on word line address, configured to: based on the comparator corresponding to the storage cell that has stored the word line address, sequentially compare whether the word line address stored in the storage cell is the same as the turned-on word line address; if there is a storage cell with the same word line address as the turned-on word line address, the count value of the counter corresponding to the indicated storage cell is increased by one; if there is no storage cell with the same word line address as the turned-on word line address, the turned-on word line address is stored in a storage cell to which the word line address is not written; a processing output module, configured to: based on a comparison of the numerical values ​​of the counters, output the word line address stored in the storage cell corresponding to the counter with the largest numerical value.

[0007] The storage unit is connected to a comparator for comparing whether the currently turned-on word line address is stored in the storage unit, and storing the unstored turned-on word line address through the storage unit. The storage unit is also connected to a counter for counting the word line addresses that are turned on multiple times, that is, counting the number of word line addresses that are turned on, and outputting the word line address that is turned on the most times by comparing between the counters, thereby realizing the monitoring of the number of word line turns on. By obtaining the word line address, the memory is subsequently optimized to avoid the loss of charge in adjacent storage cells due to frequent word line turning on.

[0008] In some embodiments, each memory cell further includes a flag bit; the flag bit includes a valid flag bit and an invalid flag bit. The valid flag bit is used to indicate that the memory cell has stored a word line address, and the invalid flag bit is used to indicate that the memory cell has not stored a word line address. The valid flag bit is also used to turn on the comparator and counter corresponding to the memory cell. By turning on the comparator connected to the memory cell by the flag bit, the memory cell that does not store a word line address can be compared with the currently enabled word line address through the comparator, thereby optimizing the process of monitoring the number of times the word line address is turned on.

[0009] In some embodiments, the plurality of storage units are arranged in the form of a linked list.

[0010] In some embodiments, the plurality of storage units are arranged in a queue.

[0011] In some embodiments, the storage judgment module includes: a receiving unit for receiving the word line address to be turned on; a control unit, connecting the receiving unit, multiple storage units and comparators corresponding to the storage units; if there is a storage unit with the same address as the turned on word line, the control unit instructs the counter corresponding to the storage unit to count up by one, and if there is no storage unit with the same address as the turned on word line, the control unit stores the turned on word line address in the storage unit that has not written the word line address.

[0012] In some embodiments, if there is a storage cell with the same address as the word line that is turned on, the control unit instructs the counter corresponding to the storage cell to count up by one, including: if there is a storage cell with the same address as the word line that is turned on, the control unit generates a first control signal and a second control signal; the counter corresponding to the storage cell storing the word line address that is turned on counts up by one based on the first control signal; the second control signal is used to indicate that the word line address that is turned on is prevented from being stored in the storage cell.

[0013] In some embodiments, the processing output module includes: a processing unit connected to counters corresponding to multiple storage units, used to compare the values ​​of multiple counters and output the counter data with the largest value; an output unit connected to the processing unit and multiple storage units, used to output the word line address stored in the corresponding storage unit according to the counter data.

[0014] In some embodiments, the processing unit includes multiple comparison subunits, each comparison subunit includes: an output comparator and a multiplexer; the multiplexer has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to input the value of a counter, the second input terminal is used to input the value of another counter, and the output terminal is used to output the larger of the value of the first input terminal and the value of the second input terminal; the output comparator is connected to the multiplexer and is configured to control the output of the multiplexer based on the comparison of the value of the first input terminal and the value of the second input terminal; multiple comparison subunits are connected in sequence to output the maximum data in multiple counters.

[0015] In some embodiments, the multiplexer further includes a third input terminal, a fourth input terminal, and a character output terminal; the third input terminal is used to input the address of the counter corresponding to the value inputted by the first input terminal; the fourth input terminal is used to input the address of the counter corresponding to the value inputted by the second input terminal; and the character output terminal is used to output the address of the counter corresponding to the value outputted by the output terminal. The address of counter 103 facilitates subsequent querying of the word line address stored in storage unit 101 corresponding to counter 103 based on the address of counter 103.

[0016] In some embodiments, the processing unit includes an output comparator, a multiplexer and a comparison memory; the multiplexer has a first input terminal, a second input terminal and an output terminal, the first input terminal is used to input the value of a counter, the second input terminal and the output terminal are connected to the comparison memory, the output terminal is used to output the larger value of the value of the first input terminal and the value of the second input terminal, the comparison memory is used to store the output value of the output terminal and input the output value to the second input terminal; the output comparator is connected to the multiplexer and is configured to control the multiplexer to output the larger value of the value of the first input terminal and the value of the second input terminal based on the comparison result of the value of the first input terminal and the value of the second input terminal; the comparison memory is also used to output the stored value of the counter.

[0017] In some embodiments, the multiplexer further includes a third input terminal, a fourth input terminal, and a character output terminal; the third input terminal is used to input the address of a counter corresponding to the value inputted by the first input terminal; the fourth input terminal and the character output terminal are connected to a comparison memory, and the character output terminal is used to output the address of the counter corresponding to the value outputted by the output terminal. The comparison memory is further used to store the address of the counter and input the address of the counter to the fourth input terminal. The address of counter 103 facilitates subsequent querying of the word line address stored in storage unit 101 corresponding to counter 103 based on the address of counter 103.

[0018] In some embodiments, the output comparator is specifically configured to, if the value of the first input terminal is greater than or equal to the value of the second input terminal, control the output terminal of the multiplexer to output the value of the first input terminal, otherwise control the output terminal of the multiplexer to output the value of the second input terminal; or, if the value of the first input terminal is less than the value of the second input terminal, control the output terminal of the multiplexer to output the value of the second input terminal, otherwise control the output terminal of the multiplexer to output the value of the first input terminal.

[0019] In some embodiments, the monitoring circuit further includes a first switch module connected to the storage determination module and configured so that when the first switch module is turned on, the storage determination module operates. The operation of the monitoring circuit is controlled by the first switch module to avoid resource consumption when monitoring is not required.

[0020] In some embodiments, the monitoring circuit further includes a second switch module connected to the processing output module and configured such that when the second switch module is turned on, the processing output module operates. The second switching module controls the output of the monitoring circuit to avoid erroneous output from the monitoring circuit when the word line address is not fully turned on.

[0021] The disclosed embodiment also provides a statistical method, which is applied to the above-mentioned monitoring circuit, including: obtaining the address of the currently turned-on word line; determining whether the turned-on word line address has been stored in a storage unit, if the turned-on word line address has been stored in the storage unit, then counting the corresponding counter of the storage unit; if the turned-on word line address has not been stored in the storage unit, then storing the word line address in the storage unit; comparing the counters corresponding to all memories that have stored word line addresses, and obtaining the word line address stored in the storage unit with the largest counter.

[0022] The embodiment of the present disclosure further provides a memory, which applies the above-mentioned monitoring circuit and protects the word line corresponding to the word line address based on the acquired word line address. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a monitoring circuit provided in one embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of a specific circuit structure of a monitoring circuit provided in one embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of the structure of a processing unit provided in one embodiment of the present disclosure;

[0026] Figure 4 A schematic structural diagram of a comparison subunit provided in one embodiment of the present disclosure;

[0027] Figure 5Another structural diagram of a processing unit provided in one embodiment of the present disclosure;

[0028] Figure 6 A flowchart of a statistical method provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As known from the background art, frequent or long-term activation of the WL may cause charge loss in adjacent memory cells, which may cause errors in the data stored in the memory cells.

[0030] The embodiment of the present disclosure provides a monitoring circuit to obtain the word line address that is turned on the most times. Through the obtained word line address, the memory is subsequently optimized to avoid the loss of charge in adjacent storage cells due to frequent turning on of the word line.

[0031] Those skilled in the art will appreciate that, in the various embodiments of the present disclosure, many technical details are provided to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0032] Figure 1 A schematic diagram of the general circuit structure of the monitoring circuit provided in this embodiment is shown in FIG. Figure 2 A schematic diagram of the specific circuit structure of the monitoring circuit provided in this embodiment, Figure 3 A schematic diagram of the structure of the processing unit provided in this embodiment. Figure 4 A schematic diagram of the structure of the comparison subunit provided in this embodiment, Figure 5 This is another structural diagram of the processing unit provided in this embodiment. The monitoring circuit provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0033] refer to Figure 1 , monitoring circuit, including:

[0034] A plurality of storage units 101 , a plurality of comparators 102 and a plurality of counters 103 , wherein each storage unit 101 is used to store a word line address, and each storage unit 101 corresponds to a comparator 102 and a counter 103 .

[0035] Figure 1 In the embodiment, 8 storage units 101, 8 comparators 102, and 8 counters 103 are used as an example for specific description, which does not constitute a limitation of this embodiment. In other embodiments, the number of storage units, comparators, and counters can be set according to the specific application scenario.

[0036] Among them, storage unit n is correspondingly connected to comparator n and counter n, and n is a natural number greater than or equal to 1 and less than or equal to 8; storage unit 1 stores word line address 1, storage unit 2 stores word line address 2, storage unit 3 stores word line address 3, storage unit 4 stores word line address 4, and storage units after storage unit 5 do not store word line addresses, that is, empty storage units.

[0037] The storage judgment module 104 is used to receive the word line address that is currently turned on and is configured to: based on the comparator 102 corresponding to the storage unit 101 that has stored the word line address, compare in sequence whether the word line address stored in the storage unit is the same as the turned-on word line address; if there is a storage unit 101 that is the same as the turned-on word line address, then instruct the count value of the counter 103 corresponding to the storage unit 101 that stores the same word line address to be increased by one; if there is no storage unit 101 that is the same as the turned-on word line address, then the turned-on word line address is stored in the storage unit 101 that has not written the word line address.

[0038] Corresponding to Figure 1 Assume that the storage judgment module 104 receives the turned-on word line address, and the storage unit 101 storing the word line address, i.e., storage unit 1 to storage unit 4, and the comparators 1 to comparator 4 corresponding to storage unit 1 to storage unit 4 respectively compare with the storage judgment module 104. If the comparison values ​​are the same, it proves that the turned-on word line address has been stored in storage unit 101, and the counter 103 corresponding to the comparator 102 increases the count by one; if the comparison values ​​are different, it proves that the turned-on word line address has not been stored in storage unit 101, and the turned-on word line address is stored in a new storage unit.

[0039] The storage unit 101 is connected to a comparator 102 for comparing whether the currently enabled word line address is stored in the storage unit 101, and storing the unstored enabled word line address through the storage unit 101. The storage unit 101 is also connected to a counter 103 for counting the word line addresses that are enabled multiple times, that is, counting the number of times the word line address is enabled.

[0040] It should be noted that, in one example, the initial value of the counter 103 is 1, that is, after the storage unit 101 stores data, the counter 103 represents that the word line address stored in the storage unit 101 is turned on once; in other embodiments, it is only necessary that the initial value of the counter is the same, and the specific initial value can be any value.

[0041] The processing and output module 105 is configured to: based on the comparison of the values ​​of the counters 103 , output the word line address stored in the storage unit 101 corresponding to the counter 103 with the largest value.

[0042] By comparing between the counters 103, the word line address that is turned on the most times is output, thereby monitoring the number of times the word line is turned on. By obtaining the word line address, the memory is subsequently optimized to avoid charge loss in adjacent storage cells due to frequent word line turning on.

[0043] It should be noted that in this embodiment, the counter 103 counts in an ascending manner, and the word line address stored in the storage unit 101 corresponding to the counter 103 that outputs the maximum value is subsequently compared, i.e., the word line address that has been activated the most times. In other embodiments, the counter may also count in a descending manner, and the word line address stored in the storage unit corresponding to the counter that outputs the minimum value is subsequently compared, i.e., the word line address that has been activated the most times.

[0044] In some embodiments, reference Figure 2 The storage judgment module 104 includes: a receiving unit 114 and a control unit 124; the receiving unit 114 is used to receive the word line address to be turned on; the control unit 124 is connected to the receiving unit 114, multiple storage units 101 and the comparator 102 corresponding to the storage unit 101; if there is a storage unit 101 with the same address as the turned on word line, the control unit 124 instructs the counter 103 corresponding to the storage unit 101 to count up by one, and if there is no storage unit 101 with the same address as the turned on word line, the control unit 124 stores the turned on word line address in the storage unit 101 that has not written the word line address.

[0045] Specifically, in one example, if there is a storage cell 101 with the same address as the enabled word line, the control unit 124 instructs the counter 103 corresponding to the storage cell 101 to count up by one; if there is no storage cell 101 with the same address as the enabled word line, the control unit 124 stores the enabled word line address in a storage cell 101 that has not been written with the word line address, including:

[0046] If there is a storage cell 101 with the same address as the word line to be turned on, the control unit 124 generates a first control signal and a second control signal, and the counter 103 corresponding to the storage cell 101 storing the word line address to be turned on counts one based on the first control signal, and the second control signal is used to indicate that the word line address to be turned on is prevented from being stored in the storage cell 101.

[0047] If the comparator 102 corresponding to the storage unit 101 storing the enabled word line address does not generate the first control signal and the second control signal, it indicates that the currently enabled word line address is not stored in the storage unit 101 , and the currently enabled word line address is stored in the storage unit 101 .

[0048] In some embodiments, the plurality of storage units 101 are arranged in the form of a linked list. Figure 1 and Figure 2 If a linked list is used, if a new word line address needs to be stored, the word line address is directly stored in the storage unit 5.

[0049] In some embodiments, the plurality of storage units 101 are arranged in a queue. Figure 1 and Figure 2 If a queue formation setting is adopted, if a new word line address needs to be stored at this time, storage unit 4 moves the data down to storage unit 5, storage unit 3 moves the data down to storage unit 4, storage unit 2 moves the data down to storage unit 3, storage unit 1 moves the data down to storage unit 2, and the new word line address is stored in storage unit 1; it should be noted that in the process of data downshifting of storage unit 101, the comparator 102 and counter 103 corresponding to storage unit 101 will move together with the storage unit 101.

[0050] In some embodiments, each memory cell further includes a flag bit, wherein the flag bit includes a valid flag bit and an invalid flag bit. The valid flag bit is used to indicate that the memory cell 101 has stored a word line address, and the invalid flag bit is used to indicate that the memory cell 101 is storing a word line address. The valid flag bit is also used to turn on the comparator 102 and counter 103 corresponding to the memory cell 101. By turning on the comparator 102 connected to the memory cell 101 via the flag bit, the process of comparing the memory cell 101 that does not store a word line address with the currently enabled word line address through the comparator 102 is eliminated, thereby optimizing the process of monitoring the number of times the word line address is turned on.

[0051] It should be noted that in specific applications, the flag bit can be one bit or multiple bits. This embodiment does not constitute a limitation on the number of bits of the flag bit. Solutions that conform to the flag bit setting method mentioned in this disclosure should all fall within the scope of protection of this disclosure.

[0052] In some embodiments, reference Figure 2 , initial output module 105 (reference Figure 1 ), including: a processing unit 115 and an output unit 125; the processing unit 115 is connected to the counters 103 corresponding to the multiple storage units 101, and is used to compare the values ​​of the multiple counters 103 and output the counter data with the largest value; the output unit 125 is connected to the processing unit 115 and the multiple storage units 101, and is used to output the word line address stored in the corresponding storage unit 101 according to the counter data.

[0053] Regarding the processing unit 115, the embodiment of the present disclosure provides two implementations of the processing unit 115, as follows:

[0054] In one example, refer to Figure 3and Figure 4 , processing unit 115 (reference Figure 2 ) includes multiple comparison sub-units 200, each comparison sub-unit 200 includes: an output comparator 202 and a multiplexer 201.

[0055] The multiplexer 201 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to input the value of a counter 103, the second input terminal is used to input the value of another comparator 103, and the output terminal is used to output the larger of the value of the first input terminal and the value of the second input terminal; the output comparator 202 is connected to the multiplexer and is configured to control the output of the multiplexer based on the comparison between the value of the first output terminal and the value of the second input terminal.

[0056] The output comparator 202 is specifically configured to, if the value of the first input terminal is greater than or equal to the value of the second input terminal, control the output terminal of the multiplexer 201 to output the value of the first input terminal; otherwise, control the multiplexer 201 to output the value of the second input terminal; or, if the value of the first output terminal is less than the value of the second output terminal, control the output terminal of the multiplexer 201 to output the value of the second input terminal; otherwise, control the output port of the multiplexer 201 to output the value of the first input terminal.

[0057] The plurality of comparison subunits 200 are sequentially connected to output the maximum data in the plurality of counters 103. Figure 3 , the outputs of the plurality of comparison subunits 200 are compared in pairs by a comparison subunit 200 to generate a comparison output.

[0058] It should be noted that Figure 3 The number of comparison subunits 200 shown is only for illustration and does not constitute a limitation of this embodiment. In a specific application, the number of comparison subunits 200 is set according to the number of comparators 103 .

[0059] Further, refer to Figure 4 Multiplexer 201 further includes a third input terminal, a fourth input terminal, and a character output terminal. The third input terminal is used to input the address of counter 103 corresponding to the value inputted by the first input terminal, the fourth input terminal is used to input the address of counter 103 corresponding to the value inputted by the second input terminal, and the character output terminal is used to output the address of counter 103 corresponding to the value outputted by the output terminal. The address of counter 103 facilitates subsequent querying of the word line address stored in storage unit 101 corresponding to counter 103 based on the address of counter 103.

[0060] In one example, refer to Figure 5 , processing unit 115 (reference Figure 2) includes an output comparator 302, a multiplexer 301 and a comparison memory 303.

[0061] The multiplexer 301 has a first input terminal, a second input terminal and an output terminal. The first input terminal is used to input the value of a counter 103. The second input terminal and the output terminal are connected to a comparison memory 303. The output terminal is used to output the larger value of the value of the first input terminal and the value of the second input terminal. The comparison memory is used to store the output value of the output terminal and input the output value to the second input terminal. The output comparator 302 is connected to the multiplexer 301 and is configured to control the multiplexer to output the larger value of the value of the first input terminal and the value of the second input terminal based on the comparison result of the value of the first input terminal and the value of the second input terminal.

[0062] The output comparator 302 is specifically configured to, if the value of the first input terminal is greater than or equal to the value of the second input terminal, control the output terminal of the multiplexer 301 to output the value of the first input terminal; otherwise, control the multiplexer 301 to output the value of the second input terminal; or, if the value of the first output terminal is less than the value of the second output terminal, control the output terminal of the multiplexer 301 to output the value of the second input terminal; otherwise, control the output port of the multiplexer 301 to output the value of the first input terminal.

[0063] The comparison memory 303 is also used to output the stored value of the counter 103. Figure 5 The larger value of the counter after each comparison is stored in the comparison memory 303. The value in the comparator memory 303 is compared with the new counter 103 value, and the maximum data in multiple comparators 103 is obtained after multiple cycles.

[0064] Further, refer to Figure 5 Multiplexer 301 further includes a third input terminal, a fourth input terminal, and a character output terminal. The third input terminal is used to input the address of counter 103 corresponding to the value inputted by the first input terminal. The fourth input terminal and the character output terminal are connected to comparison memory 303. The character output terminal is used to output the address of counter 103 corresponding to the value outputted by the output segment. Comparison memory 303 is further used to store the address of counter 103 and input the address of the counter to the fourth input terminal. The address of counter 103 facilitates subsequent querying of the word line address stored in storage unit 101 corresponding to counter 103 based on the address of counter 103.

[0065] In some embodiments, the monitoring circuit further includes: a first switch module (not shown), connected to the storage determination module 104 (refer to Figure 1), is configured such that the first switch module (not shown) is turned on and the storage determination module 104 works. The operation of the monitoring circuit is controlled by the first switch module to avoid resource consumption when no monitoring is required.

[0066] In some embodiments, the monitoring circuit further includes: a second switch module (not shown), connected to the processing output module 105 (refer to Figure 2 ), is configured such that the second switch module (not shown) is turned on and the processing output module 105 works. The output of the monitoring circuit is controlled by the second opening module to avoid erroneous output of the monitoring circuit when the statistical counting of the word line address is not completed.

[0067] The storage unit 101 is connected to a comparator 102 for comparing whether the currently turned-on word line address is stored in the storage unit 101, and storing the unstored turned-on word line address through the storage unit 101, and the storage unit 101 is connected to a counter 103 for counting the word line addresses that are turned on multiple times, that is, counting the number of word line addresses that are turned on; by comparing between the counters 103, the word line address that is turned on the most times is output, thereby realizing the monitoring of the number of word line turns on, and through the obtained word line address, the memory is optimized subsequently to avoid the loss of charge in adjacent storage cells due to frequent word line turning on.

[0068] All units involved in this embodiment are logical units. In actual applications, a logical unit can be a physical unit, a portion of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovations of this disclosure, this embodiment does not include units that are not closely related to solving the technical problems proposed by this disclosure. However, this does not mean that other units do not exist in this embodiment.

[0069] It should be noted that the features disclosed in the monitoring circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new circuit embodiments.

[0070] Another embodiment of the present disclosure provides a statistical method, which is applied to the monitoring circuit provided in the above embodiment to monitor the number of times a word line is turned on and output the address of the word line that is turned on the most times.

[0071] Figure 6 The following is a flow chart of the statistical method provided in this embodiment. The statistical method provided in this embodiment is further described in detail with reference to the accompanying drawings, as follows:

[0072] refer to Figure 6 , statistical methods, including:

[0073] Step 401: Obtain the address of the currently enabled word line.

[0074] Step 402: Process the acquired word line address.

[0075] Specifically, it is determined whether the word line address to be turned on has been stored in the storage unit. If the word line address to be turned on has been stored in the storage unit, the counter of the corresponding storage unit is counted. If the word line address to be turned on has not been stored in the storage unit, the word line address is stored in the storage unit.

[0076] Corresponding to Figure 1 Assume that the storage judgment module 104 receives the turned-on word line address, and the storage unit 101 storing the word line address, i.e., storage unit 1 to storage unit 4, and the comparators 1 to comparator 4 corresponding to storage unit 1 to storage unit 4 respectively compare with the storage judgment module 104. If the comparison values ​​are the same, it proves that the turned-on word line address has been stored in storage unit 101, and the counter 103 corresponding to the comparator 102 increases the count by one; if the comparison values ​​are different, it proves that the turned-on word line address has not been stored in storage unit 101, and the turned-on word line address is stored in a new storage unit.

[0077] The storage unit 101 is connected to a comparator 102 for comparing whether the currently enabled word line address is stored in the storage unit 101, and storing the unstored enabled word line address through the storage unit 101. The storage unit 101 is also connected to a counter 103 for counting the word line addresses that are enabled multiple times, that is, counting the number of times the word line address is enabled.

[0078] Step 403 , comparing and obtaining the word line address with the largest number of activation times.

[0079] Specifically, the counters corresponding to all memories that have stored word line addresses are compared, and the word line address stored in the storage unit with the largest counter is obtained.

[0080] By comparing between the counters 103, the word line address that is turned on the most times is output, thereby monitoring the number of times the word line is turned on. By obtaining the word line address, the memory is subsequently optimized to avoid charge loss in adjacent storage cells due to frequent word line turning on.

[0081] It should be noted that the description of the statistical method above is similar to the description of the monitoring circuit embodiment above, and has similar beneficial effects as the monitoring circuit embodiment, so it is not repeated here. For technical details not disclosed in the statistical method of the embodiment of the present disclosure, please refer to the description of the monitoring circuit in the embodiment of the present disclosure for understanding.

[0082] The stage division of the above-mentioned statistical methods is only for the purpose of clear description. During implementation, they can be merged into one statistical stage or some statistical stages can be split and decomposed into multiple statistical stages. As long as the logic of the statistical method is the same, it is within the scope of protection of this patent; in some embodiments, adding insignificant modifications or introducing insignificant designs to the above-mentioned statistical methods without changing the core design of the above-mentioned statistical methods are all within the scope of protection of this patent.

[0083] Another embodiment of the present disclosure provides a memory device that utilizes the monitoring circuits provided in the above embodiments to protect a word line corresponding to the word line address based on the acquired word line address. The memory device is optimized using the acquired word line address to prevent charge loss in adjacent memory cells due to frequent activation of the word line.

[0084] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with DDR2 memory specifications.

[0085] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with DDR3 memory specifications.

[0086] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with DDR4 memory specifications.

[0087] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip complies with the DDR5 memory specification.

[0088] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A monitoring circuit, characterized in that: include: A plurality of storage units, a plurality of comparators, and a plurality of counters, wherein each of the storage units is used to store a word line address, and each of the storage units corresponds to one of the comparators and one of the counters; a storage determination module, configured to receive a currently enabled word line address and to: based on the comparator corresponding to the storage unit that has stored the word line address, sequentially compare whether the word line address stored in the storage unit is the same as the enabled word line address; if there is a storage unit that is the same as the enabled word line address, instruct the count value of the counter corresponding to the storage unit to increase by one; if there is no storage unit that is the same as the enabled word line address, then store the enabled word line address in a storage unit that has not written a word line address; a processing output module configured to: output the word line address stored in the storage unit corresponding to the counter with the largest value based on comparison of the values ​​of the counters, the processing output module comprising a processing unit, the processing unit comprising a plurality of comparison subunits, each of the comparison subunits comprising: an output comparator and a multiplexer; The multiplexer has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to input a value of one of the counters, the second input terminal is used to input a value of another of the counters, and the output terminal is used to output the larger of the value of the first input terminal and the value of the second input terminal; The output comparator is connected to the multiplexer and is configured to control the output of the multiplexer based on a comparison between a value of the first input terminal and a value of the second input terminal; The plurality of comparison subunits are connected in sequence to output the maximum data in the plurality of counters.

2. The monitoring circuit according to claim 1, wherein: Each of the storage units also has a flag bit; The flag bit includes a valid flag bit and an invalid flag bit, wherein the valid flag bit is used to indicate that the memory cell has stored a word line address, and the invalid flag bit is used to indicate that the memory cell has not stored a word line address; The valid flag is further used to turn on the comparator and the counter corresponding to the storage unit.

3. The monitoring circuit according to claim 1, wherein: The plurality of storage units are arranged in the form of a linked list.

4. The monitoring circuit according to claim 1, wherein: The plurality of storage units are arranged in the form of a queue.

5. The monitoring circuit according to claim 1, wherein: The storage judgment module includes: A receiving unit, configured to receive the enabled word line address; a control unit connected to the receiving unit, the plurality of storage units, and the comparators corresponding to the storage units; If there is a storage cell with the same address as the word line that is turned on, the control unit instructs the counter corresponding to the storage cell to count up by one; if there is no storage cell with the same address as the word line that is turned on, the control unit stores the turned on word line address in a storage cell that has not written the word line address.

6. The monitoring circuit according to claim 5, characterized in that: If there is a storage unit with the same address as the turned-on word line, the control unit instructs the counter corresponding to the storage unit to count up by one, including: If there is a memory cell with the same address as the turned-on word line, the control unit generates a first control signal and a second control signal; The counter corresponding to the storage unit storing the turned-on word line address is incremented by one based on the first control signal; The second control signal is used to instruct to prevent the enabled word line address from being stored in the memory unit.

7. The monitoring circuit according to claim 1, wherein: The processing output module includes: a processing unit connected to the counters corresponding to the plurality of storage units, configured to compare the values ​​of the plurality of counters and output the counter data with the largest value; An output unit is connected to the processing unit and the plurality of storage units, and is used to output the word line address stored in the corresponding storage unit according to the counter data.

8. The monitoring circuit according to claim 1, wherein: The multiplexer further comprises a third input terminal, a fourth input terminal and a character output terminal; The third input terminal is used to input the address of the counter corresponding to the value inputted by the first input terminal; The fourth input terminal is used to input the address of the counter corresponding to the value inputted by the second input terminal; The character output terminal is used to output the address of the counter corresponding to the value output by the output terminal.

9. The monitoring circuit according to claim 7, wherein: The processing unit includes an output comparator, a multiplexer and a comparison memory; The multiplexer has a first input terminal, a second input terminal and an output terminal, The first input terminal is used to input a value of the counter, the second input terminal and the output terminal are connected to the comparison memory, the output terminal is used to output the larger value of the value of the first input terminal and the value of the second input terminal, and the comparison memory is used to store the output value of the output terminal and input the output value to the second input terminal; The output comparator is connected to the multiplexer and is configured to control the multiplexer to output the larger value of the value of the first input terminal and the value of the second input terminal based on a comparison result of the value of the first input terminal and the value of the second input terminal; The comparison memory is further used to output the stored value of the counter.

10. The monitoring circuit according to claim 9, characterized in that: The multiplexer further comprises a third input terminal, a fourth input terminal and a character output terminal; The third input terminal is used to input the address of the counter corresponding to the value inputted by the first input terminal; The fourth input terminal and the character output terminal are connected to the comparison memory, the character output terminal is used to output the address of the counter corresponding to the numerical value output by the output terminal, and the comparison memory is also used to store the address of the counter and input the address of the counter to the fourth input terminal.

11. The monitoring circuit according to claim 1, wherein: The output comparator is specifically configured as follows: If the value of the first input terminal is greater than or equal to the value of the second input terminal, control the output terminal of the multiplexer to output the value of the first input terminal; otherwise, control the output terminal of the multiplexer to output the value of the second input terminal; Alternatively, if the value of the first input terminal is smaller than the value of the second input terminal, the output terminal of the multiplexer is controlled to output the value of the second input terminal; otherwise, the output terminal of the multiplexer is controlled to output the value of the first input terminal.

12. The monitoring circuit according to claim 1, wherein: Also includes: The first switch module is connected to the storage determination module and is configured so that when the first switch module is turned on, the storage determination module works.

13. The monitoring circuit according to claim 1, wherein: Also includes: The second switch module is connected to the processing output module and is configured so that when the second switch module is turned on, the processing output module works.

14. A statistical method, applied to the monitoring circuit according to any one of claims 1 to 13, characterized in that: include: Get the address of the word line currently turned on; determining whether the enabled word line address has been stored in a storage unit, if the enabled word line address has been stored in the storage unit, counting a counter corresponding to the storage unit, and if the enabled word line address has not been stored in the storage unit, storing the word line address in the storage unit; The counters corresponding to all the storage units that have stored word line addresses are compared to obtain the word line address stored by the storage unit with the largest counter.

15. A memory, applied to the monitoring circuit according to any one of claims 1 to 13, characterized in that: Based on the acquired word line address, a word line corresponding to the word line address is protected.

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