Memory device, control circuit and operating method thereof

Abstract

In some aspects of the disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input / output (I / O) interface connected to the plurality of memory cells to output a data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal from an input clock signal and a chip enable (CE) signal, and to provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal from the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal from the second clock signal or the third clock signal. Embodiments of the present application also provide the control circuit and methods of operation thereof.

Description

Technical Field

[0001] Embodiments of this application relate to storage devices, control circuits, and methods of operation thereof. Background Technology

[0002] Modern system-on-a-chip (SoC) designs can contain a large amount of memory. This memory may occupy a significant portion of the SoC, and any failure in the memory can affect the SoC's operation. Therefore, design-for-test (DFT) methodologies can be used to screen for faulty chips. DFT can be implemented as a section of circuitry on a chip, board, or system used to test the circuitry itself. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a storage device is provided, comprising: a plurality of memory cells arranged in an array; an input / output (I / O) interface connected to the plurality of memory cells to output a data signal from each memory cell; and a control circuit, comprising: a first clock generator for generating a first clock signal and a second clock signal based on an input clock signal and a chip enable (CE) signal, and providing the first clock signal to the plurality of memory cells; and a second clock generator for generating a third clock signal based on the input clock signal and a design-for-testability (DFT) enable (DFTEN) signal; wherein the control circuit generates an output clock signal based on the second clock signal or the third clock signal.

[0004] According to another aspect of the embodiments of this application, a control circuit is provided, comprising: a first clock generator for generating a task mode clock (MDCK) signal based on an input clock signal and a chip enable (CE) signal; a second clock generator for generating a design-for-testability (DFT) mode clock (DDCK) signal based on an input clock signal and a DFT enable (DFTEN) signal; and a logic gate for generating an output clock signal based on the MDCK signal or the DDCK signal.

[0005] According to another aspect of the embodiments of this application, a method for operating a control circuit is provided, comprising: receiving an input clock signal, a chip enable signal, and a design-for-testability (DFT) enable (DFTEN) signal; generating a DFT mode clock (DDCK) signal and a task mode clock (MDCK) signal based on the input clock signal, the chip enable signal, and the DFTEN signal; and providing an output clock signal based on the DDCK signal or the MDCK signal. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1 A block diagram of a memory system according to some embodiments of the present disclosure is shown.

[0008] Figures 2A-2D A block diagram of a global control circuit according to some embodiments of the present disclosure is shown.

[0009] Figure 3 A circuit diagram of a Design for Testability (DFT) mode clock (DDCK) generator (DFT_CLK) according to some embodiments of the present disclosure is shown.

[0010] Figure 4 A flowchart illustrating a method for operating a global control circuit according to some embodiments of the present disclosure is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for brevity and clarity, but does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0013] This disclosure provides various embodiments of memory circuits, methods, and devices that employ separate clock generators for task-mode operation and design-for-testability (DFT) operation. Advantageously, embodiments of the memory circuits, methods, and devices improve system-level power and performance because sub-blocks are individually tuned. Power, performance, and area (PPA) can be independently tuned for DFT operation without affecting task mode. Similarly, PPA can be independently tuned for task mode without affecting DFT mode.

[0014] This disclosure provides various embodiments of memory circuits, methods, and devices for enabling or disabling a global clock within a global control circuit. Advantageously, embodiments of the memory circuits, methods, and devices improve setup and hold times, DFT cycle times, and achieve higher operating frequencies. Particularly in applications with long routes between the memory bank and the global control circuit, embodiments of the memory circuits, methods, and devices avoid long setup and hold times for the global clock by enabling or disabling the global clock within the global control circuit.

[0015] Figure 1 A block diagram of a memory system 100 according to some embodiments of the present disclosure is shown. The memory system 100 may be referred to as a memory device. The memory system 100 includes a global control circuit (GCTRL) 105. In some embodiments, the GCTRL 105 performs separate clock generation for task-mode operation and design-for-testability (DFT) operation. Task-mode operation may also be referred to as normal operation. The GCTRL 105 may be referred to as control circuitry.

[0016] GCTRL 105 includes multiple inputs. GCTRL 105 receives the Chip Enable, Active Low (CEB) signal via CEB line 110. The Chip Enable, Active Low signal can be referred to as the Chip Enable (CE) signal. GCTRL 105 receives the Clock (CLK) signal via CLK line 115. GCTRL 105 receives the Scan Enable (SE) signal via SE line 120. GCTRL 105 receives the DFT Bypass (DFTBYP) signal via DFTBYP line 125. Both the DFTBYP and SE signals can be used to enable DFT operation. The DFTBYP and SE signals can be referred to as DFT mode signals.

[0017] The signal generated from the OR operation of the DFTBYP and SE signals can be referred to as the DFT enable (DFTEN) signal. In some embodiments, the memory device 100 is in DFT mode in response to the DFTEN signal being in a first logic state. In some embodiments, the memory device 100 is in task mode in response to the DFTEN signal being in a second logic state. In some embodiments, the first logic state is a high logic state (e.g., 1, 1V, etc.) and the second logic state is a low logic state (e.g., 0, 0V, etc.).

[0018] GCTRL 105 includes multiple outputs. GCTRL 105 provides a global clock (GCK) signal via GCK line 130, which couples GCTRL 105 to LCTRL 135. In some embodiments, GCK is enabled during task mode. Memory system 100 includes Local Control Line (LCTRL) 135. In some embodiments, LCTRL 135 receives the GCK signal via GCK line 130. In some embodiments, it is advantageous for GCK line 130 to be long enough to enable or disable the GCK signal in GCTRL 105 so as not to cause delays in sending the GCK signal to LCTRL 135 and enabling or disabling the GCK signal in LCTRL 135. For example, the length of GCK line 130 may be greater than 10 micrometers, 100 micrometers, 200 micrometers, or any distance of various kinds, while still within the scope of this disclosure.

[0019] GCTRL 105 provides the DFT or task mode clock (DCK) signal via DCK line 140. The DCK signal is enabled during DFT mode or task mode. In some embodiments, DFT mode requires disabling GCK and GCK-related signals, such as word lines, bit lines, select lines, and read / write related signals. Memory system 100 includes global input / output (GIO) circuitry 145. GIO 145 receives DCK line 140 via DCK line 140.

[0020] Table 1 shows exemplary signal combinations that can enable the GCK and DCK signals. In some embodiments, "1" indicates enable and "0" indicates disable.

[0021] CLK CEB DFTEN GCK DCK 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 0 1

[0022] Table 1

[0023] Memory system 100 includes memory bank 150. Memory bank 150 may include multiple memory cells. Memory cells can be operated according to word lines, bit lines, select lines, and read / write associated signals. Although only one memory bank 150 is shown, memory system 100 may include two or more memory banks 150 without departing from the scope of this disclosure. Memory system 100 includes local input / output (LIO) circuitry 155. LIO 155 can perform I / O operations on memory bank 150. In some embodiments, LIO 155 outputs data signals from memory bank 150. In some embodiments, the distance between GCTRL 105 and each of LCTRL 135, memory bank 150, and LIO 155 is greater than 10 micrometers, 100 micrometers, 200 micrometers, or any of various distances, still within the scope of this disclosure. In some embodiments, LIO 155 is referred to as an I / O interface. Although only one LIO 155 is shown, LIO 155 may include two or more LIO 155 without departing from the scope of this disclosure. In some embodiments including two or more LIO 155s, each LIO 155 can perform I / O operations for a corresponding memory bank 150. In some embodiments, at least one of the memory bank 150 or LIO 155 receives a GCK signal via GLCK line 130. In some embodiments, the distance between GCTRL 105 and each of LCTRL 135, memory bank 150, and LIO 155 can be increased or decreased by orders of magnitude. This length is determined by the size of the memory bank 150.

[0024] Figures 2A-2D A block diagram of GCTRL 105 according to some embodiments of the present disclosure is shown. Figure 2A A block diagram of the GCTRL105A is shown, which is one implementation of the GCTRL105. The GCTRL105A includes a DFT mode clock (DDCK) generator (DFT_CLK) 205. The DFT_CLK 205 is designed, configured, and operated to generate DDCK. The DFT_CLK 205 receives the CLK signal, SE signal, and DFTBYP signal via CLK line 115, SE line 120, and DFTBYP line 125, respectively. In some embodiments, the DFT_CLK 205 provides the DDCK signal and DFTEN signal via DDCK line 225 and DFTEN line 220, respectively. (Refer to...) Figure 3 The circuit for generating the DDCK signal will be discussed further. The DFT_CLK 205 can generate the DFTEN signal by performing a logical "OR" operation on the SE and DFTYP signals.

[0025] The GCTRL 105A includes a task-mode clock generator (CLK_GEN) 210. CLK_GEN 210 is designed, configured, and operated to generate a task-mode clock. CLK_GEN 210 receives the CLK signal, CE signal, and DFTEN signal via CLK line 115, CEB line 110, and DFTEN line 220, respectively. CLK_GEN 210 provides the GCK signal and the task-mode clock (MDCK) signal via GCK line 130 and MDCK line 230, respectively. The GCK signal is the task-mode clock sent to other circuit blocks such as the LCTRL 135, and the MDCK signal is the task-mode signal used to generate signals sent to global circuits such as the GIO. In some embodiments, CLK_GEN 210 disables the GCK and MDCK signals in response to receiving an enabled DFTEN signal.

[0026] The GCTRL 105A includes an OR gate 215. The OR gate 215 receives the DDCK signal and the MDCK signal via DDCK line 225 and MDCK line 230, respectively. The OR gate 215 performs an OR operation on the DDCK and MDCK signals to generate a DCK signal. The OR gate 215 provides the DCK signal via DCK line 140. Advantageously, using an OR gate to generate a DCK signal from the MDCK and DDCK signals results in less delay than using multiple cascaded logic gates.

[0027] Table 2 shows exemplary signal combinations that enable GCK, DDCK, MDCK, and DCK signals.

[0028] CLK CEB DFTE GCK DDC MDC DCK 1 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 0 1

[0029] Table 2

[0030] In some embodiments, in response to a DFTEN signal in a first logic state (e.g., an "OR" operation of the DFTBYP and SE signals), the storage device 100 is in DFT mode, and the DCK signal generated by GCTRL 105 follows the DDCK signal. In some embodiments, in response to a DFTEN signal in a second logic state, the storage device 100 is in task mode, and the DCK signal generated by GCTRL 105 follows the MDCK signal. In some embodiments, the first logic state is a high logic state (e.g., "1", enabled, etc.), while the second logic state is a low logic state (e.g., "0", disabled, etc.).

[0031] Figure 2BA block diagram of GCTRL 105B is shown, which is one implementation of GCTRL 105. GCTRL 105B can be an implementation of GCTRL 105A. GCTRL 105B includes an OR gate 235. OR gate 215 receives the SE signal and the DFTYP signal via SE line 120 and DFTYP line 125, respectively. OR gate 215 performs an OR operation on the SE signal and the DFTYP signal to generate a DFTEN signal. In some embodiments, OR gate 215 provides the DFTEN signal to DFT_CLK 205 via DFTEN line 238. In some embodiments, DFT_CLK 205 provides a buffered DFTEN signal to CLK_GEN 210 via DFTEN line 220. The difference between the operation of GCTRL 105B and GCTRL 105A is that in GCTRL 105B, signals SE and DFTBYP are handled by OR logic outside DFT_CLK 205, while in GCTRL 105A, signals SE and DFTBYP are handled by OR logic inside DFT_CLK 205.

[0032] Figure 2C The diagram shows a block diagram of GCTRL 105C, which is one implementation of GCTRL 105. GCTRL 105C is similar to... Figure 2A The GCTRL 105A, except that the GCTRL 105C includes a NOR gate 240 and an inverter 250 instead of an OR gate 215. The advantage of using the NOR gate 240 and inverter 250 is that the NOR gate 240 can be of a first size and the inverter 250 can be sized based on the load to which the GCTRL 105C is coupled via the DCK line 140. The first size can be a fixed size and / or a standard size. In some embodiments, Figure 2A The OR gate 215 can be implemented as a NOR gate 240 and an inverter 250.

[0033] NOR gate 240 receives the DDCK and MDCK signals via DDCK line 225 and MDCK line 230, respectively. NOR gate 240 performs a NOR operation on the DDCK and MDCK signals to generate the DCKB signal. NOR gate 240 provides the DCKB signal via DCKB line 245. Inverter 250 receives the DCKB signal via DCKB line 245. Inverter 250 performs a NOT operation on the DCKB signal to generate the DCK signal. Inverter 250 provides the DCK signal via DCK line 140.

[0034] Figure 2D The diagram shows a block diagram of GCTRL 105D, which is one implementation of GCTRL 105. GCTRL 105D is similar to... Figure 2AThe GCTRL 105A, except that the GCTRL 105D includes inverters 260 and 265 and a NAND gate 275 instead of an OR gate 215. The advantage of using inverters 260, 265, and NAND gate 275 is that the NAND logic is low-cost, high-density, and supports high-speed programming / erasing applications. In some embodiments, Figure 2A The OR gate 215 is implemented as inverter 260, inverter 265 and NAND gate 275.

[0035] Inverter 260 receives the DDCK signal via DDCK line 225. Inverter 260 performs a NOT operation on the DDCK signal to generate the DDCKB signal. Inverter 260 provides the DDCKB signal via DDCKB line 270. Inverter 265 receives the MDCK signal via MDCK line 230. Inverter 265 performs a NOT operation on the MDCK signal to generate the MDCKB signal. Inverter 265 provides the MDCKB signal via MDCKB line 275.

[0036] NAND gate 275 receives the DDCKB and MDCKB signals via DDCKB line 270 and MDCKB line 275, respectively. NAND gate 275 performs a NAND operation on the DDCKB and MDCKB signals to generate the DCK signal. NAND gate 275 provides the DCK signal via DCK line 140. The operation of GCTRL 105D differs from that of GCTRL 105A in that, in GCTRL 105D, signals DDCK and MDCK are inverted and processed by NAND logic, while in GCTRL 105A, signals DDCK and MDCK are processed by OR logic.

[0037] Figure 3A circuit diagram of a DDCK generator (DFT_CLK) 205 according to some embodiments of the present disclosure is shown. DFT_CLK 205 includes circuits 305, 310, 315, and 320. Circuit 305 can be described as a NAND performing CLK and DFTEN. Circuit 305 includes transistors M1, M2, and M3. The gate of M1 is coupled to INIT line 325, and the source of M1 is coupled to a first voltage rail. INIT line 325 provides an initialization (INIT) signal. In some embodiments, the INIT signal is in a first logic state when the memory system 100 is powered on, the power-on circuit is enabled, the pulse width control circuit is enabled, DFT is enabled, the clock is high, or a combination thereof. In some embodiments, the first logic state is a high logic state. In some embodiments, the INIT signal is the result of an AND operation of CLK and DFTEN. The first voltage rail can be a power supply voltage line that receives a supply voltage (e.g., 1V or any positive voltage). The gate of M2 is coupled to CLK line 115, and the drain of M2 is coupled to the drain of M1, which can be referred to as node N1. The gate of M3 is coupled to DFTEN line 220, the drain of M3 is coupled to the source of M2, and the source of M3 is coupled to a second voltage rail. The second voltage rail can be ground (e.g., 0V).

[0038] Circuit 310 includes transistors M4 and M5. Circuit 310 can be described as an inverter. The gate of M4 is coupled to node N1, and the source of M4 is coupled to a first voltage rail. The gate of M5 is coupled to node N1, and the drain of M5 is coupled to the drain of M4, which can be referred to as node N2. The source of M5 is coupled to a second voltage rail.

[0039] Circuit 315 includes transistors M6, M7, M8, M9, and M10. Circuit 315 can be described as performing NAND operations on DFTEN and CLK. The gate of M6 is coupled to DFTEN line 220, and the source of M6 is coupled to a first voltage rail. The gate of M7 is coupled to CLK line 115, the source of M7 is coupled to the first voltage rail, and the drain of M7 is coupled to the drain of M6, which can be referred to as node N3. The gate of M8 is coupled to node N2, the source of M8 is coupled to node N3, and the drain of M8 is coupled to node N1. The gate of M9 is coupled to node N2, and the drain of M9 is coupled to node N1. The gate of M10 is coupled to INIT line 325, the drain of M10 is coupled to the source of M9, and the source of M10 is coupled to a second voltage rail.

[0040] Circuit 320 includes transistors M11 and M12. Circuit 320 can be described as an inverter. The gate of M11 is coupled to node N1, the source of M11 is coupled to a first voltage rail, and the drain is coupled to DDCK line 225. The gate of M12 is coupled to node N1, the drain is coupled to DDCK line 225, and the source of M12 is coupled to a second voltage rail.

[0041] In operation, blocks 305-320 and transistors M1-M12 operate according to the inputs INIT, CLK, and DFTEN to generate the corresponding DDCK. An example operation is described for INIT=1, CLK=1, and DFTEN=1, which generates DDCK=1. Block 305 receives the inputs INIT, CLK, and DFTEN at the corresponding transistors M1, M2, and M3. In response to INIT=1, M1 is turned off. In response to CLK=1, M2 is turned on. In response to DFTEN=1, M3 is turned on. Therefore, the signal at node N1 is 0 because it is coupled to ground through transistors M2 and M3.

[0042] Block 310 receives the signal at N1 from block 305. In response to the signal at N1 being 0, M4 is turned on and M5 is turned off. Therefore, the signal at node N2 is 1, because N2 is coupled to the power supply through transistor M4.

[0043] Block 315 receives inputs INIT, CLK, and DFTEN at the corresponding transistors M10, M7, and M6. Block 315 receives the signal at N2 from block 310 at transistors M8 and M9. In response to INIT = 1, M10 is turned on. In response to CLK = 1, M7 is turned off. In response to DFTEN = 1, M6 is turned off. In response to the signal at N2 = 1, M8 is turned off and M9 is turned on. Therefore, the signal at node N1 = 0, because N1 is coupled to ground through transistors M9 and M10 (and also through transistors M2 and M3 of block 305).

[0044] Block 320 receives the signal at N1 from blocks 305 and 315. In response to the signal at N1 being 0, M11 is turned off and M12 is turned on. Therefore, DDCK = 1, because the DDCK line 225 is coupled to the power supply through transistor M11.

[0045] An example table of operations for DFT_CLK 205 is shown in Table 3 below:

[0046] INIT CLK DFTE DDC 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1

[0047] Table 3

[0048] More generally, in response to the INIT signal voltage being below a first threshold, the drain of M1 is coupled to the source of M1 via a conductive channel. In response to the INIT signal voltage being above the first threshold, the drain of M1 is decoupled from the source of M1 via a conductive channel. In response to the CLK signal voltage being above a second threshold, the drain of M2 is coupled to the source of M2 via a conductive channel. In response to the CLK signal voltage being below the second threshold, the drain of M2 is decoupled from the source of M2 via a conductive channel. In response to the DFTEN signal voltage being above a third threshold, the drain of M3 is coupled to the source of M3 via a conductive channel. In response to the DFTEN signal voltage being below the third threshold, the drain of M3 is decoupled from the source of M3 via a conductive channel.

[0049] In response to the voltage at node N1 falling below the fourth threshold, the drain of M4 is coupled to the source of M4 via a conductive channel. In response to the voltage at node N1 falling above the fourth threshold, the drain of M4 is decoupled from the source of M4 via a conductive channel. In response to the voltage at node N1 falling above the fifth threshold, the drain of M5 is coupled to the source of M5 via a conductive channel. In response to the voltage at node N1 falling below the fifth threshold, the drain of M5 is decoupled from the source of M5 via a conductive channel. In response to the voltage of the DFTEN signal falling below the sixth threshold, the drain of M6 is coupled to the source of M6 via a conductive channel. In response to the voltage of the DFTEN signal falling above the sixth threshold, the drain of M6 is decoupled from the source of M6 via a conductive channel.

[0050] In response to the CLK signal voltage falling below the seventh threshold, the drain of M7 is coupled to the source of M7 via a conductive channel. In response to the CLK signal voltage rising above the seventh threshold, the drain of M7 is decoupled from the source of M7 via a conductive channel. In response to the N2 node voltage falling below the eighth threshold, the drain of M8 is coupled to the source of M8 via a conductive channel. In response to the N2 node voltage rising above the eighth threshold, the drain of M8 is decoupled from the source of M8 via a conductive channel. In response to the N2 node voltage rising above the ninth threshold, the drain of M9 is coupled to the source of M9 via a conductive channel. In response to the N2 node voltage falling below the ninth threshold, the drain of M9 is decoupled from the source of M9 via a conductive channel.

[0051] In response to the INIT signal voltage being higher than the tenth threshold, the drain of M10 is coupled to the source of M10 via a conductive channel. In response to the INIT signal voltage being lower than the tenth threshold, the drain of M10 is decoupled from the source of M10 via a conductive channel. In response to the N1 node voltage being lower than the eleventh threshold, the drain of M11 is coupled to the source of M11 via a conductive channel. In response to the N1 node voltage being higher than the eleventh threshold, the drain of M11 is decoupled from the source of M11 via a conductive channel. In response to the N1 node voltage being higher than the twelfth threshold, the drain of M12 is coupled to the source of M12 via a conductive channel. In response to the N1 node voltage being lower than the twelfth threshold, the drain of M12 is decoupled from the source of M12 via a conductive channel.

[0052] In response to the drain of M11 being coupled to the source of M11 and the drain of M12 being decoupled from the source of M12, the DDCK line is coupled to the source of M11, which is then coupled to the power supply voltage line. In response to the drain of M11 being decoupled from the source of M11 and the drain of M12 being coupled to the source of M12, the DDCK line is coupled to the source of M12, which is then coupled to the ground line.

[0053] The multiple transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), n-type MOSFETs (NMOS transistors), p-type MOSFETs (PMOS transistors), silicon-on-insulator (SOI) MOSFETs, bipolar junction transistors (BJTs), any other transistors suitable for memory structures, or combinations thereof. For example, M1, M4, M6, M7, M8, and M11 are PMOS transistors, while M2, M3, M5, M9, M10, and M12 are NMOS transistors, but other transistor choices are also within the scope of this disclosure. For applications where speed is a concern, NMOS transistors can be selected for the multiple transistors because, in some embodiments, read and write operations are faster using NMOS transistors than using PMOS transistors. Specifically, in some embodiments, the mobility of electrons as charge carriers in the case of NMOS transistors is approximately twice that of holes as charge carriers in PMOS transistors. For applications concerned with variation, cost, or noise, PMOS transistors can be selected for the multiple transistors because, in some embodiments, PMOS technology is a highly controllable, low-cost process compared to NMOS technology.

[0054] The multiple transistors can be any of a variety of transistor types, while still remaining within the scope of this disclosure. The multiple transistors can be one of the following: a MOS device type having a standard threshold voltage (SVT), a low threshold voltage (LVT), a high threshold voltage (HVT), a high voltage (HV), an input / output (IO), or a variety of other types of MOSFET devices.

[0055] Figure 4A flowchart illustrating a method 400 for operating the global control circuit 105 according to some embodiments of the present disclosure is provided. It should be noted that method 400 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional, fewer, or different operations may be performed. Figure 4 Method 400 is only briefly described here. Figure 4 Additional operations provided before, during, and after method 400, as well as other operations. In some embodiments, method 400 is executed by global control circuitry 105.

[0056] At operation 410, the global control circuitry (e.g., GCTRL 105) receives an input clock signal (e.g., the CLK signal via CLK line 115), a chip enable (e.g., low activation) signal (e.g., the CE signal via CEB line 110), and one or more DFT mode input signals (e.g., one or more of the following: the SE signal via SE line 120, the DFTBYP signal via DFTBYP line 125, or the DFTEN signal via DFTEN line 238). At operation 420, the global control circuitry generates a DDCK signal (e.g., the DDCK signal via DDCK line 225) and a task clock signal (e.g., the MDCK signal via MDCK line 230) based on the CLK signal, the CE signal, and one or more DFT mode input signals. At operation 430, the global control circuitry provides an output clock signal (e.g., the DCK signal via DCK line 140) based on either the DDCK signal or the MDCK signal. In some embodiments, the global control circuitry provides the DCK signal based on both the DDCK and MDCK signals.

[0057] In some embodiments, the DCK signal follows the DDCK signal in response to the DFT mode input signal being in a high logic state. In some embodiments, the DCK signal follows the MDCK signal in response to the DFT mode input signal being in a low logic state.

[0058] In some aspects of this disclosure, a storage device is disclosed. In some aspects, the storage device includes a plurality of memory cells arranged in an array, an input / output (I / O) interface connected to the plurality of memory cells to output data signals from each memory cell, and control circuitry. In some embodiments, the control circuitry includes a first clock generator for generating a first clock signal and a second clock signal based on a CLK signal and a CE signal, and providing the first clock signal to the plurality of memory cells. In some embodiments, the control circuitry includes a second clock generator for generating a third clock signal based on the CLK signal and a Design for Testability (DFT) Enable (DFTEN) signal. In some embodiments, the control circuitry generates a DCK signal based on either the second clock signal or the third clock signal.

[0059] In some embodiments, the control circuit performs a logical OR operation on the second clock signal and the third clock signal to generate the DCK signal. In some embodiments, the DFTEN signal is generated by performing a logical OR operation on the scan enable (SE) signal and the DFT bypass (DFTBYP) signal.

[0060] In some embodiments, in response to the DFTEN signal being in a high logic state, the storage device is in DFT mode, and the DCK signal generated by the control circuit follows a third clock signal. In some embodiments, in response to the DFTEN signal being in a low logic state, the DCK signal generated by the control circuit follows a second clock signal.

[0061] In some embodiments, the control circuit performs a NOR operation on the second and third clock signals to generate a fourth clock signal, which is then used to generate a DCK signal via an inverter. In some embodiments, the second clock signal is used to generate the fourth clock signal via a first inverter, and the third clock signal is used to generate the fifth clock signal via a second inverter. The control circuit then performs a NAND operation on the fourth and fifth clock signals to generate the DCK signal.

[0062] In some embodiments, a second clock generator provides a buffered DFTEN signal to a first clock generator. In some embodiments, the second clock generator generates a third clock signal based on the CLK signal, the DFTEN signal, and the INIT signal. In some embodiments, the distance between the control circuitry and each of the plurality of memory cells and the I / O interface is greater than 10 micrometers.

[0063] In some aspects of this disclosure, a control circuit is disclosed. In some embodiments, the control circuit includes a first clock generator for generating a task mode clock (MDCK) signal based on an input clock signal and a chip enable (CE) signal. In some embodiments, the control circuit includes a second clock generator for generating a design-for-test (DFT) mode clock (DDCK) signal based on an input clock signal and a DFT enable (DFTEN) signal. In some embodiments, the control circuit includes logic gates to generate an output clock signal based on either the MDCK signal or the DDCK signal.

[0064] In some embodiments, the control circuit performs a logical OR operation on the MDCK and DDCK signals to generate an output clock signal. In some embodiments, the DFTEN signal is generated by performing a logical OR operation on the scan enable (SE) and DFT bypass (DFTBYP) signals.

[0065] In some embodiments, the output clock signal generated by the logic gate is generated based on the DDCK signal in response to the DFTEN signal being in a high logic state. In some embodiments, the output clock signal generated by the logic gate is generated based on the MDCK signal in response to the DFTEN signal being in a low logic state.

[0066] In some embodiments, the control circuit performs a NOR operation on the MDCK and DDCK signals to generate a first clock signal, which is then used to generate an output clock signal via an inverter. In other embodiments, the MDCK signal is used to generate a first clock signal via a first inverter, and the DDCK signal is used to generate a second clock signal via a second inverter. The control circuit then performs a NAND operation on the first and second clock signals to generate an output clock signal.

[0067] In some embodiments, a second clock generator provides a buffered DFTEN signal to a first clock generator. In some embodiments, the second clock generator generates a DDCK signal based on an input clock signal, a DFTEN signal, and an INIT signal. In some embodiments, the first clock generator generates a global clock (GCK) signal based on an input clock signal and a chip enable (CE) signal, and provides the GCK signal to multiple memory cells.

[0068] In some aspects of this disclosure, a method is disclosed. In some embodiments, the method includes receiving an input clock signal, a chip enable signal, and a design-for-test (DFT) enable (DFTEN) signal. In some embodiments, the method includes generating a DFT mode clock (DDCK) signal and a task mode clock (MDCK) signal based on the input clock signal, the chip enable signal, and the DFTEN signal. In some embodiments, the method includes providing an output clock signal based on the DDCK signal or the MDCK signal.

[0069] In some embodiments, the output clock signal follows the DDCK signal in response to the DFTEN signal being in a high logic state. In some embodiments, the output clock signal follows the MDCK signal in response to the DFTEN signal being in a low logic state.

[0070] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: Multiple memory cells are arranged in an array; An input / output interface is provided, which is connected to the plurality of memory cells to output a data signal from each memory cell. as well as Control circuit, including: A first clock generator is configured to generate a first clock signal and a second clock signal based on an input clock signal and a chip enable signal, and to provide the first clock signal to the plurality of memory cells; and The second clock generator, unlike the first clock generator, is configured to generate a third clock signal based on the input clock signal and to provide a testability design enable signal to the first clock generator. The control circuit generates an output clock signal based on the second clock signal or the third clock signal.

2. The storage device according to claim 1, wherein, The control circuit performs a logical OR operation on the second clock signal and the third clock signal to generate the output clock signal.

3. The storage device according to claim 1, wherein, The design testability enable signal is generated by performing a logical OR operation on the scan enable signal and the design testability bypass signal.

4. The storage device according to claim 1, wherein, In response to the design-testability enable signal being in a high logic state, the storage device is in a design-testability mode, and the output clock signal generated by the control circuit follows the third clock signal. In response to the design testability enable signal being in a low logic state, the output clock signal generated by the control circuit follows the second clock signal.

5. The storage device according to claim 1, wherein, The control circuit performs a logical OR-NOT operation on the second clock signal and the third clock signal to generate a fourth clock signal, which is then used by an inverter to generate the output clock signal.

6. The storage device according to claim 1, wherein, The second clock signal generates a fourth clock signal through the first inverter, the third clock signal generates a fifth clock signal through the second inverter, and the control circuit performs a logical AND-NOT operation on the fourth clock signal and the fifth clock signal to generate the output clock signal.

7. The storage device according to claim 1, wherein, The second clock generator provides a buffered design testability enable signal to the first clock generator.

8. The storage device according to claim 1, wherein, The second clock generator generates the third clock signal based on the input clock signal, the design-for-testability enable signal, and the initialization signal.

9. The storage device according to claim 1, wherein, The distance between the control circuit and each of the plurality of memory cells and the input / output interface is greater than ten micrometers.

10. A control circuit, comprising: The first clock generator is used to generate a task mode clock signal based on the input clock signal and the chip enable signal; and The second clock generator, unlike the first clock generator, is used to generate a testability design mode clock signal based on the input clock signal and to provide a testability design enable signal to the first clock generator. as well as A logic gate is used to generate an output clock signal based on the task mode clock signal or the testability design mode clock signal.

11. The control circuit according to claim 10, wherein, The control circuit performs a logical OR operation on the task mode clock signal and the testability design mode clock signal to generate the output clock signal.

12. The control circuit according to claim 10, wherein, The design testability enable signal is generated by performing a logical OR operation on the scan enable signal and the design testability bypass signal.

13. The control circuit according to claim 10, wherein, In response to the design-for-testability enable signal being in a high logic state, the output clock signal generated by the logic gate is generated according to the design-for-testability pattern clock signal. In response to the design testability enable signal being in a low logic state, the output clock signal generated by the logic gate is generated based on the task mode clock signal.

14. The control circuit according to claim 10, wherein, The control circuit performs a logical OR-NOT operation on the task mode clock signal and the testability design mode clock signal to generate a first clock signal, and the first clock signal generates the output clock signal through an inverter.

15. The control circuit according to claim 10, wherein, The task mode clock signal is used to generate a first clock signal through a first inverter, and the testability design mode clock signal is used to generate a second clock signal through a second inverter. The control circuit performs a logical AND-NOT operation on the first clock signal and the second clock signal to generate the output clock signal.

16. The control circuit according to claim 10, wherein, The second clock generator provides a buffered design testability enable signal to the first clock generator.

17. The control circuit according to claim 10, wherein, The second clock generator generates the testability design mode clock signal based on the input clock signal, the testability design enable signal, and the initialization signal.

18. The control circuit according to claim 10, wherein, The first clock generator generates a global clock signal based on the input clock signal and the chip enable signal, and provides the global clock signal to multiple memory cells.

19. A method for operating a control circuit, comprising: Receives input clock signals, chip enable signals, and design-for-testability enable signals; The testability design mode clock signal and the task mode clock signal are generated based on the input clock signal, the chip enable signal, and the testability design enable signal. as well as The output clock signal is provided according to the testability design mode clock signal or the task mode clock signal. The first clock generator receives the input clock signal and the chip enable signal to generate the task mode clock signal. The second clock generator, unlike the first clock generator, generates the testability design mode clock signal based on the input clock signal and provides the testability design enable signal to the first clock generator.

20. The method according to claim 19, wherein, In response to the Design for Testability enable signal being in a high logic state, the output clock signal follows the Design for Testability mode clock signal. In response to the design testability enable signal being in a low logic state, the output clock signal follows the task mode clock signal.

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