Electronic panel, display device and method for manufacturing a display device

Abstract

An electronic panel, a display device, and a method for manufacturing a display device are provided. The display device includes a substrate, a driving element, a plurality of pads, an insulating layer, a plurality of signal pads, and an electronic component, wherein the substrate includes a display area and a non-display area; the driving element is disposed in the display area; the plurality of pads is disposed in the non-display area and electrically connected to the driving element; the insulating layer is partially disposed on the pads to partially expose the pads; the plurality of signal pads is respectively disposed on the pads exposed by the insulating layer and electrically connected to the pads; and the electronic component includes a plurality of driving bumps respectively disposed on the signal pads and electrically connected to the signal pads. A first portion of a first driving bump of the plurality of driving bumps is in direct contact with a first signal pad of the plurality of signal pads, and a second portion of the first driving bump is in direct contact with a portion of the insulating layer that does not overlap the first signal pad.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2017-0124503, filed on September 26, 2017, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to display devices, and more specifically, to electronic panels, display devices, and methods for manufacturing display devices. Background Technology

[0004] Various display devices have been developed for use in multimedia devices such as televisions, mobile phones, tablets, navigation systems, and game consoles.

[0005] Display devices typically include a display panel for displaying images. The display panel includes multiple gate lines, multiple data lines, and multiple pixels connected to the gate lines and data lines. The display device may also include electronic components connected to the display panel to provide electrical signals for displaying images to the gate lines or data lines. Summary of the Invention

[0006] In display devices, electronic components can be mounted on the display panel using either anisotropic conductive films or ultrasonic methods. Compared to using anisotropic conductive films, ultrasonic methods improve conductivity and reduce manufacturing processes when connecting the display panel to electronic components.

[0007] Embodiments of the present invention may provide a method for connecting electronic components and electronic panels using ultrasonic methods, an electronic panel capable of checking the bonding strength between electronic components and electronic panels, a display device, and a method for manufacturing the display device.

[0008] In an embodiment of the present invention, a display device includes a substrate, a driving element, a plurality of pads, an insulating layer, a plurality of signal pads, and electronic components. The substrate includes a display area and a non-display area. The driving element is disposed in the display area. The plurality of pads are disposed in the non-display area and electrically connected to the driving element. The insulating layer is disposed on the pads, wherein each of the plurality of pads is partially exposed through the insulating layer. The plurality of signal pads are respectively disposed on the pads exposed through the insulating layer and electrically connected to the pads. The electronic components include a plurality of driving bumps respectively disposed on the signal pads, wherein each of the plurality of signal pads is electrically connected to a corresponding pad among the plurality of pads. In this embodiment, a first portion of a first driving bump of the plurality of driving bumps directly contacts a first signal pad among the plurality of signal pads, and a second portion of the first driving bump directly contacts a portion of the insulating layer that does not overlap with the first signal pad.

[0009] In one embodiment, the first drive bump may be aligned with the first signal pad such that the area of ​​the first drive bump that does not overlap with the first signal pad in a plan view is in the range of approximately 10% to approximately 90% of the total area of ​​the first drive bump.

[0010] In one embodiment, the first drive bump may be aligned with a first pad among the plurality of pads, such that the area of ​​the first drive bump that does not overlap with the first pad in a plan view is in the range of approximately 10% to approximately 90% of the total area of ​​the first drive bump.

[0011] In some embodiments, the display device may also include another insulating layer disposed between the pads and the substrate.

[0012] In an embodiment, the display device may further include another insulating layer disposed between a first pad and a second pad among the plurality of pads.

[0013] In this implementation, the structure of each of the signal pads may be the same as that of the first signal pad.

[0014] In an embodiment, the signal pad may further include a second signal pad that is in direct contact with both the first portion and the second portion of the second drive protrusion among the plurality of drive protrusions.

[0015] In this embodiment, the signal pad may further include a third signal pad and a fourth signal pad, and the first to fourth signal pads may be arranged sequentially. In this embodiment, the structure of the third signal pad may be the same as that of the first signal pad, and the structure of the fourth signal pad may be the same as that of the second signal pad.

[0016] In one embodiment, the first pad among the plurality of pads may overlap with the first portion of the first driving protrusion, but may not overlap with the second portion of the first driving protrusion.

[0017] In one embodiment, the pad may include a first pad and a second pad. In this embodiment, the first pad may overlap with a first portion of the first drive bump, but may not overlap with a second portion of the first drive bump. In this embodiment, the second pad may include a first pad portion that overlaps with a first portion of a second drive bump among a plurality of drive bumps, and a second pad portion that overlaps with a second portion of the second drive bump.

[0018] In one embodiment, the second pad portion may be covered by an insulating layer, and an opening may be defined in at least one region of the second pad portion.

[0019] In one embodiment, the driving element may include a plurality of pixels for displaying an image. In this embodiment, the display device may also include a plurality of signal lines disposed on a substrate and connected between pads and pixels.

[0020] In one implementation, the electronic component may include a data driver chip disposed in a non-display area.

[0021] In one implementation, the electronic components may include printed circuit boards partially disposed in a non-display area.

[0022] In one embodiment, the driving element may include multiple input sensing electrodes. In this embodiment, the display device may also include multiple signal lines disposed on a substrate and connected between multiple pads and the input sensing electrodes.

[0023] In one implementation, the electronic components may include an input sensing driver chip disposed in a non-display area.

[0024] In one implementation, the electronic components may include flexible printed circuit boards partially disposed in a non-display area.

[0025] In another embodiment of the invention, a method for manufacturing a display device includes: providing a display panel including signal pads; aligning a protrusion of an electronic component with the signal pads of the display panel such that the area of ​​the protrusion that does not overlap with the signal pads in a plan view is in the range of about 10% to about 90% of the total area of ​​the protrusion, wherein the protrusion has a larger planar area than the signal pads; contacting the protrusion with the signal pads; and applying ultrasonic vibration to the protrusion and the signal pads.

[0026] In one implementation, applying ultrasonic vibration may include applying ultrasonic vibration to the interface between the protrusion and the signal pad.

[0027] In another embodiment of the invention, the electronic panel includes a substrate, signal lines, an insulating layer, signal pads, and electronic components. The substrate includes a pad region; a portion of the signal line is disposed within the pad region; the insulating layer is configured to expose the portion of the signal line on the substrate that overlaps with the pad region; the signal pad is disposed on the insulating layer and electrically connected to the portion of the signal line; the electronic component includes a drive bump disposed on the signal pad and electrically connected to the signal pad. In this embodiment, a first portion of the drive bump is in direct contact with the signal pad, and a second portion of the drive bump is in direct contact with a portion of the insulating layer that does not overlap with the signal pad. Attached Figure Description

[0028] The above and other features of the invention will become more apparent from the exemplary embodiments described in more detail with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a perspective view showing a display device according to an embodiment of the present invention;

[0030] Figure 2 This is an exploded perspective view showing a display device according to an embodiment of the present invention;

[0031] Figure 3 This is a cross-sectional view showing a display module according to an embodiment of the present invention;

[0032] Figure 4 This is a plan view showing a display panel according to an embodiment of the present invention;

[0033] Figure 5 yes Figure 4 The equivalent circuit diagram of the pixel shown;

[0034] Figure 6 This is an enlarged cross-sectional view showing a display panel according to an embodiment of the present invention;

[0035] Figure 7A yes Figure 4 A magnified view of region AA;

[0036] Figure 7B It is along Figure 7A A sectional view taken from line II′;

[0037] Figure 7C This is an exploded perspective view showing the driver chip and substrate according to an embodiment of the present invention;

[0038] Figure 7D It is along Figure 7C A sectional view taken from line II-II′;

[0039] Figure 7EThis is a diagram illustrating the contact between the signal pads and the drive bumps according to an embodiment of the present invention;

[0040] Figure 8A yes Figure 4 A magnified view of region BB;

[0041] Figure 8B It is along Figure 8A A sectional view taken from line III-III′;

[0042] Figure 8C It is along Figure 8A A sectional view taken by line IV-IV′;

[0043] Figure 8D yes Figure 4 A magnified view of region CC;

[0044] Figure 8E It is along Figure 8D A cross-sectional view taken by line VV′;

[0045] Figures 9A to 9C This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention;

[0046] Figure 10A Is with Figure 4 An enlarged view of region AA' corresponding to region AA, which shows the display panel according to an alternative embodiment of the present invention;

[0047] Figure 10B It is along Figure 10A A sectional view taken by line VI-VI′;

[0048] Figure 11A Is with Figure 4 An enlarged view of region AA' corresponding to region AA', which shows a display panel according to another alternative embodiment of the present invention;

[0049] Figure 11B It is along Figure 11A A sectional view taken by line VII-VII′;

[0050] Figure 12 This is a cross-sectional view showing a display device according to an embodiment of the present invention;

[0051] Figure 13 This is a plan view illustrating an input sensing unit according to an embodiment of the present invention;

[0052] Figure 14A yes Figure 13 A magnified view of the EE region;

[0053] Figure 14B It is along Figure 14A A sectional view taken by line AA′;

[0054] Figure 14C This is an exploded perspective view showing the input sensing driver chip and packaging substrate according to an embodiment of the present invention;

[0055] Figure 14D This is an illustration of a display device according to an embodiment of the present invention. Figure 14C A sectional view taken by line BB′;

[0056] Figure 14E This illustrates a display device according to an alternative embodiment of the invention. Figure 14C A sectional view taken by line BB′; and

[0057] Figure 15 This is a cross-sectional view illustrating a display device according to another alternative embodiment of the present invention. Detailed Implementation

[0058] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout.

[0059] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being on another element, it may be directly on said other element, or there may be intermediate elements present. Conversely, the term "directly" implies the absence of intermediate elements.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context explicitly specifies otherwise, as used herein, the singular forms “a,” “an,” and “described” are intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including,” when used in this specification, indicate the presence of the described features, areas, integrals, steps, operations, elements, and / or components, without excluding the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0061] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship of one element or feature relative to another element or feature, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as being below or beneath other elements or features would be oriented above those other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein should be interpreted accordingly.

[0062] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings of this document, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0063] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0064] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those as defined in commonly used dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field of this disclosure, and not in an idealized or overly formal sense, unless expressly defined herein.

[0065] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have rounded or curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0066] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 This is a perspective view showing a display device according to an embodiment of the present invention. Figure 2 This is an exploded perspective view showing a display device according to an embodiment of the present invention. Figure 3 This is a cross-sectional view showing a display module according to an embodiment of the present invention.

[0068] like Figure 1 As shown, the display device DD can display the image IM through its display surface DD-IS. The display surface DD-IS is parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-IS (i.e., the thickness direction of the display device DD) is indicated by the third direction DR3.

[0069] The front (or top) and rear (or bottom) surfaces of each of the components or elements described herein are defined by the normal direction of the surface DD-IS or the third direction DR3. However, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to... Figure 1 Those shown. Here, the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts and can be changed to other directions.

[0070] Figure 1 An embodiment of a display device DD having a flat display surface DD-IS is shown. However, embodiments of the invention are not limited thereto. In alternative embodiments, the display device DD may include a curved display surface or a three-dimensional (3D) display surface. A 3D display surface may include a plurality of display areas extending in different directions from each other. In one embodiment, for example, the 3D display surface may include a polygonal columnar display surface.

[0071] In one embodiment, the display device DD can be a rigid display device. However, the embodiments of the present invention are not limited thereto. In an alternative embodiment, the display device DD can be a flexible display device. Figure 2 The accompanying drawings illustrate an embodiment of a display device DD applicable to mobile phones. Although not shown in the drawings, electronic modules, camera modules, and power modules disposed (e.g., mounted) on a main circuit board can be arranged together with the display device DD in a frame and / or housing to constitute a mobile phone. The display device DD according to the invention can be applied to large electronic devices (e.g., televisions and monitors) and small to medium-sized electronic devices (e.g., tablet computers, car navigation units, game consoles, and smartwatches).

[0072] In the implementation method, such as Figure 1 As shown, the display surface DD-IS includes a display area DD-DA in which the image IM is displayed, and a non-display area DD-NDA adjacent to the display area DD-DA. The image is not displayed in the non-display area DD-NDA. In an embodiment, as... Figure 1 As shown, the image IM can be an icon image.

[0073] In the implementation method, such as Figure 1 As shown, the display area DD-DA can have a quadrilateral shape (e.g., a rectangular shape). The non-display area DD-NDA can surround the display area DD-DA. However, embodiments of the invention are not limited thereto. The shapes of the display area DD-DA and the non-display area DD-NDA can be modified differently.

[0074] Reference Figure 2 The display device DD may include a window component WM, a display module DM, a driver chip DC, and a receiving component BC.

[0075] A window element WM may be disposed on a display module DM and may transmit images provided from the display module DM through its display area DA. In one embodiment, for example, the window element WM may comprise, for example, glass, sapphire, or plastic, or may be formed of, for example, glass, sapphire, or plastic. The window element WM may include a display area DA and a non-display area NDA. The display area DA and non-display area NDA of the window element WM may overlap with the display area DD-DA and non-display area DD-NDA of the aforementioned display device DD, respectively. Here, when one element overlaps with another element, the element overlaps with the other element when viewed from a plan view in the thickness direction or a third direction DR3 of the display device DD.

[0076] In the implementation method, such as Figure 2As shown, the window component WM has a single-layer structure. However, embodiments of the present invention are not limited thereto. In alternative embodiments, the window component WM may have a multi-layer structure. In one embodiment, for example, the window component WM may include a base layer and at least one border layer disposed on the bottom surface of the base layer corresponding to the non-display area NDA.

[0077] The display module DM is disposed between the window member WM and the receiving member BC. The display module DM includes a display panel DP and an input sensing unit ISU. The input sensing unit ISU can be disposed between the window member WM and the display panel DP.

[0078] According to embodiments of the present invention, the display panel DP can be an organic light-emitting diode display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a microelectromechanical system (MEMS) display panel, or an electrowetting display panel.

[0079] For ease of description, embodiments of the display panel DP being an organic light-emitting diode (OLED) display panel will be described in detail below. However, the embodiments of the present invention are not limited thereto. In alternative embodiments, the display panel DP can be other types of display panels.

[0080] In this embodiment, the display panel DP can output images and provide images to the window component WM. The display panel DP can overlap with the display area DD-DA.

[0081] The input sensing unit (ISU) acquires information related to the coordinates of an external input. The ISU can be directly mounted on the display panel (DP). In one embodiment, the ISU can be integrally formed with the display panel (DP) through a continuous process. However, the embodiments of the present invention are not limited thereto. In an alternative embodiment, the ISU can be formed independently of the display panel (DP) and then attached to the display panel (DP) via an adhesive member.

[0082] In an embodiment, although not shown in the drawings, the display module DM may also include an anti-reflective layer. The anti-reflective layer may include a color filter, a stacked structure of conductive / dielectric / conductive layers, or an optical component. The anti-reflective layer may absorb externally incident light, destructively interfere with externally incident light, or polarize externally incident light to reduce reflection of external light.

[0083] Reference Figure 3The display panel DP of the display module DM may include a substrate SUB, a circuit layer CL, a display element layer ED, and a thin-film encapsulation layer TFE. The circuit layer CL, the display element layer ED, and the thin-film encapsulation layer TFE may be disposed on the substrate SUB. The substrate SUB may include a plastic film. The substrate SUB may be a flexible substrate and may include, for example, a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0084] The circuit layer CL may include multiple insulating layers, multiple conductive layers, and semiconductor layers. The multiple conductive layers of the circuit layer CL may include signal lines and / or pixel control circuitry. The display element layer ED may include organic light-emitting diodes (OLEDs).

[0085] The display element layer (ED) may include a plurality of organic light-emitting diodes (OLEDs) corresponding to light-emitting elements. The display element layer (ED) may also include an organic layer such as a pixel defining layer.

[0086] The thin-film encapsulation layer (TFE) is used to encapsulate the display element layer (ED). The TFE includes an insulating layer. In one embodiment, the TFE may include an inorganic layer (hereinafter referred to as the encapsulation inorganic layer). In another embodiment, the TFE may include an organic layer (hereinafter referred to as the encapsulation organic layer) and an encapsulation inorganic layer.

[0087] The encapsulation inorganic layer protects the display element layer (ED) from water / oxygen, while the encapsulation organic layer protects the ED from foreign materials such as dust particles. The encapsulation inorganic layer may include, but is not limited to, at least one of the following: silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer, and aluminum oxide layer. The encapsulation organic layer may include, but is not limited to, acrylic-based organic layers.

[0088] However, embodiments of the present invention are not limited thereto. In alternative embodiments, the display module DM may include an encapsulation substrate configured to encapsulate the display element layer ED in place of the thin-film encapsulation layer TFE. The encapsulation substrate may include glass, sapphire, or plastic, or be formed of glass, sapphire, or plastic.

[0089] According to an embodiment of the present invention, the input sensing unit (ISU) is directly disposed on the thin-film encapsulation layer (TFE). The input sensing unit (ISU) includes input sensing electrodes and signal lines. The input sensing electrodes and signal lines may have a single-layer or multi-layer structure. According to an alternative embodiment of the present invention, the input sensing unit (ISU) can be attached to the thin-film encapsulation layer (TFE) via an adhesive member disposed on the TFE. This will be referred to later. Figure 15 To describe in more detail.

[0090] The input sensing electrodes and signal lines may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, or graphene. In some embodiments, the input sensing electrodes and signal lines may include a metal layer, such as molybdenum, silver, titanium, copper, aluminum, or any alloy thereof. The input sensing electrodes and signal lines may have the same layer structure as each other or different layer structures. The input sensing unit (ISU) will be described in more detail later.

[0091] Figure 4 This is a plan view showing a display panel according to an embodiment of the present invention. Figure 5 yes Figure 4 The equivalent circuit diagram of the pixel is shown.

[0092] In an exemplary embodiment, when viewed in a plan view, the display panel DP includes a display area DP-DA and a non-display area DP-NDA. In the embodiment, as... Figure 4 As shown, the non-display area DP-NDA can be defined as adjacent to the display area DP-DA. In one embodiment, for example, the non-display area DP-NDA can be defined along the boundary of the display area DP-DA. The display area DP-DA and the non-display area DP-NDA of the display panel DP are respectively adjacent to... Figure 1 The display area DD-DA and the non-display area DD-NDA of the display device DD are shown.

[0093] The display panel DP may include a driver circuit GDC, multiple signal lines SGL, multiple drive signal pads DP-PD, multiple connection signal pads DPS-PD, and multiple pixels PX. Pixels PX are disposed within the display area DP-DA. Each of the multiple pixels PX includes an organic light-emitting diode (OLED) and a pixel driver circuit connected to the OLED. The driver circuit GDC, signal lines SGL, drive signal pads DP-PD, connection signal pads DPS-PD, and pixel driver circuit may be included in... Figure 3 In the circuit layer CL shown.

[0094] The driving circuit GDC may include a scan driving circuit. The scan driving circuit generates multiple scan signals and sequentially outputs these signals to multiple scan lines GL, which will be described below. The scan driving circuit may also output other control signals to the pixel driving circuit of pixel PX.

[0095] The scan driving circuit may include multiple thin-film transistors formed using the same process as the pixel driving circuit of the pixel PX (e.g., low-temperature polycrystalline silicon (LTPS) process or low-temperature polycrystalline oxide (LTPO) process).

[0096] The signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the multiple scan lines GL is connected to a corresponding pixel PX, and each of the multiple data lines DL is connected to a corresponding pixel PX. The power lines PL are connected to the pixels PX. The control signal lines CSL provide control signals to the scan drive circuitry.

[0097] The signal line SGL overlaps with the display area DP-DA and the non-display area DP-NDA. Each of the multiple signal lines SGL may include a pad portion and a line portion. The line portion overlaps with the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to one end of the line portion. The pad portion is located in the non-display area DP-NDA and overlaps with a corresponding one of the drive signal pads DP-PD. This will be described in more detail later. The area of ​​the non-display area DP-NDA where the drive signal pad DP-PD is located can be defined as the drive pad area NDA-DC.

[0098] According to the implementation method, Figure 2 The driver chip DC shown can be mounted on the driver pad area NDA-DC. In this embodiment, the drive signal pad DP-PD can be electrically connected to the driver chip DC to send the electrical signal received from the driver chip DC to the signal line SGL.

[0099] In this embodiment, the drive signal pads DP-PD are respectively connected to the connection signal lines of the connection signal pads DPS-PD (see...). Figure 8A The connection signal line (DSL) can be located in the non-display area DP-NDA. One or more of the connection signal lines can be connected to the drive circuit GDC, and the other parts of the connection signal lines can be connected to the connection signal pads DPS-PD.

[0100] Each of the connection signal lines may include a connection pad portion and a connection line portion. The connection pad portion is connected to the end of the connection line portion. The connection pad portion overlaps with a corresponding one of the connection signal pads DPS-PD. This will be described in more detail later. The area where the connection signal pads DPS-PD are provided may be defined as the connection pad area NDA-PC.

[0101] According to an embodiment of the present invention, a region of the printed circuit board (PCB) may be disposed on the connection pad region NDA-PC. In this embodiment, the connection signal pad DPS-PD may be electrically connected to the PCB to transmit electrical signals received from the PCB to the drive signal pad DP-PD. The PCB may be rigid or flexible. In one embodiment, for example, where the PCB is expected to be flexible, the PCB may be a flexible printed circuit board.

[0102] Generally, the line connecting to pixel PX constitutes most of the signal line SGL. The line connects to the transistor of pixel PX (see...). Figure 5 (Transistors T1 and T2). The wire portion may have a single-layer or multi-layer structure. The wire portion may be a single integral or may comprise two or more parts. The two or more parts may be disposed on different layers and may be connected to each other through contact holes defined as penetrating an insulating layer disposed between the two or more parts.

[0103] In the implementation method, such as Figure 4 As shown, the printed circuit board (PCB) is electrically connected to the display panel (DP). The PCB can be a rigid or flexible printed circuit board. The PCB can be directly connected to the display panel (DP), or it can be connected to the display panel (DP) via another printed circuit board. For ease of description, the implementation of the PCB being directly connected to the connection pad area NDA-PC of the display panel (DP) will be described in detail below.

[0104] In this embodiment, a timing control circuit for controlling the operation of the display panel DP can be disposed on a printed circuit board (PCB). The timing control circuit can be mounted on the PCB as an integrated chip. In this embodiment, although not shown in the accompanying drawings, a timing control circuit for controlling the input sensing unit (ISU) (see...) is also present. Figure 3 The input sensing circuit can be mounted on a printed circuit board (PCB). The input sensing circuit can be integrated into a single chip and mounted on the PCB.

[0105] In one embodiment, the timing control circuit and the input sensing circuit are mounted on a printed circuit board (PCB). However, the embodiments of the present invention are not limited thereto. In an alternative embodiment, the timing control circuit and the input sensing circuit may be directly mounted in the non-display area DP-NDA of the display panel (DP). In another alternative embodiment, the timing control circuit and the input sensing circuit may be manufactured as a single integrated chip, and said single integrated chip may be mounted on the printed circuit board (PCB) or in the non-display area DP-NDA of the display panel (DP).

[0106] The printed circuit board (PCB) may include a printed circuit board pad DPS-PDz electrically connected to the display panel (DP). The printed circuit board pad DPS-PDz overlaps with and is electrically connected to the connection signal pad DPS-PD.

[0107] Figure 5 The scan line GL, data line DL, power line PL, and the pixels PX connected to them are shown. However, the configuration of the pixels PX is not limited to... Figure 5 Instead, it can be modified in different ways.

[0108] The organic light-emitting diode (OLED) of a pixel PX can be a front-surface type or a rear-surface type OLED. A pixel PX includes a first transistor (or switching transistor) T1, a second transistor (or driving transistor) T2, and a capacitor Cst, which together constitute a pixel driving circuit for driving the OLED. A first power supply voltage ELVDD is provided to the second transistor T2, and a second power supply voltage ELVSS is provided to the OLED. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD.

[0109] The first transistor T1, in response to a scan signal applied to it via scan line GL, outputs a data signal applied to it via data line DL. The capacitor Cst is charged using a voltage corresponding to the data signal received from the first transistor T1. The second transistor T2 is connected to the organic light-emitting diode (OLED). The second transistor T2 controls the driving current flowing through the OLED in response to the amount of charge stored in the capacitor Cst.

[0110] Figure 5 The equivalent circuit shown is only an exemplary implementation of the pixel PX, and the embodiments of the invention are not limited thereto. In alternative embodiments, the pixel PX may also include multiple transistors and / or may include two or more capacitors. In another alternative embodiment, an organic light-emitting diode (OLED) may be connected between the power line PL and the second transistor T2.

[0111] Figure 6 This is an enlarged cross-sectional view showing a display panel according to an embodiment of the present invention.

[0112] Reference Figure 6 In the display panel DP, the circuit layer CL, the display element layer ED, and the thin-film encapsulation layer TFE are sequentially stacked on the substrate SUB. In this embodiment, the circuit layer CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30, wherein the buffer layer BFL is an inorganic layer. Each of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may include an inorganic layer or an organic layer. In one embodiment, for example, each of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may include both an inorganic layer and an organic layer. The materials of the inorganic and organic layers are not limited to specific materials, and the buffer layer BFL may be selectively omitted in some embodiments of the invention.

[0113] Semiconductor pattern OSP1 of the first transistor T1 (hereinafter referred to as the "first semiconductor pattern") and semiconductor pattern OSP2 of the second transistor T2 (hereinafter referred to as the "second semiconductor pattern") are disposed on the buffer layer BFL. Each of the first semiconductor pattern OSP1 and the second semiconductor pattern OSP2 may comprise amorphous silicon, polycrystalline silicon, or metal oxide semiconductor.

[0114] A first insulating layer 10 is disposed on a first semiconductor pattern OSP1 and a second semiconductor pattern OSP2. A control electrode GE1 of the first transistor T1 (hereinafter referred to as the "first control electrode") and a control electrode GE2 of the second transistor T2 (hereinafter referred to as the "second control electrode") are disposed on the first insulating layer 10. The first control electrode GE1 and the second control electrode GE2 can be connected to a scan line GL (see...) Figure 4 and Figure 5 It is formed using the same photolithography process.

[0115] The second insulating layer 20 is disposed on the first insulating layer 10 and covers the first control electrode GE1 and the second control electrode GE2. The input electrode DE1 (hereinafter, the first input electrode) and output electrode SE1 (hereinafter, the first output electrode) of the first transistor T1, and the input electrode DE2 (hereinafter, the second input electrode) and output electrode SE2 (hereinafter, the second output electrode) of the second transistor T2 are disposed on the second insulating layer 20.

[0116] The first input electrode DE1 and the first output electrode SE1 are connected to a portion of the first semiconductor pattern OSP1 via a first via CH1 and a second via CH2, wherein each of the first via CH1 and the second via CH2 is defined to penetrate the first insulating layer 10 and the second insulating layer 20. The second input electrode DE2 and the second output electrode SE2 are connected to a portion of the second semiconductor pattern OSP2 via a third via CH3 and a fourth via CH4, wherein the third via CH3 and the fourth via CH4 are defined to penetrate the first insulating layer 10 and the second insulating layer 20. In an alternative embodiment, at least one of the first transistor T1 and the second transistor T2 may have a bottom gate structure.

[0117] A third insulating layer 30 is disposed on the second insulating layer 20 and covers the first input electrode DE1, the second input electrode DE2, the first output electrode SE1, and the second output electrode SE2. The third insulating layer 30 may have a flat upper surface to provide a flat surface thereon.

[0118] The display element layer ED is disposed on the third insulating layer 30. The display element layer ED may include a pixel defining layer PDL and an organic light-emitting diode (OLED). The pixel defining layer PDL may include an organic material. A first electrode AE ​​is disposed on the third insulating layer 30. The first electrode AE ​​is connected to a second output electrode SE2 through a fifth through-hole CH5 defined to penetrate the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE. In an alternative embodiment of the invention, the pixel defining layer PDL may be omitted.

[0119] Pixel PX can be disposed within the display area DP-DA. The display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA. In an embodiment, the light-emitting area PXA is defined to correspond to a portion of the first electrode AE ​​exposed through the opening OP.

[0120] According to one embodiment, the light-emitting region PXA may overlap with at least one of the first transistor T1 and the second transistor T2. In this embodiment, the opening OP may be further extended to overlap with at least one of the first transistor T1 and the second transistor T2, and the first electrode AE ​​and the light-emitting layer EML, which will be described later, may therefore be further extended.

[0121] A hole control layer HCL can be commonly disposed in the emitting region PXA and the non-emitting region NPXA. Although not shown in the accompanying drawings, common layers such as the hole control layer HCL can be commonly disposed in the pixel PX (see [reference]). Figure 4 In this context, when layers are commonly set in multiple regions or areas, a single layer is set to overlap with all of the regions or areas.

[0122] An emissive layer (EML) is disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (OP). In this embodiment, the EMLs of pixels (PX) can be separated from each other or spaced apart. The EML can comprise organic and / or inorganic materials. The EML can generate light with a predetermined color.

[0123] In one implementation, the emissive layer EML can be patterned. However, in an alternative implementation, the emissive layer EML can be commonly disposed within the pixel PX. In this implementation, the emissive layer EML can generate white light. In this implementation, the emissive layer EML can have a multi-layer structure referred to as "tandem".

[0124] The electronic control layer (ECL) is disposed on the emissive layer (EML). Although not shown in the accompanying drawings, the electronic control layer (ECL) can be commonly disposed on pixel PX (see [reference]). Figure 4The second electrode CE is disposed on the electronic control layer ECL. The second electrode CE is commonly disposed in pixel PX.

[0125] A thin-film encapsulation layer (TFE) is disposed on the second electrode (CE). The TFE is also commonly disposed within the pixel (PX). In one embodiment, the TFE directly covers the second electrode (CE). In another embodiment, a capping layer covering the second electrode (CE) may be further disposed between the TFE and the second electrode (CE). In this embodiment, the TFE may directly cover the capping layer.

[0126] Figure 7A yes Figure 4 A magnified view of region AA. Figure 7B It is along Figure 7A The sectional view taken from line II′. Figure 7C This is an exploded perspective view showing the driver chip and substrate according to an embodiment of the present invention. Figure 7D It is along Figure 7C A sectional view taken from line II-II′. Figure 7E This is a diagram illustrating the contact between the signal pads and the drive bumps according to an embodiment of the present invention.

[0127] Figure 7A The diagram shows the wire portion DL-L and the pad portion DL-P of two data lines DL. In this embodiment, Figure 4 The data line DL includes a line portion DL-L and a pad portion DL-P. However, in an alternative embodiment, the line portion DL-L and the pad portion DL-P may be provided or formed independently of each other. In this embodiment, the display panel DP may include data lines DL corresponding to the line portions and pads respectively connected to the data lines DL. Here, the pads may each correspond to the pad portion DL-P. In this embodiment, Figure 4 The data cable DL and the pads (or pads) connected to it DL-P can be a single unit or can be configured as separate components connected to each other.

[0128] In this embodiment, the area of ​​the pad portion DL-P per unit length can be greater than the area of ​​the line portion DL-L per unit length. In this embodiment, the width of the pad portion DL-P can be greater than the width of the line portion DL-L. In this embodiment, the pad portion DL-P has the following characteristics: Figure 7A The shape shown is a quadrilateral. However, the shape of the pad portion DL-P can be modified or changed in different manufacturing processes.

[0129] In the implementation method, such as Figure 7BAs shown, the pad portion DL-P of the data line DL can be disposed on the second insulating layer 20. The third insulating layer 30 can cover the pad portion DL-P of the data line DL. Drive signal pads DP-PD are disposed on the third insulating layer 30. Each of the drive signal pads DP-PD is connected to a corresponding pad portion DL-P. Each of the drive signal pads DP-PD can be electrically connected to the corresponding pad portion DL-P through a contact hole CNT defined to penetrate the third insulating layer 30. In this embodiment, the third insulating layer 30 exposes each of the pad portions DL-P through the contact hole CNT, and the drive signal pads DP-PD and the pad portions DL-P can be electrically contacted to each other through the portions of the pad portions DL-P exposed by the contact hole CNT of the third insulating layer 30.

[0130] Reference Figure 7C The driver chip DC may include a top surface DC-US and a bottom surface DC-DS, and may include a plurality of drive bumps DC-BP disposed on the bottom surface DC-DS. In an alternative embodiment, the drive bumps DC-BP may not be components included in the driver chip DC, and the drive bumps DC-BP may be configured as additional components for mounting the driver chip DC to the drive pad area NDA-DC.

[0131] The drive signal pads DP-PD disposed on the substrate SUB may include multiple first drive signal pads DP-PD1 and multiple second drive signal pads DP-PD2. The drive bumps DC-BP disposed on the bottom surface DC-DS of the driver chip DC may include multiple first drive bumps DC-BP1 and multiple second drive bumps DC-BP2.

[0132] The first drive signal pad DP-PD1 will be connected to the signal pad DPS-PD (see...). Figure 4 The second drive signal pad DP-PD2 is electrically connected to the first drive bump DC-BP1. The second drive signal pad DP-PD2 electrically connects the second drive bump DC-BP2 to the signal line SGL (see...). Figure 4 ).

[0133] In one embodiment, the driver chip DC may include circuit elements (not shown) that generate a signal to be provided to the pixel based on an electrical signal received from the first driver bump DC-BP1. The second driver bump DC-BP2 may send a signal output from the circuit elements of the driver chip DC to the second driver signal pad DP-PD2.

[0134] Reference Figure 7DThe driver chip DC includes a circuit substrate DC-PB, circuit pads DC-PD disposed on the circuit substrate DC-PB, and solder paste DC-SR disposed on the circuit substrate DC-PB to expose the circuit pads DC-PD. Although not shown in the figures, the circuit pads DC-PD may include multiple circuit pads corresponding to drive bumps DC-BP respectively. One of the drive bumps DC-BP is disposed on the circuit pads. DC-PD The corresponding one is connected to a circuit pad DC-PD.

[0135] In the following text, reference will be made to Figure 7D A more detailed description is provided of a drive signal pad DP-PD, a pad section DL-P, and a drive bump DC-BP that are connected to each other.

[0136] According to embodiments of the present invention, such as Figure 7D As shown, a contact area (CTA) and a non-contact area (NCTA) can be defined in the substrate SUB. The drive bump DC-BP directly contacts the drive signal pad DP-PD in the contact area CTA, while the drive bump DC-BP does not contact the drive signal pad DP-PD in the non-contact area NCTA.

[0137] The pad portion DL-P may overlap with the contact area CTA and may be disposed on the second insulating layer 20. The third insulating layer 30 may cover the pad portion DL-P and may be disposed on the second insulating layer 20. In this embodiment, as described above, the third insulating layer 30 is defined by reference to... Figure 7B The contact hole CNT exposes the pad portion DL-P.

[0138] The drive signal pad DP-PD may not overlap with the non-contact area NCTA. The drive signal pad DP-PD may be disposed on the third insulating layer 30 such that at least a portion of the drive signal pad DP-PD is disposed on the pad portion DL-P. Alternatively, the drive signal pad DP-PD may be disposed only on the pad portion DL-P.

[0139] According to an embodiment of the present invention, the drive bump DC-BP may include a first portion overlapping the contact area CTA and a second portion overlapping the non-contact area NCTA. In this embodiment, the first portion of the drive bump DC-BP directly contacts the drive signal pad DP-PD, while the second portion of the drive bump DC-BP does not overlap with the drive signal pad DP-PD but directly contacts the third insulating layer 30.

[0140] According to the embodiment, as described above, the pad portion DL-P and the drive signal pad DP-PD overlap with the contact area CTA but not with the non-contact area NCTA. Therefore, an electrical connection is formed between the drive bump DC-BP and the drive signal pad DP-PD in the contact area CTA, while no electrical connection is formed between the drive bump DC-BP and the drive signal pad DP-PD in the non-contact area NCTA.

[0141] In an embodiment of the present invention, the first and second portions of the drive bump DC-BP can be respectively connected to the drive signal pad DP-PD and the third insulating layer 30 by ultrasonic thermoforming. Hereinafter, the interface between the first portion of the drive bump DC-BP and the drive signal pad DP-PD is defined as the first interface SC1, and the interface between the second portion of the drive bump DC-BP and the third insulating layer 30 is defined as the second interface SC2.

[0142] In this embodiment, when ultrasonic vibration is applied to the first interface SC1, frictional heat can be generated between the first portion of the drive protrusion DC-BP and the drive signal pad DP-PD. Therefore, the first portion of the drive protrusion DC-BP and the drive signal pad DP-PD can be bonded to each other (e.g., soldered) by frictional heat.

[0143] In this embodiment, when ultrasonic vibration is applied to the second interface SC2, frictional heat can be generated between the second portion of the driving protrusion DC-BP and the third insulating layer 30 overlapping with the non-contact region NCTA. Therefore, the second portion of the driving protrusion DC-BP and the third insulating layer 30 overlapping with the non-contact region NCTA can be bonded to each other (e.g., welded) by frictional heat.

[0144] According to an embodiment of the invention, the adhesion status (or adhesion strength) between the drive protrusion DC-BP and the drive signal pad DP-PD can be inspected based on the color at the second interface SC2 on which ultrasonic vibration is applied. In this embodiment, the color of the second interface SC2 can be inspected via the rear surface of the substrate SUB (i.e., the rear surface of the display panel DP on which no image is displayed). In another embodiment, the color at the second interface SC2 can be inspected using an external inspection device. In one embodiment, for example, the external inspection device can be a microscope. However, embodiments of the invention are not limited thereto. Various inspection devices can be used as external inspection devices.

[0145] Both the drive bump DC-BP and the drive signal pad DP-PD may be made of metallic material. After ultrasonic vibration is applied to the first interface SC1, the contact surfaces between the drive bump DC-BP and the drive signal pad DP-PD maintain or exhibit the same or constant color regardless of the bonding state (or bonding strength).

[0146] However, when ultrasonic vibration is applied to the second interface SC2, the color of the third insulating layer 30 may change due to friction between the third insulating layer 30 and the second portion of the driving protrusion DC-BP. In this embodiment, the color of the third insulating layer 30 may change depending on the adhesion state (or adhesion strength) between the third insulating layer 30 and the second portion of the driving protrusion DC-BP. In one embodiment, for example, the color of the third insulating layer 30 may gradually darken as the adhesion strength decreases, and the color of the third insulating layer 30 may gradually brighten as the adhesion strength increases.

[0147] Therefore, in this embodiment, the bonding status (or bonding strength) between the drive protrusion DC-BP and the drive signal pad DP-PD can be determined by examining the color of the second interface SC2 to which ultrasonic vibration is applied.

[0148] If the portion of the drive bump DC-BP that does not overlap with the drive signal pad DP-PD is too small, the color of the second interface SC2, which provides ultrasonic vibration, may not be effectively inspected. Therefore, in an embodiment of the invention, the drive bump DC-BP is aligned with the drive signal pad DP-PD such that, in a plan view (i.e., when viewed from a top or flat view in the thickness direction of the substrate SUB), the area of ​​the drive bump DC-BP that does not overlap with the drive signal pad DP-PD is in the range of approximately 10% to approximately 90% of the total area of ​​the drive bump DC-BP. In this embodiment of the invention, the drive bump DC-BP and the drive signal pad DP-PD are bonded to each other by ultrasonication rather than by conductive components (e.g., anisotropic conductive films). Therefore, the conductivity between the drive bump DC-BP and the drive signal pad DP-PD can be increased or improved.

[0149] Therefore, in this embodiment, in the plan view as described above, the area of ​​the drive bump DC-BP that does not overlap with the drive signal pad DP-PD is within the range of 10% to 90% of the total area of ​​the drive bump DC-BP, making it possible to effectively inspect the color at the second junction SC2. In this embodiment, the overlapping area of ​​the third insulating layer 30 and the drive bump DC-BP is within the range of approximately 10% to approximately 90% of the total area of ​​the drive bump DC-BP, making it possible to effectively inspect the color at the second junction SC2.

[0150] In an embodiment of the invention, the drive bump DC-BP can be aligned with the first pad portion in the pad portion DL-P, such that the area of ​​the drive bump DC-BP that does not overlap with the first pad portion in a plan view is in the range of approximately 10% to approximately 90% of the total area of ​​the drive bump DC-BP. Since the area of ​​the drive bump DC-BP that does not overlap with the pad portion DL-P in a plan view is in the range of approximately 10% to approximately 90% of the total area of ​​the drive bump DC-BP, the color at the second junction SC2 can be effectively inspected.

[0151] Reference Figure 7E The color at the first boundary SC1 in the contact area CTA and the color at the second boundary SC2 in the non-contact area NCTA are shown. Figure 7E The shape can be from Figure 7D Substrate SUB to Figure 7D The image obtained by observing the circuit substrate DC-PB in the direction.

[0152] like Figure 7E As shown, after the driving protrusion DC-BP is bonded to the third insulating layer 30 by ultrasonic vibration, the second interface SC2 in the non-contact area NCTA may have color. Figure 7E In the process, the color of the first boundary SC1 in the contact area CTA may not be effectively checked due to the drive signal pad DP-PD, which makes it possible to check the color of the drive signal pad DP-PD in the contact area CTA.

[0153] Therefore, the bonding status (or bonding strength) between the drive bump DC-BP and the drive signal pad DP-PD can be determined by checking the color of the second junction SC2 in the non-contact area NCTA.

[0154] Figure 8A yes Figure 4 A magnified view of region BB. Figure 8B It is along Figure 8A The sectional view taken from line III-III′. Figure 8C It is along Figure 8A A sectional view taken from line IV-IV′. Figure 8D yes Figure 4 A magnified view of region CC. Figure 8E It is along Figure 8D A cross-sectional view taken by line VV′.

[0155] Figure 8AThe control signal line CSL and connection signal line DSL are shown, which are connected to the printed circuit board pad DPS-PDz in the NDA-PC connection pad area. The control signal line CSL and connection signal line DSL include connection line portions CSL-L and DSL-L, and connection pad portions CSL-P and DSL-P.

[0156] The area per unit length of each of the connecting pad portions CSL-P and DSL-P can be larger than the area per unit length of each of the connecting line portions CSL-L and DSL-L. In an embodiment, the connecting pad portions CSL-P and DSL-P have... Figure 8A The quadrilateral shape is used. However, the shape of the connecting pads CSL-P and DSL-P can be modified or changed in different ways during the manufacturing process.

[0157] The control signal line CSL is connected to the drive circuit GDC via the CSL-L connector (see [link]). Figure 4 The DSL-L connector and the DSL-L connector are electrically connected to the first drive signal pad DP-PD1.

[0158] In the implementation method, such as Figure 8B As shown, the connection pad CSL-P of the control signal line CSL can be disposed on the first insulating layer 10, and the connection pad DSL-P of the signal line DSL can be disposed on the second insulating layer 20. The third insulating layer 30 can cover the connection pad DSL-P of the signal line DSL.

[0159] According to one embodiment, the connection signal pad DPS-PD may be disposed on the third insulating layer 30. In this embodiment, the connection pad portion CSL-P of the control signal line CSL can be connected to one of the connection signal pads DPS-PD through a contact hole CNTa defined to penetrate the second insulating layer 20 and the third insulating layer 30.

[0160] According to the embodiment, the connection pad portion DSL-P of the connection signal line DSL can be connected to the corresponding connection signal pad DPS-PD in the connection signal pad DPS-PD through the contact hole CNT defined in the third insulating layer 30.

[0161] According to the embodiment, as described above, the number of insulating layers defined to be penetrated by the contact hole can be determined based on the position of the pad portion of the signal line in the cross-sectional view. Although not shown in the drawings, the pad portion of the scan line can be provided in the same layer as the connection pad portion CSL-P of the control signal line CSL, and can be connected to the corresponding signal pad.

[0162] According to the implementation method, such as Figure 8CAs shown, the printed circuit board (PCB) includes a first circuit substrate (PCB-PB), a first circuit pad (PCB-PD) disposed on the first circuit substrate (PCB-PB), and a first solder paste (PB-SR) disposed on the first circuit substrate (PCB-PB) to expose the first circuit pad (PCB-PD). Although not shown in the figures, the first circuit pad (PCB-PD) may include a plurality of first circuit pads, each corresponding to a connecting bump (PCB-BP). Each of the connecting bumps (PCB-BP) is disposed on a corresponding one of the first circuit pads (PCB-PD) and is electrically connected to said one first circuit pad (PCB-PD).

[0163] According to an embodiment of the present invention, the connecting bump PCB-BP can be aligned with the connecting signal pad DPS-PD such that the area of ​​the connecting bump PCB-BP that does not overlap with the connecting signal pad DPS-PD in a plan view is in the range of 10% to 90% of the total area of ​​the connecting bump PCB-BP. Therefore, it is not necessary for the entire bottom surface of the connecting bump PCB-BP to contact the connecting signal pad DPS-PD, but only a portion of the connecting bump PCB-BP can make electrical contact with the connecting signal pad DPS-PD.

[0164] In this embodiment, Figure 8C The bonding structure between the connection bumps PCB-BP and the connection signal pads DPS-PD in the printed circuit board (PCB) can be... Figure 7D The bonding structure between the DC driver chip and the DP-PD driver signal pads is largely the same, and therefore any repeated detailed descriptions will be omitted.

[0165] In this embodiment, the connection bump PCB-BP may be electrically connected to the connection signal pad DPS-PD only in the contact area CTA. In this embodiment, as described above, the adhesion status (or adhesion strength) between the connection bump PCB-BP and the connection signal pad DPS-PD in the contact area CTA can be checked based on the color at the interface between the connection bump PCB-BP in the non-contact area NCTA and the third insulating layer 30 where ultrasonic vibration is applied.

[0166] Reference Figure 8D and Figure 8E In one embodiment, unlike the pad portion DL-P of the data line DL disposed on the second insulating layer 20, the pad portion PL-P overlapping the drive pad region NDA-DC can be disposed on the first insulating layer 10. In this embodiment, the pad portion PL-P can be connected to another line portion, instead of the line portion DL-L of the data line DL. In one embodiment, for example, the pad portion PL-P can be connected to the line portion PL-L of the power line PL used to provide driving power to the pixel.

[0167] The power signal pad PL-PD can be disposed on the third insulating layer 30. The power signal pad PL-PD can be connected to the pad portion PL-P through a contact hole CNTb defined to penetrate the second insulating layer 20 and the third insulating layer 30.

[0168] Figures 9A to 9C This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0169] Figures 9A to 9C The diagram illustrates the use of electronic components (e.g., driver chips or printed circuit boards) and the above references. Figure 7D This describes an implementation method for bonding the display panel DP to the drive signal pad DP-PD. In the following text, reference will be made to... Figures 9A to 9C An exemplary implementation of a method for bonding a driver chip DC and a display panel DP is described.

[0170] In this embodiment, such as Figure 9A As shown, a display panel DP including drive signal pads DP-PD and a driver chip DC including drive bumps DC-BP are provided. In this embodiment, as described above, the drive bumps DC-BP may be included as a single unit in the driver chip DC, or may be configured as a separate component disposed on the driver chip DC.

[0171] When viewed in a plan view, the area of ​​the drive bump DC-BP of the driver chip DC can be larger than the area of ​​the drive signal pad DP-PD. In this embodiment, the drive bump DC-BP can be aligned with the drive signal pad DP-PD such that the area of ​​the drive bump DC-BP that does not overlap with the drive signal pad DP-PD in the plan view is in the range of approximately 10% to approximately 90% of the total area of ​​the drive bump DC-BP.

[0172] Subsequently, as Figure 9B As shown, the drive bump DC-BP is brought into contact with the drive signal pad DP-PD, and then the drive bump DC-BP is squeezed in the direction toward the substrate SUB or in the direction parallel to the third direction DR3.

[0173] Subsequently, as Figure 9C As shown, ultrasonic vibration can be applied to the first junction SC1 between the drive signal pad DP-PD and the drive bump DC-BP overlapping with the contact area CTA, and the second junction SC2 between the third insulating layer 30 and the drive bump DC-BP overlapping with the non-contact area NCTA. In this embodiment, the ultrasonic vibration can be applied to the first junction SC1 and the second junction SC2 in a first direction DR1 corresponding to the lateral direction of the substrate SUB.

[0174] Therefore, frictional heat can be generated at the first junction SC1 and the second junction SC2, causing the drive protrusion DC-BP and the drive signal pad DP-PD to adhere to each other.

[0175] Figure 10A Is with Figure 4 An enlarged view of region AA' corresponding to region AA, which shows a display panel according to an alternative embodiment of the present invention. Figure 10B It is along Figure 10A A sectional view taken from line VI-VI′.

[0176] Reference Figure 10A and Figure 10B This shows two data lines (i.e., the first data line DL and the second data line DLa). The first data line DL has the same characteristics as... Figure 7A The data line DL shown has the same structure, and therefore any repeated detailed descriptions will be omitted.

[0177] In the implementation method, such as Figure 10A As shown, the second data line DLa includes a line portion DL-La and a pad portion DL-Pa. The line portion DL-La of the second data line DLa may have the same structure as the line portion DL-L of the first data line DL. In this embodiment, the area of ​​the pad portion DL-Pa of the second data line DLa may be larger than the area of ​​the pad portion DL-P of the first data line DL. In this embodiment, Figure 10B The area of ​​the drive signal pad DP-PDa shown can be greater than Figure 7D The area of ​​the drive signal pads DP-PD shown is shown.

[0178] In this embodiment, the drive signal pad DP-PDa can be connected to the drive protrusion DC-BP in the contact area CTA and the non-contact area NCTA. In this embodiment, the drive signal pad DP-PDa can be connected to the pad portion DL-Pa through a contact hole CNT1 defined to penetrate the third insulating layer 30.

[0179] According to an embodiment of the present invention, the drive signal pad DP-PD may have Figure 7D The structure of the drive signal pad DP-PD is shown.

[0180] According to an alternative embodiment of the present invention, Figure 7D The drive signal pads DP-PD and shown Figure 10B The drive signal pads DP-PDa shown can be alternately arranged in the drive pad areas NDA-DC.

[0181] In one embodiment, for example, the drive signal pads may include a first signal pad to a fourth signal pad arranged in sequence, the first signal pad and the third signal pad may have Figure 7DThe diagram shows the structure of the drive signal pad DP-PD, and the second and fourth signal pads may have... Figure 10B The structure of the drive signal pad DP-PDa is shown.

[0182] Figure 11A Is with Figure 4 An enlarged view of region AA' corresponding to region AA″, which shows a display panel according to another alternative embodiment of the present invention. Figure 11B It is along Figure 11A A sectional view taken from line VII-VII′.

[0183] Reference Figure 11A and Figure 11B This shows two data lines (i.e., the first data line DL and the second data line DLb). The first data line DL has the same characteristics as... Figure 7A The data line DL shown has the same structure, and therefore any repeated detailed descriptions will be omitted.

[0184] In the implementation method, such as Figure 11A As shown, the second data line DLb includes a line portion DL-Lb and a pad portion DL-Pb. The line portion DL-Lb of the second data line DLb may have the same structure as the line portion DL-L of the first data line DL. In this embodiment, the area of ​​the pad portion DL-Pb of the second data line DLb may be larger than the area of ​​the pad portion DL-P of the first data line DL.

[0185] According to an embodiment, the DL-Pb pad portion may include a first pad portion and a second pad portion. The first pad portion may overlap with the contact area CTA and may be disposed on the second insulating layer 20. The second pad portion may overlap with the non-contact area NCTA and may be disposed on the second insulating layer 20. In an embodiment, as... Figure 11B As shown, the open ODP can be defined at least in one area of ​​the second pad portion. In this embodiment, when inspecting the color of the second junction SC2 after applying ultrasonic vibration as described above, the color of the second junction SC2 can be inspected more effectively through the open ODP.

[0186] Figure 12 This is a cross-sectional view showing a display device according to an embodiment of the present invention. Figure 13 This is a plan view illustrating an input sensing unit according to an embodiment of the present invention.

[0187] Reference Figure 12The display device DD includes a display panel DP and an input sensing unit ISU disposed on the display panel DP. In this embodiment, the display panel DP may include a substrate SUB, a circuit layer DP-CL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. In this embodiment, the input sensing unit ISU may include a first conductive layer IS-CL1, a first input sensing insulating layer IS-IL1 disposed on the first conductive layer IS-CL1, a second conductive layer IS-CL2 disposed on the first input sensing insulating layer IS-IL1, and a second input sensing insulating layer IS-IL2 disposed on the second conductive layer IS-CL2. Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single-layer structure or may have a multilayer structure including multiple layers stacked along a third direction DR3.

[0188] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 includes multiple patterns. The first conductive layer IS-CL1 includes a first conductive pattern, and the second conductive layer IS-CL2 includes a second conductive pattern. The first conductive pattern may include an input sensing electrode and a signal line, and the second conductive pattern may include an input sensing electrode and a signal line.

[0189] Reference Figure 13 The input sensing unit (ISU) may include an active region AR and an inactive region NAR surrounding the active region AR, wherein the active region AR and... Figure 4 The display area DD-DA corresponds to and senses external input. The printed circuit board (PCB) may include PCB pads TC-PDz electrically connected to the input sensing unit (ISU).

[0190] In the implementation method, such as Figure 13 As shown, the input sensing unit (ISU) may include first sensing electrodes IE1-1 to IE1-5, first signal lines SL1-1 to SL1-5 connected to the first sensing electrodes IE1-1 to IE1-5, second sensing electrodes IE2-1 to IE2-4, and second signal lines SL2-1 to SL2-4 connected to the second sensing electrodes IE2-1 to IE2-4.

[0191] The first sensing electrodes IE1-1 to IE1-5 intersect with the second sensing electrodes IE2-1 to IE2-4. The first sensing electrodes IE1-1 to IE1-5 are arranged on a first direction DR1, and each of the first sensing electrodes IE1-1 to IE1-5 extends on a second direction DR2. External input, such as a touch on the first sensing electrodes IE1-1 to IE1-5, can be sensed using mutual capacitance and / or self-capacitance. The coordinates of the external input can be calculated during a first cycle using mutual capacitance, and then recalculated during a second cycle using self-capacitance.

[0192] Each of the first sensing electrodes IE1-1 to IE1-5 includes a first sensor portion SP1 and a first connecting portion CP1. Each of the second sensing electrodes IE2-1 to IE2-4 includes a second sensor portion SP2 and a second connecting portion CP2. The size of the two first sensor portions SP1 located at both ends of each of the first sensing electrodes IE1-1 to IE1-5 may be smaller than the size of the first sensor portion SP1 located at the center of each of the first sensing electrodes IE1-1 to IE1-5. In one embodiment, for example, the size of the two first sensor portions SP1 located at both ends may be equal to half the size of the first sensor portion SP1 located at the center. The size of the two second sensor portions SP2 located at both ends of each of the second sensing electrodes IE2-1 to IE2-4 may be smaller than the size of the second sensor portion SP2 located at the center of each of the second sensing electrodes IE2-1 to IE2-4. In one embodiment, for example, the size of the two second sensor portions SP2 located at both ends may be equal to half the size of the second sensor portion SP2 located at the center.

[0193] However, the embodiments of the present invention are not limited to Figure 13 The shapes of the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 are shown. In an alternative embodiment of the invention, each of the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may have a shape that does not distinguish between the sensor portion and the connection portion (e.g., a strip shape). Figure 13 An embodiment in which the first sensor portion SP1 and the second sensor portion SP2 have a rhomboid shape is shown. However, the embodiments of the present invention are not limited thereto. In alternative embodiments, the first sensor portion SP1 and the second sensor portion SP2 may have other polygonal shapes.

[0194] The first signal lines SL1-1 to SL1-5 and the second signal lines SL2-1 to SL2-4 may overlap with the inactive region NAR, and each of the first signal lines SL1-1 to SL1-5 and the second signal lines SL2-1 to SL2-4 may include a pad portion and a line portion. The line portion overlaps with the inactive region NAR and is connected to the input sensing electrode and the pad portion. Hereinafter, the first signal lines SL1-1 to SL1-5 and the second signal lines SL2-1 to SL2-4 will be referred to as signal lines SL.

[0195] The pad portion overlaps with a corresponding input sensing signal pad ISU-PD. The area of ​​the inactive region NAR in which the input sensing signal pad ISU-PD is set can be defined as the sensing pad region NAR-ISC.

[0196] The input sensing signal pad ISU-PD includes multiple first input sensing signal pads ISU-PD1 and multiple second input sensing signal pads ISU-PD2. The first input sensing signal pads ISU-PD1 electrically connect the connection signal pad TC-PD to the input sensing driver chip ISC (see [link]). Figure 14C The first protrusion ISC-BP1 on the input sensing signal pad is connected to the signal line SL via the second input sensing signal pad ISU-PD2.

[0197] According to the implementation method, the input sensing driver chip ISC (see...) Figure 14C It can be installed on the sensing pad area NAR-ISC. In this embodiment, the input sensing signal pad ISU-PD is electrically connected to the input sensing driver chip ISC to send the electrical signal received from the input sensing driver chip ISC to the signal line SL.

[0198] In this embodiment, the connection signal line for connecting the input sensing signal pad ISU-PD and the connection signal pad TC-PD can be disposed in the inactive area NAR. Each of the connection signal lines may include a connection pad portion and a connection line portion.

[0199] The connection pads are individually connected to the ends of the connection lines. The connection pads overlap with a corresponding connection signal pad (TC-PD). The area where the connection signal pad (TC-PD) is located can be defined as the connection pad area (NAR-PC).

[0200] According to an embodiment of the present invention, the area of ​​the flexible printed circuit board (FPC) can be disposed on the connection pad area (NAR-PC). In this embodiment, the connection signal pad (TC-PD) can be electrically connected to the flexible printed circuit board (FPC) to send electrical signals received from the flexible printed circuit board (FPC) to the input sensing signal pad (ISU-PD).

[0201] Figure 14A yes Figure 13 A magnified view of the EE region. Figure 14B It is along Figure 14A The sectional view taken by line AA′. Figure 14C This is an exploded perspective view showing an input sensing driver chip and a packaging substrate according to an embodiment of the present invention. Figure 14D It is along Figure 14C A cross-sectional view taken by line BB′, which shows a display device according to an embodiment of the present invention. Figure 14EIt is along Figure 14C A cross-sectional view taken by line BB′, which shows a display device according to an alternative embodiment of the present invention.

[0202] Figure 14A The diagram shows the line portion SL-L and the pad portion SL-P of two signal lines SL. In this embodiment, reference is made as described above. Figure 13 As described above, the signal line SL includes a line portion SL-L and a pad portion SL-P. However, in an alternative embodiment, the line portion SL-L and the pad portion SL-P may be provided separately. In this embodiment, the input sensing unit ISU may include a signal line SL corresponding to the line portion and pads respectively connected to the signal line SL. In this embodiment, the pads may each correspond to the pad portion SL-P. In embodiments of the present invention, Figure 13 The signal line SL and the pad portion (or pad) SL-P connected to it can form a single unit, or they can be set as separate components connected to each other.

[0203] The area per unit length of each pad in the SL-P section can be larger than the area per unit length of each line in the SL-L section. The pad section SL-P has the following characteristics: Figure 14A The shape shown is a quadrilateral. However, the shape of the pad portion SL-P can be modified or changed in different manufacturing processes.

[0204] In the implementation method, such as Figure 14B As shown, the pad portion SL-P of the signal line SL can be disposed on the thin-film encapsulation layer TFE. The first input sensing insulating layer IS-IL1 can cover the pad portion SL-P of the signal line SL. The second input sensing insulating layer IS-IL2 is disposed on the first input sensing insulating layer IS-IL1, and the input sensing signal pad ISU-PD is disposed on the second input sensing insulating layer IS-IL2.

[0205] Each of the input sensing signal pads ISU-PD is connected to a corresponding pad in the pad section SL-P. Each of the input sensing signal pads ISU-PD can be electrically connected to the corresponding pad section SL-P through a contact hole CNTz defined to penetrate the first input sensing insulating layer IS-IL1 and the second input sensing insulating layer IS-IL2.

[0206] Reference Figure 14C The input sensing driver chip ISC may include a top surface ISC-US and a bottom surface ISC-DS, and may include a plurality of raised ISC-BPs disposed on the bottom surface ISC-DS. In an embodiment, the raised ISC-BPs may be configured as additional components for mounting the input sensing driver chip ISC on the sensing pad area NAR-ISC, and the raised ISC-BPs may not be components of the input sensing driver chip ISC.

[0207] The input sensing signal pads ISU-PD disposed on the thin-film encapsulation layer TFE may include multiple first input sensing signal pads ISU-PD1 and multiple second input sensing signal pads ISU-PD2. The bumps ISC-BP disposed on the bottom surface ISC-DS of the input sensing driver chip ISC may include multiple first bumps ISC-BP1 and multiple second bumps ISC-BP2.

[0208] Reference Figure 14D The input sensing driver chip ISC includes a circuit substrate ISC-PB, circuit pads ISC-PD disposed on the circuit substrate ISC-PB, and solder paste ISC-SR disposed on the circuit substrate ISC-PB to expose the circuit pads ISC-PD. Although not shown in the figures, the circuit pads ISC-PD may include a plurality of circuit pads respectively corresponding to the bumps ISC-BP. Each of the bumps ISC-BP is disposed on a corresponding one of the circuit pads ISC-PD and is electrically connected to a circuit pad ISC-PD.

[0209] Figure 14D The bonding structure between the input sensing signal pad ISU-PD and the bump ISC-BP of the input sensing driver chip ISC can be with Figure 7D The bonding structure between the DC driver chip and the DP-PD driver signal pads is largely the same, so any repeated detailed descriptions will be omitted.

[0210] In this embodiment, the protrusion ISC-BP may be electrically connected to the input sensing signal pad ISU-PD only in the contact area CTA. In this embodiment, as described above, the adhesion status (or adhesion strength) between the protrusion ISC-BP and the input sensing signal pad ISU-PD in the contact area CTA can be checked based on the color of the interface between the protrusion ISC-BP and the second input sensing insulating layer IS-IL2 in the non-contact area NCTA to which ultrasonic vibration is applied.

[0211] Reference Figure 14E In an alternative embodiment of the invention, the pad portion SL-P of the signal line SL may be disposed on the first input sensing insulating layer IS-IL1, instead of on the thin-film encapsulation layer TFE. In this embodiment, the input sensing signal pad ISU-PD may be connected to the pad portion SL-P through a contact hole CNTh defined to penetrate the second input sensing insulating layer IS-IL2.

[0212] Figure 15 This is a cross-sectional view illustrating a display device according to another alternative embodiment of the present invention.

[0213] Reference Figure 15The display device DD may include a display panel DP, an input sensing panel ISP, an anti-reflective panel RPP, a window panel WP, and an adhesive component OCA. In this embodiment, the stacking order of the input sensing panel ISP and the anti-reflective panel RPP may be... Figure 15 Modify it differently as shown.

[0214] exist Figure 15 In the implementation of the display device DD, the input sensing panel ISP and the display panel DP can be set as separate components and can be connected to each other by an adhesive member OCA.

[0215] In this embodiment, Figure 15 The bonding structure between the protrusion of the display panel DP and the signal pads of the input sensing panel ISP shown can be the same as the bonding structure described above.

[0216] According to an embodiment of the present invention, a first portion of a protrusion disposed on an electronic component may directly contact a signal pad disposed on a substrate, and a second portion of the protrusion may directly contact an insulating layer. In this embodiment, the adhesion strength between the signal pad and the first portion of the protrusion can be checked based on the color of the contact surface between the insulating layer and the second portion of the protrusion.

[0217] According to the embodiments of the present invention described herein, the electrical connection status between the substrate and electronic components can be effectively checked, and the overall driving reliability of the display device can be improved.

[0218] Although the invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, it should be understood that the above embodiments are not restrictive but exemplary. Accordingly, the scope of the invention is to be determined by the broadest permissible meaning of the appended claims and their equivalents, and should not be limited or restricted by the foregoing description.

Claims

1. A display device, comprising: Substrate, including display area and non-display area; An insulating layer is disposed on the substrate; Signal pads overlap the non-display area and are respectively disposed on a plurality of contact holes defined in the insulating layer; as well as Electronic components, including multiple drive bumps electrically connected to the signal pads, Wherein, the first portion of the first driving protrusion among the plurality of driving protrusions is disposed on the first signal pad in the signal pad, and The second portion of the first driving protrusion is disposed on the portion of the insulating layer that does not overlap with the first signal pad.

2. The display device as claimed in claim 1, wherein, The first driving bump is aligned with the first signal pad such that the area of ​​the first driving bump that does not overlap with the first signal pad in the plan view is within the range of 10% to 90% of the total area of ​​the first driving bump.

3. The display device as claimed in claim 1, further comprising: Multiple pads are respectively disposed between the substrate and the signal pads. Wherein, the first driving protrusion is aligned with the first pad among the plurality of pads, such that the area of ​​the first driving protrusion that does not overlap with the first pad in the plan view is within the range of 10% to 90% of the total area of ​​the first driving protrusion.

4. The display device as claimed in claim 3, further comprising: Another insulating layer is disposed between the plurality of pads and the substrate.

5. The display device as claimed in claim 3, wherein, The first pad of the plurality of pads overlaps with the first portion of the first drive protrusion, but does not overlap with the second portion of the first drive protrusion.

6. The display device as claimed in claim 1, wherein, The first portion of the first driving protrusion directly faces the first signal pad, and the second portion of the first driving protrusion directly faces the insulating layer.

7. The display device as claimed in claim 1, wherein, The first portion of the first driving protrusion is in direct contact with the first signal pad.

8. The display device as claimed in claim 1, wherein, The structure of each of the signal pads is the same as that of the first signal pad.

9. The display device as claimed in claim 1, wherein, The signal pads also include: The second signal pad is in direct contact with both the first and second portions of the second drive protrusion among the plurality of drive protrusions.

10. The display device as claimed in claim 1, wherein, The electronic component is a data driver chip located in the non-display area.

11. The display device as claimed in claim 1, wherein, The electronic components are flexible printed circuit boards that are partially disposed in the non-display area.

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