Diode-like thyristor-based electrostatic protection device

Abstract

The application discloses a static protection device based on a silicon-controlled rectifier, which comprises a semiconductor substrate, a deep buried layer isolation region embedded into the semiconductor substrate, a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially arranged on the deep buried layer isolation region, a plurality of shallow trench isolation regions sequentially arranged on the upper half of the interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region to isolate the four regions in the surface layer, a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region sequentially arranged from left to right on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, a ground end electrically connected with the semiconductor substrate through a fifth P-type doped region, an input end electrically connected with the semiconductor substrate through the fourth P-type doped region and an output end.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic chip, and particularly relates to a static protection device based on a diode-like thyristor. BACKGROUND

[0002] Electro-static discharge (ESD) is a common cause of reliability problems in integrated circuits, and an ESD protection device can quickly respond to electro-static discharge to provide a low-impedance path for the instantaneous energy of electro-static discharge, thereby improving the reliability of integrated circuits. The ESD protection device is widely used in various electronic products, and different components have different requirements for the ESD protection device. High Definition Multimedia Interface (HDMI), Universal Serial Bus (USB) and Ethernet have very high transmission rates, and since the ESD protection unit related to them is connected in parallel with the protected unit, the protection principle is as shown in Figure 1 , so it is required that the smaller the capacitance of the ESD protection unit is, the better, and the interference on the protected device is reduced. For the ESD protection device, the size of the capacitance is directly related to the junction area of the ESD protection unit, and the smaller the junction area is, the smaller the capacitance is; but in order to have a large ESD capacity, a large junction area is also needed, so the high ESD capacity and the low capacitance requirement are the main contradictions of ESD protection.

[0003] In order to reduce the capacitance of the ESD diode, a low-capacitance diode is often integrated in the ESD protection device in the traditional process, and the low-capacitance diode is connected in series with the ESD protection unit, and the more the number of series connection is, the smaller the capacitance is, such as Figure 2 and Figure 3The internal circuit schematic diagrams of the traditional unidirectional ESD protection device and bidirectional ESD protection device are shown respectively. The new ESD protection unit is composed of D1, D2 and ESD / TVS in series and parallel. The capacitance of the unit is determined by the sum of the capacitances of the two low-capacitance diodes. Different connections are adopted according to requirements to form bidirectional or unidirectional ESD protection units or 4-channel or 8-channel ESD protection units. There are two implementation methods for this method of reducing capacitance by series diodes. One is to integrate diodes on the chip, and the other is to connect diodes in series through copper wires during packaging. Whether the series diodes are integrated in the IC (integrated circuit) or connected by copper wires in the package, the series diodes will introduce body resistance, causing the clamping voltage of the ESD protection device to increase, which cannot effectively realize the protection function. The more diodes in series, the greater the resistance introduced. The method of connecting diodes in series through copper wires during packaging not only introduces the body resistance of diodes, but also introduces the resistance of copper wires. The overall ESD discharge capacity will decrease significantly, and the package size will also increase accordingly. The more diodes in series, the higher the cost. Therefore, generally only one diode can be connected in series.

[0004] In the process of implementing the ESD protection unit, various devices will be used, such as Silicon Controlled Rectifier (SCR), GGNMOS, Diode, etc. The current capacity of SCR, GGNMOS, and Diode decreases in turn.

[0005] The SCR structure is generally composed of PNPN, equivalent to two forward diodes in series, and the capacitance is half of a single diode. The structure of SCR is shown in Figure 4 SCR has strong current capacity, and under the same conditions, the current capacity of SCR structure is about twice that of a forward diode. However, due to the existence of NW → PW reverse diode, this will cause the trigger voltage of the entire ESD device to be too large, and the IV curve of the SCR structure has a snapback phenomenon, which will lead to latchup problems, and cannot meet the application requirements. The generated IV curve is shown in Figure 5

[0006] Although the SCR structure has relatively low capacitance and relatively high current capacity, the existence of the NW SUMMARY

[0007] ​In view of the above problems, the present application provides a static protection device based on a diode-like thyristor, which can reduce the capacitance of an ESD protection unit while increasing its ESD capability.

[0008] To solve the above technical problems, the present application adopts the following technical solutions:

[0009] In a first aspect, the present application provides a static protection device based on a diode-like thyristor, which comprises:

[0010] a semiconductor substrate;

[0011] a deep buried layer isolation region embedded into the semiconductor substrate;

[0012] a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region arranged in sequence on the deep buried layer isolation region;

[0013] a plurality of shallow trench isolation regions arranged in sequence on the upper half of the interface of each of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, thereby isolating the four regions in the surface layer;

[0014] a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region arranged in sequence from left to right on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region.

[0015] a ground terminal electrically connected to the semiconductor substrate through a fifth P-type doped region;

[0016] an input terminal electrically connected to the semiconductor substrate through the fourth P-type doped region;

[0017] an output terminal electrically connected to the semiconductor substrate through the third N-type doped region.

[0018] In a possible implementation, the ground terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

[0019] In a possible implementation, the input terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

[0020] In a possible implementation, the power terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

[0021] In a possible implementation, the present application further comprises a forward diode, the ground terminal is electrically connected to the anode of the forward diode, and the cathode of the forward diode is electrically connected to the semiconductor substrate through the third N-type doped region.

[0022] In a possible implementation, the semiconductor substrate is a P-type semiconductor substrate; an N-type semiconductor substrate epitaxial P-type epitaxial layer, or an N-type semiconductor substrate epitaxial P-type epitaxial layer:

[0023] In a second aspect, the application provides a track-based ESD static protection circuit, two or more series-connected diodes are used between PAD and VDD, the anode of the diode is connected to PAD, and the cathode is connected to VDD, to discharge static electricity from PAD to VDD; two or more series-connected diodes are used between PAD and VSS, the anode of the diode is connected to VSS, and the cathode is connected to PAD, to discharge static electricity from PAD to VSS; a transient voltage suppression diode is used between VDD and VSS to discharge static electricity between VDD and VSS, wherein the diode and the transient voltage suppression diode are the static protection devices based on the silicon-controlled rectifier-like diode as described in any of the above.

[0024] In a possible implementation, the diode series is connected such that the output end of the previous static protection device based on the silicon-controlled rectifier-like diode is connected to the input end of the next static protection device based on the silicon-controlled rectifier-like diode.

[0025] In a third aspect, the application provides a local floating track ESD static protection circuit, two or more series-connected diodes are used between PAD and ESDP, the anode of the diode is connected to PAD, and the cathode is connected to ESDP, to discharge positive static electricity from PAD to ESDP; two or more series-connected diodes are used between PAD and ESDN, the anode of the diode is connected to ESDN, and the cathode is connected to PAD, to discharge negative static electricity from PAD to ESDN; a transient voltage suppression diode is used between ESDP and ESDN to discharge positive static electricity between VDD and VSS, wherein the diode or the transient voltage suppression diode is the static protection device based on the silicon-controlled rectifier-like diode as described in any of the above.

[0026] In a possible implementation, the diode series is connected such that the output end of the previous static protection device based on the silicon-controlled rectifier-like diode is connected to the input end of the next static protection device based on the silicon-controlled rectifier-like diode.

[0027] The application has the following beneficial effects: the application provides a new electrostatic protection device based on a diode-like silicon-controlled rectifier (DL-SCR), two (or more) forward diodes connected in series in the body replace a single diode D1 or D2 in the traditional process, for the convenience of expression, the structure of two or more forward diodes connected in series is defined as "diode-like silicon-controlled rectifier structure: Diode-Like SCR, abbreviated as DL-SCR". The DL-SCR is composed of P / NW (the first forward diode) and PW / N (the second forward diode) connected in the body, and is isolated by P / PW+N / NW+DNW, which removes the parasitic effect of the DL-SCR and other devices, so that the DL-SCR does not produce snapback effect, and since two diodes are connected in series, the capacitance of the DL-SCR is half of that of a single diode. The structure Pad is connected with the P region, VDD is connected with the N region, and the metal wire is used to integrate the ESD / TVS protection unit on a chip, and the path is responsible for the positive ESD pulse path. The negative ESD pulse path is discharged through another DL-SCR structure. The low-capacitance structure connected in series and parallel is one time lower than the low-capacitance diode in the traditional process, so the capacitance of the overall structure is one time lower than that of the traditional method. At the same time, the DL-SCR changes from the low-current-capability forward diode structure in the traditional method to the high-current-capability SCR structure due to its SCR structure, and the resistance per unit area is also correspondingly reduced. Without increasing the cost and losing the performance, the design requirement of low capacitance is achieved. The application not only reduces the capacitance, but also improves the overall ESD capability of the module and reduces the clamping voltage of the module. Therefore, the application has an important breakthrough in improving the contradiction between the ESD protection capability and the capacitance. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a schematic diagram of an ESD protection circuit in the prior art;

[0029] Figure 2 It is a schematic diagram of a unidirectional ESD protection circuit in the prior art;

[0030] Figure 3 It is a schematic diagram of a bidirectional ESD protection circuit in the prior art;

[0031] Figure 4 It is a schematic diagram of an SCR equivalent circuit in the prior art;

[0032] Figure 5 It is an IV curve diagram of a parasitic effect of an SCR equivalent circuit in the prior art;

[0033] Figure 6 It is a schematic diagram of an electrostatic protection device based on a diode-like silicon-controlled rectifier in embodiment 1 of the application;

[0034] Figure 7A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 2 of the present application;

[0035] Figure 8 A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 3 of the present application;

[0036] Figure 9 A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 4 of the present application;

[0037] Figure 10 A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 5 of the present application;

[0038] Figure 11 A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 6 of the present application;

[0039] Figure 12 A schematic diagram of a static protection device based on a silicon-controlled rectifier diode according to Embodiment 7 of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the protection scope of the present application.

[0041] Embodiment 1

[0042] Referring to FIG. 1, a static protection device based on a silicon-controlled rectifier diode according to Embodiment 1 of the present application is shown, Figure 6 as shown in the upper right part, comprising: Figure 6 a semiconductor substrate (P-sub);

[0043] a deep well isolation region (DNW) embedded into the semiconductor substrate;

[0044] a first N-type doped region (NW), a first P-type doped region (PW), a second N-type doped region (NW) and a second P-type doped region (PW) arranged in sequence on the deep well isolation region;

[0045] a plurality of shallow trench isolation regions (STI) arranged in sequence on the upper half of each interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, isolating the four regions in the surface layer;

[0046] a plurality of shallow trench isolation regions (STI) arranged in sequence on the upper half of each interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, isolating the four regions in the surface layer;

[0047] The third N-type doped region, the third P-type doped region, the fourth P-type doped region and the fourth N-type doped region are sequentially arranged from left to right on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region;

[0048] The ground end (Gnd) is electrically connected with the semiconductor substrate through the fifth P-type doped region;

[0049] The input end (Vin) is electrically connected with the semiconductor substrate through the fourth P-type doped region;

[0050] The output end (Vout) is electrically connected with the semiconductor substrate through the third N-type doped region.

[0051] In the structure, the DL-SCR is composed of P / NW / PW / N internally connected, the input end is above the P / NW, and the output end is above the N / PW. The DL-SCR is located in the isolation region composed of N / NW+DNW+P / PW, the P / PW is located between the P / NW and the N / NW, and the N / NW+DNW+P / PW are all suspended and do not lead to any electrode. All the above structures are located on the P-Sub, and the P-Sub is led to the Gnd through P. The structure can be repeated to multiple channels according to application requirements. For example, two channels, PAD1 and PAD2 are equivalent.

[0052] In actual application, for example, Figure 6 As shown in the left part of the circuit, the upward SCR1 is replaced by the DL-SCR, the input end of the DL-SCR is connected with the PAD, the output end is connected with the VDD, and the GND electrode is grounded. The downward SCR2 is replaced by the DL-SCR, the input end of the DL-SCR is connected with the Gnd, the output end is connected with the PAD, and the VSS and the GND electrode are both ground electrodes.

[0053] When the PAD1 or the PAD2 has a positive ESD pulse, the current path flows to the upward DL-SCR structure through the PAD1 or the PAD2, the current path in the DL-SCR is P→NW→PW→N, and then flows to the ESD / TVS unit through the VDD and finally flows to the VSS for discharge.

[0054] When the PAD1 or the PAD2 has a negative ESD pulse, the current path flows into the downward series-connected DL-SCR structure through the VSS, the current path in the structure is P→NW→PW→N, and then flows into the PAD for discharge.

[0055] When a forward ESD occurs between VSS and VDD, there are two current paths, the first path is the DL-SCR parasitic SCR3: P→P-sub→DNW→PW→N, the other path is the forward of ESD / TVS. The discharge path from VSS to PAD is only one, which is VSS→P→NW→PW→N→PAD described in SCR2. In a specific application example, the semiconductor substrate is a P-type semiconductor substrate; an N-type semiconductor substrate epitaxial P-type epitaxial layer, or an N-type semiconductor substrate epitaxial P-type epitaxial layer.

[0056] Embodiment 2

[0057] Based on embodiment 1, referring to Figure 7 , another embodiment of the static protection device based on silicon-controlled diode includes:

[0058] A semiconductor substrate;

[0059] A deep buried layer isolation region embedded into the semiconductor substrate;

[0060] A first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region are sequentially arranged on the deep buried layer isolation region;

[0061] A plurality of shallow trench isolation regions are sequentially arranged on the upper half of the interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, and the four regions are isolated in the surface layer;

[0062] A third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right;

[0063] The ground end is electrically connected to the semiconductor substrate through the fifth P-type doped region;

[0064] The input end is electrically connected to the semiconductor substrate through the fourth P-type doped region;

[0065] The output end is electrically connected to the semiconductor substrate through the third N-type doped region;

[0066] The ground end is also electrically connected to the semiconductor substrate through the third P-type doped region.

[0067] In the structure, the DL-SCR is composed of P / NW / PW / N internally connected, the input end is above the P / NW, and the output end is above the N / PW. The DL-SCR is located in an isolation region composed of N / NW+DNW+P / PW, the P / PW is located between the P / NW and the N / NW, the N / NW+DNW is suspended, and the P / PW is led out to the ground electrode Gnd, so that the current discharge path of the positive ESD pulse of VSS can be increased. All the above structures are located on the P-Sub, and the P-Sub leads out the ground electrode Gnd through P. The structure can be repeated into multiple channels according to application needs, such as two channels, PAD1 and PAD2 are equivalent.

[0068] In practical applications, as shown in the circuit, Figure 7 As shown in the circuit, the upward SCR1 is replaced by the DL-SCR, the input end of the DL-SCR is connected with the PAD, the output end is linked with the VDD, and the GND electrode is grounded; the downward SCR2 is replaced by the DL-SCR, the input end of the DL-SCR is connected with the Gnd, the output end is connected with the PAD, and the VSS and the GND electrode are both ground electrodes.

[0069] When the PAD1 or the PAD2 has a positive ESD, the current path flows to the upward DL-SCR structure through the PAD1 or the PAD2, the current path in the low-capacitance structure is P→NW→PW→N, and then flows to the ESD / TVS device through the VDD and finally flows to the VSS for discharge.

[0070] When the PAD1 or the PAD2 has a negative ESD, the current path flows into the downward series-connected DL-SCR structure through the VSS, the current path in the structure is P→NW→PW→N, and then flows into the PAD for discharge.

[0071] When the VSS has a positive ESD pulse, there are two current paths from the VSS to the VDD, the first path is the DL-SCR parasitic SCR3: P→P-sub→DNW→PW→N, and the other path is the positive direction of the ESD / TVS. The discharge path of the VSS to the PAD has only one path, which is the VSS→P→NW→PW→N→PAD described in the SCR2.

[0072] Embodiment 3

[0073] On the basis of the embodiment 1, as shown in the circuit, Figure 8 The electrostatic protection device based on the silicon-controlled diode-like device according to the embodiment of the application comprises:

[0074] A semiconductor substrate;

[0075] A deep buried layer isolation region embedded into the semiconductor substrate;

[0076] The first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region are sequentially arranged on the deep buried isolation region;

[0077] The plurality of shallow trench isolation regions are sequentially arranged on the upper half of each interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, and the four regions are isolated in the surface layer;

[0078] The third N-type doped region, the third P-type doped region, the fourth P-type doped region and the fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right;

[0079] The ground terminal is electrically connected with the semiconductor substrate through the fifth P-type doped region;

[0080] The input terminal is electrically connected with the semiconductor substrate through the fourth P-type doped region;

[0081] The output terminal is electrically connected with the semiconductor substrate through the third N-type doped region;

[0082] The input terminal is electrically connected with the semiconductor substrate through the third P-type doped region.

[0083] In the structure, the DL-SCR is composed of P / NW / PW / N internally connected, the input terminal is above the P / NW, and the output terminal is above the N / PW. The DL-SCR is located in the isolation region composed of N / NW+DNW+P / PW, the P / PW is located between the P / NW and the N / NW, the N / NW+DNW is floating, and the P / PW is short-circuited to the input terminal, which can increase the current discharge path of the input terminal when a forward ESD pulse occurs. All the above structures are located on the P-Sub, and the P-Sub leads out the Vss electrode through P. The structure can be repeated into multiple channels according to application needs, such as two channels, PAD1 and PAD2 are equivalent.

[0084] In actual application, as shown in the circuit, Figure 8 As shown in the circuit, the upward SCR1 is replaced by the DL-SCR, the input terminal of the DL-SCR is connected with the PAD, the output terminal of the DL-SCR is connected with the VDD, and the GND electrode is grounded. The downward SCR2 is replaced by the DL-SCR, the input terminal of the DL-SCR is connected with the Gnd, the output terminal of the DL-SCR is connected with the PAD, and the VSS and the GND electrodes are both ground electrodes.

[0085] When the PAD1 or the PAD2 has a forward ESD, there are two current paths, one is:

[0086] PAD→P→PW→DNW→PW→N→VDD; another path is: PAD→P→NW→PW→N→VDD, and then flows to the ESD / TVS device through VDD, and finally flows to VSS to discharge.

[0087] When a negative ESD occurs at PAD1 or PAD2, the current path flows into the lower series low-cap structure through VSS, the current path in the structure is P→NW→PW→N, and then flows into PAD to discharge.

[0088] When a positive ESD pulse occurs at VSS, there are two current paths from VSS to VDD, the first path is the DL-SCR parasitic SCR3: P→P-sub→DNW→PW→N, and the other path is the positive direction of the ESD / TVS. The discharge path from VSS to PAD has only one path, which is VSS→P→NW→PW→N→PAD described in SCR2.

[0089] Embodiment 4

[0090] Referring to Figure 9 , a static protection device based on a thyristor-like diode according to an embodiment of the present application is shown, comprising:

[0091] a semiconductor substrate;

[0092] a deep buried isolation region embedded into the semiconductor substrate;

[0093] a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region, which are sequentially arranged on the deep buried isolation region;

[0094] a plurality of shallow trench isolation regions, which are sequentially arranged on the upper half of each interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, and isolate the four regions in the surface layer;

[0095] a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right;

[0096] a ground terminal, which is electrically connected to the semiconductor substrate through the fifth P-type doped region;

[0097] an input terminal, which is electrically connected to the semiconductor substrate through the fourth P-type doped region;

[0098] an output terminal, which is electrically connected to the semiconductor substrate through the third N-type doped region and also electrically connected to the semiconductor substrate through the third P-type doped region.

[0099] The DL-SCR is isolated by P / PW+N / NW+DNW, in which the DL-SCR is composed of P / NW / PW / N internally connected, the input end is above P / NW, and the output end is above N / PW. The DL-SCR is located in the isolation region composed of N / NW+DNW+P / PW, P / PW is located between P / NW and N / NW, N / NW+DNW is floating, P / PW is led out to the output end, and a negative pulse discharge path is added from the input end to the output end. All the above structures are located on the P-Sub, and the P-Sub leads out the Vss electrode through P. The structure can be repeated into multiple channels according to application needs, such as two channels, PAD1 and PAD2 are equivalent.

[0100] In practical applications, such as Figure 9 As shown in the circuit, the upward SCR1 is replaced by the DL-SCR, the input end of the DL-SCR is connected with PAD, the output end is linked with VDD, and the GND electrode is grounded; the downward SCR2 is replaced by the DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end is connected with PAD, and the VSS and GND electrodes are both ground electrodes.

[0101] When the PAD1 or PAD2 has a positive ESD, the current path is: PAD→P→NW→PW→N→VDD, and then flows to the ESD / TVS device through VDD, and finally flows to VSS for discharge.

[0102] When the PAD1 or PAD2 has a negative ESD, there are three current discharge paths. One current path flows into the lower series low-capacitance structure through VSS, the current path in the structure is VSS→P→NW→PW→N→PAD, and flows into PAD for discharge. Another current path is VDD

[0103] When the VSS has a positive ESD pulse, there are two current paths from VSS to VDD, the first path is the DL-SCR parasitic SCR3: P→P-sub→DNW→PW→N, and the other path is the positive direction of the ESD / TVS. The discharge path from VSS to PAD has only one path, which is VSS→P→NW→PW→N→PAD described in SCR2.

[0104] Embodiment 5

[0105] Referring to Figure 10 , a static protection device based on a thyristor-like diode according to an embodiment of the present application is shown, which comprises:

[0106] A semiconductor substrate;

[0107] A deep buried layer isolation region embedded into the semiconductor substrate;

[0108] The first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region are sequentially arranged on the deep buried isolation region;

[0109] The plurality of shallow trench isolation regions are sequentially arranged on the upper half of each interface of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, and the four regions are isolated in the surface layer;

[0110] The third N-type doped region, the third P-type doped region, the fourth P-type doped region and the fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right;

[0111] The ground terminal is electrically connected to the semiconductor substrate through the fifth P-type doped region;

[0112] The input terminal is electrically connected to the semiconductor substrate through the fourth P-type doped region;

[0113] The output terminal is electrically connected to the semiconductor substrate through the third N-type doped region;

[0114] The positive terminal of the forward diode is electrically connected to the ground terminal, and the negative terminal of the forward diode is electrically connected to the semiconductor substrate through the third N-type doped region. The forward diode can be a clamping diode, a MOS diode or a Schottky diode, etc.

[0115] The N region of the DL-SCR is connected to the outside through a forward diode (which can also be any other ESD device, such as GGNMOS, SCR, Zener-Diode, etc.), so as to achieve the purpose of controlling the basic carriers.

[0116] In actual application, for example, Figure 10 As shown in the circuit, the upward SCR1 is replaced by the DL-SCR, the input terminal of the DL-SCR is connected to the PAD, the output terminal of the DL-SCR is connected to the VDD, and the GND electrode is grounded. The downward SCR2 is replaced by the DL-SCR, the input terminal of the DL-SCR is connected to the Gnd, the output terminal of the DL-SCR is connected to the PAD, and the VSS and the GND electrode are both grounded electrodes.

[0117] Embodiment 6

[0118] Referring to Figure 11, as shown in an embodiment of the present application is a kind of ESD static protection circuit based on rail, for PAD to rail and the static protection design between the PAD of common rail. Between PAD and VDD, two or more first-end connected diode is used in series, the anode of diode is connected to PAD, cathode is connected to VDD, the static electricity of PAD is discharged to VDD;PAD to VSS, two or more first-end connected diode is used in series, the anode of diode is connected to VSS, cathode is connected to PAD, the static electricity of PAD is discharged to VSS;VDD to VSS is connected using transient voltage suppression diode, and the static electricity between VDD and VSS is discharged. The diode or transient voltage suppression diode in it adopts the static protection device based on silicon-controlled diode like any one of embodiment 1 to embodiment 5. Wherein diode series connection is: the output end of the last static protection device based on silicon-controlled diode is connected to the input end of the next static protection device based on silicon-controlled diode.

[0119] Embodiment 7

[0120] Reference Figure 12 , as shown in an embodiment of the present application is a kind of ESD static protection circuit based on rail, for PAD to rail and the static protection design between the PAD of common rail. Between PAD and VDD, two or more first-end connected diode is used in series, the anode of diode is connected to PAD, cathode is connected to VDD, the static electricity of PAD is discharged to VDD;PAD to VSS, two or more first-end connected diode is used in series, the anode of diode is connected to VSS, cathode is connected to PAD, the static electricity of PAD is discharged to VSS;VDD to VSS is connected using transient voltage suppression diode, and the static electricity between VDD and VSS is discharged. The diode or transient voltage suppression diode in it adopts the static protection device based on silicon-controlled diode like any one of embodiment 1 to embodiment 5. Wherein diode series connection is: the output end of the last static protection device based on silicon-controlled diode is connected to the input end of the next static protection device based on silicon-controlled diode.

[0121] It should be understood that the exemplary embodiments described herein are illustrative and non-limiting. Although one or more embodiments of the present application are described in conjunction with the attached figures, it should be understood that various changes in form and detail can be made without departing from the spirit and scope of the application as defined by the appended claims.

Claims

1. An electrostatic discharge protection device based on a silicon controlled rectifier diode, characterized in that, include: Semiconductor substrate (P-sub); The buried isolation region (DNW) is embedded in the semiconductor substrate (P-sub); A first N-type doped region (NW), a first P-type doped region (PW), a second N-type doped region (NW), and a second P-type doped region (PW) are sequentially disposed on the buried layer isolation region (DNW); Multiple shallow trench isolation regions (STIs) are sequentially disposed in the upper half of the interfaces of the first N-type doped region (NW), the first P-type doped region (PW), the second N-type doped region (NW), and the second P-type doped region (PW), thus isolating these four regions on the surface. A third N-type doped region (N) is provided on the first N-type doped region (NW), a third P-type doped region (P) is provided on the first P-type doped region (PW), a fourth P-type doped region (P) is provided on the second N-type doped region (NW), and a fourth N-type doped region (N) is provided on the second P-type doped region (PW). The ground terminal (GND) is electrically connected to the semiconductor substrate through the fifth P-type doped region (P); The input terminal (Vin) is electrically connected to the semiconductor substrate through the fourth P-type doped region (P); The output terminal (Vout) is electrically connected to the semiconductor substrate through the third N-type doped region (N); The diode-like silicon controlled rectifier (DL-SCR) structure is composed of four interconnected P-type doped regions (P), two N-type doped regions (NW), two P-type doped regions (PW), and four N-type doped regions (N). The input terminal (Vin) is located above the four P-type doped regions (P) and the two N-type doped regions (NW), and the output terminal (Vout) is located above the four N-type doped regions (N) and the two P-type doped regions (PW).

2. The electrostatic discharge protection device based on a quasi-thyristor diode as described in claim 1, characterized in that, The grounding terminal is electrically connected to the semiconductor substrate through a third P-type doped region.

3. The electrostatic discharge protection device based on a quasi-thyristor diode as described in claim 1, characterized in that, The input terminal is electrically connected to the semiconductor substrate through a third P-type doped region.

4. The electrostatic discharge protection device based on a quasi-thyristor diode as described in claim 1, characterized in that, The output terminal is electrically connected to the semiconductor substrate through a third P-type doped region.

5. The electrostatic discharge protection device based on a quasi-thyristor diode as described in claim 2, characterized in that, It further includes a forward diode, the ground terminal being electrically connected to the positive terminal of the forward diode, and the negative terminal of the forward diode being electrically connected to the semiconductor substrate through a third N-type doped region.

6. The electrostatic discharge protection device based on a quasi-thyristor diode as described in any one of claims 1 to 5, characterized in that, The semiconductor substrate is a P-type semiconductor substrate; an N-type semiconductor substrate is epitaxially layered with a P-type epitaxial layer, or an N-type semiconductor substrate is epitaxially layered with a P-type epitaxial layer.

7. A rail-based ESD electrostatic protection circuit, characterized in that, A first electrostatic discharge (ESD) protection device is used between PAD and VDD. The anode of the first ESD protection device is connected to PAD and the cathode is connected to VDD to discharge the static electricity of PAD to VDD. A second electrostatic discharge (ESD) protection device is used between PAD and VSS. The anode of the second ESD protection device is connected to VSS and the cathode is connected to PAD to discharge the static electricity of PAD to VSS. A third electrostatic discharge (ESD) protection device is used to connect VDD to VSS to discharge static electricity between VDD and VSS. The first, second, and third ESD protection devices are ESD protection devices based on quasi-thyristor diodes as described in any one of claims 1 to 6.

8. The rail-based ESD electrostatic protection circuit as described in claim 7, characterized in that, The output terminal of the first electrostatic discharge (ESD) protection device is connected to the input terminal of the second ESD protection device.

9. An ESD electrostatic protection circuit for a partially floating rail, characterized in that, A fourth electrostatic discharge (ESD) protection device exists between PAD and ESDP, with its anode connected to PAD and its cathode connected to ESDP, discharging positive static electricity from PAD to ESDP. A fifth ESD protection device exists between PAD and ESDN, with its anode connected to ESDN and its cathode connected to PAD, discharging negative static electricity from PAD to ESDN. A sixth ESD protection device is used to connect ESDP to ESDN, discharging positive static pulses between VDD and VSS. The fourth, fifth, and sixth ESD protection devices are ESD protection devices based on quasi-thyristor diodes as described in any one of claims 1 to 6.

10. The ESD electrostatic protection circuit for a partially floating rail as described in claim 9, characterized in that, The output terminal of the fourth electrostatic discharge protection device is connected to the input terminal of the fifth electrostatic discharge protection device.

Images