A beamformed data processing system

Abstract

This invention discloses a beamforming data processing system. The data processing system includes multiple first-column cascaded pre-multiplier sequences, second-column cascaded pre-multiplier sequences, third-column cascaded pre-multiplier sequences, a first adder, and a second adder. The number of pre-multipliers in the first, second, and third-column cascaded pre-multiplier sequences is the same, equal to the stream number N of the multidimensional complex input signal. The number of pre-multipliers in the beamforming data processing system is 3*N. Through this embodiment, a beamforming data processing system can be constructed using a relatively small number of pre-multipliers.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a beamforming data processing system. Background Technology

[0002] The core technologies in fourth-generation mobile communication systems (4G) and fifth-generation wireless communication systems (5G) include beamforming, which is a technique that uses an antenna array to construct the radiation direction of radio frequency signals. By adjusting parameters such as the phase of the antenna array, signals at certain angles will have constructive interference, while signals at other angles will have destructive interference, thereby constructing the direction and shape of the beam.

[0003] In existing technologies, beamforming is mathematically essentially a complex matrix multiplication operation, and its data processing can be represented as the following complex matrix multiplication operation: Y = A × X, where X = (x ij ) N×L For a one-dimensional or multi-dimensional complex input signal, A = (a ij ) M×N Beamforming a 2D complex matrix, Y = (y ij ) M×L The output signal is a one-dimensional or multi-dimensional complex number. The complex matrix multiplication operation requires a large number of multipliers in the chip or field programmable gate array (FPGA) implementation, resulting in a large resource consumption and high cost of multipliers.

[0004] In summary, reducing the number of multipliers in complex matrix operations is a problem that needs to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a beamforming data processing system that can reduce the number of multipliers during complex matrix operations.

[0006] In a first aspect, embodiments of the present invention provide a beamforming data processing system, the system comprising: a plurality of first column cascaded pre-multiplier sequences, a second column cascaded pre-multiplier sequences, a third column cascaded pre-multiplier sequences, a first adder, and a second adder;

[0007] In the first cascaded pre-multiplier sequence, the input of the first pre-multiplier is the real part of the beamforming complex matrix. The imaginary part of the beamforming complex matrix and the real part of the multidimensional complex input signal The output of the last pre-multiplier in the first cascaded pre-multiplier sequence is

[0008] The input to the first pre-multiplier in the second cascaded pre-multiplier sequence is the imaginary part of the beamforming complex matrix. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal The output of the last pre-multiplier in the second cascaded pre-multiplier sequence is

[0009] The input to the first pre-multiplier in the third cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal The output of the last pre-multiplier in the third cascaded pre-multiplier sequence is:

[0010] The inputs of the first adder are the outputs of the last pre-multiplier in the first cascaded pre-multiplier sequence and the output of the last pre-multiplier in the second cascaded pre-multiplier sequence. The output of the first adder is the real part of the multidimensional complex output signal.

[0011] The inputs of the second adder are the outputs of the last pre-adder in the first cascaded pre-adder multiplier sequence and the output of the last pre-adder multiplier in the third cascaded pre-adder multiplier sequence. The output of the second adder is the imaginary part of the multidimensional complex output signal.

[0012] Wherein, N is the stream number of the multidimensional complex input signal, and N is greater than or equal to 2.

[0013] Optionally, the number of pre-multipliers in the first, second, and third cascaded pre-multiplier sequences is the same, and the number is equal to the stream number of the multidimensional complex input signal.

[0014] Optionally, the input to the 2nd to Nth pre-multipliers in the first cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The imaginary part of the beamforming complex matrix The real part of the multidimensional complex input signal And the output of the previous pre-multiplier;

[0015] The input to the 2nd to Nth pre-multipliers in the second cascaded pre-multiplier sequence is the imaginary part of the beamforming complex matrix. The real part of the multidimensional complex input signal The imaginary part of the multidimensional complex input signal And the output of the previous pre-multiplier;

[0016] The input to the 2nd to Nth premultipliers in the third cascaded premultiplier sequence is the imaginary part of the beamforming complex matrix. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal And the output of the previous pre-multiplier.

[0017] Optionally, the input port of the pre-multiplier is a normal input port or a cascaded input port, and the output port of the pre-multiplier is a normal output port or a cascaded output port.

[0018] Optionally, the input port of the first pre-multiplier in each column of the first, second, and third cascaded pre-multiplier sequences is a normal input port, and the input ports of the second to Nth pre-multipliers in each column are cascaded input ports.

[0019] Optionally, the output ports of the first to the (N-1)th pre-multipliers in each column of the first, second, and third cascaded pre-multiplier sequences are cascaded output ports, and the output port of the Nth pre-multiplier in each column is a normal output port.

[0020] Optionally, the system further includes: multiple registers, wherein the registers are inserted into the first column of cascaded pre-multiplier sequences, the second column of cascaded pre-multiplier sequences, the third column of cascaded pre-multiplier sequences, and the signal input position of the pre-multiplier.

[0021] Optionally, the register is inserted into the first column of cascaded pre-accumulator multiplier sequences, the second column of cascaded pre-accumulator multiplier sequences, and the third column of cascaded pre-accumulator multiplier sequences, specifically including:

[0022] For each cascaded pre-multiplier sequence, the register is inserted between the normal output port of multiple pre-multipliers in each cascaded pre-multiplier and the normal input port of the next pre-multiplier, according to the requirements of cascade structure optimization.

[0023] Optionally, the register is inserted at the signal input position of the pre-multiplier, specifically including:

[0024] The register is inserted into the real part of the beamforming complex matrix of the pre-multiplier. The imaginary part of the beamforming complex matrix The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal The input location.

[0025] Optionally, the number of registers at the input positions varies and increases with the number of streams N.

[0026] The data processing system of this invention includes multiple first-column cascaded pre-multiplier sequences, second-column cascaded pre-multiplier sequences, third-column cascaded pre-multiplier sequences, a first adder, and a second adder. The number of pre-multipliers in the first, second, and third-column cascaded pre-multiplier sequences is the same, equal to the stream number N of the multidimensional complex input signal. The number of pre-multipliers in the beamforming data processing system is 3*N. Through the above embodiment, a beamforming data processing system can be constructed using a relatively small number of pre-multipliers. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a schematic diagram of the structure of a pre-multiplier according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a beamforming data processing system according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of another beamforming data processing system according to an embodiment of the present invention. Detailed Implementation

[0031] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0032] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0033] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0034] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0035] In existing technologies, beamforming is mathematically essentially a complex matrix multiplication operation, and its data processing can be represented as the following complex matrix multiplication operation: Y = A × X, where X = (x ij ) N×L For a one-dimensional or multi-dimensional complex input signal, A = (a ij ) M×N Beamforming a 2D complex matrix, Y = (y ij ) M×L The output signal is a one-dimensional or multi-dimensional complex number. The complex matrix multiplication operation requires a large number of multipliers in its implementation on a chip or field-programmable gate array (FPGA), resulting in high resource consumption and cost. Specifically, N is the stream number or layer dimension of the multi-dimensional complex input signal, L is the time dimension, M is the antenna dimension, and Y = (y ij ) M×L It can be represented as:

[0036]

[0037] For the multidimensional complex input signal complex data x nj and beamforming 2D complex matrix a i Decompose the real and imaginary parts, so that Furthermore, the multidimensional complex output signal y ij It is expressed as follows:

[0038]

[0039]

[0040] As can be seen from the above formulas (1) and (2), the existing technology requires four multiplier sequences to construct a beamforming data processing system, each used for processing... and

[0041] Specifically, each multiplier sequence includes N multipliers, which are connected in a cascaded manner. In existing technologies, 4*N multipliers are required for each antenna dimension. Therefore, constructing a beamforming data processing system for M antenna dimensions requires 4*N*M multipliers, which is a large number. Furthermore, the cascading of N multipliers in each multiplier sequence, along with the simple structure, can lead to static timing issues such as time delays. Therefore, reducing the number of multipliers required to construct a beamforming data processing system and resolving static timing problems are current challenges that need to be addressed.

[0042] In this embodiment of the invention, to address the issue of a large number of multipliers when constructing a beamforming data processing system, a pre-addition multiplier is used instead of the multipliers employed in the prior art. Specifically, the structure of the pre-addition multiplier is as follows: Figure 1 As shown, the input side of the pre-multiplier includes an A input interface, a B input interface, a C input interface, a Pin input interface, and a Pcin input interface. The output side of the pre-multiplier includes a Pout output interface and a Pcout output interface. The A, B, C, and Pin input interfaces are ordinary input ports, while the Pcin input interface is a cascaded input port. The Pout output interface is an ordinary output port, and the Pcout output interface is a cascaded output port. Only one of the Pin and Pcin input interfaces can be used at a time, and only one of the Pout and Pcout output interfaces can be used at a time.

[0043] Because the pre-multiplier has a cascading function, the Pcin cascading input port of the pre-multiplier can only be connected to the Pcout cascading output port of another pre-multiplier through a dedicated connection. Similarly, the Pcout cascading output port of the pre-multiplier can only be connected to the Pcin cascading input port of another pre-multiplier through a dedicated connection.

[0044] In this embodiment of the invention, the pre-multiplier can be configured to perform the following functions, specifically: Pout / Pcout = (A+B)*C; or, Pout / Pcout = (AB)*C; or, Pout / Pcout = (A+B)*C+Pin / Pcin; or, Pout / Pcout = (AB)*C+Pin / Pcin.

[0045] In this embodiment of the invention, the pre-multiplier is used as the basic unit to construct a beamforming data processing system. Figure 2 This is a schematic diagram of a beamforming data processing system according to an embodiment of the present invention. Figure 2As shown, the system includes: multiple first-column cascaded pre-multiplier sequences, second-column cascaded pre-multiplier sequences, third-column cascaded pre-multiplier sequences, a first adder, and a second adder; wherein, the input of the first pre-multiplier in the first-column cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The imaginary part of the beamforming complex matrix and the real part of the multidimensional complex input signal The output of the last pre-multiplier in the first cascaded pre-multiplier sequence is The input to the first pre-multiplier in the second cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal The output of the last pre-multiplier in the second cascaded pre-multiplier sequence is The input to the first pre-multiplier in the third cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal The output of the last pre-multiplier in the third cascaded pre-multiplier sequence is: The inputs of the first adder are the outputs of the last pre-multiplier in the first cascaded pre-multiplier sequence and the output of the last pre-multiplier in the second cascaded pre-multiplier sequence. The output of the first adder is the real part of the multidimensional complex output signal. The inputs of the second adder are the outputs of the last pre-adder in the first cascaded pre-adder multiplier sequence and the output of the last pre-adder multiplier in the third cascaded pre-adder multiplier sequence. The output of the second adder is the imaginary part of the multidimensional complex output signal. Wherein, N is the stream number of the multidimensional complex input signal, and N is greater than or equal to 2.

[0046] In one possible implementation, the number of pre-multipliers in the first, second, and third cascaded pre-multiplier sequences is the same, and this number is equal to the stream number of the multidimensional complex input signal.

[0047] In one possible implementation, the input to the 2nd to Nth pre-multipliers in the first cascaded pre-multiplier sequence is the real part of the beamforming complex matrix. The imaginary part of the beamforming complex matrix The real part of the multidimensional complex input signal The input to the second to Nth pre-multipliers in the second cascaded pre-multiplier sequence is the imaginary part of the beamforming complex matrix, along with the output of the previous pre-multiplier. The real part of the multidimensional complex input signal The imaginary part of the multidimensional complex input signal The input to the second to Nth pre-multipliers in the third cascaded pre-multiplier sequence is the real part of the beamforming complex matrix, along with the output of the previous pre-multiplier. The real part of the multidimensional complex input signal and the imaginary part of the multidimensional complex input signal And the output of the previous pre-multiplier.

[0048] In one possible implementation, the input port of the first pre-accumulator in each column of the first, second, and third cascaded pre-accumulator sequences is a normal input port, and the input ports of the 2nd to Nth pre-accumulators in each column are cascaded input ports; the output ports of the first to N-1th pre-accumulators in each column of the first, second, and third cascaded pre-accumulator sequences are cascaded output ports, and the output port of the Nth pre-accumulator in each column is a normal output port.

[0049] The following is about the above. Figure 2 To provide a detailed description, assuming N equals 8, the first cascaded pre-accumulator multiplier sequence includes a 1st pre-accumulator multiplier, a 2nd pre-accumulator multiplier, a 3rd pre-accumulator multiplier, a 4th pre-accumulator multiplier, a 5th pre-accumulator multiplier, a 6th pre-accumulator multiplier, a 7th pre-accumulator multiplier, and an 8th pre-accumulator multiplier; the second cascaded pre-accumulator multiplier sequence includes a 9th pre-accumulator multiplier, a 10th pre-accumulator multiplier, and an 11th pre-accumulator multiplier. The third cascaded pre-multiplier sequence includes the 17th, 18th, 19th, 20th, 21st, 22nd, 23rd, and 24th pre-multipliers.

[0050] In one possible implementation, the function of the first pre-multiplier can be configured as Pcout = (A + B) * C, and the input of the A input interface of the first pre-multiplier is... The input of the B input interface of the first pre-multiplier is The input of the C input interface of the first pre-multiplier is The output interface of the first pre-multiplier is a cascaded output port Pcout; the function of the second pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the second pre-multiplier is... The input of the B input interface of the second pre-multiplier is The input of the C input interface of the second pre-multiplier is The input interface of the second pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the first pre-multiplier; the output interface of the second pre-multiplier is a cascaded output port Pcout; the function of the third pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the third pre-multiplier is... The input of the B input interface of the third pre-multiplier is The input of the C input interface of the third pre-multiplier is The input interface of the third pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the second pre-multiplier; the output interface of the third pre-multiplier is a cascaded output port Pcout; the function of the fourth pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the fourth pre-multiplier is... The input of the B input interface of the fourth pre-multiplier is The input of the C input interface of the fourth pre-multiplier is The input interface of the fourth pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the third pre-multiplier; the output interface of the fourth pre-multiplier is a cascaded output port Pcout; the function of the fifth pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the fifth pre-multiplier is... The input of the B input interface of the fifth pre-multiplier is The input of the C input interface of the fifth pre-multiplier is The input interface of the 5th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 4th pre-multiplier; the output interface of the 5th pre-multiplier is a cascaded output port Pcout; the function of the 6th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 6th pre-multiplier is... The input of the B input interface of the sixth pre-multiplier is The input of the C input interface of the sixth pre-multiplier is The input interface of the 6th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 5th pre-multiplier; the output interface of the 6th pre-multiplier is a cascaded output port Pcout; the function of the 7th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 7th pre-multiplier is... The input of the B input interface of the 7th pre-multiplier is The input of the C input interface of the 7th pre-multiplier is The input interface of the 7th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 6th pre-multiplier; the output interface of the 7th pre-multiplier is a cascaded output port Pcout; the function of the 8th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 8th pre-multiplier is... The input of the B input interface of the 8th pre-multiplier is The input of the C input interface of the 8th pre-multiplier is The input interface of the 8th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 7th pre-multiplier; the output interface of the 8th pre-multiplier is a general-purpose output port Pout, and the output value is...

[0051] In one possible implementation, the function of the 9th pre-multiplier can be configured as Pcout = (A + B) * C, and the input of the A input interface of the 9th pre-multiplier is... The input of the B input interface of the 9th pre-multiplier is The input of the C input interface of the 9th pre-multiplier is The output interface of the 9th pre-multiplier is a cascaded output port Pcout; the function of the 10th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 10th pre-multiplier is... The input of the B input interface of the 10th pre-multiplier is The input of the C input interface of the 10th pre-multiplier is The input interface of the 10th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 9th pre-multiplier; the output interface of the 10th pre-multiplier is a cascaded output port Pcout; the function of the 11th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 11th pre-multiplier is... The input of the B input interface of the 11th pre-multiplier is The input of the C input interface of the 11th pre-multiplier is The input interface of the 11th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 10th pre-multiplier; the output interface of the 11th pre-multiplier is a cascaded output port Pcout; the function of the 12th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 12th pre-multiplier is... The input of the B input interface of the 12th pre-multiplier is The input of the C input interface of the 12th pre-multiplier is The input interface of the 12th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 11th pre-multiplier; the output interface of the 12th pre-multiplier is a cascaded output port Pcout; the function of the 13th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 13th pre-multiplier is... The input of the B input interface of the 13th pre-multiplier is The input of the C input interface of the 13th pre-multiplier is The input interface of the 13th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 12th pre-multiplier; the output interface of the 13th pre-multiplier is a cascaded output port Pcout; the function of the 14th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 14th pre-multiplier is... The input of the B input interface of the 14th pre-multiplier is The input of the C input interface of the 14th pre-multiplier is The input interface of the 14th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 13th pre-multiplier; the output interface of the 14th pre-multiplier is a cascaded output port Pcout; the function of the 15th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 15th pre-multiplier is... The input of the B input interface of the 15th pre-multiplier is The input of the C input interface of the 15th pre-multiplier is The input interface of the 15th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 14th pre-multiplier; the output interface of the 15th pre-multiplier is a cascaded output port Pcout; the function of the 16th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 16th pre-multiplier is... The input of the B input interface of the 16th pre-multiplier is The input of the C input interface of the 16th pre-multiplier is The input interface of the 16th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 15th pre-multiplier. The output interface of the 16th pre-multiplier is a cascaded output port Pcout; the output interface of the 16th pre-multiplier is a general-purpose output port Pout, with an output value of...

[0052] In one possible implementation, the function of the 17th pre-multiplier can be configured as Pcout = (A + B) * C, where the input of the A input interface of the 17th pre-multiplier is... The input of the B input interface of the 17th pre-multiplier is The input of the C input interface of the 17th pre-multiplier is The output interface of the 17th pre-multiplier is a cascaded output port Pcout; the function of the 18th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 18th pre-multiplier is... The input of the B input interface of the 18th pre-multiplier is The input of the C input interface of the 18th pre-multiplier is The input interface of the 18th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 17th pre-multiplier; the output interface of the 18th pre-multiplier is a cascaded output port Pcout; the function of the 19th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 19th pre-multiplier is... The input of the B input interface of the 19th pre-multiplier is The input of the C input interface of the 19th pre-multiplier is The input interface of the 19th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 18th pre-multiplier; the output interface of the 19th pre-multiplier is a cascaded output port Pcout; the function of the 20th pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 20th pre-multiplier is... The input of the B input interface of the 20th pre-multiplier is The input of the C input interface of the 20th pre-multiplier is The input interface of the 20th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 19th pre-multiplier; the output interface of the 20th pre-multiplier is a cascaded output port Pcout; the function of the 21st pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 21st pre-multiplier is... The input of the B input interface of the 21st pre-multiplier is The input of the C input interface of the 21st pre-multiplier is The input interface of the 21st pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 20th pre-multiplier; the output interface of the 21st pre-multiplier is a cascaded output port Pcout; the function of the 22nd pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 22nd pre-multiplier is... The input of the B input interface of the 22nd pre-multiplier is The input of the C input interface of the 22nd pre-multiplier is The input interface of the 22nd pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 21st pre-multiplier; the output interface of the 22nd pre-multiplier is a cascaded output port Pcout; the function of the 23rd pre-multiplier can be configured as Pcout = (A + B) * C + Pcin, and the input of the A input interface of the 23rd pre-multiplier is... The input of the B input interface of the 23rd pre-multiplier is The input of the C input interface of the 23rd pre-multiplier is The input interface of the 23rd pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 22nd pre-multiplier; the output interface of the 23rd pre-multiplier is a cascaded output port Pcout; the function of the 24th pre-multiplier can be configured as Pout = (A + B) * C + Pcin, and the input of the A input interface of the 24th pre-multiplier is... The input of the B input interface of the 24th pre-multiplier is The input of the C input interface of the 24th pre-multiplier is The input interface of the 24th pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 23rd pre-multiplier; the output interface of the 24th pre-multiplier is a general-purpose output port Pout, and the output value is...

[0053] The first adder is configured to perform the following function: C = BA, where the output of the first adder is the real part of the multidimensional complex output signal. The input of the A interface of the first adder is It can be considered as an intermediate variable: The input of the B interface of the first adder is It can be regarded as an intermediate variable In conclusion, The second adder is configured to perform the following function: C = BA, where the output of the second adder is the imaginary part of the multidimensional complex output signal. The input of the A interface of the first adder is It can be considered as an intermediate variable: The input of the B interface of the first adder is It can be regarded as an intermediate variable In conclusion,

[0054] In this embodiment of the invention, the construction of the beamforming data processing system is mathematically based on the decomposition of formulas (1) and (2) by a pre-multiplier. Specifically, formula (1) is split into formula (3), as follows:

[0055]

[0056] Formula (2) can be broken down into formula (4), as follows:

[0057]

[0058] Further breaking down formula (3) yields formula (5), as follows:

[0059]

[0060] Further breaking down formula (4) yields formula (6), as follows:

[0061]

[0062] Introducing intermediate variables in formulas (5) and (6) Specifically as follows:

[0063]

[0064]

[0065]

[0066] Finally, formula (5) becomes formula (7), and formula (6) becomes formula (8), as follows:

[0067]

[0068]

[0069] In this embodiment of the invention, through the above... Figure 2 It is built for each antenna dimension. The number of pre-multipliers in the beamforming data processing system built for antenna dimension M is 3*N*M, which can save 25% of the multipliers compared to the number of multipliers of 4*N*M in the prior art.

[0070] In this embodiment of the invention, the number of streams N is determined according to actual conditions. The larger the number of streams, the more pre-multipliers are cascaded in each pre-multiplier sequence, resulting in a larger total number of pre-multipliers in the beamforming data processing system. Similarly, the more antennas there are, the more pre-multipliers the beamforming data processing system will have. However, for different antenna elements, the cascaded structure of the beamforming pre-multipliers is too simplistic, which can lead to static timing problems when implementing the beamforming data processing system on a chip or FPGA. For example, a serious static timing problem was encountered when designing a large-scale multiple-input multiple-output (Massive MIMO) beamforming data processing system with 16 streams and 64 antennas (this is merely an example). To solve this timing problem, registers are inserted at regular intervals in the beamforming data processing system to break the pre-multiplier cascade.

[0071] In one possible implementation, the system further includes: multiple registers, wherein the registers are inserted into the first, second, and third cascaded pre-multiplier sequences, and also into the signal input positions of the pre-multipliers; the insertion of the registers into the first, second, and third cascaded pre-multiplier sequences specifically includes: for each cascaded pre-multiplier sequence, inserting the registers between the general output ports of multiple pre-multipliers in each cascaded pre-multiplier sequence and the general input port of the next pre-multiplier, according to preset requirements; the insertion of the registers into the signal input positions of the pre-multipliers specifically includes: the registers being inserted into the real part of the beamforming complex matrix of the pre-multiplier. The real part of the multidimensional complex input signal The imaginary part of the multidimensional complex input signal Or the real part of the multidimensional complex input signal The number of registers at the input positions varies and increases with the number of streams N.

[0072] The following detailed description uses a specific embodiment as an example. Figure 3As shown, assuming N equals 8, the first cascaded pre-adding multiplier sequence includes a 1' pre-adding multiplier, a 2' pre-adding multiplier, a 3' pre-adding multiplier, a 4' pre-adding multiplier, a 5' pre-adding multiplier, a 6' pre-adding multiplier, a 7' pre-adding multiplier, and an 8' pre-adding multiplier; the second cascaded pre-adding multiplier sequence includes a 9' pre-adding multiplier, a 10' pre-adding multiplier, an 11' pre-adding multiplier, and... The 12', 13', 14', 15', and 16' pre-adder multipliers are listed; the third cascaded pre-adder multiplier sequence includes the 17', 18', 19', 20', 21', 22', 23', and 24' pre-adder multipliers. In one possible implementation, the function of the 1' pre-adder multiplier can be configured as Pcout = (A + B) * C, and the input of the A input interface of the 1' pre-adder multiplier is... The input of the B input interface of the first pre-multiplier is The input of the C input interface of the first pre-multiplier is The output interface of the first pre-multiplier is a cascaded output port Pcout; the function of the second pre-multiplier can be configured as Pout = (A + B) * C + Pcin, and the input of the A input interface of the second pre-multiplier is... The input of the B input interface of the second pre-multiplier is The input of the C input interface of the second pre-multiplier is The input interface of the 2' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 1' pre-multiplier; the output interface of the 2' pre-multiplier is a normal output port Pout; the function of the 3' pre-multiplier can be configured as Pcout = (A + B) * C + Pin, and the input of the A input interface of the 3' pre-multiplier is... The input of the B input interface of the 3' pre-multiplier is The input of the C input interface of the third pre-multiplier is The input interface of the 3' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 2' pre-multiplier. Two sets of registers (the number is variable) are inserted at the signal input positions of the A, B, and C input interfaces and the general-purpose input port Pin. The output interface of the 3' pre-multiplier is a cascaded output port Pcout. The function of the 4' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 4' pre-multiplier is... The input of the B input interface of the 4' pre-multiplier is The input of the C input interface of the 4' pre-multiplier is The input interface of the 4' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 3' pre-multiplier. Two sets of registers are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 4' pre-multiplier is a general-purpose output port Pout. The function of the 5' pre-multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 5' pre-multiplier is... The input of the B input interface of the 5' pre-multiplier is The input of the C input interface of the 5' pre-multiplier is The input interface of the 5' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 4' pre-multiplier. Two more sets of registers (a total of four sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 5' pre-multiplier is a cascaded output port Pcout. The function of the 6' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 6' pre-multiplier is... The input of the B input interface of the 6' pre-multiplier is The input of the C input interface of the 6' pre-multiplier is The input interface of the 6' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 5' pre-multiplier. Two more sets of registers (a total of four registers) are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 6' pre-multiplier is a general-purpose output port Pout. The function of the 7' pre-multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 7' pre-multiplier is... The input of the B input interface of the 7' pre-multiplier is The input of the C input interface of the 7' pre-multiplier is The input interface of the 7' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 6' pre-multiplier. Two more sets of registers (a total of six sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 7' pre-multiplier is a cascaded output port Pcout. The function of the 8' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 8' pre-multiplier is... The input of the B input interface of the 8' pre-multiplier is The input of the C input interface of the 8' pre-multiplier is The input interface of the 8' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 7' pre-multiplier. Two more sets of registers (a total of six registers) are inserted at the signal input positions of input interfaces A, B, and C. The output interface of the 8' pre-multiplier is a general-purpose output port Pout, with an output value of...

[0073] In one possible implementation, the function of the 9th pre-multiplier can be configured as Pcout = (A + B) * C, and the input of the A input interface of the 9th pre-multiplier is... The input of the B input interface of the 9' pre-multiplier is The input of the C input interface of the 9' pre-multiplier is The output interface of the 9th pre-multiplier is a cascaded output port Pcout; the function of the 10th pre-multiplier can be configured as Pout = (A + B) * C + Pcin, and the input of the A input interface of the 10th pre-multiplier is... The input of the B input interface of the 10' pre-multiplier is The input of the C input interface of the 10' pre-multiplier is The input interface of the 10' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 9' pre-multiplier. The output interface of the 10' pre-multiplier is a normal output port Pout. The function of the 11' pre-multiplier can be configured as Pcout = (A + B) * C + Pin, and the input of the A input interface of the 11' pre-multiplier is... The input of the B input interface of the 11' pre-multiplier is The input of the C input interface of the 11' pre-multiplier is The input interface of the 11' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 10' pre-multiplier. Two sets of registers (the number is variable) are inserted at the signal input positions of the A, B, and C input interfaces and the general-purpose input port Pin. The output interface of the 11' pre-multiplier is a cascaded output port Pcout. The function of the 12' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 12' pre-multiplier is... The input of the B input interface of the 12' pre-multiplier is The input of the C input interface of the 12' pre-multiplier is The input interface of the 12' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 11' pre-multiplier. Two sets of registers are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 12' pre-multiplier is a general-purpose output port Pout. The function of the 13' pre-multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 13' pre-multiplier is... The input of the B input interface of the 13' pre-multiplier is The input of the C input interface of the 13' pre-multiplier is The input interface of the 13' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 12' pre-multiplier. Two more sets of registers (a total of four sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 13' pre-multiplier is a cascaded output port Pcout. The function of the 14' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 14' pre-multiplier is... The input of the B input interface of the 14' pre-multiplier is The input of the C input interface of the 14' pre-multiplier is The input interface of the 14' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 13' pre-multiplier. Two more sets of registers (a total of four sets) are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 14' pre-multiplier is a general-purpose output port Pout. The function of the 15' pre-multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 15' pre-multiplier is... The input of the B input interface of the 15' pre-multiplier is The input of the C input interface of the 15' pre-multiplier is The input interface of the 15' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 14' pre-multiplier. Two more sets of registers (a total of six sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 15' pre-multiplier is a cascaded output port Pcout. The function of the 16' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 16' pre-multiplier is... The input of the B input interface of the 16' pre-multiplier is The input of the C input interface of the 16' pre-multiplier is The input interface of the 16' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 15' pre-multiplier. Two more sets of registers (a total of six sets) are inserted at the signal input positions of input interfaces A, B, and C. The output interface of the 16' pre-multiplier is a general-purpose output port Pout, with an output value of...

[0074] In one possible implementation, the function of the 17' pre-multiplier can be configured as Pcout = (A + B) * C, and the input of the A input interface of the 17' pre-multiplier is... The input of the B input interface of the 17' pre-multiplier is The input of the C input interface of the 17' pre-multiplier is The output interface of the 17' pre-multiplier is a cascaded output port Pcout; the function of the 18' pre-multiplier can be configured as Pout = (A + B) * C + Pcin, and the input of the A input interface of the 18' pre-multiplier is... The input of the B input interface of the 18' pre-multiplier is The input of the C input interface of the 18' pre-multiplier is The input interface of the 18' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 17' pre-multiplier. The output interface of the 18' pre-multiplier is a normal output port Pout. The function of the 19' pre-multiplier can be configured as Pcout = (A + B) * C + Pin, and the input of the A input interface of the 19' pre-multiplier is... The input of the B input interface of the 19' pre-multiplier is The input of the C input interface of the 19' pre-multiplier is The input interface of the 19' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 18' pre-multiplier. Two sets of registers (the number is variable) are inserted at the signal input positions of the A, B, and C input interfaces and the general-purpose input port Pin. The output interface of the 19' pre-multiplier is a cascaded output port Pcout. The function of the 20' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 20' pre-multiplier is... The input of the B input interface of the 20' pre-multiplier is The input of the C input interface of the 20' pre-multiplier is The input interface of the 20' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 19' pre-multiplier. Two sets of registers are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 20' pre-multiplier is a general-purpose output port Pout. The function of the 21' pre-multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 21' pre-multiplier is... The input of the B input interface of the 21st pre-multiplier is The input of the C input interface of the 21st pre-multiplier is The input interface of the 21' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pout of the 20' pre-multiplier. Two more sets of registers (a total of four sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 21' pre-multiplier is a cascaded output port Pcout. The function of the 22' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 22' pre-multiplier is... The input of the B input interface of the 22' pre-multiplier is The input of the C input interface of the 22' pre-multiplier is The input interface of the 22' pre-addition multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 21' pre-addition multiplier. Two more sets of registers (a total of four sets) are inserted at the signal input positions of the A, B, and C input interfaces. The output interface of the 22' pre-addition multiplier is a general-purpose output port Pout. The function of the 23' pre-addition multiplier can be configured as Pcout = (A + B) * C + Pin. The input of the A input interface of the 23' pre-addition multiplier is... The input of the B input interface of the 23' pre-multiplier is The input of the C input interface of the 23' pre-multiplier is The input interface of the 23' pre-multiplier is a general-purpose input port Pin, which is connected to the general-purpose output port Pcout of the 22' pre-multiplier. Two more sets of registers (a total of six sets) are inserted into the A, B, and C input interfaces, and two more sets of registers are inserted at the signal input position of the general-purpose input port Pin. The output interface of the 23' pre-multiplier is a cascaded output port Pcout. The function of the 24' pre-multiplier can be configured as Pout = (A + B) * C + Pcin. The input of the A input interface of the 24' pre-multiplier is... The input of the B input interface of the 24' pre-multiplier is The input of the C input interface of the 24' pre-multiplier is The input interface of the 24' pre-multiplier is a cascaded input port Pcin, which is connected to the cascaded output port Pcout of the 23' pre-multiplier. Two more sets of registers (a total of six registers) are inserted at the signal input positions of input interfaces A, B, and C. The output interface of the 24' pre-multiplier is a general-purpose output port Pout, with an output value of...

[0075] The first (a) adder is configured to perform the following function: C = BA, where the output of the first (a) adder is the real part of the multidimensional complex output signal. The input of the A interface of the first (a) adder is It can be considered as an intermediate variable: The input of the B interface of the first (a) adder is It can be regarded as an intermediate variable In conclusion, The second (a) adder is configured to perform the following function: C = BA, where the output of the second (a) adder is the imaginary part of the multidimensional complex output signal. The input of the A interface of the first (a) adder is It can be considered as an intermediate variable: The input of the B interface of the first (a) adder is It can be regarded as an intermediate variable In conclusion,

[0076] In this embodiment of the invention, after inserting the register, due to the change in the latency of the data processing system, it is necessary to perform corresponding latency matching on the subsequent input data and beamforming matrix coefficients to ensure the overall function of beamforming, such as... Figure 3In China Registers of the corresponding number of stages are inserted at the input to ensure delay matching. By inserting registers, the problem of excessively high cascade number of multipliers is solved, which can greatly increase the flexibility of layout and routing of data processing systems in FPGA or chip implementation, and effectively alleviate the static timing problems caused by multi-stage cascaded beamforming and simple structure.

[0077] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0078] Embodiments of the present invention relate to a non-volatile storage medium for storing a computer-readable program, the computer-readable program being used by a computer to execute some or all of the above-described method embodiments.

[0079] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0080] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A beamformed data processing system, characterized by, The system comprises a plurality of first columnar cascaded pre-multiplier sequences, a second columnar cascaded pre-multiplier sequence, a third columnar cascaded pre-multiplier sequence, a first adder and a second adder. wherein the input of the first pre-multiplier in the first column of cascaded pre-multipliers is the real part of the beamforming complex matrix the imaginary part of the beamforming complex matrix and the real part of the multi-dimensional complex input signal the output of the last pre-multiplier in the first column of cascaded pre-multipliers is an input of a first pre-multiplier in the second column cascade pre-multiplier sequence is an imaginary part of the beamforming complex matrix a real part of the multi-dimensional complex input signal and an imaginary part of the multi-dimensional complex input signal an output of a last pre-multiplier in the second column cascade pre-multiplier sequence is an input of a first pre-multiplier in the third column cascade pre-multiplier sequence is a real part of the beamforming complex matrix a real part of the multi-dimensional complex input signal and an imaginary part of the multi-dimensional complex input signal an output of a last pre-multiplier in the third column cascade pre-multiplier sequence is an input of the first adder is an output of a last precoder in the first column of cascaded precoder sequences and an output of a last precoder in the second column of cascaded precoder sequences, and an output of the first adder is a real part of a multi-dimensional complex number output signal An input of the second adder is an output of a last pre-multiplier in the first columnar cascaded pre-multiplier sequence and an output of a last pre-multiplier in the third columnar cascaded pre-multiplier sequence, and an output of the second adder is an imaginary part of a multi-dimensional complex number output signal Wherein, N is a stream number of the multi-dimensional complex number input signal, and N is greater than or equal to 2.

2. The system of claim 1, wherein, The number of pre-multipliers in the first columnar cascaded pre-multiplier sequence, the second columnar cascaded pre-multiplier sequence and the third columnar cascaded pre-multiplier sequence is the same, and the number is equal to the stream number of the multi-dimensional complex number input signal.

3. The system of claim 1, wherein, an input of a second to an Nth precoder in the first column-wise cascaded precoder sequence is a real part of the beamforming complex matrix an imaginary part of the beamforming complex matrix a real part of the multi-dimensional complex input signal and an output of a previous precoder an input of a 2nd to Nth pre-multiplier in the second column-wise cascaded pre-multiplier sequence is an imaginary part of the beamforming complex matrix a real part of the multi-dimensional complex input signal an imaginary part of the multi-dimensional complex input signal and an output of a previous pre-multiplier the input of the 2nd to Nth pre-multipliers in the third column-wise cascaded pre-multiplier sequence is the real part of the beamforming complex matrix the real part of the multi-dimensional complex input signal and the imaginary part of the multi-dimensional complex input signal and the output of the previous pre-multiplier.

4. The system of claim 1, wherein, An input port of the pre-multiplier is a normal input port or a cascaded input port, and an output port of the pre-multiplier is a normal output port or a cascaded output port.

5. The system of claim 4, wherein, An input port of a first pre-multiplier in each column of the first columnar cascaded pre-multiplier sequence, the second columnar cascaded pre-multiplier sequence and the third columnar cascaded pre-multiplier sequence is a normal input port, and input ports of the 2th to Nth pre-multipliers in the column are cascaded input ports.

6. The system of claim 4, wherein, An output port of the first to N-1th pre-multipliers in each column of the first columnar cascaded pre-multiplier sequence, the second columnar cascaded pre-multiplier sequence and the third columnar cascaded pre-multiplier sequence is a cascaded output port, and an output port of the Nth pre-multiplier in the column is a normal output port.

7. The system of claim 1, wherein, The system further comprises a plurality of registers, wherein the registers are inserted in the first columnar cascaded pre-multiplier sequence, the second columnar cascaded pre-multiplier sequence, the third columnar cascaded pre-multiplier sequence, and signal input positions of the pre-multipliers.

8. The system of claim 7, wherein, The registers inserted in the first columnar cascaded pre-multiplier sequence, the second columnar cascaded pre-multiplier sequence and the third columnar cascaded pre-multiplier sequence specifically comprise: For each columnar cascaded pre-multiplier sequence, the registers are inserted between normal output ports of a plurality of pre-multipliers in each columnar cascaded pre-multiplier sequence and normal input ports of next pre-multipliers according to requirements of cascaded structure optimization.

9. The system of claim 8, wherein, The registers inserted in signal input positions of the pre-multipliers specifically comprise: said register is inserted in the real part of the beamforming complex matrix of the pre-multiplier said register is inserted in the imaginary part of the beamforming complex matrix said register is inserted in the real part of the multi-dimensional complex input signal said register is inserted in the imaginary part of the multi-dimensional complex input signal input position.

10. The system of claim 9, wherein, The number of registers in the input positions is different and increases with an increase of the stream number N.

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