Ethernet Gigabit and Ten Gigabit Adaptive Connection Device, Method and Electronic Equipment

Abstract

The present invention relates to the field of Ethernet high-speed communication technology, and specifically to an Ethernet Gigabit and 10 Gigabit adaptive connection device, method and electronic device, the device comprising: an FPGA chip and a PHY chip, the FPGA chip comprising a controller, a switching module, a first speed module and a second speed module, the controller connecting the switching module and the PHY chip, the switching module connecting the first speed module or the second speed module; the PHY chip is used to obtain the speed of the device currently connected to its copper wire end; the controller is used to obtain the speed and control the switching module to connect with the first speed module or the second speed module according to the speed. The present invention realizes dynamic switching of Gigabit and 10 Gigabit Ethernet based on the adaptive switching technology of FPGA, so as to realize adaptive connection of Ethernet devices of different speeds to corresponding computer network cards.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of Ethernet high-speed communication, and in particular to an Ethernet Gigabit and Ten Gigabit adaptive connection device, method and electronic equipment. Background Art

[0002] With the rapid development of Ethernet, devices that generally support Gigabit Ethernet can adapt to 10M / 100M / 1000M speeds. However, they cannot adapt to higher speeds. This is mainly due to the different PHY chips, configurations, and network cable speed levels of the network, which results in Ethernet devices of different speeds being unable to adapt to connect to the corresponding computer network cards.

[0003] In the process of implementing the embodiments of the present invention, the inventors found that the inability to adaptively connect mainly occurs at the MAC end using the Ethernet PHY chip. Generally, the copper wire end of the PHY chip can achieve adaptive connection at different rates through the self-negotiation mechanism of the Ethernet protocol. The connection speed of the MAC end is determined by the connection speed of the copper wire end. However, the FPGA chip connected to the MAC end of the PHY chip cannot dynamically change the connection rate according to the connection speed of the copper wire end of the PHY chip, resulting in the inability to adaptively connect. Summary of the invention

[0004] The embodiment of the present invention mainly solves the problem that Ethernet devices with different speeds cannot be adaptively connected to corresponding computer network cards.

[0005] In view of the above problems, the embodiments of the present invention provide an Ethernet Gigabit / 10Gbit adaptive connection device, method and electronic device, which overcome the above problems or at least partially solve the above problems.

[0006] According to one aspect of an embodiment of the present invention, there is provided an Ethernet Gigabit / 10Gbit adaptive connection device, comprising: an FPGA chip and a PHY chip, wherein the FPGA chip comprises a controller, a switching module, a first speed module, and a second speed module, wherein the controller is connected to the switching module and the PHY chip, and the switching module is connected to the first speed module or the second speed module. The PHY chip is used to obtain the speed of the device currently connected to its copper wire end; the controller is used to obtain the speed, and control the switching module to connect to the first speed module or the second speed module according to the speed; wherein the FPGA chip also comprises a GTH high-speed connector, wherein the GTH high-speed connector is respectively connected to the switching module and the PHY chip; the GTH high-speed connector is used to send data to the PHY chip at different speeds, and is also used to receive data sent by the PHY chip.

[0007] Optionally, if the speed corresponding to the first speed module is 1G, the speed corresponding to the second speed module is 10G; if the speed corresponding to the first speed module is 10G, the speed corresponding to the second speed module is 1G.

[0008] Optionally, the FPGA chip further includes a clock and reset module, which is connected to the first speed module and the second speed module respectively, and is used to manage the clock and reset of the FPGA chip and the PHY chip.

[0009] Optionally, the FPGA chip further includes a dynamic configuration interface, which is respectively connected to the controller and the GTH high-speed connector, and is used to receive a speed switching instruction sent by the controller and forward the speed switching instruction to the GTH high-speed connector.

[0010] According to another aspect of an embodiment of the present invention, there is provided an Ethernet Gigabit and Ten Gigabit adaptive connection method, the method comprising: initializing the FPGA chip and the PHY chip, controlling the PHY chip to detect whether the copper wire end is connected to a new device; if connected to a new device, controlling the PHY chip to obtain the speed to be determined of the new device, controlling the controller to read the speed to be determined from the PHY chip; judging whether the speed to be determined is a preset first transmission speed; if so, controlling the controller to modify the data transmission speed of the GTH high-speed connector to a first speed transmission mode, controlling the controller to modify the switching module to switch to the first speed module connection; if not, controlling the controller The controller modifies the data transmission speed of the GTH high-speed connector to the second speed transmission mode, and controls the controller to modify the switching module to switch to the second speed module connection; wherein, the control of the controller to modify the data transmission speed of the GTH high-speed connector to the first speed transmission mode includes: controlling the controller to send the speed switching instruction to the dynamic configuration interface; the dynamic configuration interface receives the speed switching instruction, and the dynamic configuration interface forwards the speed switching instruction to the GTH high-speed connector; the GTH high-speed connector receives the speed switching instruction, and switches to the first speed mode or the second speed mode according to the speed mode contained in the speed switching instruction.

[0011] Optionally, before controlling the PHY chip to obtain the speed to be determined of the new device, it also includes: resetting the clocks in the FPGA chip and the PHY chip through the clock and reset module.

[0012] Optionally, after the controller modifies the switching module to switch to the first speed module connection, or after the controller modifies the switching module to switch to the second speed module connection, it also includes: controlling the first speed module or the second speed module to obtain a clock source from the clock and reset module, and the clock source is used to assist data transmission.

[0013] According to another aspect of the embodiments of the present invention, there is provided an electronic device, the electronic device comprising any one of the above Ethernet Gigabit / Ten Gigabit adaptive connection devices.

[0014] Different from the related art, the embodiments of the present invention provide an Ethernet Gigabit and 10 Gigabit adaptive connection device, method and electronic device, which adopts the controller inside the FPGA chip to control the external 10 Gigabit network PHY chip, and obtains the current connection speed of the copper wire end of the 10 Gigabit network PHY chip by reading the register of the 10 Gigabit network PHY chip. The controller inside the FPGA chip is controlled according to the connection speed of the copper wire end of the PHY chip to realize dynamic control of the GTH high-speed connector, so that it can dynamically work at different speeds of 1G and 10G, so as to realize the adaptive connection of Ethernet devices of different speeds to the corresponding computer network cards. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0016] Figure 1 It is a structural schematic diagram of an Ethernet Gigabit and 10 Gigabit adaptive connection device provided by an embodiment of the present invention;

[0017] Figure 2 It is a flow chart of an Ethernet Gigabit / Ten Gigabit adaptive connection method provided by an embodiment of the present invention;

[0018] Figure 3 The embodiment of the present invention provides Figure 2 A flow chart of modifying the data transmission speed of the GTH high-speed connector;

[0019] Figure 4 It is a flow chart of an Ethernet Gigabit / Ten Gigabit adaptive connection method provided by an embodiment of the present invention;

[0020] Figure 5 The embodiment of the present invention provides Figure 4 A flow chart of modifying the data transmission speed of the GTH high-speed connector;

[0021] Figure 6It is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] It should be noted that, if there is no conflict, the various features in the embodiments of the present invention can be combined with each other, and all are within the protection scope of the present invention. In addition, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order from the module division in the device schematic diagram or the order in the flow chart.

[0024] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0025] With the development of Ethernet technology, a variety of connection speeds have emerged, such as: 10M / 100M / 1000M, 1.25Gbps, 2.5Gbps, 5Gbps, 10Gbps, 25Gbps, 40Gbps, 100Gbps and other specifications. Generally, devices that support Gigabit Ethernet can adapt to the speed of 10M / 100M / 1000M, but the speed above cannot be adaptively supported. The copper wire end of the Ethernet PHY chip can generally achieve adaptive connection at different rates through the self-negotiation mechanism of the Ethernet protocol. The main reason for the inability to adaptively connect is that the FPGA chip connected to the MAC end of the PHY chip cannot dynamically change the connection speed according to the connection speed of the copper wire end of the PHY chip.

[0026] Based on this, the embodiment of the present invention provides an Ethernet Gigabit and 10 Gigabit adaptive connection device, method and electronic device, which uses a soft-core processor inside an FPGA chip to control an external 10 Gigabit network PHY chip, and obtains the connection speed of the copper wire end of the current 10 Gigabit network PHY chip by reading the register of the 10 Gigabit network PHY chip. According to the connection speed of the copper wire end of the PHY chip, the controller inside the FPGA chip is controlled to realize dynamic control of the GTH high-speed connector, so that it can dynamically work at different speeds of 1G and 10G, so as to realize adaptive connection of Ethernet devices of different speeds to the corresponding computer network card. Regardless of whether the network card of the other end is a Gigabit network card or a 10 Gigabit network card, there is no need to set up the device or change the firmware of the FPGA, and adaptive connection can be realized, so as to realize plug-and-play of the device, improve the adaptability of the device, greatly facilitate the application of the device on site, and at the same time, it is not necessary to use different versions of hardware and software for Gigabit and 10 Gigabit when producing the device. Among them, the controller is specifically the internal MCU in the FPGA chip, that is, the soft-core processor in the FPGA chip.

[0027] Specifically, the Ethernet Gigabit and 10 Gigabit adaptive connection device is described below through embodiments.

[0028] See also Figure 1 , Figure 1 The present invention provides a schematic diagram of the structure of an Ethernet Gigabit and 10 Gigabit adaptive connection device. Figure 1 As shown, the Ethernet Gigabit and Ten Gigabit adaptive connection device includes: an FPGA chip 1 and a PHY chip 2, the FPGA chip 1 includes a controller 11, a switching module 12, a first speed module 13 and a second speed module 14, the controller 11 is connected to the switching module 12 and the PHY chip 2, and the switching module 12 is connected to the first speed module 13 or the second speed module 14.

[0029] The FPGA chip 1 uses the internal soft-core processor and the MDIO interface of the PHY chip 2 to read the register of the PHY chip 2 to obtain the current connection speed of the copper wire end of the PHY chip 2, and then controls the switching module 12 inside the FPGA chip 1 to achieve 1G or 10G speed module switching, that is, to achieve Gigabit and 10 Gigabit Ethernet speed switching.

[0030] Among them, the FPGA chip 1 is a programmable logic device, and the model of the FPGA chip 1 can be specifically Xilinx's XCKU060 chip. The internal soft-core processor of the FPGA chip 1 adopts a Microblaze soft-core processor, or uses Altera's FPGA chip and uses a NiosII soft-core processor, or uses Xilinx / Altera's FPGA chip with an ARM soft-core processor series. It can be selected according to actual conditions, and the present disclosure does not make specific restrictions on this, as long as the same technical effect can be achieved; the 10 Gigabit Ethernet PHY chip 2 adopts BoardCom's 84891L, and the use of 10 Gigabit Ethernet PHY chips from other manufacturers or other series of 10 Gigabit Ethernet PHY chips of BoardCom itself can also achieve the same effect. It can be selected according to actual conditions, and the present disclosure does not make specific restrictions on this.

[0031] The PHY chip 2 is a 10G PHY chip that can send and receive Ethernet data frames to all the above speed levels. When a Cat7 or higher network cable is used to connect the Ethernet interface of this device to the network card of a PC, server or workstation, the 10G network PHY chip of this device conducts self-negotiation with the opposite device to achieve a network connection of the corresponding speed, wherein the Cat7 is a type of cable.

[0032] Specifically, the PHY chip 2 is used to obtain the speed of the device currently connected to its copper wire end; the controller 11 is used to obtain the speed and control the switching module 12 to connect to the first speed module 13 or the second speed module 14 according to the speed. The speed corresponding to the first speed module 13 is 1G, and the speed corresponding to the second speed module 14 is 10G; the speed corresponding to the first speed module 13 is 10G, and the speed corresponding to the second speed module 14 is 1G.

[0033] In addition, the FPGA chip 1 also includes a clock and reset module 15, which is respectively connected to the first speed module 13 and the second speed module 14, and is used to manage the clock and reset of the FPGA chip 1 and the PHY chip 2; the FPGA chip 1 also includes a GTH high-speed connector 16, which is respectively connected to the switching module 12 and the PHY chip 2, and is used to send data to the PHY chip 2 at different speeds, and is also used to receive data sent by the PHY chip 2; the FPGA chip 1 also includes a dynamic configuration interface 17, which is respectively connected to the controller 11 and the GTH high-speed connector 16, and is used to receive the speed switching instruction sent by the controller 11, and forward the speed switching instruction to the GTH high-speed connector 16.

[0034] In some other embodiments, the data interface of the front-end user logic is connected to both the first speed module 13 and the second speed module 14, thereby ensuring that no matter whether the back-end switches to the first speed module 13 to connect to the GTH high-speed connector or switches to the second speed module 14 to connect to the GTH high-speed connector, the data of the front-end user logic can be completely and accurately connected to the back-end transmission module, thereby ensuring stable transmission of user data.

[0035] In an embodiment of the present invention, an Ethernet Gigabit and 10 Gigabit adaptive connection device is provided, comprising: an FPGA chip and a PHY chip, the FPGA chip comprising a controller, a switching module, a first speed module and a second speed module, the controller connecting the switching module and the PHY chip, the switching module connecting the first speed module or the second speed module; the PHY chip is used to obtain the speed of the device currently connected to its copper wire end; the controller is used to obtain the speed, and control the switching module to connect with the first speed module or the second speed module according to the speed. The embodiment of the present invention can realize the dynamic switching of Gigabit and 10 Gigabit Ethernet based on the adaptive switching technology of FPGA, so as to realize the adaptive connection of Ethernet devices of different speeds to the corresponding computer network cards, thereby improving the adaptability of the device.

[0036] See also Figure 2 , Figure 2 A schematic diagram of a process for an Ethernet Gigabit / Ten-Gigabit adaptive connection method provided by an embodiment of the present invention Figure 2 .like Figure 2 As shown, the Ethernet Gigabit and 10 Gigabit adaptive connection method is applied to the Ethernet Gigabit and 10 Gigabit adaptive connection device in the above embodiment, and the method includes:

[0037] S31, initializing the FPGA chip 1 and the PHY chip 2, and controlling the PHY chip 2 to detect whether the copper wire end is connected to a new device.

[0038] Among them, the FPGA chip 1 and the PHY chip 2 need to have a certain initial state after power-on, that is, the initialization is to set the initial state of each component inside the chip to a known state to ensure that the internal logic of the device quickly enters the normal working state; because the copper wire end of the PHY chip 2 can achieve adaptive connection at different rates through the self-negotiation mechanism of the Ethernet protocol, the connection speed of the MAC end of the PHY chip 2 is determined according to the connection speed of the copper wire end, but the FPGA chip 1 connected to the MAC end of the PHY chip 2 cannot dynamically change the connection rate according to the connection speed of the copper wire end of the PHY chip 2, resulting in the inability to adaptively connect. The purpose of controlling the PHY chip 2 to detect whether the copper wire end is connected to a new device is to obtain the working speed of the copper wire end of the PHY chip 2 after negotiation with the opposite device through a self-negotiation mechanism. The self-negotiation mechanism is the key to interconnecting different devices in Ethernet. Ethernet devices produced by different manufacturers, including network cards, switches, etc., need to identify the working mode of the opposite network device when interconnected. In order to solve this problem, an automatic configuration method is provided to enable Ethernet devices to correctly identify the working mode. This is the self-negotiation mechanism of the Ethernet protocol. In Ethernet, devices on both sides of the link exchange information through a self-negotiation mechanism, and the speeds are negotiated in sequence from high to low. The highest speed is connected first, and the highest speed supported by both parties is automatically selected to determine the best acceptable working mode. The new device can specifically be a network card of a PC, server or workstation.

[0039] S32 : If a new device is connected, control the PHY chip 2 to obtain the speed to be determined of the new device, and control the controller 11 to read the speed to be determined from the PHY chip 2 .

[0040] When the copper wire end of the PHY chip 2 is connected to a new device such as a network card of a PC, server or workstation, the PHY chip 2 is controlled to read the register of the PHY chip 2 through its MDIO interface, and the register contains the status information of the PHY chip 2, so as to obtain the current connection speed of the copper wire end of the PHY chip 2. The current connection speed of the copper wire end of the PHY chip 2 is the speed to be determined, and the speed to be determined is the optimal working rate set by the copper wire end of the PHY chip 2 and the new device through the self-negotiation mechanism of the Ethernet protocol. The MDIO interface is a two-wire serial interface, which is used to operate and manage physical layer information such as the PHY chip 2.

[0041] S33: Determine whether the speed to be determined is a preset first transmission speed.

[0042] The preset first transmission speed is the speed corresponding to the first speed module 13, which can be 1G or 10G. When the speed corresponding to the first speed module 13 is 1G and the speed corresponding to the second speed module 14 is 10G, the preset first transmission speed is 1G; when the speed corresponding to the first speed module 13 is 10G and the speed corresponding to the second speed module 14 is 1G, the preset first transmission speed is 10G. Compare the speed of the current connection of the copper wire end of the PHY chip 2 with the preset first transmission speed, and obtain the comparison result.

[0043] S34, if yes, control the controller 11 to modify the data transmission speed of the GTH high-speed connector 16 to the first speed transmission mode, and control the controller 11 to modify the switching module 12 to switch to the first speed module 13. The GTH high-speed connector 16 is a high-speed serial transceiver inside the FPGA chip 1, which is used to realize data conversion and transmission. The data transmission speed is specifically 1G or 10G. The first speed transmission mode is that the GTH high-speed connector 16 uses the speed corresponding to the first speed module 13 to transmit data.

[0044] Specifically, when the preset first transmission speed is 1G and the speed to be determined is 1G, the speed to be determined is the preset first transmission speed, and the controller 11 is controlled to transmit data to the GTH high-speed connector 16 at a speed of 1G, and the controller 11 is controlled to connect with the corresponding first speed module 13, that is, to connect with the speed module with a corresponding speed of 1G; when the preset first transmission speed is 10G and the speed to be determined is 10G, the speed to be determined is the preset first transmission speed, and the controller 11 is controlled to transmit data to the GTH high-speed connector 16 at a speed of 10G, and the controller 11 is controlled to connect with the corresponding first speed module 13, that is, to connect with the speed module with a corresponding speed of 10G.

[0045] See also Figure 3 , Figure 3 A flow chart of modifying the data transmission speed of the GTH high-speed connector provided in an embodiment of the present invention, wherein the controller 11 is controlled to modify the data transmission speed of the GTH high-speed connector 16 to the first speed transmission mode, including:

[0046] S341 , controlling the controller 11 to send the speed switching instruction to the dynamic configuration interface 17 .

[0047] The speed switching instruction modifies the data transmission speed of the MAC end of the PHY chip 2 to the copper wire end speed of the PHY chip 2, that is, modifies it to the speed to be determined.

[0048] S342 , the dynamic configuration interface 17 receives the speed switching instruction, and the dynamic configuration interface 17 forwards the speed switching instruction to the GTH high-speed connector 16 .

[0049] The dynamic configuration interface 17 receives the speed switching instruction issued by the MCU inside the FPGA chip 1 , and sends the speed switching instruction to the GTH high-speed connector 16 .

[0050] S343: The GTH high-speed connector 16 receives the speed switching instruction, and switches to the first speed mode or the second speed mode according to the speed mode included in the speed switching instruction.

[0051] The speed mode includes a first speed mode and a second speed mode, wherein the first speed mode is a working mode for data transmission at a speed corresponding to the first speed module, and the second speed mode is a working mode for data transmission at a speed corresponding to the second speed module. The controller 11 is connected to the DRP port of the GTH high-speed connector 16 to dynamically control the GTH high-speed connector 16 to make its working rate 1G or 10G, wherein the DRP port is a dynamic reconfiguration port, which provides a control port as a switch, and can read and write the relevant addresses in the address table to achieve the function of obtaining data or changing configuration.

[0052] S35 , if not, control the controller 11 to modify the data transmission speed of the GTH high-speed connector 16 to the second speed transmission mode, and control the controller 11 to modify the switching module 12 to switch to the second speed module 14 for connection.

[0053] Specifically, when the preset first transmission speed is 1G and the speed to be determined is 10G, the speed to be determined is not the preset first transmission speed, and the controller 11 is controlled to transmit data to the GTH high-speed connector 16 at a speed of 10G, and the controller 11 is controlled to connect to the corresponding second speed module 14, that is, to connect to the speed module with a corresponding speed of 10G; when the preset first transmission speed is 10G and the speed to be determined is 1G, the speed to be determined is not the preset first transmission speed, and the controller 11 is controlled to transmit data to the GTH high-speed connector 16 at a speed of 1G, and the controller 11 is controlled to connect to the corresponding second speed module 14, that is, to connect to the speed module with a corresponding speed of 1G.

[0054] In an embodiment of the present invention, a method for adaptively connecting 1G and 10G Ethernet is provided, in which a soft-core processor inside an FPGA chip is used to control an external 10G PHY chip, and the connection speed of the copper wire end of the current 10G PHY chip is obtained by reading the register of the 10G PHY chip. The controller inside the FPGA chip is controlled according to the connection speed of the copper wire end of the PHY chip to realize dynamic control of the GTH high-speed connector, so that it can dynamically work at different speeds of 1G and 10G, so as to realize adaptive connection of Ethernet devices of different speeds to corresponding computer network cards.

[0055] See also Figure 4 , Figure 4 A schematic diagram of another process of Ethernet Gigabit and 10 Gigabit adaptive connection method provided by an embodiment of the present invention. Figure 4 As shown, the Ethernet Gigabit and 10 Gigabit adaptive connection method is applied to the Ethernet Gigabit and 10 Gigabit adaptive connection device in the above embodiment, and the method includes:

[0056] S41, initializing the FPGA chip 1 and the PHY chip 2, and controlling the PHY chip 2 to detect whether the copper wire end is connected to a new device. The step S41 is the same invention concept as the above step S31, and please refer to the relevant content of step S31 for details.

[0057] S42, resetting the clocks in the FPGA chip 1 and the PHY chip 2 through the clock and reset module 15.

[0058] The clock and reset module 15 is used to generate a reset signal so as to perform a reset operation when the device is just running. The reset acts as a synchronization signal and can set all storage elements to a known state.

[0059] S43 : If a new device is connected, control the PHY chip 2 to obtain the speed to be determined of the new device, and control the controller 11 to read the speed to be determined from the PHY chip 2 .

[0060] S44: Determine whether the speed to be determined is a preset first transmission speed.

[0061] S45 , if yes, control the controller 11 to modify the data transmission speed of the GTH high-speed connector 16 to the first speed transmission mode, and control the controller 11 to modify the switching module 12 to switch to the first speed module 13 for connection.

[0062] See also Figure 5 , Figure 5A flow chart of modifying the data transmission speed of the GTH high-speed connector provided in an embodiment of the present invention, wherein the controller 11 is controlled to modify the data transmission speed of the GTH high-speed connector 16 to the first speed transmission mode, including:

[0063] S451 , controlling the controller 11 to send the speed switching instruction to the dynamic configuration interface 17 .

[0064] S452 , the dynamic configuration interface 17 receives the speed switching instruction, and the dynamic configuration interface forwards the speed switching instruction to the GTH high-speed connector 16 .

[0065] S453: The GTH high-speed connector 16 receives the speed switching instruction, and switches to the first speed mode or the second speed mode according to the speed mode included in the speed switching instruction.

[0066] S46 , if not, control the controller 11 to modify the data transmission speed of the GTH high-speed connector 16 to the second speed transmission mode, and control the controller 11 to modify the switching module 12 to switch to the second speed module 14 for connection.

[0067] Among them, the steps S43 to S46 are the same inventive concept as the above steps S32 to S35, and please refer to the relevant contents of steps S32 to S35 for details.

[0068] S47, control the first speed module 13 or the second speed module 14 to obtain a clock source from the clock and reset module 15, wherein the clock source is used to assist data transmission. The clock source is used to provide a clock signal to establish the operation rhythm of the Ethernet Gigabit and 10 Gigabit adaptive connection device, and the clock signal provided by the clock source can achieve time synchronization to avoid confusion during data transmission.

[0069] Specifically, when the speed to be determined is the first transmission speed, the controller 11 is controlled to modify the data transmission speed of the GTH high-speed connector 16 to the first speed transmission mode, the controller 11 is controlled to modify the switching module 12 to switch to the first speed module 13 connection, and the first speed module 13 is controlled to obtain the clock source from the clock and reset module 15 to provide a clock signal to assist data transmission; when the speed to be determined is not the first transmission speed, the controller 11 is controlled to modify the data transmission speed of the GTH high-speed connector 16 to the second speed transmission mode, the controller 11 is controlled to modify the switching module 12 to switch to the second speed module 14 connection, and the second speed module 14 is controlled to obtain the clock source from the clock and reset module 15 to provide a clock signal to assist data transmission.

[0070] In an embodiment of the present invention, a method for adaptively connecting 1G and 10G Ethernet is provided, wherein a soft-core processor inside an FPGA chip is used to control an external 10G PHY chip, and after reset, the register of the 10G PHY chip is read to obtain the connection speed of the copper wire end of the current 10G PHY chip, and the controller inside the FPGA chip is controlled according to the connection speed of the copper wire end of the PHY chip to realize dynamic control of the GTH high-speed connector, so that it can dynamically work at different speeds of 1G and 10G, and the clock signal generated by the clock and reset module is used to assist data transmission, so as to realize adaptive connection of Ethernet devices of different speeds to corresponding computer network cards.

[0071] The embodiment of the present invention further provides an electronic device 500. Figure 6 , Figure 6 is a structural block diagram of an electronic device 500 provided in an embodiment of the present invention, which shows a device capable of executing Figures 2 to 5 The hardware structure of the electronic device 500 of the Ethernet Gigabit / Ten-Gigabit adaptive connection method, for example, the electronic device 500 is a high-speed camera.

[0072] The electronic device 500 includes: at least one processor 51; and a memory 52, wherein the memory 52 is communicatively connected to the processor 51, and the memory 52 stores instructions that can be executed by the at least one processor 51, and the instructions are executed by the at least one processor 51 so that the at least one processor 51 can execute the Ethernet Gigabit and 10 Gigabit adaptive connection method described in the above embodiment.

[0073] The processor 51 and the memory 52 may be connected via a bus or other means. Figure 6 In the example of bus connection, the memory 52 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The processor 51 executes various functional applications and data processing by running the non-volatile software programs, instructions and modules stored in the memory 52, that is, the Ethernet Gigabit and 10 Gigabit adaptive connection method described in the above embodiment is realized.

[0074] The memory 52 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function. In addition, the memory 52 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 52 may optionally include a memory 52 remotely arranged relative to the processor 51. These remote memories 52 may be connected to the electronic device 500 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0075] The one or more modules are stored in the memory 52, and when executed by the one or more processors 51, the Ethernet Gigabit and 10 Gigabit adaptive connection method in any of the above embodiments is executed, for example, Figures 2 to 5 The method steps in .

[0076] The above-mentioned product can execute the Ethernet Gigabit and 10 Gigabit adaptive connection method provided in the embodiment of the present invention, and has the corresponding functional modules for executing the Ethernet Gigabit and 10 Gigabit adaptive connection method. For technical details not described in detail in this embodiment, please refer to the Ethernet Gigabit and 10 Gigabit adaptive connection method provided in the embodiment of the present invention.

[0077] Through the description of the above implementation methods, ordinary technicians in this field can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, it can also be implemented by hardware. Ordinary technicians in this field can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An Ethernet Gigabit / 10Gbit adaptive connection device, comprising: FPGA chip and PHY chip, characterized in that the FPGA chip includes a controller, a switching module, a first speed module and a second speed module, the controller is connected to the switching module and the PHY chip, and the switching module is connected to the first speed module or the second speed module; The PHY chip is used to obtain the speed of the device currently connected to its copper wire end; The controller is used to read the register of the PHY chip through the MDIO interface of the PHY chip to obtain the speed, and control the switching module to connect with the first speed module or the second speed module according to the speed; Wherein, the FPGA chip further comprises a GTH high-speed connector, and the GTH high-speed connector is respectively connected to the switching module and the PHY chip; The GTH high-speed connector is used to send data to the PHY chip at different speeds, and is also used to receive data sent by the PHY chip.

2. The Ethernet Gigabit / Ten Gigabit adaptive connection device according to claim 1, characterized in that: If the speed corresponding to the first speed module is 1G, the speed corresponding to the second speed module is 10G; If the speed corresponding to the first speed module is 10G, the speed corresponding to the second speed module is 1G.

3. The Ethernet Gigabit / Ten Gigabit adaptive connection device according to claim 1, characterized in that: The FPGA chip also includes a clock and reset module, which is connected to the first speed module and the second speed module respectively, and is used to manage the clock and reset of the FPGA chip and the PHY chip.

4. The Ethernet Gigabit / Ten Gigabit adaptive connection device according to claim 1, characterized in that: The FPGA chip also includes a dynamic configuration interface, which is respectively connected to the controller and the GTH high-speed connector. The dynamic configuration interface is used to receive a speed switching instruction sent by the controller and forward the speed switching instruction to the GTH high-speed connector.

5. An Ethernet 1000M to 1000M adaptive connection method, applied to the Ethernet adaptive connection device according to any one of claims 1 to 4, characterized in that: include: Initializing the FPGA chip and the PHY chip, and controlling the PHY chip to detect whether the copper wire end is connected to a new device; If connected to a new device, control the PHY chip to read the register of the PHY chip through its MDIO interface to obtain the to-be-determined speed of the new device, and control the controller to read the to-be-determined speed from the PHY chip; Determining whether the speed to be determined is a preset first transmission speed; If yes, control the controller to modify the data transmission speed of the GTH high-speed connector to the first speed transmission mode, and control the controller to modify the switching module to switch to the first speed module connection; If not, control the controller to modify the data transmission speed of the GTH high-speed connector to a second speed transmission mode, and control the controller to modify the switching module to switch to the second speed module connection; The controlling the controller to modify the data transmission speed of the GTH high-speed connector to a first speed transmission mode includes: Controlling the controller to send a speed switching instruction to a dynamic configuration interface; The dynamic configuration interface receives the speed switching instruction, and the dynamic configuration interface forwards the speed switching instruction to the GTH high-speed connector; The GTH high-speed connector receives the speed switching instruction and switches to the first speed mode or the second speed mode according to the speed mode included in the speed switching instruction.

6. The Ethernet Gigabit / Ten Gigabit adaptive connection method according to claim 5, characterized in that: Before controlling the PHY chip to obtain the to-be-determined speed of the new device, the method further includes: The clocks in the FPGA chip and the PHY chip are reset through the clock and reset module.

7. The Ethernet Gigabit / Ten Gigabit adaptive connection method according to claim 5, characterized in that: After the controlling the controller to modify the switching module to switch to the first speed module connection, or after the controlling the controller to modify the switching module to switch to the second speed module connection, the method further includes: The first speed module or the second speed module is controlled to obtain a clock source from a clock and reset module, where the clock source is used to assist data transmission.

8. An electronic device, characterized in that: include: The Ethernet Gigabit / Ten Gigabit adaptive connection device according to any one of claims 1 to 4.

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