A circuit for hysteresis current control to generate a hysteresis window that varies with input and output

Abstract

The present invention provides a circuit for hysteresis current control to generate a hysteresis window that varies with input and output, including an input / output signal processing circuit and a hysteresis window generation circuit, which is used to stabilize the switching frequency of LED driving. When the input / output voltage changes, the hysteresis window circuit generates a hysteresis window that is a function of the input and output, so that the switching frequency remains fixed, reducing the cost of EMI design. The present invention can also set the frequency at the required frequency to solve the crosstalk with other modules, and can be widely applied in LED driving with hysteresis current control, improving the reliability of the driver and having a wide range of application scenarios. In addition, the present invention uses an operational amplifier with a common-gate input to enable the sampling of an input voltage range of 7V - 40V and an output voltage of 5V - 15V, greatly reducing the complexity of input / output sampling and the complexity of signal multiplication and division processing, and improving the sampling accuracy in a wide input / output range.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a circuit for generating a hysteresis window that varies with input and output and is used for hysteresis current control. Background Art

[0002] LED lighting has been widely used in general lighting, special lighting, video screens and other application fields due to its advantages of energy saving, high efficiency, long service life and environmental protection. The use of LED is inseparable from the cooperation of the driver. The normal operation of different types of LED lamp beads in different environments requires drivers with different performances to cooperate with them, making the driving technology particularly critical.

[0003] Since LED lamp beads are sensitive to voltage changes, the LED driver is basically used to stabilize the average current of the LED to make the LED light stable. Among them, hysteresis current control is the current mainstream control method. The function of the hysteresis window is to generate a peak potential V PK and valley potential V VY , which is used to determine the peak current and valley current, and the average value of the peak current and valley current is the LED current. Therefore, the generation of the hysteresis window is the basis of hysteresis current control and is particularly important.

[0004] The window of the traditional hysteresis window circuit remains unchanged when the input voltage and output voltage change, which will cause the switching frequency to change, resulting in a large range of switching frequency changes, and further causing other effects. Therefore, its application has great limitations. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a circuit for hysteresis current control to generate a hysteresis window that varies with input and output. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a circuit for hysteresis current control to generate a hysteresis window that changes with input and output, comprising: an input-output signal processing circuit and a hysteresis window generating circuit; the output of the output signal processing circuit is connected to the input of the hysteresis window generating circuit;

[0007] The input-output signal processing circuit is used to generate a current having a functional relationship with the input and output;

[0008] The hysteresis window circuit is used to convert a current having a functional relationship with an input and an output into a voltage having a functional relationship with the input and an output.

[0009] Beneficial effects of the present invention:

[0010] The present invention provides a circuit for hysteresis current control to generate a hysteresis window that varies with input and output, which is used to stabilize the switching frequency of LED driving. The circuit includes an input-output signal processing circuit and a hysteresis window generation circuit. When the input-output voltage changes, the hysteresis window circuit generates a hysteresis window that is a function of the input and output, so that the switching frequency remains fixed, reducing the cost of EMI design. The present invention can also set the frequency at the required frequency to solve crosstalk with other modules, and can be widely applied to LED driving with hysteresis current control, improving the reliability of the driver and having a wide range of application scenarios. In addition, the present invention uses an operational amplifier with a common-gate input to enable sampling of the input voltage range from 7V to 40V and the output voltage from 5V to 15V, greatly reducing the complexity of input-output sampling and the complexity of signal multiplication and division processing, and greatly improving the sampling accuracy for a wide input-output range.

[0011] The following will further describe the present invention in detail with reference to the accompanying drawings and embodiments. Description of the Drawings

[0012] Figure 1 is the input-output signal processing circuit in a circuit for hysteresis current control to generate a hysteresis window that varies with input and output according to the present invention;

[0013] Figure 2 is the hysteresis window generation circuit in a circuit for hysteresis current control to generate a hysteresis window that varies with input and output according to the present invention;

[0014] Figure 3 is a schematic diagram of a BULK-type LED driving structure;

[0015] Figure 4 is the present invention at V OUT = 6V, the simulation waveform diagram of the hysteresis window varying with V IN ;

[0016] Figure 5 is the present invention at V IN = 40V, the simulation waveform diagram of the hysteresis window varying with V OUT ; Detailed Embodiments

[0017] The following will further describe the present invention in detail with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0018] The present invention provides a circuit for hysteresis current control to generate a hysteresis window that varies with input and output, including: an input-output signal processing circuit and a hysteresis window generation circuit; the output of the output-output signal processing circuit is connected to the input of the hysteresis window generation circuit;

[0019] The input / output signal processing circuit is used to generate a current that is a function of the input / output;

[0020] The hysteresis window circuit is used to convert the current that is a function of the input / output into a voltage that is a function of the input / output.

[0021] As Figure 1 shown, the input / output signal processing circuit includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24, a first BJT Q1, a second BJT Q2, a third BJT Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10;

[0022] wherein, the first end of the first resistor R1 is connected to the source ends of the first MOS transistor M1 and the seventh MOS transistor M7, and the second end is connected to the input voltage V IN ; the first end of the second resistor R2 is connected to the source end of the second MOS transistor M2, and the second end is connected to the output voltage V of the driver OUT ; the first end of the third resistor R3 is connected to the source ends of the third MOS transistor M3 and the eighth MOS transistor M8, and the second end is connected to the voltage V obtained by sampling the output voltage of the driver OUT ; the first end of the fourth resistor R4 is connected to the source end of the fourth MOS transistor M4, and the second end is connected between the seventh resistor R7 and the eighth resistor R8; the first end of the fifth resistor R5 is connected to the source ends of the fifth MOS transistor M5 and the ninth MOS transistor M9, and the second end is connected to the input voltage V IN; The first end of the sixth resistor R6 is connected to the source end of the sixth MOS transistor M6, and the second end is connected between the ninth resistor R9 and the tenth resistor R10; the gate end and the drain end of the first MOS transistor M1 are shorted; the gate end and the drain end of the third MOS transistor M3 are shorted; the gate end and the drain end of the fifth MOS transistor M5 are shorted; the drain end of the tenth MOS transistor M10 is connected to the drain end of the first MOS transistor M1, the source end is connected to the drain end of the nineteenth MOS transistor M19, and the gate end is connected to the power supply voltage VDD; the drain end of the tenth MOS transistor M10 is connected to the drain end of the first MOS transistor M1, the source end is connected to the drain end of the nineteenth MOS transistor M19, and the gate end is connected to the power supply voltage VDD; the drain end of the tenth MOS transistor M10 is connected to the drain end of the first MOS transistor M1, the source end is connected to the drain end of the nineteenth MOS transistor M19, and the gate end is connected to the power supply voltage VDD; the drain end of the eleventh MOS transistor M11 is connected to the drain end of M2 and the gate end of the seventh MOS transistor M7, the source end is connected to the drain end of M20, and the gate end is connected to the power supply voltage VDD; the drain end of the twelfth MOS transistor M12 is connected to the drain end of the seventh MOS transistor M7, the source end is connected to the collector of the first BJT Q1, and the gate end is connected to the power supply voltage VDD; the drain end of the thirteenth MOS transistor M13 is connected to the drain end of the third MOS transistor M3, the source end is connected to the drain end of the twenty-first MOS transistor M21, and the gate end is connected to the power supply voltage VDD; the drain end of the fourteenth MOS transistor M14 is connected to the drain end of the fourth MOS transistor M4 and the gate end of the eighth MOS transistor M8, the source end is connected to the drain end of the twenty-second MOS transistor M22, and the gate end is connected to the power supply voltage VDD; the drain end of the fifteenth MOS transistor M15 is connected to the drain end of the eighth MOS transistor M8, the source end is connected to the collector of the second BJT Q2, and the gate end is connected to the power supply voltage VDD; the drain end of the sixteenth MOS transistor M16 is connected to the drain end of the fifth MOS transistor M5, the source end is connected to the drain end of the twenty-third MOS transistor M23, and the gate end is connected to the power supply voltage VDD; the drain end of the seventeenth MOS transistor M17 is connected to the drain end of the sixth MOS transistor M6 and the gate end of the ninth MOS transistor M9, the source end is connected to the drain end of the twenty-fourth MOS transistor M24, and the gate end is connected to the power supply voltage VDD; the drain end of the eighteenth MOS transistor M18 is connected to the drain end of the ninth MOS transistor M9, the source end is connected to the collector of the third BJT Q3, and the gate end is connected to the power supply voltage VDD;

[0023] After the collector and the base of the first BJT Q1 are shorted, it serves as the first output end of the input-output signal processing circuit, and outputs the voltage V BE1 , and the emitter of the first BJT Q1 is grounded; after the collector and the base of the second BJT Q2 are shorted, it serves as the second output end of the input-output signal processing circuit, and outputs the voltage V BE2 , and the emitter is grounded; after the collector and the base of the third BJT Q3 are shorted, it serves as the third output end of the input-output signal processing circuit, and outputs the voltage V BE3, the emitter is grounded; the source terminals of the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty - first MOS transistor M21, the twenty - second MOS transistor M22, the twenty - third MOS transistor M23, and the twenty - fourth MOS transistor M24 are all grounded, and the gate terminals are all connected to the first input voltage VBIAS.

[0024] As Figure 2 shown, the hysteresis window generation circuit includes the twenty - fifth MOS transistor M25, the twenty - sixth MOS transistor M26, the twenty - seventh MOS transistor M27, the twenty - eighth MOS transistor M28, the twenty - ninth MOS transistor M29, the thirtieth MOS transistor M30, the thirty - first MOS transistor M31, the thirty - second MOS transistor M32, the thirty - third MOS transistor M33, the thirty - fourth MOS transistor M34, the fourth BJT Q4, the first operational amplifier AMP1, the second operational amplifier AMP2, the third operational amplifier AMP3, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, and the sixteenth resistor R16;

[0025] The first end of the eleventh resistor R11 is connected to the first output terminal V BE1 of the input - output signal processing circuit, and the second end is connected to the non - inverting terminal of the first operational amplifier AMP1; the first end of the twelfth resistor R12 is connected to the second output terminal V BE2 of the input - output signal processing circuit, and the second end is connected to the non - inverting terminal of the second operational amplifier AMP2; the first end of the thirteenth resistor R13 is connected to the third output terminal V BE3 of the input - output signal processing circuit, and the second end is connected to the inverting terminal of the first operational amplifier AMP1; the output terminal of the first operational amplifier AMP1 is connected to the non - inverting terminal of the second operational amplifier AMP2; the inverting terminal of the second operational amplifier AMP2 is connected to the base of the fourth BJT Q4 and the source terminal of the twenty - fifth MOS transistor M25, and the output terminal is connected to the gate terminal of the twenty - fifth MOS transistor M25; the drain terminal of the twenty - fifth MOS transistor M25 is connected to the power supply voltage VDD; the gate and drain of the twenty - sixth MOS transistor M26 are short - circuited, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of the twenty - ninth MOS transistor M29; the gate terminal of the twenty - seventh MOS transistor M27 is connected to the gate terminal of the twenty - sixth MOS transistor M26, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of the thirtieth MOS transistor M30; the gate terminal of the twenty - eighth MOS transistor M28 is connected to the output terminal of the third operational amplifier AMP3, the source terminal is connected to the power supply voltage VDD, the drain terminal is connected to the first end of the fifteenth resistor R15, and the second end of the fifteenth resistor R15 is the first output terminal for outputting the high voltage V H; The gate and drain of the twenty-ninth MOS transistor M29 are shorted, and the drain terminal is connected to the collector of the fourth BJT Q4; the gate terminal of the thirtieth MOS transistor M30 is connected to the gate terminal of the twenty-ninth MOS transistor M29, and the drain terminal is connected to the drain terminal of the thirty-first MOS transistor M31; the gate and drain of the thirty-first MOS transistor M31 are shorted, the gate terminal is connected to the gate terminal of the thirty-second MOS transistor M32, and the source terminal is connected to the drain terminal of the thirty-third MOS transistor M33; the drain terminal of the thirty-second MOS transistor M32 is connected to the second terminal of the sixteenth resistor R16, and the second terminal is the second output terminal, outputting a low voltage V L , and the source terminal is connected to the drain terminal of the thirty-fourth MOS transistor M34; the gate and drain of the thirty-third MOS transistor M33 are shorted, the gate terminal is connected to the gate terminal of the thirty-fourth MOS transistor M34, and the source terminal is grounded; the source terminal of the thirty-fourth MOS transistor M34 is grounded; the emitter of the fourth BJT Q4 is grounded; the non-inverting terminal of the third operational amplifier AMP3 is connected to an externally input voltage V REF , and the inverting terminal is connected between the fifteenth resistor R15 and the sixteenth resistor R16; the fifteenth resistor R15 and the sixteenth resistor R16 are connected in series.

[0026] The circuit principle of generating a hysteresis window that changes with input and output in an LED driver for hysteresis current control of the present invention will be described below:

[0027] In the BULK type switching power supply LED driver, the expression of the switching frequency is as follows

[0028]

[0029]

[0030] where A is a constant proportionality coefficient; V IN refers to the sampled V in the output signal processing circuit IN ; V OUT refers to the sampled V in the output signal processing circuit OUT ; V H , V L i.e., the output of the hysteresis window generation circuit in the present invention.

[0031]

[0032] where K is a constant proportionality coefficient.

[0033] When V H - V L satisfies Equation (4), substituting Equation (4) into Equation (2) gives:

[0034]

[0035] Substituting Equation (5) into (1) gives:

[0036]

[0037] Where A and K are constants; L is the inductance value in the LED drive, which is determined to be a constant by the design.

[0038] Using the input-output signal processing circuit to construct Equation (4), in the input-output signal processing circuit: R1 = R2, R3 = R4, R5 = R6. M1 and M2 serve as the first-stage common-gate amplifiers, and M7 serves as the second-stage common-gate amplifier. M10 and M11 have their gates connected to VDD for high-voltage protection. M19 and M20 are current mirror loads, providing bias current for M1 and M2. This makes the source voltages of M1 and M2 equal, so the current flowing through Q1 is (V IN -V OUT ) / R1. According to the BJT current formula, the voltage of V BE1 is:

[0039]

[0040] Similarly, VBE2 is:

[0041]

[0042] Where N is the voltage division ratio of R7 and R8 to V OUT .

[0043] Similarly, VBE3 is:

[0044]

[0045] Where M is the voltage division ratio of R9 and R10 to V IN , I S is the saturation current of the BJT transistor, V T is the thermal voltage of the BJT transistor, and the saturation current and thermal voltage are default values.

[0046] Input the obtained V BE1 , V BE2 , V BE3 into the hysteresis window generation circuit. In the hysteresis window generation circuit, through AMP1 and AMP2, perform addition and subtraction operations on the obtained V BE1 , V BE2 , V BE3 to get V BE4 = V BE1 + V BE2 - V BE3

[0047]

[0048] And V BE4 is the base of Q4, so the current I Q4 flowing through Q4 is:

[0049]

[0050] I Q4 is copied to the branch where M28 is located through the current mirror formed by M26, M27, M29, M30, M31, M32, M33, M34. M28 and AMP3 form a clamping circuit such that the mid-value of V H -V L is V REF Therefore, it can be obtained that ΔV H = V H -V L is:

[0051]

[0052] Then the F SW generated by this hysteresis window is:

[0053]

[0054] where R1, R3, R15, R16, A, M, N, L are all given by the design.

[0055] Thus, a switching frequency independent of the input and output is obtained.

[0056] Please refer to Figure 4 , Figure 4 which is the simulation waveform diagram of the hysteresis window varying with V OUT when V IN = 6V. The ideal waveform simulation waveform ΔV H and the deviation between the two are shown in Figure 4 . When V OUT is fixed at 6V and V IN varies from 7V to 40V, it can be seen that the maximum deviation is 3.4332%.

[0057] Please refer to Figure 5 , Figure 5 which is the simulation waveform diagram of the hysteresis window varying with V IN when V IN = 40V. The ideal waveform simulation waveform ΔV H and the deviation between the two are shown in Figure 5 . The green line is the deviation between the two. When V IN is fixed at 40V and V OUT varies from 5V to 15V, it can be seen that the maximum deviation is 1.39083%.

[0058] The present invention provides an input / output signal processing circuit in a circuit for generating a hysteresis window that varies with input / output in an LED driver for hysteresis current control, such that the switching frequency of the hysteresis current-controlled LED driver is not affected by the input / output.

[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0060] Although the present application has been described in conjunction with various embodiments, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of cases.

[0061] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited only to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A circuit for hysteresis current control to generate a hysteresis window that varies with input and output, characterized in that, Comprising: An input / output signal processing circuit and a hysteresis window generation circuit; The output of the output signal processing circuit is connected to the input of the hysteresis window generation circuit; The input / output signal processing circuit is used to generate a current that has a functional relationship with the input / output; The hysteresis window circuit is used to convert the current that has a functional relationship with the input / output into a voltage that has a functional relationship with the input / output; The input / output signal processing circuit includes: a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5), a sixth MOS transistor (M6), a seventh MOS transistor (M7), an eighth MOS transistor (M8), a ninth MOS transistor (M9), a tenth MOS transistor (M10), an eleventh MOS transistor (M11), a twelfth MOS transistor (M12), a thirteenth MOS transistor (M13), a fourteenth MOS transistor (M14), a fifteenth MOS transistor (M15), a sixteenth MOS transistor (M16), a seventeenth MOS transistor (M17), an eighteenth MOS transistor (M18), a nineteenth MOS transistor (M19), a twentieth MOS transistor (M20), a twenty-first MOS transistor (M21), a twenty-second MOS transistor (M22), a twenty-third MOS transistor (M23), a twenty-fourth MOS transistor (M24), a first BJT (Q1), a second BJT (Q2), a third BJT (Q3), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), and a tenth resistor (R10); Among them, the first end of the first resistor (R1) is connected to the source ends of the first MOS transistor (M1) and the seventh MOS transistor (M7), and the second end is connected to the input voltage V IN ; the first end of the second resistor (R2) is connected to the source end of the second MOS transistor (M2), and the second end is connected to the output voltage (V OUT ) of the driver; the first end of the third resistor (R3) is connected to the source ends of the third MOS transistor (M3) and the eighth MOS transistor (M8), and the second end is connected to the voltage V OUT obtained by sampling the output voltage of the driver; the first end of the fourth resistor (R4) is connected to the source end of the fourth MOS transistor (M4), and the second end is connected between the seventh resistor (R7) and the eighth resistor (R8); the first end of the fifth resistor (R5) is connected to the source ends of the fifth MOS transistor (M5) and the ninth MOS transistor (M9), and the second end is connected to the input voltage V IN ; The first end of the sixth resistor (R6) is connected to the source end of the sixth MOS transistor (M6), and the second end is connected between the ninth resistor (R9) and the tenth resistor (R10); the gate terminal and the drain terminal of the first MOS transistor (M1) are short-circuited; the gate terminal and the drain terminal of the third MOS transistor (M3) are short-circuited; the gate terminal and the drain terminal of the fifth MOS transistor (M5) are short-circuited; the drain terminal of the tenth MOS transistor (M10) is connected to the drain terminal of the first MOS transistor (M1), the source end is connected to the drain terminal of the nineteenth MOS transistor (M19), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the tenth MOS transistor (M10) is connected to the drain terminal of the first MOS transistor (M1), the source end is connected to the drain terminal of the nineteenth MOS transistor (M19), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the tenth MOS transistor (M10) is connected to the drain terminal of the first MOS transistor (M1), the source end is connected to the drain terminal of the nineteenth MOS transistor (M19), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the eleventh MOS transistor (M11) is connected to the drain terminal of M2 and the gate terminal of the seventh MOS transistor (M7), the source end is connected to the drain terminal of M20, and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the twelfth MOS transistor (M12) is connected to the drain terminal of the seventh MOS transistor (M7), the source end is connected to the collector of the first BJT (Q1), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the thirteenth MOS transistor (M13) is connected to the drain terminal of the third MOS transistor (M3), the source end is connected to the drain terminal of the twenty-first MOS transistor (M21), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the fourteenth MOS transistor (M14) is connected to the drain terminal of the fourth MOS transistor (M4) and the gate terminal of the eighth MOS transistor (M8), the source end is connected to the drain terminal of the twenty-second MOS transistor (M22), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the fifteenth MOS transistor (M15) is connected to the drain terminal of the eighth MOS transistor (M8), the source end is connected to the collector of the second BJT (Q2), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the sixteenth MOS transistor (M16) is connected to the drain terminal of the fifth MOS transistor (M5), the source end is connected to the drain terminal of the twenty-third MOS transistor (M23), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the seventeenth MOS transistor (M17) is connected to the drain terminal of the sixth MOS transistor (M6) and the gate terminal of the ninth MOS transistor (M9), the source end is connected to the drain terminal of the twenty-fourth MOS transistor (M24), and the gate terminal is connected to the power supply voltage (VDD); the drain terminal of the eighteenth MOS transistor (M18) is connected to the drain terminal of the ninth MOS transistor (M9), the source end is connected to the collector of the third BJT (Q3), and the gate terminal is connected to the power supply voltage (VDD); After the collector and the base of the first BJT (Q1) are short-circuited, it serves as the first output terminal of the input / output signal processing circuit, and outputs voltage V BE1 , and the emitter of the first BJT (Q1) is grounded; after the collector and the base of the second BJT (Q2) are short-circuited, it serves as the second output terminal of the input / output signal processing circuit, and outputs voltage V BE2 , and the emitter is grounded; after the collector and the base of the third BJT (Q3) are short-circuited, it serves as the third output terminal of the input / output signal processing circuit, and outputs voltage V BE3 , and the emitter is grounded; the source terminals of the nineteenth MOS transistor (M19), the twentieth MOS transistor (M20), the twenty-first MOS transistor (M21), the twenty-second MOS transistor (M22), the twenty-third MOS transistor (M23), and the twenty-fourth MOS transistor (M24) are all grounded, and the gate terminals are all connected to the first input voltage (VBIAS); The hysteresis window generation circuit includes a twenty-fifth MOS transistor (M25), a twenty-sixth MOS transistor (M26), a twenty-seventh MOS transistor (M27), a twenty-eighth MOS transistor (M28), a twenty-ninth MOS transistor (M29), a thirtieth MOS transistor (M30), a thirty-first MOS transistor (M31), a thirty-second MOS transistor (M32), a thirty-third MOS transistor (M33), a thirty-fourth MOS transistor (M34), a fourth BJT (Q4), a first operational amplifier (AMP1), a second operational amplifier (AMP2), a third operational amplifier (AMP3), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16); The first terminal of the eleventh resistor (R11) is connected to the first output terminal (V BE1 ) of the input / output signal processing circuit, and the second terminal is connected to the non-inverting terminal of the first operational amplifier (AMP1); the first terminal of the twelfth resistor (R12) is connected to the second output terminal (V BE2 ) of the input / output signal processing circuit, and the second terminal is connected to the non-inverting terminal of the second operational amplifier (AMP2); the first terminal of the thirteenth resistor (R13) is connected to the third output terminal (V BE3 ) of the input / output signal processing circuit, and the second terminal is connected to the inverting terminal of the first operational amplifier (AMP1); the output terminal of the first operational amplifier (AMP1) is connected to the non-inverting terminal of the second operational amplifier (AMP2); the inverting terminal of the second operational amplifier (AMP2) is connected to the base of the fourth BJT (Q4) and the source terminal of the twenty-fifth MOS transistor (M25), and the output terminal is connected to the gate terminal of the twenty-fifth MOS transistor (M25); the drain terminal of the twenty-fifth MOS transistor (M25) is connected to the power supply voltage VDD; the gate and drain of the twenty-sixth MOS transistor (M26) are short-circuited, the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of the twenty-ninth MOS transistor (M29); the gate terminal of the twenty-seventh MOS transistor (M27) is connected to the gate terminal of the twenty-sixth MOS transistor (M26), the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of the thirtieth MOS transistor (M30); the gate terminal of the twenty-eighth MOS transistor (M28) is connected to the output terminal of the third operational amplifier (AMP3), the source terminal is connected to the power supply voltage VDD, and the drain terminal is connected to the first terminal of the fifteenth resistor (R15), and the second terminal of the fifteenth resistor (R15) is the first output terminal for outputting the high voltage V H ; the gate and drain of the twenty-ninth MOS transistor (M29) are short-circuited, and the drain terminal is connected to the collector of the fourth BJT (Q4); the gate terminal of the thirtieth MOS transistor (M30) is connected to the gate terminal of the twenty-ninth MOS transistor (M29), and the drain terminal is connected to the drain terminal of the thirty-first MOS transistor (M31); the gate and drain of the thirty-first MOS transistor (M31) are short-circuited, the gate terminal is connected to the gate terminal of the thirty-second MOS transistor (M32), and the source terminal is connected to the drain terminal of the thirty-third MOS transistor (M33); the drain terminal of the thirty-second MOS transistor (M32) is connected to the second terminal of the sixteenth resistor (R16), and the second terminal is the second output terminal for outputting the low voltage V L , and the source terminal is connected to the drain terminal of the thirty-fourth MOS transistor (M34); the gate and drain of the thirty-third MOS transistor (M33) are short-circuited, the gate terminal is connected to the gate terminal of the thirty-fourth MOS transistor (M34), and the source terminal is grounded; the source terminal of the thirty-fourth MOS transistor (M34) is grounded; the emitter of the fourth BJT (Q4) is grounded; the non-inverting terminal of the third operational amplifier (AMP3) is connected to the externally input voltage V REF , and the inverting terminal is connected between the fifteenth resistor (R15) and the sixteenth resistor (R16); the fifteenth resistor (R15) and the sixteenth resistor (R16) are connected in series.

2. The circuit for hysteresis current control to generate a hysteresis window that varies with input and output according to claim 1, characterized in that, Wherein, N is the voltage division ratio of the sixth MOS transistor (M6) and the seventh MOS transistor (M7) to voltage V OUT ; M is the voltage division ratio of the ninth MOS transistor (M9) and the tenth MOS transistor (M10) to voltage V IN ; I S is the saturation current of the BJT transistor, V T is the thermal voltage of the BJT transistor, and the saturation current and the thermal voltage are default values.

3. The circuit for hysteresis current control to generate a hysteresis window that varies with input and output according to claim 2, characterized in that, The hysteresis window generation circuit performs addition and subtraction operations on the obtained voltages V BE1 , V BE2 , V BE3 to obtain V BE4 = V BE1 + V BE2 - V BE3 ; ΔV H = V H - V L is: The switching frequency F generated by the hysteresis window SW is as follows: Wherein, A and L are given values.

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