Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a display area and a peripheral area; the peripheral area comprises a first pin setting area and a second pin setting area arranged oppositely; the display panel comprises a low-voltage line; the display panel comprises at least one high-voltage signal pin and at least one low-voltage signal pin arranged in the first pin setting area, and at least one high-voltage signal pin and at least one low-voltage signal pin arranged in the second pin setting area; the high-voltage signal pin transmits a high-voltage signal to the high-voltage line, and the low-voltage signal pin transmits a low-voltage signal to the low-voltage line; at least part of the high-voltage signal pins and at least part of the low-voltage signal pins are arranged alternately; the pins of the display panel are arranged in sequence along a first direction; the first pin setting area and the second pin setting area are arranged along a second direction; and the first direction and the second direction intersect. The application can improve the brightness uniformity of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related technologies, as AMOLED (Active-matrix organic light-emitting diode) technology matures, OLED is increasingly being used in application scenarios other than mobile phones, such as laptops and in-vehicle display products. However, large-size display products, especially high-brightness portrait display products such as 15.6-inch and 17.3-inch, have a larger IR Drop due to their larger size, and the brightness uniformity will deteriorate. In particular, display products with a brightness of more than 800 nits often have a brightness uniformity of less than 60%. Poor brightness uniformity results in higher power consumption, resulting in a higher temperature rise in the display product, which seriously affects the user experience of the display product and shortens the service life of the display product. Summary of the Invention

[0003] The main purpose of the present invention is to provide a display panel and a display device to solve the problem of poor brightness uniformity of existing AMOLED display products.

[0004] An embodiment of the present invention provides a display panel, comprising a display area and a peripheral area; wherein the peripheral area comprises a first pin arrangement area and a second pin arrangement area disposed opposite to each other; the display panel comprises a high voltage line disposed in the display area and a low voltage line at least partially disposed in the peripheral area;

[0005] The display panel includes at least one high voltage signal pin and at least one low voltage signal pin arranged in a first pin arrangement area, and at least one high voltage signal pin and at least one low voltage signal pin arranged in a second pin arrangement area;

[0006] The high voltage signal pin is used to transmit a high voltage signal to the high voltage line, and the low voltage signal pin is used to transmit a low voltage signal to the low voltage line;

[0007] At least some of the high voltage signal pins and at least some of the low voltage signal pins are alternately arranged;

[0008] The pins included in the display panel are arranged in sequence along a first direction; the first pin setting area and the second pin setting area are arranged along a second direction;

[0009] The first direction and the second direction intersect.

[0010] Optionally, the display panel includes a base substrate, at least two high voltage signal pins and at least two low voltage signal pins arranged in a first pin arrangement area; the high voltage signal pins and the low voltage signal pins are both arranged on the base substrate;

[0011] In the first pin arrangement area, the high voltage signal pins and the low voltage signal pins are alternately arranged;

[0012] In the first pin arrangement area, an orthographic projection of at least one of the high-voltage signal pins on the base substrate overlaps with an orthographic projection of at least one of the low-voltage signal pins on the base substrate.

[0013] Optionally, the display panel includes a base substrate, at least two low voltage signal pins and at least one high voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are both arranged on the base substrate;

[0014] In the first pin arrangement area, the at least one high voltage signal pin is arranged between two adjacent low voltage signal pins;

[0015] In the first pin arrangement area, an orthographic projection of the high voltage signal pin on the base substrate does not overlap with an orthographic projection of the low voltage signal pin on the base substrate.

[0016] Optionally, the first pin arrangement area includes a first sub-area and a second sub-area adjacently arranged along the first direction;

[0017] The display panel includes a base substrate, a first pin block arranged in the first sub-region, and a second pin block arranged in the second sub-region;

[0018] The first pin block includes at least two low-voltage signal pins electrically connected to each other, and the second pin block includes at least two high-voltage signal pins electrically connected to each other;

[0019] In the first cathode setting area, the orthographic projection of the low voltage signal pin on the substrate does not overlap with the orthographic projection of the high voltage signal pin on the substrate; the orthographic projection of the high voltage signal pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate;

[0020] The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

[0021] Optionally, the display panel includes a base substrate, at least two high voltage signal pins and at least one low voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are arranged on the base substrate;

[0022] In the first pin arrangement area, the at least one low voltage signal pin is arranged between two adjacent high voltage signal pins;

[0023] In the first pin arrangement area, the orthographic projection of the high voltage signal pin on the substrate does not overlap with the orthographic projection of the low voltage signal pin on the substrate; the orthographic projection of the high voltage signal pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate;

[0024] The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

[0025] Optionally, the display panel includes a base substrate, at least one initial voltage pin arranged in a first pin arrangement area, at least one initial voltage pin arranged in a second pin arrangement area, and an initial voltage line arranged in a display area;

[0026] The initial voltage pin and the initial voltage line are both provided on the base substrate;

[0027] The initial voltage pin is used to provide an initial voltage for the initial voltage line;

[0028] In the first pin arrangement area, the orthographic projection of the initial voltage pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate; the low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin;

[0029] In the second pin arrangement area, the orthographic projections of the pins on the substrate do not overlap;

[0030] The initial voltage pin is arranged between the high voltage signal pin and the low voltage signal pin.

[0031] Optionally, the display panel includes a first initial voltage pin and a second initial voltage pin arranged in the first pin arrangement area, and a third initial voltage pin and a fourth initial voltage pin arranged in the second pin arrangement area;

[0032] The display panel further includes a first first initial voltage line, a first second initial voltage line, a second first initial voltage line and a second second initial voltage line arranged in the display area;

[0033] The first first initial voltage line is electrically connected with a first initial voltage pin arranged in the first pin arrangement area, the first second initial voltage line is electrically connected with a second initial voltage pin arranged in the first pin arrangement area, the second first initial voltage line is electrically connected with a first initial voltage pin arranged in the second pin arrangement area, and the second second initial voltage line is electrically connected with a second initial pin arranged in the second pin arrangement area.

[0034] The first initial voltage pin is used to provide a first initial voltage signal to the first first initial voltage line, and the third initial voltage pin is used to provide a first initial voltage signal to the second first initial voltage line.

[0035] The second initial voltage pin is used to provide a second initial voltage to the first second initial voltage line, and the fourth initial voltage pin is used to provide a second initial voltage signal to the second second initial voltage line.

[0036] Optionally, the display panel comprises a substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in the first pin arrangement area; the display panel further comprises at least one high-level signal pin and at least one low-level signal pin arranged in the second pin arrangement area; the high-level signal pin and the low-level signal pin are arranged on the substrate.

[0037] The display panel further comprises a high-level signal line and a low-level signal line arranged in the peripheral area.

[0038] The high-level signal line is electrically connected with the high-level signal pin, the high-level signal pin is used to provide a high-level signal to the high-level signal line, and the low-level signal pin is used to provide a low-level signal to the low-level signal line.

[0039] The high-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin, and the low-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin.

[0040] In the first pin arrangement area and the second pin arrangement area, the orthographic projection of each pin on the substrate does not overlap.

[0041] Optionally, the display panel comprises a substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in the first pin arrangement area.

[0042] The display panel further comprises at least one high-level signal pin and at least one low-level signal pin arranged in the second pin arrangement area; the high-level signal pin and the low-level signal pin are arranged on the substrate.

[0043] The display panel further comprises a high-level signal line and a low-level signal line arranged in the peripheral region;

[0044] The high-level signal line is electrically connected with the high-level signal pin, and the high-level signal pin is configured to provide a high-level signal for the high-level signal line, and the low-level signal pin is configured to provide a low-level signal for the low-level signal line;

[0045] In the first pin arrangement region, the high-level signal pin is arranged between the first initial voltage pin and the high-voltage signal pin, and the low-level signal pin is arranged between the high-voltage signal pin and the second initial voltage pin.

[0046] Optionally, in the first pin arrangement region, the orthographic projections of the pins on the substrate do not overlap.

[0047] Optionally, the display panel comprises a substrate and a plurality of conductive layers arranged on the substrate in layers;

[0048] The pins comprised by the display panel are formed in the conductive layers;

[0049] When the orthographic projections of two pins comprised by the display panel on the substrate do not overlap, the two pins are arranged in the same layer;

[0050] When the orthographic projections of two pins comprised by the display panel on the substrate overlap, the two pins are arranged in different layers.

[0051] Optionally, the display panel further comprises a display substrate, a first flexible circuit board and a second flexible circuit board;

[0052] The pins in the first pin arrangement region and the pins in the second pin arrangement region are both arranged on the display substrate;

[0053] The first flexible circuit board is arranged on the side of the pins in the first pin arrangement region away from the display substrate, and the first flexible circuit board is configured to provide corresponding signals for the pins in the first pin arrangement region;

[0054] The second flexible circuit board is arranged on the side of the pins in the second pin arrangement region away from the display substrate, and the second flexible circuit board is configured to provide corresponding signals for the pins in the second pin arrangement region.

[0055] Optionally, the display substrate is a flexible substrate;

[0056] The pins in the first pin arrangement region and the first flexible circuit board can be bent to the non-display surface of the display panel;

[0057] The pins arranged in the second pin arrangement area and the second flexible circuit board can be bent to the non-display surface of the display panel.

[0058] An embodiment of the present invention further provides a display device including the above-mentioned display panel.

[0059] In an embodiment of the present invention, a first pin setting area is provided on the upper portion of the display panel, and a second pin setting area is provided on the lower portion of the display panel. A high-voltage signal pin and a low-voltage signal pin are provided in each pin setting area, respectively, to reduce IR drop (IR drop, which refers to a phenomenon in which the voltage drops or rises on the power supply and ground networks in an integrated circuit), improve brightness uniformity, and reduce the in-plane temperature difference and temperature rise of large-size AMOLED display products. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0061] Figure 2 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0062] Figure 3 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0063] Figure 4 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0064] Figure 5 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0065] Figure 6 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0066] Figure 7 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0067] Figure 8 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0068] Figure 9 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0069] Figure 10 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention;

[0070] Figure 11 is a circuit diagram of a related pixel circuit;

[0071] Figure 12 FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0073] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first electrode and the other pole is referred to as the second electrode.

[0074] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode can be a drain electrode and the second electrode can be a source electrode; or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0075] The display panel according to the embodiments of the present application comprises a display area and a peripheral area; the peripheral area comprises oppositely arranged first pin arrangement areas and second pin arrangement areas; the display panel comprises high-voltage lines arranged in the display area and low-voltage lines arranged at least partially in the peripheral area.

[0076] The display panel comprises at least one high-voltage signal pin and at least one low-voltage signal pin arranged in the first pin arrangement area, and at least one high-voltage signal pin and at least one low-voltage signal pin arranged in the second pin arrangement area.

[0077] The high-voltage signal pin is used to transmit a high-voltage signal VDD to the high-voltage line, and the low-voltage signal pin is used to transmit a low-voltage signal VSS to the low-voltage line.

[0078] At least part of the high-voltage signal pins and at least part of the low-voltage signal pins are arranged alternately.

[0079] The pins comprised by the display panel are arranged in a first direction in sequence; the first pin arrangement area and the second pin arrangement area are arranged in a second direction.

[0080] The first direction and the second direction intersect.

[0081] In at least one embodiment of the present application, the first direction can be a horizontal direction and the second direction can be a vertical direction, but the present application is not limited thereto.

[0082] In at least one embodiment of the present invention, alternating arrangement of at least some of the high voltage signal pins and at least some of the low voltage signal pins means:

[0083] At least one high voltage signal pin is disposed between two low voltage signal pins, and / or at least one low voltage signal pin is disposed between two low voltage signal pins.

[0084] In an embodiment of the present invention, the peripheral area includes a first pin setting area and a second pin setting area that are arranged opposite to each other. In the first pin setting area, the display panel includes a high-voltage signal pin and a low-voltage signal pin, and in the second pin setting area, the display panel includes a high-voltage signal pin and a low-voltage signal pin. When providing a high-voltage signal to a pixel circuit arranged in the display area, the high-voltage signal pin arranged in the first pin setting area and the high-voltage signal pin arranged in the second pin setting area provide the high-voltage signal to the pixel circuit, thereby reducing IR drop (IR drop, which refers to a phenomenon in which the voltage drops or rises on the power supply and ground networks in an integrated circuit) when transmitting the high-voltage signal.

[0085] In a specific implementation, when providing a high voltage signal to a pixel circuit arranged in a display area, a low voltage signal is provided to the pixel circuit by a low voltage signal pin arranged in a first pin setting area and a low voltage signal pin arranged in a second pin setting area, and an IR Drop is small when transmitting the low voltage signal.

[0086] An embodiment of the present invention provides a display panel, which adds a bonding pad (pin) on the upper part, sets a first pin setting area on the upper part of the display panel, and sets a second pin setting area on the lower part of the display panel. A high-voltage signal pin and a low-voltage signal pin are respectively set in each pin setting area to reduce IR drop, improve brightness uniformity, and reduce the in-plane temperature difference and temperature rise of large-size AMOLED (Active-matrix organic light-emitting diode) display products.

[0087] In a specific implementation, each pin (pad) is provided on the flexible display screen, and the flexible circuit board (FPC) is attached to the pins. Each pin provides high-voltage and low-voltage signals to the pixel circuits provided in the display area through the FPC. In the first pin arrangement area and the second pin arrangement area (the first pin arrangement area can be provided above the display panel, and the second pin arrangement area can be provided below the display panel, but is not limited thereto), the pins and the FPC can be bent simultaneously to reduce the upper and lower bezels of the display panel.

[0088] According to a specific embodiment, the display panel includes a base substrate, at least two high voltage signal pins and at least two low voltage signal pins arranged in a first pin arrangement area; the high voltage signal pins and the low voltage signal pins are both arranged on the base substrate;

[0089] The high voltage signal pins and the low voltage signal pins are alternately arranged;

[0090] An orthographic projection of at least one of the high-voltage signal pins on the substrate partially overlaps with an orthographic projection of at least one of the low-voltage signal pins on the substrate.

[0091] exist Figure 1 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0092] The first pin arrangement area A1 is provided with a first upper low voltage signal pin P11, a first upper high voltage signal pin P21, a second upper low voltage signal pin P12, a second upper high voltage signal pin P22, a third upper low voltage signal pin P13, a third upper high voltage signal pin P23 and a fourth upper low voltage signal pin P14;

[0093] The first upper low voltage signal pin P11, the first upper high voltage signal pin P21, the second upper low voltage signal pin P12, the second upper high voltage signal pin P22, the third upper low voltage signal pin P13, the third upper high voltage signal pin P23 and the fourth upper low voltage signal pin P14 are arranged in sequence from left to right;

[0094] The second pin arrangement area A2 is provided with a first lower low voltage signal pin P31, a first lower high voltage signal pin P41, a second lower low voltage signal pin P32, a third lower low voltage signal pin P33, a fourth lower low voltage signal pin P34, a fifth lower low voltage signal pin P35, a second lower high voltage signal pin P42 and a sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0095] exist Figure 1 In the figure, the line labeled VSS1 is the first low voltage line, the line labeled VSS2 is the second low voltage line, the line labeled VDD0 is the high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line; VSS1 is electrically connected to P11, VSS2 is electrically connected to P14; VDD0 is electrically connected to P21, P22 and P23; VSS1 is electrically connected to P31, VSS2 is electrically connected to P36; VDD0 is electrically connected to P41 and P42;

[0096] VSS1 and VSS2 are disposed in the peripheral area of ​​the display panel, VSS1 is disposed on the left side of the display panel, and VSS2 is disposed on the right side of the display panel.

[0097] In at least one embodiment of the present invention, the area labeled A0 is a display area.

[0098] In at least one embodiment of the present invention, the low-voltage lines may also be disposed in the display area and may also be designed in a grid shape.

[0099] exist Figure 1 In at least one embodiment shown, in the first pin setting area, high voltage signal pins and the low voltage signal pins are alternately arranged to further reduce IR Drop when transmitting high voltage signals and reduce IR Drop when transmitting low voltage signals.

[0100] exist Figure 1 In at least one embodiment shown, in the first pin setting area and the second pin setting area, the high voltage signal pin and the low voltage signal pin are alternately arranged, which can reduce the VDD (VDD is a high voltage signal) Drop (voltage drop) to 0.2613V, the VSS (VSS is a low voltage signal) Drop to 2.5593V, and the LRU (brightness uniformity) to 70.41%; compared with the conventional solution, Figure 1 In at least one embodiment shown, the LRU is improved by 16.6%.

[0101] exist Figure 1 In at least one embodiment shown, the first orthographic projection overlaps with the orthographic projection of the second upper high-voltage signal pin P22 on the substrate;

[0102] The first orthographic projection includes an orthographic projection of P12 on the base substrate and an orthographic projection of P13 on the base substrate.

[0103] In at least one embodiment of the present invention, in the first pin arrangement area, the high voltage signal pins can be connected to each other, and the low voltage signal pins can be connected to each other;

[0104] In the second pin arrangement area, the high voltage signal pins can be connected to each other, and the low voltage signal pins can be connected to each other;

[0105] But it is not limited to this.

[0106] According to another specific embodiment, the display panel includes a base substrate, at least two low voltage signal pins and at least one high voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are both arranged on the base substrate;

[0107] The at least one high voltage signal pin is arranged between two adjacent low voltage signal pins;

[0108] The orthographic projection of the high voltage signal pin on the base substrate does not overlap with the orthographic projection of the low voltage signal pin on the base substrate.

[0109] exist Figure 2 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0110] In the first pin arrangement area A1, a first upper low voltage signal pin P11, a second upper low voltage signal pin P12, a first upper high voltage signal pin P21, a second upper high voltage signal pin P22, a third upper high voltage signal pin P23, a third upper low voltage signal pin P13 and a fourth upper low voltage signal pin P14 are arranged;

[0111] The first upper low voltage signal pin P11, the second upper low voltage signal pin P12, the first upper high voltage signal pin P21, the second upper high voltage signal pin P22, the third upper high voltage signal pin P23, the third upper low voltage signal pin P13 and the fourth upper low voltage signal pin P14 are arranged in sequence from left to right;

[0112] In the first pin arrangement area A1, P21, P22 and P23 are arranged between P12 and P13;

[0113] The second pin arrangement area A2 is provided with a first lower low voltage signal pin P31, a first lower high voltage signal pin P41, a second lower low voltage signal pin P32, a third lower low voltage signal pin P33, a fourth lower low voltage signal pin P34, a fifth lower low voltage signal pin P35, a second lower high voltage signal pin P42 and a sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0114] exist Figure 2 In the figure, the line labeled VSS1 is a first low voltage line, the line labeled VSS2 is a second low voltage line, the line labeled VDD0 is a high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line;

[0115] VSS1 and VSS2 are arranged in the peripheral area of ​​the display panel, VSS1 is arranged on the left side of the display panel, and VSS2 is arranged on the right side of the display panel;

[0116] VSS1 is electrically connected to P11, P12, P13, and P14, VSS2 is electrically connected to P11, P12, P13, and P14; VSS1 is electrically connected to P31, VSS2 is electrically connected to P36;

[0117] VDD0 is electrically connected to P21 , P22 , and P23 , and VDD0 is electrically connected to P41 and P42 .

[0118] exist Figure 2 In at least one embodiment shown, in the first pin setting area, the middle is a high voltage signal pin and the two sides are low voltage signal pins. By optimizing VSS Drop and VDD Dropo at the same time, VDD Drop (voltage drop) can be reduced to 0.2738V, VSS Drop to 2.5549V, and LRU (brightness uniformity) can be achieved by 70.41%. Compared with the conventional solution, Figure 1 In at least one embodiment shown, the LRU is improved by 16.6%.

[0119] exist Figure 2 In at least one embodiment shown, the orthographic projection of P11 on the substrate, the orthographic projection of P12 on the substrate, the orthographic projection of P21 on the substrate, the orthographic projection of P22 on the substrate, the orthographic projection of P23 on the substrate, the orthographic projection of P13 on the substrate, and the orthographic projection of P14 on the substrate do not overlap;

[0120] The orthographic projection of P11 on the substrate, the orthographic projection of P12 on the substrate, the orthographic projection of P21 on the substrate, the orthographic projection of P22 on the substrate, the orthographic projection of P23 on the substrate, the orthographic projection of P13 on the substrate, and the orthographic projection of P14 on the substrate do not overlap;

[0121] According to another specific embodiment, the first pin arrangement area includes a first sub-area and a second sub-area adjacently arranged along a first direction;

[0122] The display panel includes a base substrate, a first pin block arranged in the first sub-region, and a second pin block arranged in the second sub-region;

[0123] The first pin block includes at least two low-voltage signal pins electrically connected to each other, and the second pin block includes at least two high-voltage signal pins electrically connected to each other;

[0124] The orthographic projection of the low voltage signal pin on the substrate does not overlap with the orthographic projection of the high voltage signal pin on the substrate;

[0125] The orthographic projection of the high voltage signal pin on the substrate partially overlaps with the orthographic projection of the low voltage signal lead on the substrate;

[0126] The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

[0127] In at least one embodiment of the present invention, the first direction may be a horizontal direction, but is not limited to the first direction.

[0128] exist Figure 3 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0129] In the first pin setting area A1, a first pin block and a second pin block are set;

[0130] The first pin block includes a first upper low voltage signal pin P11, a second upper low voltage signal pin P12, a third upper low voltage signal pin P13, and a fourth upper low voltage signal pin P14 electrically connected to each other; the second pin block includes a first upper high voltage signal pin P21, a second upper high voltage signal pin P22, and a third upper high voltage signal pin P23 electrically connected to each other;

[0131] The first upper low voltage signal pin P11, the second upper low voltage signal pin P12, the third upper low voltage signal pin P13, the fourth upper low voltage signal pin P14, the first upper high voltage signal pin P21, the second upper high voltage signal pin P22 and the third upper high voltage signal pin P23 are arranged in sequence from left to right;

[0132] The first pin setting area A1 includes a first sub-area A11 and a second sub-area A12;

[0133] The first upper low voltage signal pin P11, the second upper low voltage signal pin P12, the third upper low voltage signal pin P13 and the fourth upper low voltage signal pin P14 are disposed in the first sub-area A11, and the first upper high voltage signal pin P21, the second upper high voltage signal pin P22 and the third upper high voltage signal pin P23 are disposed in the second sub-area A12;

[0134] exist Figure 3 In the first pin arrangement area A1, the orthographic projection of each low voltage signal pin on the base substrate does not overlap with the orthographic projection of each high voltage signal pin on the base substrate;

[0135] The first low voltage signal lead LY1 is a connection line between P14 and VSS2.

[0136] The orthographic projection of P21 on the base substrate overlaps with the orthographic projection of LY1 on the base substrate, the orthographic projection of P22 on the base substrate overlaps with the orthographic projection of LY1 on the base substrate, and the orthographic projection of P23 on the base substrate overlaps with the orthographic projection of LY1 on the base substrate;

[0137] like Figure 3As shown, in the second pin setting area A2, there are arranged a first lower low voltage signal pin P31, a first lower high voltage signal pin P41, a second lower low voltage signal pin P32, a third lower low voltage signal pin P33, a fourth lower low voltage signal pin P34, a fifth lower low voltage signal pin P35, a second lower high voltage signal pin P42 and a sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0138] exist Figure 3 In at least one embodiment shown, P11 , P12 , P13 , and P14 are electrically connected to each other, and P21 , P22 , and P23 are electrically connected to each other.

[0139] exist Figure 3 In at least one embodiment shown, in the first pin setting area A1, multiple low voltage signal pins are set on the left and multiple high voltage signal pins are set on the right. The multiple low voltage signal pins are electrically connected to each other, and the multiple high voltage signal pins are electrically connected to each other.

[0140] exist Figure 3 In the figure, the line labeled VSS1 is a first low voltage line, the line labeled VSS2 is a second low voltage line, the line labeled VDD0 is a high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line;

[0141] VSS1 and VSS2 are arranged in the peripheral area of ​​the display panel, VSS1 is arranged on the left side of the display panel, and VSS2 is arranged on the right side of the display panel;

[0142] like Figure 3 As shown, VSS1 is electrically connected to P11, P12 and P13, VSS2 is electrically connected to P11, P12 and P13, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21, P22 and P23, and VDD0 is electrically connected to P41 and P42.

[0143] Optionally, the first pin arrangement area and the second pin arrangement area are arranged along the second direction;

[0144] The first direction and the second direction intersect.

[0145] In at least one embodiment of the present invention, the second direction may be a vertical direction, but is not limited thereto.

[0146] exist Figure 4 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0147] In the first pin arrangement area A1, a first upper low voltage signal pin P11, a second upper low voltage signal pin P12, a third upper low voltage signal pin P13, a first upper high voltage signal pin P21, a fourth upper low voltage signal pin P14, a fifth upper low voltage signal pin P15 and a sixth upper low voltage signal pin P16 are arranged;

[0148] A first upper low voltage signal pin P11, a second upper low voltage signal pin P12, a third upper low voltage signal pin P13, a first upper high voltage signal pin P21, a fourth upper low voltage signal pin P14, a fifth upper low voltage signal pin P15 and a sixth upper low voltage signal pin P16 are arranged in sequence from left to right;

[0149] In the first pin arrangement area A1, P21 is arranged between P13 and P14;

[0150] In the second pin setting area A2, there are the first lower low voltage signal pin P31, the first lower high voltage signal pin P41, the second lower low voltage signal pin P32, the third lower low voltage signal pin P33, the fourth lower low voltage signal pin P34, the fifth lower low voltage signal pin P35, the second lower high voltage signal pin P42 and the sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0151] like Figure 4 As shown, in the first pin arrangement area A1, the orthographic projection of P21 on the substrate does not overlap with the orthographic projection of each low voltage signal pin on the substrate.

[0152] exist Figure 4 In at least one embodiment shown, P11 , P12 , and P13 are electrically connected, and P14 , P15 , and P16 are electrically connected.

[0153] exist Figure 4 In at least one embodiment shown, since the high voltage lines are designed in a mesh pattern in the display area, the VDD Drop is small and the VSS Drop is large. Therefore, in the first pin setting area A1, the first high voltage signal pin P21 is set in the middle position, and the other pins in the first pin setting area A1 are all high voltage signal pins.

[0154] exist Figure 4 In the figure, the line labeled VSS1 is a first low voltage line, the line labeled VSS2 is a second low voltage line, the line labeled VDD0 is a high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line;

[0155] VSS1 and VSS2 are arranged in the peripheral area of ​​the display panel, VSS1 is arranged on the left side of the display panel, and VSS2 is arranged on the right side of the display panel;

[0156] VSS1 is electrically connected to P11, P12, and P13, VSS2 is electrically connected to P14, P15, and P16, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21, and VDD0 is electrically connected to P41 and P42.

[0157] According to another specific embodiment, the display panel includes a base substrate, at least two high voltage signal pins and at least one low voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are arranged on the base substrate;

[0158] In the first pin arrangement area, the at least one low voltage signal pin is arranged between two adjacent high voltage signal pins;

[0159] In the first pin arrangement area, the orthographic projection of the high voltage signal pin on the substrate does not overlap with the orthographic projection of the low voltage signal pin on the substrate; the orthographic projection of the high voltage signal pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate;

[0160] The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

[0161] exist Figure 5 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0162] In the first pin arrangement area A1, a first upper high voltage signal pin P21, a second upper high voltage signal pin P22, a first upper low voltage signal pin P11, a second upper high voltage signal pin P12, a third upper low voltage signal pin P13, a third upper high voltage signal pin P23 and a fourth upper high voltage signal pin P24 are arranged;

[0163] The first upper high voltage signal pin P21, the second upper high voltage signal pin P22, the first upper low voltage signal pin P11, the second upper low voltage signal pin P12, the third upper low voltage signal pin P13, the third upper high voltage signal pin P23 and the fourth upper high voltage signal pin P24 are arranged in sequence from left to right;

[0164] In the first pin arrangement area A1, P11, P12 and P13 are arranged between P22 and P23;

[0165] In the first pin setting area A1,

[0166] The orthographic projection of P21 on the base substrate overlaps with the orthographic projection of the second low-voltage signal lead LY2 on the base substrate, and the orthographic projection of P22 on the base substrate overlaps with the orthographic projection of the second low-voltage signal lead LY2 on the base substrate;

[0167] The orthographic projection of P23 on the base substrate overlaps with the orthographic projection of the third low-voltage signal lead LY3 on the base substrate, and the orthographic projection of P24 on the base substrate overlaps with the orthographic projection of the third low-voltage signal lead LY3 on the base substrate;

[0168] exist Figure 5 In the embodiment, the second low voltage signal lead LY2 is a connection line between VSS1 and P11, and the second low voltage signal lead LY3 is a connection line between VSS2 and P24.

[0169] exist Figure 5 In the second pin setting area A2, there are arranged a first lower low voltage signal pin P31, a first lower high voltage signal pin P41, a second lower low voltage signal pin P32, a third lower low voltage signal pin P33, a fourth lower low voltage signal pin P34, a fifth lower low voltage signal pin P35, a second lower high voltage signal pin P42 and a sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0170] exist Figure 5 In at least one embodiment shown, in the first pin setting area A1, the pins on both sides are high voltage signal pins for overall access to high voltage signals, and the middle one is a low voltage signal pin for providing low voltage signals.

[0171] exist Figure 5 In the figure, the line labeled VSS1 is a first low voltage line, the line labeled VSS2 is a second low voltage line, the line labeled VDD0 is a high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line;

[0172] VSS1 and VSS2 are arranged in the peripheral area of ​​the display panel, VSS1 is arranged on the left side of the display panel, and VSS2 is arranged on the right side of the display panel;

[0173] VSS1 is electrically connected to P11, P12 and P13, VSS2 is electrically connected to P11, P12 and P13, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21, P22, P23 and P24, and VDD0 is electrically connected to P41 and P43.

[0174] In at least one embodiment of the present application, the display panel comprises a substrate, at least one initial voltage pin arranged in the first pin arrangement area, at least one initial voltage pin arranged in the second pin arrangement area, and an initial voltage line arranged in the display area;

[0175] The initial voltage pin and the initial voltage line are arranged on the substrate;

[0176] The initial voltage pin is used to provide an initial voltage for the initial voltage line;

[0177] In the first pin arrangement area, the orthogonal projection of the initial voltage pin on the substrate overlaps with the orthogonal projection of a low-voltage signal lead on the substrate; the low-voltage signal lead is a connecting line between the low-voltage line and the low-voltage signal pin;

[0178] In the second pin arrangement area, the orthogonal projection of each pin on the substrate does not overlap;

[0179] The initial voltage pin is arranged between the high-voltage signal pin and the low-voltage signal pin.

[0180] In specific implementation, at least one initial voltage pin can be arranged in the first pin arrangement area and the second pin arrangement area, respectively, to transmit an initial voltage signal.

[0181] Optionally, the display panel comprises a first initial voltage pin and a second initial voltage pin arranged in the first pin arrangement area, and a third initial voltage pin and a fourth initial voltage pin arranged in the second pin arrangement area;

[0182] The display panel further comprises a first first initial voltage line, a first second initial voltage line, a second first initial voltage line, and a second second initial voltage line arranged in the display area;

[0183] The first first initial voltage line is electrically connected to the first initial voltage pin arranged in the first pin arrangement area, the first second initial voltage line is electrically connected to the second initial voltage pin arranged in the first pin arrangement area, the second first initial voltage line is electrically connected to the first initial voltage pin arranged in the second pin arrangement area, and the second second initial voltage line is electrically connected to the second initial pin arranged in the second pin arrangement area;

[0184] The first initial voltage pin is used to provide a first initial voltage signal to the first first initial voltage line, and the third initial voltage pin is used to provide a first initial voltage signal to the second first initial voltage line;

[0185] The second initial voltage pin is configured to provide a second initial voltage signal to a first second initial voltage line, and the fourth initial voltage pin is configured to provide a second initial voltage signal to a second second initial voltage line.

[0186] In Figure 6 , A1 is a first pin setting area, and A2 is a second pin setting area;

[0187] In the first pin setting area A1, a first upper high voltage signal pin P21, a first initial voltage pin I11, a first upper low voltage signal pin P11, a second upper low voltage signal pin P12, a third upper low voltage signal pin P13, a second initial voltage pin I12, and a second upper high voltage signal pin P22 are arranged.

[0188] The first upper low voltage signal pin P11, the first initial voltage pin I11, the first upper high voltage signal pin P21, the second upper high voltage signal pin P22, the third upper high voltage signal pin P23, the second initial voltage pin I12, and the second upper high voltage signal pin P22 are arranged from left to right.

[0189] The first initial voltage pin I11 is configured to provide a first initial voltage signal, and the second initial voltage pin I12 is configured to provide a second initial voltage signal.

[0190] In the first pin setting area A1, the orthographic projection of I11 on the substrate substrate overlaps the orthographic projection of the fourth low voltage signal lead LY4 on the substrate substrate; the fourth low voltage signal lead LY4 is a connection line between VSS1 and P11.

[0191] The orthographic projection of I12 on the substrate substrate overlaps the orthographic projection of the fifth low voltage signal lead LY5 on the substrate substrate; the fifth low voltage signal lead LY5 is a connection line between VSS2 and P13. As Figure 6 shown, the second pin setting area A2 is provided with a first lower low voltage signal pin P31, a first lower high voltage signal pin P41, a second lower low voltage signal pin P32, a third lower low voltage signal pin P33, a fourth lower low voltage signal pin P34, a fifth lower low voltage signal pin P35, a second lower high voltage signal pin P42, and a sixth lower low voltage signal pin P36 arranged from left to right.

[0192] In Figure 6 , VSS1 is a first low voltage line, VSS2 is a second low voltage line, VDD0 is a high voltage line arranged in a display area, and the high voltage line VDD0 is a mesh-shaped voltage line.

[0193] VSS1 and VSS2 are arranged in the peripheral region of the display panel, VSS1 is arranged at the left side of the display panel, and VSS2 is arranged at the right side of the display panel.

[0194] In Figure 6 , the first first initial voltage line is marked as LI1, and the first second initial voltage line is marked as LI2, LI1 is electrically connected with I11, and LI2 is electrically connected with I12.

[0195] In Figure 6 , in at least one embodiment shown, the first initial voltage pin I11 is used to provide a first initial voltage signal, the second initial voltage pin I12 is used to provide a second initial voltage signal, and in the display region of the display panel, an initial voltage line is arranged, each initial voltage pin provides an initial voltage signal to the initial voltage line, and the initial voltage line provides the initial voltage signal to the pixel circuit.

[0196] In Figure 6 , in at least one embodiment shown, VSS1 is electrically connected with P11, P12 and P13, VSS2 is electrically connected with P11, P12 and P13, VSS1 is electrically connected with P31, VSS2 is electrically connected with P36, VDD0 is electrically connected with P21 and P22, and VDD0 is electrically connected with P41 and P42.

[0197] In the specific implementation, since the initial voltage accessed by the pixel circuit also affects the display quality, the stability of the initial voltage is also important, therefore, at least one embodiment of the present application arranges the first initial voltage pin I11 and the second initial voltage pin I12 in the first pin arrangement region, which is beneficial to the stability of the initial voltage signal and improves the display quality.

[0198] In Figure 6 , in at least one embodiment shown, the first initial voltage signal and the second initial voltage signal can be different initial voltage signals, or the first initial voltage signal and the second initial voltage signal can be the same initial voltage signal.

[0199] As Figure 7 shown, in Figure 6 , on the basis of at least one embodiment shown, in the second pin arrangement region A2, a third initial voltage pin I21 and a fourth initial voltage pin I22 are further arranged;

[0200] The third initial voltage pin I21 is used to provide a first initial voltage signal, and the fourth initial voltage pin I22 is used to provide a second initial voltage signal.

[0201] The third initial voltage pin I21 can be arranged between the first lower high voltage signal pin P41 and the second lower low voltage signal pin P32.

[0202] The fourth initial voltage pin I22 may be provided at the fifth lower low voltage signal pin P35 and the second lower high voltage signal pin P42.

[0203] exist Figure 7 , the line labeled LI3 is the second first initial voltage line, the line labeled LI4 is the second second initial voltage line, LI3 is electrically connected to I21, and LI4 is electrically connected to I22.

[0204] like Figure 7 As shown, in the second pin setting area A2, the orthographic projections of the pins on the substrate do not overlap with each other. Figure 7 In at least one embodiment shown, VSS1 is electrically connected to P11, P12, and P13, VSS2 is electrically connected to P11, P12, and P13, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21 and P22, and VDD0 is electrically connected to P41 and P42.

[0205] In at least one embodiment of the present invention, initial voltage pins may be provided in both the first pin arrangement area A1 and the second pin arrangement area A2 to further reduce the IR Drop of the initial voltage signal.

[0206] In specific implementation, in the first pin setting area and the second pin setting area, the setting position of each initial voltage pin can be set according to the situation and is not limited to Figure 7 The location shown in .

[0207] In at least one embodiment of the present invention, the display panel includes a base substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in a first pin arrangement area;

[0208] The display panel further includes at least one high-level signal pin and at least one low-level signal pin arranged in the second pin arrangement area; the high-level signal pin and the low-level signal pin are both arranged on the base substrate;

[0209] The display panel further includes a high-level signal line and a low-level signal line arranged in the peripheral area;

[0210] The high-level signal line is electrically connected to the high-level signal pin, the high-level signal pin is used to provide a high-level signal to the high-level signal line, and the low-level signal pin is used to provide a low-level signal to the low-level signal line;

[0211] The high-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin, and the low-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin;

[0212] In the first pin arrangement region and the second pin arrangement region, orthographic projections of the pins on the base substrate do not overlap.

[0213] In a specific implementation, since the stability of the high-level signal Vgh and the stability of the low-level signal Vgl will affect the stability of the waveform of the driving signal output by the driving circuit, at least one high-level signal pin and at least one low-level signal pin are set in the first pin setting area to facilitate improving the output fluctuation margin of the driving circuit and improving the overall display quality.

[0214] In a specific implementation, at least one high-level signal pin and at least one low-level signal pin may also be set in the second pin setting area to transmit the high-level signal Vgh and the low-level signal Vgl respectively, thereby further improving the stability of the high-level signal Vgh and the stability of the low-level signal Vgl.

[0215] In at least one embodiment of the present invention, the display panel may include a high-level signal pin and a low-level signal pin arranged in a first pin setting area, and include a high-level signal pin and a low-level signal pin arranged in a second pin setting area, so as to provide a high-level signal Vgh through the high-level signal pin and provide a low-level signal Vgl through the low-level signal pin.

[0216] exist Figure 8 Among them, the area labeled A1 is the first pin setting area, and the area labeled A2 is the second pin setting area;

[0217] In the first pin arrangement area A1, a first upper low voltage signal pin P11, a first upper high level signal pin H11, a first upper high voltage signal pin P21, a first upper low level signal pin L11 and a second upper low voltage signal pin P12 are arranged;

[0218] The first upper low voltage signal pin P11, the first upper high level signal pin H11, the first upper high voltage signal pin P21, the first upper low level signal pin L11 and the second upper low voltage signal pin P12 are arranged in sequence from left to right;

[0219] At least one embodiment of the present invention provides a first upper high-level signal pin H11 and a first upper low-level signal pin L11 in the first pin arrangement area, which is beneficial to the stability of high-level signals and low-level signals and improves display quality;

[0220] In the second pin setting area A2, there are the first lower low voltage signal pin P31, the first lower high voltage signal pin P41, the second lower low voltage signal pin P32, the third lower low voltage signal pin P33, the fourth lower low voltage signal pin P34, the fifth lower low voltage signal pin P35, the second lower high voltage signal pin P42 and the sixth lower low voltage signal pin P36, which are arranged in sequence from left to right.

[0221] exist Figure 8 In at least one embodiment shown, the orthographic projection of P11 on the substrate, the orthographic projection of H11 on the substrate, the orthographic projection of P21 on the substrate, the orthographic projection of L11 on the substrate, and the orthographic projection of P12 on the substrate do not overlap.

[0222] exist Figure 8 In the figure, the line labeled VSS1 is a first low voltage line, the line labeled VSS2 is a second low voltage line, the line labeled VDD0 is a high voltage line set in the display area, and the high voltage line VDD0 is a grid-shaped voltage line;

[0223] The line labeled VH1 is a first high-level signal line, the line labeled VH2 is a second high-level signal line, the line labeled VL1 is a first low-level signal line, and the line labeled VL2 is a second low-level signal line;

[0224] VH1 and VL1 are set on the left side of the display area, and VH2 and VL2 are set on the right side of the display area;

[0225] VH1 is electrically connected to the first upper high-level signal pin H11, and VGL2 is electrically connected to the first upper low-level signal pin L11;

[0226] VH1 and VH2 are used to transmit high-level signals, and VL1 and VL2 are used to transmit low-level signals;

[0227] VSS1 , VSS2 , VH1 , VH2 , VL1 , and VL2 are all disposed in the peripheral area of ​​the display panel.

[0228] exist Figure 8 In at least one embodiment shown, VSS1 is electrically connected to P11, VSS2 is electrically connected to P12, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21, and VDD0 is electrically connected to P41 and P42.

[0229] like Figure 9 As shown, in Figure 8 On the basis of at least one embodiment shown, a first lower high-level signal pin H21 and a first lower low-level signal pin L21 may be further provided in the second pin arrangement area A2;

[0230] The first lower high level signal pin H21 may be disposed between the first lower high voltage signal pin P41 and the second lower low voltage signal pin P32;

[0231] The first lower low level signal pin L21 may be disposed between the fifth lower low voltage signal pin P35 and the second lower high voltage signal pin P42 .

[0232] like Figure 9 As shown, VH1 can be electrically connected to H21, and VL2 can be electrically connected to L21.

[0233] like Figure 9 As shown, the orthographic projection of P31 on the substrate, the orthographic projection of P41 on the substrate, the orthographic projection of H21 on the substrate, the orthographic projection of P32 on the substrate, the orthographic projection of P33 on the substrate, the orthographic projection of P34 on the substrate, the orthographic projection of P35 on the substrate, the orthographic projection of L21 on the substrate, the orthographic projection of P42 on the substrate and the orthographic projection of P36 on the substrate do not overlap.

[0234] like Figure 9 As shown, VSS1 is electrically connected to P11, VSS2 is electrically connected to P12, VSS1 is electrically connected to P31, VSS2 is electrically connected to P36, VDD0 is electrically connected to P21, and VDD0 is electrically connected to P41 and P42.

[0235] In at least one embodiment of the present invention, high-level signal pins and low-level signal pins may be provided in both the first pin arrangement area A1 and the second pin arrangement area A2 to further reduce IR Drop of high-level signals and IR Drop of low-level signals.

[0236] In specific implementation, in the first pin setting area and the second pin setting area, the setting position of each high level signal pin and the setting position of each low level signal pin can be set according to the situation and are not limited to Figure 9 The location shown in .

[0237] Optionally, the display panel includes a base substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in a first pin arrangement area;

[0238] The display panel further includes at least one high-level signal pin and at least one low-level signal pin arranged in the second pin arrangement area; the high-level signal pin and the low-level signal pin are both arranged on the base substrate;

[0239] The display panel further includes a high-level signal line and a low-level signal line arranged in the peripheral area;

[0240] The high-level signal line is electrically connected with the high-level signal pin, the high-level signal pin is used for providing a high-level signal for the high-level signal line, and the low-level signal pin is used for providing a low-level signal for the low-level signal line.

[0241] In the first pin arrangement region, the high-level signal pin is arranged between the first initial voltage pin and the high-voltage signal pin, and the low-level signal pin is arranged between the high-voltage signal pin and the second initial voltage pin.

[0242] In at least one embodiment of the present application, in the first pin arrangement region, the orthographic projection of each pin on the substrate substrate can not overlap.

[0243] As shown in Figure 10 As shown in Figure 8 On the basis of at least one embodiment of the display panel shown in

[0244] The first initial voltage pin I11 is arranged between the first upper low-voltage signal pin P11 and the first upper high-level signal pin H11, and the second initial voltage pin I12 is arranged between the first upper low-level signal pin L11 and the second upper low-voltage signal pin P12.

[0245] In Figure 10 LI1 is the first first initial voltage line, and LI2 is the first second initial voltage line, LI1 is electrically connected with I11, and LI2 is electrically connected with I12.

[0246] As shown in Figure 10 The orthographic projection of P11 on the substrate substrate, the orthographic projection of I11 on the substrate substrate, the orthographic projection of H11 on the substrate substrate, the orthographic projection of P21 on the substrate substrate, the orthographic projection of L11 on the substrate substrate, the orthographic projection of I12 on the substrate substrate and the orthographic projection of P12 on the substrate substrate do not overlap.

[0247] In Figure 10 VSS1 is electrically connected with P11, VSS2 is electrically connected with P12, VSS1 is electrically connected with P31, VSS2 is electrically connected with P36, and VDD0 is electrically connected with P21, P41 and P42.

[0248] In at least one embodiment of the present application, the display panel comprises a substrate substrate and a plurality of conductive layers stacked on the substrate substrate;

[0249] Each pin included in the display panel is formed in the conductive layer;

[0250] When the orthographic projections of two pins included in the display panel on the base substrate do not overlap, the two pins may be arranged in the same layer;

[0251] When the orthographic projections of two pins included in the display panel overlap on the base substrate, the two pins are arranged in different layers to prevent the two pins from being short-circuited with each other.

[0252] Figure 11 is a circuit diagram of the related pixel circuit.

[0253] like Figure 11 As shown, the relevant pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst and an organic light emitting diode EL;

[0254] exist Figure 11 In the figure, VDD is a high voltage signal, VSS is a low voltage signal, Vinit1 is a first initial voltage, Vinit2 is a second initial voltage, Gate is a gate line, data is a data line, EM is a light emitting control line, Reset1 is a first reset control line, and Reset2 is a second reset control line.

[0255] The display panel according to at least one embodiment of the present invention further includes a display substrate, a first flexible circuit board and a second flexible circuit board;

[0256] Each pin in the first pin arrangement area and each pin in the second pin arrangement area are arranged on the display substrate;

[0257] The first flexible circuit board is arranged on a side of each pin in the first pin arrangement area away from the display substrate, and the first flexible circuit board is used to provide corresponding signals to each pin arranged in the first pin arrangement area;

[0258] The second flexible circuit board is arranged on a side of each pin in the second pin arrangement area away from the display substrate, and is used to provide corresponding signals to each pin arranged in the second pin arrangement area.

[0259] In a specific implementation, the display panel may include a display substrate, a first flexible circuit board and a second flexible circuit board, and the above pins are all set on the display substrate, the first flexible circuit board is set in a first pin setting area, and the second flexible circuit board is set in a second pin setting area. The first flexible circuit board provides corresponding signals for each pin set in the first pin setting area, and the second flexible circuit board is used to provide corresponding signals for each pin set in the second pin setting area.

[0260] In at least one embodiment of the present invention, the display substrate is a flexible substrate;

[0261] The pins arranged in the first pin arrangement area and the first flexible circuit board can be bent to the non-display surface of the display panel to reduce the upper frame;

[0262] The pins arranged in the second pin arrangement area and the second flexible circuit board can be bent to the non-display surface of the display panel to reduce the bottom frame.

[0263] At least one embodiment of the present invention can reduce the upper and lower borders to achieve an ultra-narrow border.

[0264] Figure 12 It is a schematic diagram of the display panel after the upper and lower frames are bent. Figure 12 In the figure, the one labeled P0 is the display panel, the one labeled P1 is the upper frame, and the one labeled P2 is the lower frame.

[0265] The display device according to the embodiment of the present invention includes the above-mentioned display panel.

[0266] In at least one embodiment of the present invention, the display device may be an AMOLED display device, but is not limited thereto.

[0267] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0268] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A display panel comprising a display area and a peripheral area; characterized in that: The peripheral area includes a first pin setting area and a second pin setting area that are oppositely arranged; the display panel includes a high voltage line arranged in the display area and a low voltage line at least partially arranged in the peripheral area; The display panel includes at least one high voltage signal pin and at least one low voltage signal pin arranged in a first pin arrangement area, and at least one high voltage signal pin and at least one low voltage signal pin arranged in a second pin arrangement area; The high voltage signal pin is used to transmit a high voltage signal to the high voltage line, and the low voltage signal pin is used to transmit a low voltage signal to the low voltage line; At least some of the high voltage signal pins and at least some of the low voltage signal pins are alternately arranged; The pins included in the display panel are arranged in sequence along a first direction; the first pin setting area and the second pin setting area are arranged along a second direction; The first direction and the second direction intersect; The display panel includes a base substrate and a plurality of conductive layers stacked on the base substrate; each pin included in the display panel is formed on the conductive layer; when the orthographic projections of two pins included in the display panel on the base substrate do not overlap, the two pins are arranged in the same layer; when the orthographic projections of two pins included in the display panel on the base substrate overlap, the two pins are arranged in different layers; or, The display panel also includes a display substrate, a first flexible circuit board and a second flexible circuit board; each pin in the first pin setting area and each pin in the second pin setting area are set on the display substrate; the first flexible circuit board is set on the side of each pin in the first pin setting area away from the display substrate, and the first flexible circuit board is used to provide corresponding signals for each pin set in the first pin setting area; the second flexible circuit board is set on the side of each pin in the second pin setting area away from the display substrate, and the second flexible circuit board is used to provide corresponding signals for each pin set in the second pin setting area.

2. The display panel according to claim 1, wherein The display panel includes a base substrate, at least two high voltage signal pins and at least two low voltage signal pins arranged in a first pin arrangement area; the high voltage signal pins and the low voltage signal pins are both arranged on the base substrate; In the first pin arrangement area, the high voltage signal pins and the low voltage signal pins are alternately arranged; In the first pin arrangement area, an orthographic projection of at least one of the high-voltage signal pins on the base substrate overlaps with an orthographic projection of at least one of the low-voltage signal pins on the base substrate.

3. The display panel according to claim 1, wherein The display panel includes a base substrate, at least two low voltage signal pins and at least one high voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are both arranged on the base substrate; In the first pin arrangement area, the at least one high voltage signal pin is arranged between two adjacent low voltage signal pins; In the first pin arrangement area, an orthographic projection of the high voltage signal pin on the base substrate does not overlap with an orthographic projection of the low voltage signal pin on the base substrate.

4. The display panel according to claim 1, wherein: The first pin arrangement area includes a first sub-area and a second sub-area adjacently arranged along a first direction; The display panel includes a base substrate, a first pin block arranged in the first sub-region, and a second pin block arranged in the second sub-region; The first pin block includes at least two low-voltage signal pins electrically connected to each other, and the second pin block includes at least two high-voltage signal pins electrically connected to each other; In the first cathode setting area, the orthographic projection of the low voltage signal pin on the substrate does not overlap with the orthographic projection of the high voltage signal pin on the substrate; the orthographic projection of the high voltage signal pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate; The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

5. The display panel according to claim 1, wherein The display panel includes a base substrate, at least two high voltage signal pins and at least one low voltage signal pin arranged in a first pin arrangement area; the high voltage signal pin and the low voltage signal pin are arranged on the base substrate; In the first pin arrangement area, the at least one low voltage signal pin is arranged between two adjacent high voltage signal pins; In the first pin arrangement area, the orthographic projection of the high voltage signal pin on the substrate does not overlap with the orthographic projection of the low voltage signal pin on the substrate; the orthographic projection of the high voltage signal pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate; The low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin.

6. The display panel according to claim 1, wherein: The display panel includes a base substrate, at least one initial voltage pin arranged in a first pin arrangement area, at least one initial voltage pin arranged in a second pin arrangement area, and an initial voltage line arranged in a display area; The initial voltage pin and the initial voltage line are both provided on the base substrate; The initial voltage pin is used to provide an initial voltage for the initial voltage line; In the first pin arrangement area, the orthographic projection of the initial voltage pin on the substrate overlaps with the orthographic projection of the low voltage signal lead on the substrate; the low voltage signal lead is a connection line between the low voltage line and the low voltage signal pin; In the second pin arrangement area, the orthographic projections of the pins on the substrate do not overlap; The initial voltage pin is arranged between the high voltage signal pin and the low voltage signal pin.

7. The display panel according to claim 6, wherein: The display panel includes a first initial voltage pin and a second initial voltage pin arranged in the first pin arrangement area, and a third initial voltage pin and a fourth initial voltage pin arranged in the second pin arrangement area; The display panel further includes a first first initial voltage line, a first second initial voltage line, a second first initial voltage line and a second second initial voltage line arranged in the display area; The first first initial voltage line is electrically connected to the first initial voltage pin provided in the first pin setting area, the first second initial voltage line is electrically connected to the second initial voltage pin provided in the first pin setting area, the second first initial voltage line is electrically connected to the first initial voltage pin provided in the second pin setting area, and the second second initial voltage line is electrically connected to the second initial pin provided in the second pin setting area; The first initial voltage pin is used to provide a first initial voltage signal to a first first initial voltage line, and the third initial voltage pin is used to provide a first initial voltage signal to a second first initial voltage line; The second initial voltage pin is used to provide a second initial voltage to a first second initial voltage line, and the fourth initial voltage pin is used to provide a second initial voltage signal to a second second initial voltage line.

8. The display panel according to claim 1, wherein: The display panel includes a base substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in a first pin arrangement area; the display panel also includes at least one high-level signal pin and at least one low-level signal pin arranged in a second pin arrangement area; the high-level signal pin and the low-level signal pin are both arranged on the base substrate; The display panel further includes a high-level signal line and a low-level signal line arranged in the peripheral area; The high-level signal line is electrically connected to the high-level signal pin, the high-level signal pin is used to provide a high-level signal to the high-level signal line, and the low-level signal pin is used to provide a low-level signal to the low-level signal line; The high-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin, and the low-level signal pin is arranged between the high-voltage signal pin and the low-voltage signal pin; In the first pin arrangement region and the second pin arrangement region, the orthographic projections of the pins on the base substrate do not overlap.

9. The display panel according to claim 7, wherein: The display panel includes a base substrate, and at least one high-level signal pin and at least one low-level signal pin arranged in a first pin arrangement area; The display panel further includes at least one high-level signal pin and at least one low-level signal pin arranged in the second pin arrangement area; the high-level signal pin and the low-level signal pin are both arranged on the base substrate; The display panel further includes a high-level signal line and a low-level signal line arranged in the peripheral area; The high-level signal line is electrically connected to the high-level signal pin, the high-level signal pin is used to provide a high-level signal to the high-level signal line, and the low-level signal pin is used to provide a low-level signal to the low-level signal line; In the first pin setting area, the high level signal pin is set between the first initial voltage pin and the high voltage signal pin, and the low level signal pin is set between the high voltage signal pin and the second initial voltage pin.

10. The display panel according to claim 9, wherein: In the first pin arrangement area, the orthographic projections of the pins on the base substrate do not overlap.

11. The display panel according to claim 1, wherein: The display panel further includes a display substrate, a first flexible circuit board and a second flexible circuit board; the display substrate is a flexible substrate; The pins arranged in the first pin arrangement area and the first flexible circuit board can be bent to the non-display surface of the display panel; The pins arranged in the second pin arrangement area and the second flexible circuit board can be bent to the non-display surface of the display panel.

12. A display device, characterized in that: A display panel comprising the display panel according to any one of claims 1 to 11.

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