Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a substrate substrate, a plurality of pixel driving circuits, a first planarization layer, a plurality of light emitting devices, a first power signal line and a data signal line, the substrate substrate comprising a first display area and a second display area, the first planarization layer comprising a device connection via electrically connecting at least one of the plurality of pixel driving circuits and at least one of the plurality of light emitting devices, a power supply via electrically connecting at least one of the plurality of pixel driving circuits and the first power signal line, and a data via electrically connecting at least one of the plurality of pixel driving circuits and the data signal line DT, the device connection via, the power supply via and the data via being arranged along a first direction. The display substrate has better reliability.

Description

[0001] This application claims priority to PCT International Application No. PCT / CN2021 / 118279, filed on September 14, 2021, and PCT International Application No. PCT / CN2022 / 082809, filed on March 24, 2022, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] This disclosure provides at least one embodiment of a display substrate, which includes a substrate, a plurality of pixel driving circuits, a first planarization layer, a plurality of light-emitting devices, a first power signal line, and a data signal line. The substrate includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the transmittance of the second display area is greater than that of the first display area; the plurality of pixel driving circuits are located on the substrate and in the first display area; the first planarization layer is located on the side of the plurality of pixel driving circuits away from the substrate; the plurality of light-emitting devices are located on the side of the first planarization layer away from the substrate; the first power signal line... The power signal line is located on the side of the first planarization layer away from the substrate and in the first display area; the data signal line is located on the side of the first planarization layer away from the substrate and in the first display area; wherein, the first planarization layer includes a device connection via electrically connecting at least one of the plurality of pixel driving circuits to at least one of the plurality of light-emitting devices, a power via electrically connecting at least one of the plurality of pixel driving circuits to the first power signal line, and a data via electrically connecting at least one of the plurality of pixel driving circuits to the data signal line, the device connection via, the power via, and the data via being arranged along a first direction.

[0005] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a first initialization signal line configured to provide a first initialization signal to at least one of a plurality of pixel driving circuits; wherein the shortest distance between the device connection via, the power supply via, and the data via and the first initialization signal line is substantially equal.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit, the plurality of light-emitting devices include a first light-emitting device located in the first display area and a second light-emitting device located in the second display area, the device connection vias include a first via and a second via, the first light-emitting device is electrically connected to the first pixel driving circuit through the first via, the second light-emitting device is electrically connected to the second pixel driving circuit through a first connection trace located in the first display area and the second display area, and in the first display area, the first connection trace is electrically connected to the second pixel driving circuit through the second via.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of pixel driving circuits include a plurality of pixel circuit groups extending along a first direction and arranged along a second direction. At least one of the plurality of pixel circuit groups includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits. The plurality of first vias, a plurality of second vias, a plurality of power vias, and a plurality of data vias used by the plurality of first pixel driving circuits and the plurality of second pixel driving circuits are arranged along the first direction, and the first direction and the second direction intersect.

[0008] For example, in the display substrate provided in at least one embodiment of this disclosure, the multiple first vias, multiple second vias, multiple power vias, and multiple data vias used by the multiple first pixel driving circuits and multiple second pixel driving circuits in the at least one set of pixel circuit groups are substantially the same as the shortest distance to the first initialization signal line.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of first vias, plurality of second vias, plurality of power vias, and plurality of data vias used by the plurality of first pixel driving circuits and plurality of second pixel driving circuits in the at least one set of pixel circuit groups are located on the same straight line, and the same straight line extends along the first direction.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the first connection trace is located on at least one side of the same straight line in a direction parallel to the substrate.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the extension direction of the first connection trace from the first display area to the second display area is parallel to the first direction.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the first pixel driving circuit and the second pixel driving circuit respectively include a first transistor as a reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor. The gate electrode of the first transistor is connected to a reset signal line, the first electrode of the first transistor is connected to a first initialization signal line, the second electrode of the first transistor is connected to the first electrode of the second transistor and the gate electrode of the third transistor, the gate electrode of the second transistor is connected to a scan signal line, and the second electrode of the second transistor is connected to the second electrode of the third transistor. The gate electrodes of the first transistor, the second transistor, the third transistor, the scan signal line, and the reset signal line are located on a first conductive layer on the substrate. The first initialization signal line is located on a second conductive layer, and the second conductive layer is located on the side of the first conductive layer away from the substrate.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the first pixel driving circuit and the second pixel driving circuit further include a storage capacitor, a fourth transistor as a data writing transistor, and a fifth transistor as a light-emitting control transistor, respectively. The gate electrode of the fourth transistor is connected to a scan signal line, the first electrode of the fourth transistor is connected to a data signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor, the gate electrode of the fifth transistor is connected to a light-emitting control line, the first electrode of the fifth transistor is connected to the second plate of the storage capacitor, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor; the light-emitting control line is located in the first conductive layer.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the first pixel driving circuit and the second pixel driving circuit further include a sixth transistor as a light-emitting control transistor and a seventh transistor as a reset transistor, respectively. The gate electrode of the sixth transistor is connected to the light-emitting control line, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, the first light-emitting device or the second light-emitting device is connected to the second electrode of the sixth transistor, the gate electrode of the seventh transistor is connected to the reset signal line, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; the second initialization signal line is located in the second conductive layer.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the second initialization signal line, the reset signal line, the first initialization signal line, and the scan signal line for the same first pixel driving circuit or second pixel driving circuit are arranged sequentially in a first direction parallel to the substrate.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the second transistor includes an active layer and two gate electrodes. The active layer is a semiconductor material layer located between the first metal layer and the substrate. The active layer includes a first portion, the orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the two gate electrodes on the substrate. The second conductive layer includes a shielding pattern, the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the shielding pattern on the substrate.

[0017] For example, in at least one embodiment of the display substrate provided in this disclosure, the blocking pattern is integrally connected with the first initialization signal line.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the semiconductor material layer includes a semiconductor pattern connecting the active layer of the second transistor and the active layer of the first transistor, wherein the orthographic projection of the semiconductor pattern on the substrate overlaps with the orthographic projection of the shading pattern on the substrate.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the first and second electrodes of the first transistor, the first and second electrodes of the second transistor, and the first and second electrodes of the third transistor are located in a third conductive layer, and the third conductive layer is located on the side of the second conductive layer away from the substrate.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the first power signal line is located in a fourth conductive layer, and the fourth conductive layer is located on the side of the third conductive layer away from the substrate.

[0021] For example, in at least one embodiment of the display substrate provided in this disclosure, the data signal line is located in the fourth conductive layer.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the third conductive layer further includes a connection portion located between the second electrode of the first transistor and the gate electrode of the third transistor, and the first power signal line further includes a protrusion, wherein the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the protrusion on the substrate.

[0023] For example, in at least one embodiment of the display substrate provided in this disclosure, the orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the protrusion on the substrate.

[0024] For example, in the display substrate provided in at least one embodiment of this disclosure, the spacing between the patterns of the third conductive layer of the first pixel driving circuit and the second pixel driving circuit located in adjacent rows is 7.0 micrometers to 10.0 micrometers.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, among a plurality of first pixel driving circuits and a plurality of second pixel driving circuits located in the same row, two first pixel driving circuits are disposed between each pair of adjacent second pixel driving circuits.

[0026] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 This is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0029] Figure 2 for Figure 1 A schematic diagram of the cross-section of the display substrate along the BB line;

[0030] Figure 3 for Figure 1 A schematic diagram of the cross-section of the display substrate along line AA;

[0031] Figure 4 A partial planar schematic diagram of a first display area and a second display area in a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 5 A plan view of a portion of the functional layers of a display substrate provided in at least one embodiment of this disclosure;

[0033] Figure 6 This is a plan view of a portion of a functional layer of another display substrate provided in at least one embodiment of the present disclosure;

[0034] Figure 7 A circuit diagram of a first pixel driving circuit for a display substrate provided in at least one embodiment of this disclosure;

[0035] Figure 8A circuit diagram of a second pixel driving circuit for a display substrate provided in at least one embodiment of this disclosure;

[0036] Figures 9-15 A plan view of each functional layer of a display substrate provided in at least one embodiment of this disclosure, and a plan view showing the sequential overlapping of each functional layer; and

[0037] Figures 16A-16D A plan view of a portion of the functional layers of another display substrate provided for at least one embodiment of this disclosure, and a plan view showing the sequential overlapping of the portion of the functional layers. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] With the development of display technology, full-screen or narrow-bezel products, with their large screen-to-body ratio and ultra-narrow bezels, have gradually become the development trend of display products. For products such as smart terminals, it is usually necessary to set up hardware such as front-facing cameras, fingerprint sensors, or light sensors. In order to improve the screen-to-body ratio, full-screen or narrow-bezel products usually adopt under-display camera technology (Full display with camera, or FDC) or under-display fingerprint technology, placing the camera and other sensors in the under-display camera area (Under Display Camera, or UDC) of the display substrate. The under-display camera area not only has a certain transmittance, but also has display function, thereby realizing full display in the camera area (Full Display in Camera, or FDC).

[0041] To improve the light transmittance of the under-display camera area, the display sub-pixels in this area typically only contain light-emitting devices. The pixel driving circuits that drive these devices can be located in other display areas to avoid reducing the light transmittance of the under-display camera area. However, in this approach, the light-emitting devices need to be connected to the pixel driving circuits in other display areas via long traces. These long traces often have high resistance, causing voltage drops. Furthermore, these long traces may form parasitic capacitances with other circuit patterns on the display substrate, affecting the electrical signal transmission. On the other hand, at high refresh rates, the charging time of the display sub-pixels in the under-display camera area is often insufficient, thus affecting the brightness of the light-emitting devices. Additionally, for electrical connections between circuits, the display substrate typically has many vias. Circuits or traces above these vias are prone to forming depressions at the via locations, leading to open circuits and other defects, thus reducing the reliability of the display substrate.

[0042] At least one embodiment of this disclosure provides a display substrate, which includes a substrate, a plurality of pixel driving circuits, a first planarization layer, a plurality of light-emitting devices, a first power signal line, and a data signal line. The substrate includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the transmittance of the second display area is greater than that of the first display area. The plurality of pixel driving circuits are located on the substrate and in the first display area. The first planarization layer is located on the side of the plurality of pixel driving circuits away from the substrate. The plurality of light-emitting devices are located on the side of the first planarization layer away from the substrate. The first power signal line is located on the side of the first planarization layer away from the substrate and in the first display area. The data signal line is located on the side of the first planarization layer away from the substrate and in the first display area. The first planarization layer includes a device connection via electrically connecting at least one of the plurality of pixel driving circuits to at least one of the plurality of light-emitting devices, a power via electrically connecting at least one of the plurality of pixel driving circuits to the first power signal line, and a data via electrically connecting at least one of the plurality of pixel driving circuits to the data signal line. The device connection via, the power via, and the data via are arranged along a first direction.

[0043] In the display substrate provided in the embodiments of this disclosure, a variety of traces and circuit patterns are provided on the first planarization layer. By arranging the multiple vias of the first planarization layer along the first direction, the arrangement space of the multiple vias can be made more compact and regular, thereby facilitating the various traces and circuit patterns provided on the first planarization layer to avoid these vias, so as to avoid the collapse of these traces or circuit patterns at the position of the vias, causing short circuits and other defects, thereby improving the stability of these traces and circuit patterns, and thus improving the reliability of the display substrate.

[0044] The following detailed description of the display substrate provided in this disclosure will be achieved through a specific embodiment.

[0045] This disclosure provides a display substrate in at least one embodiment. Figure 1 A planar schematic diagram of the display substrate is shown. Figure 2 It shows Figure 1 A schematic cross-sectional view of the display substrate along line BB. Figure 3 It shows Figure 1 A schematic cross-sectional view of the display substrate along line AA. Figure 4 It shows Figure 1 A partial planar schematic diagram of the display substrate in the first and second display areas. (See attached diagram.) Figures 1-4As shown, the display substrate includes a substrate BS, multiple pixel driving circuits DR1 / DR2, a first planarization layer PLN1, multiple light-emitting devices EM1 / EM2, a first power signal line VDD, and a data signal line DT. The substrate BS includes a first display area 10 and a second display area 20, with the first display area 10 at least partially surrounding the second display area 20. Figure 1 The diagram shows the first display area 10 completely surrounding the second display area 20. In other embodiments, the first display area 10 may partially surround the second display area 20.

[0046] The transmittance of the second display area 20 is greater than that of the first display area 10. For example, the second display area 20 can be a light-transmitting display area of ​​the display substrate, which can transmit some light signals.

[0047] For example, multiple pixel driving circuits DR1 / DR2 are located on the substrate BS and in the first display area 10; the first planarization layer PLN1 is located on the side of the multiple pixel driving circuits DR1 / DR2 away from the substrate BS; multiple light-emitting devices EM1 / EM2 are located on the side of the first planarization layer PLN1 away from the substrate BS; the first power signal line VDD is located on the side of the first planarization layer PLN1 away from the substrate BS and in the first display area 10; and the data signal line DT is located on the side of the first planarization layer PLN1 away from the substrate 110 and in the first display area 10.

[0048] refer to Figure 6 The first planarization layer PLN1 includes at least one (e.g., each) of a plurality of pixel driving circuits DR1 / DR2 and at least one of a plurality of light-emitting devices EM1 / EM2.

[0049] For example, each of the following: electrically connected device connection vias V1 / V2; power via V3 electrically connecting at least one (e.g., each) of the plurality of pixel driving circuits to the first power signal line VDD; and data via V4 electrically connecting at least one (e.g., each) of the plurality of pixel driving circuits to the data signal line DT. The device connection vias V1 / V2, power via V3, and data via V4 are along a first direction (e.g., ...). Figure 6 Arranged horizontally in the middle.

[0050] For example, refer to Figure 12BThe display substrate further includes a first initialization signal line Vin1, which is configured to provide a first initialization signal to at least one of a plurality of pixel driving circuits DR1 / DR2. The shortest distance between the device connection vias V1 / V2, power vias V3, and data vias V4 and the first initialization signal line Vin1 is substantially equal; that is, the device connection vias V1 / V2, power vias V3, and data vias V4 are located at positions substantially the same distance from the first initialization signal line Vin1. For example, the first initialization signal line Vin1 extends along the aforementioned first direction.

[0051] As a result, the arrangement of multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 is more compact and regular, which facilitates the setting of various traces (such as first connection traces TL) on the first planarization layer PLN1, and the circuit pattern avoids these vias, thereby improving the stability of these traces and circuit patterns and thus improving the reliability of the display substrate.

[0052] For example, in Figure 1 In this embodiment, the second display area 20 is circular. In other embodiments, the second display area 20 may also be a rectangle, triangle, ellipse, or other shapes. For example, when the second display area 20 is circular, the diameter of the circle may be approximately 3mm to 5mm; when the second display area 20 is rectangular, the length of the long side and the length of the end side may be approximately 3mm to 5mm. The embodiments of this disclosure do not limit the specific shape and size of the second display area 20.

[0053] For example, the multiple pixel driving circuits include multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2, and the multiple light-emitting devices include a first light-emitting device EM1 located in the first display area 10 and a second light-emitting device EM2 located in the second display area 20. The device connection vias include a first via V1 and a second via V2. The first light-emitting device EM1 is electrically connected to the first pixel driving circuit DR1 through the first via V1, and the second light-emitting device EM2 is electrically connected to the second pixel driving circuit DR2 through a first connection trace TL located in the first display area 10 and the second display area 20. In the first display area 10, the first connection trace TL is electrically connected to the second pixel driving circuit DR2 through the second via V2.

[0054] For example, such as Figure 2 and Figure 3 As shown, the first display area 10 is configured for image display, including multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2, a first planarization layer PLN1, and multiple first light-emitting devices EL1; the multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 are arranged in multiple rows and multiple columns, such as... Figure 4As shown, the row direction is, for example, the horizontal direction in the figure, and the column direction is, for example, the vertical direction in the figure. A first planarization layer PLN1 is disposed on the side of the plurality of first pixel driving circuits DR1 and the plurality of second pixel driving circuits DR2 away from the substrate BS. A plurality of first light-emitting devices EL1 are disposed on the side of the first planarization layer PLN1 away from the substrate BS.

[0055] For example, the first pixel driving circuit DR1 and the second pixel driving circuit DR2 respectively include a 2T1C structure (i.e., including two transistors and one storage capacitor C), a 3T1C structure, a 7T1C structure, or an 8T2C structure, etc. The embodiments of this disclosure do not limit the specific form of the first pixel driving circuit DR1 and the second pixel driving circuit DR2. For example, Figure 2 and Figure 3 The transistor shown is the driving transistor, such as the third transistor T3 in the 7T1C structure, which will be described in detail later.

[0056] For example, such as Figure 2 and Figure 3 As shown, the third transistor T3 in the first pixel driving circuit DR1 and the second pixel driving circuit DR2 includes an active layer T3a, a gate electrode T3g, a first electrode T3s, and a second electrode T3d. The storage capacitor C includes a first electrode C1 and a second electrode C2. For example, the gate electrode T3g and the first electrode C1 are disposed in the first conductive layer Gate1 (described in detail later), the second electrode C2 is disposed in the second conductive layer Gate2 (described in detail later) located on the side of the first conductive layer away from the substrate, and the first electrode T3s and the second electrode T3d are disposed in the third conductive layer SD1 (described in detail later) located on the side of the second conductive layer away from the substrate.

[0057] For example, a first gate insulating layer GI1 is disposed between the active layer T3a and the gate electrode T3g, a second gate insulating layer GI2 is disposed between the first electrode C1 and the second electrode C2, and an interlayer insulating layer IDL is disposed between the second electrode C2 and the first electrode T3s and the second electrode T3d. For example, the active layer T3a includes a channel region and a first region and a second region located on both sides of the channel region. The semiconductor material of the first region and the second region is conductive. The first electrode T3s and the second electrode T3d are respectively connected to the first region and the second region of the active layer T3a through vias in the first gate insulating layer GI1 and the second gate insulating layer GI2.

[0058] For example, the first light-emitting device EL1 and the second light-emitting device EL2 can be electrically connected to the first pixel driving circuit DR1 and the second pixel driving circuit DR2 respectively through the connecting electrode CE. The connecting electrode CE is disposed on the fourth conductive layer SD2 located on the side of the third conductive layer away from the substrate (details to follow).

[0059] For example, the first light-emitting device EL1 and the second light-emitting device EL2 can be OLEDs, including a stacked first electrode E1 (e.g., anode), an organic light-emitting layer E2, and a second electrode E3 (e.g., cathode), referenced. Figure 2 and Figure 3 Alternatively, the first light-emitting device EL1 and the second light-emitting device EL2 can also be QLEDs, including a first electrode E1 (e.g., an anode), a quantum dot layer E2, and a second electrode E3 (e.g., a cathode) stacked together. For example, in some embodiments, the second electrode E3 of the first light-emitting device EL1 and the second light-emitting device EL2 can be a surface electrode continuously disposed on the display substrate.

[0060] For example, the first light-emitting device EL1 and the second light-emitting device EL2 are provided with an encapsulation layer EN. For example, the encapsulation layer EN may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer (not shown in the figure) stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, such as silicon oxide, silicon nitride or silicon oxynitride, etc. The second encapsulation layer may be made of organic materials, such as polyimide, resin, etc. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external moisture cannot enter the first light-emitting device EL1 and the second light-emitting device EL2.

[0061] For example, Figure 6 It shows Figure 1 A planar schematic diagram of some functional layers of the display substrate, as shown in the figure. Figure 2 , Figure 3 and Figure 6 As shown, the first planarization layer PLN1 includes multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4. Multiple first light-emitting devices EL1 are electrically connected to multiple first pixel driving circuits DR1 through the multiple first vias V1 (e.g., the first electrode connection electrode CE is disposed in the first via V1), for example, electrically connected to the first or second electrode of the third transistor. Therefore, the multiple first light-emitting devices EL1 are driven in an "in-situ" driving manner, such as... Figure 3 As shown.

[0062] like Figure 2 , Figure 4 and Figure 6As shown, the second display area 20 is configured for image display and light transmission, including multiple second light-emitting devices EL2. These multiple second light-emitting devices EL2 are electrically connected to multiple second pixel driving circuits DR2 via multiple first connection traces TL extending from the first display area 10 and the second display area 20, for example, electrically connected to the first or second electrode of a third transistor. Furthermore, in the first display area 10, the multiple first connection traces TL are electrically connected to the multiple second pixel driving circuits DR2 via multiple second vias V2 (for example, via a first electrode connection electrode CE disposed in the second via V2). Thus, the multiple second light-emitting devices EL2 are driven in a "remote" driving manner, such as... Figure 2 As shown.

[0063] It should be noted that, in the embodiments of this disclosure, an electrical connection between one structure and another structure via a via means that the one structure is directly connected to the other structure via the via, or that the one structure is indirectly connected to the other structure via a connection structure provided in the via, as long as the electrical connection between the one structure and the other structure is achieved through the via.

[0064] For example, in some embodiments, such as Figure 1 The display substrate may further include a third display area 30, which is the main display area of ​​the display substrate. It also includes multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2, and multiple third light-emitting devices. The multiple first pixel driving circuits DR1 in the third display area 30 are electrically connected to the multiple third light-emitting devices to drive the multiple third light-emitting devices. However, unlike the second display area 20, the second pixel driving circuits DR2 in the third display area 30 are not connected to the light-emitting devices.

[0065] For example, such as Figure 6 As shown, the first power signal line VDD is electrically connected to multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 through multiple power vias V3, so as to provide power signals, such as high-level signals, to the first pixel driving circuits DR1 and multiple second pixel driving circuits DR2.

[0066] For example, such as Figure 6As shown, the multiple pixel driving circuits include multiple pixel circuit groups G (e.g., pixel driving circuit rows, one group / row shown in the figure as an example) extending along a first direction (horizontal direction in the figure) and arranged along a second direction (e.g., vertical direction in the figure). At least one of the multiple pixel circuit groups G includes multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2. The multiple first vias V1, multiple second vias V2, multiple power vias V3 and multiple data vias V4 used by the multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 are arranged along the first direction, and the first direction and the second direction intersect.

[0067] For example, the shortest distance between the multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 used by multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 in at least one set of pixel circuit groups G and the first initialization signal line Vin1 is substantially the same.

[0068] For example, the multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 used by multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 in at least one set of pixel circuit groups G are located on the same straight line L1, which extends along a first direction.

[0069] As a result, the arrangement of multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 is more compact and regular, which facilitates the setting of various traces (such as first connection traces TL) on the first planarization layer PLN1, and the circuit pattern avoids these vias, thereby improving the stability of these traces and circuit patterns and thus improving the reliability of the display substrate.

[0070] For example, in embodiments of this disclosure, multiple vias located on the same straight line means that the same straight line can be used to sequentially pass through the multiple vias, for example, passing through any position of each via, and not limited to passing through the center of the multiple vias. Of course, in some embodiments, the centers of the multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 can be located on the same straight line L1, so as to maximize the regularity of the arrangement of the multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4.

[0071] For example, in some embodiments, in a direction parallel to the substrate BS, multiple first connection traces TL are located on at least one side of the same straight line (i.e., the first straight line L1). For example, the multiple first connection traces TL are located between the straight line L1 containing multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 used by each of two adjacent rows of first pixel driving circuits DR1 and second pixel driving circuits DR2.

[0072] For example, in some embodiments, the extension direction of multiple first connection traces TL from the first display area 10 to the second display area 20 (i.e., the horizontal direction in the figure) is parallel to the same straight line (i.e., the first straight line L1), for example, extending along the first direction. Thus, in the direction perpendicular to the substrate, the multiple first connection traces TL will not overlap with the multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4 provided on the first straight line L1, thereby avoiding the multiple first connection traces TL being located above the vias, which could cause short circuits, open circuits, or other defects in the multiple first connection traces TL.

[0073] For example, in some display substrates, such as Figure 5 As shown, the data signal line DT is electrically connected to multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 through multiple data vias V4. The orthographic projection of the multiple data vias V4 on the substrate BS lies between the orthographic projections of two adjacent first connection traces TL on the substrate BS. Figure 5 In the first pixel driving circuit DR1 and the second pixel driving circuit DR2, the multiple first vias V1, multiple second vias V2 and multiple power vias V3 are located on the first straight line L1, and the multiple data vias V4 used by the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are located on the second straight line L2, which is different from the first straight line L1.

[0074] Compared to Figure 5 In the embodiments, Figure 6 In the embodiment, multiple vias in the first planarization layer PLN1 located on the first pixel driving circuit DR1 and the second pixel driving circuit DR2 in the same group (e.g., the same row) are concentrated on the same straight line, which can further save the via arrangement space and allow multiple first connection traces TL to fully avoid the multiple vias in the first planarization layer PLN1, thereby improving the reliability of multiple first connection traces TL.

[0075] For example, Figure 7 The circuit diagram of the first pixel driving circuit DR1 is shown. Figure 8 The circuit diagram of the second pixel driving circuit DR2 is shown, as follows: Figure 7 and Figure 8As shown, the first pixel driving circuit DR1 and the second pixel driving circuit DR2 respectively include a first transistor T1 as a reset transistor, a second transistor T2 as a compensation transistor, and a third transistor T3 as a driving transistor. The gate electrode of the first transistor T1 is connected to the reset signal line Res, the first terminal of the first transistor T1 is connected to the first initialization signal line Vin1, the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first plate C1 of the storage capacitor C, respectively. The gate electrode of the second transistor T2 is connected to the scan signal line Gate, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T2.

[0076] For example, the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first plate C1 of the storage capacitor C intersect at node N1.

[0077] For example, the gate electrode of the first transistor T1, the gate electrode of the second transistor T2, the gate electrode of the third transistor T3, the first plate C1 of the storage capacitor C, the scan signal line Gate, and the reset signal line Res are located on a first conductive layer on the substrate BS, hereinafter also referred to as the Gate1 layer. The first initialization signal line Vin1 is located on a second conductive layer, hereinafter also referred to as the Gate2 layer, which is located on the side of the first conductive layer away from the substrate BS.

[0078] For example, such as Figure 7 and Figure 8 As shown, the first pixel driving circuit DR1 and the second pixel driving circuit DR2 also include a storage capacitor C, a fourth transistor T4 as a data writing transistor, and a fifth transistor T5 as a light-emitting control transistor. The gate electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line DT, the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3, the gate electrode of the fifth transistor T5 is connected to the light-emitting control line EM, the first electrode of the fifth transistor T5 is connected to the second plate C2 of the storage capacitor C, and the first electrode of the fifth transistor T5 and the second plate C2 of the storage capacitor C are connected to the first power supply signal line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0079] For example, the second terminal of the fourth transistor T4, the first terminal of the third transistor T3, and the second terminal of the fifth transistor T5 intersect at node N2.

[0080] For example, the gate electrode of the fourth transistor T4, the gate electrode of the fifth transistor T5, and the light-emitting control line EN are located in the first conductive layer.

[0081] For example, such as Figure 7 and Figure 8As shown, the first pixel driving circuit DR1 and the second pixel driving circuit DR2 also include a sixth transistor T6 as a light-emitting control transistor and a seventh transistor T7 as a reset transistor, respectively. The gate electrode of the sixth transistor T6 is connected to the light-emitting control line EM, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, the first electrode of the first light-emitting device EL1 or the second light-emitting device EL2 is connected to the second electrode of the sixth transistor T6, the gate electrode of the seventh transistor T7 is connected to the reset signal line Res, the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vin2, and the second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6.

[0082] For example, the first terminal of the sixth transistor T6 and the second terminal of the third transistor T3 meet at node N3. The second terminals of the sixth transistor T6 and the seventh transistor T7 meet at node N4.

[0083] For example, the second electrodes of the first light-emitting device EL1 and the second light-emitting device EL2 are connected to the second power line VSS. For example, the signal transmitted by the second power line VSS is a low-level signal, and the signal transmitted by the first power signal line VDD is a high-level signal.

[0084] thus, Figure 7 and Figure 8 In the embodiment shown, the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are formed as a 7T1C structure (i.e., including seven transistors and a storage capacitor).

[0085] For example, the gate electrode of the sixth transistor T6 and the gate electrode of the seventh transistor T7 are located in the first conductive layer, and the second plate C2 of the storage capacitor C and the second initialization signal line Vin2 are located in the second conductive layer.

[0086] For example, the first and second terminals of the first transistor T1, the first and second terminals of the second transistor T2, the first and second terminals of the third transistor T3, the first and second terminals of the fourth transistor T4, the first and second terminals of the fifth transistor T5, the first and second terminals of the sixth transistor T6, and the first and second terminals of the seventh transistor T7 are located in the third conductive layer (also known as the SD1 layer), which is located on the side of the second conductive layer away from the substrate BS.

[0087] In embodiments of this disclosure, the first electrode can be the drain electrode of a transistor, and the second electrode can be the source electrode of a transistor, or the first electrode can be the source electrode of a transistor, and the second electrode can be the drain electrode of a transistor. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged.

[0088] For example, the first power signal line VDD is located in the fourth conductive layer (also known as the SD2 layer), which is located on the side of the third conductive layer away from the substrate BS. Similarly, the data signal line DT is also located in the fourth conductive layer.

[0089] For example, in Figure 2 and Figure 3 In the first pixel driving circuit DR1 and the second pixel driving circuit DR2 shown, the thin-film transistor connected to the first light-emitting device EL1 and the second light-emitting device EL2 is the aforementioned third transistor T3.

[0090] For example, the circuit structures of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 are the same, the difference being that... Figure 8 As shown, since the second light-emitting device EL2 is connected to the second pixel driving circuit DR2 through a long first connection trace TL extending from the first display area 10 and the second display area 20, it is equivalent to connecting a resistor R-TL in series and a capacitor C-TL in parallel between the node N4 where the sixth thin film transistor T6 and the seventh thin film transistor intersect and the second light-emitting device EL2.

[0091] For example, in embodiments of this disclosure, such as Figures 4-6 As shown, among the multiple first pixel driving circuits DR1 and multiple second pixel driving circuits DR2 located in the same row, two first pixel driving circuits DR1 are arranged between every two adjacent second pixel driving circuits DR2. That is, in the first display area 10, every two first pixel driving circuits DR1 and one second pixel driving circuit DR2 constitute a repeating unit, and multiple repeating units are periodically arranged in the first display area 10.

[0092] Therefore, the multiple second pixel driving circuits DR2 used to connect multiple second light-emitting devices EL2 are positioned close to the second display area 20, thereby significantly reducing the length of the first connection trace TL. This weakens or even eliminates the resistance R-TL and capacitance C-TL between node N4 and the second light-emitting device EL2, and solves problems such as dim light emission of the second light-emitting device EL2 in the second display area 20 and insufficient charging time at high frequencies. On the other hand, the number of first pixel driving circuits DR1 through which the first connection trace TL passes is reduced, which can also reduce the occurrence of problems such as open circuits in the first pixel driving circuit DR1.

[0093] For example, in some embodiments, the first transistor T1 to the seventh transistor T7 can be thin-film transistors, such as P-type thin-film transistors or N-type thin-film transistors. Using the same type of transistor in the first pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0094] For example, in some embodiments, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0095] For example, taking the first transistor T1 to the seventh transistor T7 as all being P-type thin-film transistors, the operation of the first pixel driving circuit may include:

[0096] The first stage, A1, is called the reset stage. The reset signal line Res is on, while the scan signal line Gate and the light-emitting signal line EM are off. The on signal of Res turns on the first transistor T1. The signal of the first initialization signal line Vin1 is provided to the first node N1 through the first transistor T1, initializing (resetting) the storage capacitor C and clearing its original charge. The on signal of Res turns on the seventh transistor T7. The signal of the second initialization signal line Vin2 is provided to the first electrode of the first light-emitting device EL1 or the second light-emitting device EL2 through the seventh transistor T7, initializing (resetting) the first electrode of either EL1 or EL2, clearing its internal pre-stored voltage, and completing the initialization. The off signals of the scan signal line Gate and the light-emitting signal line EM turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the first light-emitting device EL1 or the second light-emitting device EL2 does not emit light.

[0097] The second stage, A2, is called the data writing stage or threshold compensation stage. The signal on the scan signal line Gate is the on signal, while the signals on the reset signal line Res and the light-emitting signal line EM are the off signals. The data signal line DT outputs the data voltage. During this stage, because the first plate of the storage capacitor C is at a low level, the third transistor T3 is turned on. The on signal on the scan signal line Gate turns on the second transistor T2 and the fourth transistor T4. The data voltage output by the data signal line DT is supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line DT and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage on the first plate of the storage capacitor C (first node N1) is Vd - |Vth|, where Vd is the data voltage output by the data signal line DT, and Vth is the threshold voltage of the third transistor T3. The off signal on the reset signal line Res turns off the first transistor T1 and the seventh transistor T7, and the off signal on the light-emitting signal line EM turns off the fifth transistor T5 and the sixth transistor T6.

[0098] The third stage, A3, is called the light-emitting stage. The signal on the light-emitting signal line EM is the on signal, while the signals on the scan signal line Gate and the reset signal line Res are the off signals. The on signal on the light-emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply signal line VDD provides a driving voltage to the first electrode of the first light-emitting device EL1 or the second light-emitting device EL2 through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving either the first light-emitting device EL1 or the second light-emitting device EL2 to emit light.

[0099] During the driving processes of the first pixel driving circuit DR1 and the second pixel driving circuit DR2, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0100] I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*[(Vdd-Vd]2

[0101] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the first light-emitting device EL1 or the second light-emitting device EL2, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply signal line VDD.

[0102] For example, Figures 9-15 It shows Figure 5 The illustrated embodiment shows a planar schematic diagram of the various functional layers of the display substrate.

[0103] Figure 9 A planar schematic diagram of the semiconductor layer ACT disposed on a substrate is shown. Figure 9 As shown, the semiconductor layer ACT includes the active layer T1a of the first transistor T1, the active layer T2a of the second transistor T2, the active layer T3a of the third transistor T3, the active layer T4a of the fourth transistor T4, the active layer T5a of the fifth transistor T5, the active layer T6a of the sixth transistor T6, and the seventh active layer T7a of the seventh transistor T7.

[0104] For example, the active layers of these transistors are interconnected as a single structure. For instance, in each column of pixel driving circuits, the active layer T6a of the sixth transistor T6 in the Mth row of pixel driving circuits is interconnected with the seventh active layer T7a of the seventh transistor T7 in the M+1th row of pixel driving circuits. That is, the semiconductor layers of adjacent pixel driving circuits in each column of pixel driving circuits are interconnected as a single structure.

[0105] For example, the active layer T1a of the first transistor T1 can be shaped like an "n", the active layer T2a of the second transistor T2 can be shaped like an "L", the active layer T3a of the third transistor T3 can be shaped like an "Ω", and the active layer T4a of the fourth transistor T4, the active layer T5a of the fifth transistor T5, the active layer T6a of the sixth transistor T6, and the seventh active layer T7a of the seventh transistor T7 can be shaped like an "I".

[0106] For example, the active layer of each transistor may include a channel region and a first region and a second region located on both sides of the channel region. The first region and the second region are conductive and are used to electrically connect to the first electrode and the second electrode of each transistor, respectively.

[0107] For example, refer to Figure 2 and Figure 3 The first gate insulating layer GI1 is formed on the semiconductor layer ACT, which will not be described in detail here.

[0108] Figure 10A A planar schematic diagram of the first conductive layer Gate1 disposed on the semiconductor layer is shown. Figure 10B A planar schematic diagram showing the overlap of the first conductive layer Gate1 and the semiconductor layer ACT is shown. Figure 10A and Figure 10B As shown, the pattern of the first conductive layer Gate1 of each first pixel driving circuit and each second pixel driving circuit includes at least a reset signal line Res, a scan signal line Gate, a light emission control line EM, and the first plate C1 of the storage capacitor C.

[0109] For example, the first electrode C1 of the storage capacitor C can be rectangular, with chamfered corners. The orthographic projection of the first electrode C1 onto the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 onto the substrate. For example, the first electrode C1 of the storage capacitor C can also serve as the gate electrode of the third transistor T3.

[0110] For example, the shapes of the reset signal line Res, the scan signal line Gate, and the light emission control line EM can be line shapes in which the main body extends along the row direction of the pixel driving circuit.

[0111] like Figure 10B As shown, the region where the scan signal line Gate overlaps with the active layer of the second transistor T2 can serve as the gate electrode T2g of the second transistor T2. The scan signal line Gate is provided with a protrusion that protrudes toward the reset signal line Res. The orthographic projection of the protrusion on the substrate overlaps at least partially with the orthographic projection of the active layer of the second transistor T2 on the substrate, thereby forming a second transistor T2 with a dual-gate structure.

[0112] For example, the region where the scan signal line Gate overlaps with the active layer of the fourth transistor T4 is used as the gate electrode T4g of the fourth transistor T4; the region where the reset signal line Res overlaps with the active layer of the first transistor is used as the gate electrode T1g of the first transistor T1 in the dual-gate structure; the region where the reset signal line Res overlaps with the active layer of the seventh transistor T7 is used as the gate electrode T7g of the seventh transistor T7; the region where the light emission control line EM overlaps with the active layer of the fifth transistor T5 is used as the gate electrode T5g of the fifth transistor T5; and the region where the light emission control line EM overlaps with the active layer of the sixth transistor T6 is used as the gate electrode T6g of the sixth transistor T6.

[0113] For example, refer to Figure 2 and Figure 3 A second gate insulating layer GI2 is formed on the first conductive layer Gate1, which will not be described in detail here.

[0114] Figure 11A A planar schematic diagram of a second conductive layer Gate2 disposed on a first conductive layer Gate1 is shown. Figure 11B A schematic planar diagram showing the overlap of the second conductive layer Gate2 with the first conductive layer Gate1 and the semiconductor layer ACT is shown. Figure 11A and Figure 11B As shown, the pattern of the second conductive layer Gate2 of each first pixel driving circuit and each second pixel driving circuit includes at least a first initialization signal line Vin1, a second initialization signal line Vin2, a second electrode C2 of the storage capacitor C, and a masking pattern SH.

[0115] For example, such as Figure 11B As shown, the active layer of the second transistor T2 has a first portion P1 between its two gate electrodes. The orthographic projection of the first portion P1 on the substrate does not overlap with the orthographic projection of the two gate electrodes on the substrate. However, the orthographic projection of the first portion P1 on the substrate overlaps with the orthographic projection of the shielding pattern SH (e.g., the first shielding portion SH1 of the shielding pattern SH) on the substrate. Thus, the shielding pattern SH can provide shielding and voltage regulation for the active layer of the second transistor T2.

[0116] For example, the shape of the blocking pattern SH can be a broken line. The blocking pattern SH is integrally connected with the first initialization signal line Vin1, so that the blocking pattern SH can obtain a constant voltage signal from the first initialization signal line Vin1 to fully achieve the function of voltage stabilization.

[0117] For example, such as Figure 11B As shown, the semiconductor material layer ACT includes a semiconductor pattern P2 that connects the active layer of the second transistor T2 and the active layer of the first transistor T1. The orthographic projection of the semiconductor pattern P2 on the substrate overlaps with the orthographic projection of the shielding pattern SH (e.g., the second shielding portion SH2 of the shielding pattern SH) on the substrate.

[0118] Therefore, the masking pattern SH can also shield the impact of data voltage jumps on critical nodes (such as node N1), preventing data voltage jumps from affecting the potential of critical nodes in the pixel driving circuit, thus achieving a voltage stabilization effect.

[0119] For example, the second plate C2 of the storage capacitor C can be located between the scan signal line Gate and the light emission control line EM. Adjacent second plates C2 in the row direction can be electrically connected to ensure that multiple second plates C2 in the same row have the same potential, which helps to improve the uniformity of the display substrate and thus improve the display effect of the display substrate.

[0120] For example, the outline of the second electrode C2 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode C2 on the substrate at least partially overlaps with the orthographic projection of the first electrode C1 on the substrate to form the storage capacitor C of the pixel driving circuit. An opening is provided on the second electrode C2, which can be located in the middle of the second electrode C2. The opening can be rectangular, allowing the second electrode C2 to form a ring structure. For example, the opening is configured to accommodate a subsequently formed connection via, which is located within the opening and exposes the first electrode C1, allowing the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode C1 through the connection via.

[0121] For example, the shapes of the first initialization signal line Vin1 and the second initialization signal line Vin2 can be linear shapes that extend along the row direction of the main body.

[0122] For example, such as Figure 11B As shown, in a first direction parallel to the substrate, i.e., the column direction in the figure, the second initialization signal line Vin2, the reset signal line Res, the first initialization signal line Vin1, and the scan signal line Gate for the same first pixel driving circuit DR1 or second pixel driving circuit DR2 are arranged sequentially. Thus, the signal lines in the first conductive layer Gate1 and the second conductive layer Gate2 are arranged alternately to avoid excessive density of signal lines in the same conductive layer, which could lead to signal crosstalk, short circuits, and other defects.

[0123] For example, refer to Figure 2 and Figure 3 An interlayer insulating layer (IDL) is formed on the second conductive layer Gate2, which will not be described in detail here.

[0124] Figure 12A A planar schematic diagram of the third conductive layer SD1 disposed on the second conductive layer Gate2 is shown. Figure 12B A schematic planar diagram showing the overlap of the third conductive layer SD1 with the second conductive layer Gate2, the first conductive layer Gate1, and the semiconductor layer ACT is shown. Figure 12A and Figure 12B As shown, the pattern of the third conductive layer SD1 of each first pixel driving circuit and each second pixel driving circuit includes at least a first connecting electrode 11, a second connecting electrode 12, a third connecting electrode 13, a fourth connecting electrode 14, a fifth connecting electrode 15 and a sixth connecting electrode 16.

[0125] For example, the first connecting electrode 11 can be a strip shape extending along the column direction of the main body. The first end of the first connecting electrode 11 is connected to the first electrode plate C1 through a via, and the second end of the first connecting electrode 11 is connected to the second region of the active layer of the first transistor T1 (which is also the first region of the active layer of the second transistor T1) through a via, so that the first electrode plate C1, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. For example, the first connecting electrode 41 can simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0126] For example, the second connection electrode 12 can be a strip shape extending along the row direction. The first end of the second connection electrode 12 is connected to the first region of the active layer of the first transistor through a via, and the second end of the second connection electrode 12 is connected to the first initialization signal line Vin1 through a via. For example, the second connection electrode 12 can serve as the first electrode of the first transistor T1, enabling the first initialization signal line Vin1 to write the first initial signal into the first transistor T1.

[0127] For example, the third connection electrode 13 can be shaped like a broken line. The first end of the third connection electrode 13 is connected to the first region of the active layer of the seventh transistor through a via, and the second end of the third connection electrode 13 is connected to the second initialization signal line Vint2 through a via. For example, the third connection electrode 13 can serve as the first electrode of the seventh transistor T7, enabling the second initialization signal line Vint2 to write the second initial signal into the seventh transistor T7.

[0128] For example, the fourth connection electrode 14 can be dumbbell-shaped, and the fourth connection electrode 14 is connected to the first region of the active layer of the fourth transistor through a via. For example, the fourth connection electrode 14 can serve as the first electrode of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to the subsequently formed data signal line DT.

[0129] For example, the shape of the fifth connecting electrode 15 can be approximately "Z" shaped. The first end of the fifth connecting electrode 15 is connected to the first region of the active layer of the fifth transistor T5 through a via, and the second end of the fifth connecting electrode 15 is connected to the second electrode C2 through a via, so that the second electrode C2 and the first region of the active layer of the fifth transistor T5 have the same potential. For example, the fifth connecting electrode 15 can serve as the first electrode of the fifth transistor T5.

[0130] For example, the sixth connection electrode 16 can be rectangular in shape. The sixth connection electrode 16 is connected to the second region of the active layer of the sixth transistor T6 (which is also the second region of the active layer of the seventh transistor T7) through a via, so that the second regions of the active layers of the sixth transistor T6 and the seventh transistor T7 have the same potential. For example, the sixth connection electrode 16 can serve as the second electrode of the sixth transistor T6 (or the second electrode of the seventh transistor T7).

[0131] For example, such as Figure 12A As shown, the spacing D1 between the patterns of the third conductive layer SD1 of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 in adjacent rows is 7.0 micrometers to 10.0 micrometers, such as 8.0 micrometers, 8.5 micrometers, 9.0 micrometers, or 9.5 micrometers. Therefore, the patterns of the third conductive layer SD1 of the first pixel driving circuit DR1 and the second pixel driving circuit DR2 in adjacent rows have a large spacing, which provides space for the arrangement of other circuit patterns and traces on the display substrate.

[0132] For example, Figure 13 A planar schematic diagram of the first planarization layer PLN1 disposed on the third conductive layer SD1 is shown, as follows. Figure 13As shown, the first planarization layer PLN1 includes multiple first vias V1, multiple second vias V2, multiple power vias V3, and multiple data vias V4. The multiple first vias V1 are used to connect the first electrode connection electrode CE of the first light-emitting device EL1 to the first pixel driving circuit DR1; the multiple second vias V2 are used to connect the first electrode connection electrode CE of the second light-emitting device EL2 to the second pixel driving circuit DR2; the multiple power vias V3 are used to connect the subsequent first power signal line VDD to the first pixel driving circuit DR1 / second pixel driving circuit DR2; and the multiple data vias V4 are used to connect the subsequent data signal line DT to the first pixel driving circuit DR1 / second pixel driving circuit DR2.

[0133] In this embodiment, multiple first vias V1, multiple second vias V2, and multiple power vias V3 are located on the same straight line, i.e., on the first straight line L1, while multiple data vias V4 are located on another straight line, i.e., on the second straight line L2.

[0134] Figure 14A A planar schematic diagram of the fourth conductive layer SD2 disposed on the first planarization layer PLN1 is shown. Figure 14B A planar schematic diagram showing the overlap of the fourth conductive layer SD2 and the third conductive layer SD1 is shown; Figure 14C A schematic planar diagram showing the overlap of the fourth conductive layer SD2 with the third conductive layer SD1, the second conductive layer Gate2, the first conductive layer Gate1, and the semiconductor layer ACT. (See diagram below.) Figure 14A , Figure 14B as well as Figure 14C As shown, the pattern of the fourth conductive layer SD2 of each first pixel driving circuit and each second pixel driving circuit includes at least a first electrode connection electrode CE, a data signal line DT, and a first power signal line VDD.

[0135] For example, the first electrode connecting electrode CE is used to connect the first light-emitting device EL1 to the first pixel driving circuit DR1, or to connect the first electrode E1 of the second light-emitting device EL2 to the second pixel driving circuit DR2.

[0136] For example, the data signal line DT can be a straight line extending along the column direction, and the data signal line DT is connected to the fourth connection electrode 14 through the data via V4. Since the fourth connection electrode 14 is connected to the first region of the active layer of the fourth transistor T4 through the via, the data signal line DT writes the data signal to the first electrode of the fourth transistor T4.

[0137] For example, the first power signal line VDD can be a zigzag line extending along the column direction of the main body. The first power signal line VDD is connected to the fifth connection electrode 15 through a power via V3. Since the fifth connection electrode 15 is connected to the first region of the active layer of the second electrode C2 and the fifth transistor T5 through the via, the first power signal line VDD writes the first power signal into the first electrode of the fifth transistor T5, and makes the second electrode C2 and the first electrode of the fifth transistor T5 have the same potential.

[0138] For example, such as Figure 14B As shown, the third conductive layer SD1 includes a connection portion (i.e., the aforementioned first connection electrode 11) located between the second electrode of the first transistor T1 and the gate electrode of the third transistor T3. The first power signal line VDD also includes a protrusion VDP. The orthographic projection of the connection portion (i.e., the aforementioned first connection electrode 11) on the substrate overlaps with the orthographic projection of the protrusion VDP on the substrate. For example, the orthographic projection of the connection portion (i.e., the aforementioned first connection electrode 11) on the substrate is located within the orthographic projection of the protrusion VDP on the substrate. Thus, the protrusion VDP can shield the N1 node.

[0139] Therefore, in the embodiments of this disclosure, the third conductive layer SD1 only includes connection electrodes (first to sixth connection electrodes 11-16) for signal transfer and jumper functions, thus allowing for a larger gap D1 to accommodate other circuits or traces, such as... Figure 12A As shown. The fourth conductive layer SD2 includes both a first power signal line VDD and a data signal line DT. The first power signal line VDD includes a protrusion VDP to shield point N1. The data signal line DT is located in the fourth conductive layer SD2 to reduce signal transmission voltage drop, reduce charging time, and achieve a high refresh rate display.

[0140] For example, refer to Figure 2 and Figure 3 A second planarization layer PLN2 is disposed on the fourth conductive layer SD2, and a first connection trace TL can be disposed on the second planarization layer PLN2, such as... Figure 15 As shown, a third planarization layer PLN3 is provided on the first connection trace TL.

[0141] For example, in some embodiments, the first connection trace TL can be disposed in multiple functional layers. In this case, a portion of the first connection trace TL can be disposed on the second planarization layer PLN2, a third planarization layer PLN3 can be disposed on the portion of the first connection trace TL, another portion of the first connection trace TL can be disposed on the third planarization layer PLN3, a fourth planarization layer can be disposed on the other portion of the first connection trace TL, a further portion of the first connection trace TL can be disposed on the fourth planarization layer, and a fifth planarization layer PLN5 can be disposed on the further portion of the first connection trace TL.

[0142] For example, the first light-emitting device EL1 and the second light-emitting device EL2 described above can be disposed on the fifth planarization layer PLN5. An encapsulation layer EN is disposed on the first light-emitting device EL1 and the second light-emitting device EL2.

[0143] For example, the material of the first connecting trace TL can be a transparent conductive material, such as transparent metal oxides like indium tin oxide (ITO) or indium zinc oxide (IZO), to further improve the light transmittance of the second display area 20.

[0144] For example, in Figure 6 In this embodiment, the third conductive layer SD1 and the first planarization layer PLN1 of the display substrate are slightly different from those in the above embodiment. For example... Figure 16A As shown, in Figure 6 In one embodiment, the pattern of the fourth connecting electrode 14 in the third conductive layer SD1 has a longer straight line portion; such as Figure 16B As shown, multiple first vias V1, multiple second vias V2, multiple power vias V3 and multiple data vias V4 in the first planarization layer PLN1 are located on the same straight line, that is, on the first straight line L1. Figure 16C A schematic diagram showing the overlap between the fourth conductive layer SD2 and the first conductive layer SD1 is shown. Figure 16D A schematic diagram showing the overlap of the first connection trace TL with the fourth conductive layer SD2 and the first conductive layer SD1 is shown, as follows. Figure 16D As shown, the extension direction of the first connecting trace TL is parallel to the extension direction of the first straight line L1, and is the row direction of the multiple first pixel driving circuits DR1 and second pixel driving circuits DR2.

[0145] For example, in embodiments of this disclosure, the substrate BS can be a flexible substrate or a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass and quartz, while the flexible substrate can include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. For example, in some examples, the flexible substrate can include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0146] For example, the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2 can be made of metallic materials, such as any one or more of titanium (Ti), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first connection trace TL can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO. The first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The planarization layers, such as the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3, can be made of organic materials, such as polyimide or resin. The semiconductor material layer ACT can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc.

[0147] For example, the first electrode E1 of the first light-emitting device EL1 and the second light-emitting device EL2 can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO), or a stack of transparent metal oxide and metal (such as silver). The material of the second electrode E2 can be a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0148] The embodiments disclosed herein do not specifically limit the materials of each functional layer on the display substrate.

[0149] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0150] The following points also need to be explained:

[0151] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0152] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0153] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0154] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area, wherein the first display area at least partially surrounds the second display area, and the light transmittance of the second display area is greater than that of the first display area; Multiple pixel driving circuits are located on the substrate and in the first display area; The first planarization layer is located on the side of the plurality of pixel driving circuits away from the substrate. Multiple light-emitting devices are located on the side of the first planarization layer away from the substrate. A first power signal line is located on the side of the first planarization layer away from the substrate and within the first display area; and The data signal line is located on the side of the first planarization layer away from the substrate and is located in the first display area; The first planarization layer includes a device connection via electrically connecting at least one of the plurality of pixel driving circuits to at least one of the plurality of light-emitting devices, a power via electrically connecting at least one of the plurality of pixel driving circuits to the first power signal line, and a data via electrically connecting at least one of the plurality of pixel driving circuits to the data signal line. The device connection vias, power vias, and data vias are arranged along a first direction, which is perpendicular to the extension direction of the data signal line.

2. The display substrate according to claim 1, further comprising: The first initialization signal line is configured to provide a first initialization signal to at least one of a plurality of pixel driving circuits; The shortest distance between the device connection via, the power supply via, and the data via and the first initialization signal line is substantially equal.

3. The display substrate according to claim 2, wherein, The plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit, and the plurality of light-emitting devices include a first light-emitting device located in the first display area and a second light-emitting device located in the second display area. The device connection vias include a first via and a second via. The first light-emitting device is electrically connected to the first pixel driving circuit through the first via. The second light-emitting device is electrically connected to the second pixel driving circuit through a first connection trace located in the first display area and the second display area. In the first display area, the first connection trace is electrically connected to the second pixel driving circuit through the second via.

4. The display substrate according to claim 3, wherein, The plurality of pixel driving circuits include a plurality of pixel circuit groups extending along a first direction and arranged along a second direction, wherein at least one of the plurality of pixel circuit groups includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits. The plurality of first vias, plurality of second vias, plurality of power vias, and plurality of data vias used in the plurality of first pixel driving circuits and the plurality of second pixel driving circuits are arranged along the first direction, and the first direction and the second direction intersect.

5. The display substrate according to claim 4, wherein, The multiple first vias, multiple second vias, multiple power vias, and multiple data vias used in the multiple first pixel driving circuits and multiple second pixel driving circuits in the at least one set of pixel circuit groups are substantially the same as the shortest distance from the first initialization signal line.

6. The display substrate according to claim 4 or 5, wherein, The plurality of first vias, plurality of second vias, plurality of power vias, and plurality of data vias used in the plurality of first pixel driving circuits and plurality of second pixel driving circuits in the at least one set of pixel circuit groups are located on the same straight line, and the same straight line extends along the first direction.

7. The display substrate according to claim 6, wherein, In a direction parallel to the substrate, the first connection trace is located on at least one side of the same straight line.

8. The display substrate according to claim 7, wherein, The first connection trace extends from the first display area to the second display area in a direction parallel to the first direction.

9. The display substrate according to any one of claims 3-5, wherein, The first pixel driving circuit and the second pixel driving circuit each include a first transistor as a reset transistor, a second transistor as a compensation transistor, and a third transistor as a driving transistor. The gate electrode of the first transistor is connected to the reset signal line, the first terminal of the first transistor is connected to the first initialization signal line, the second terminal of the first transistor is connected to the first terminal of the second transistor and the gate electrode of the third transistor, the gate electrode of the second transistor is connected to the scan signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor. The gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the scan signal line, and the reset signal line are located on a first conductive layer on the substrate. The first initialization signal line is located in the second conductive layer, which is located on the side of the first conductive layer away from the substrate.

10. The display substrate according to claim 9, wherein, The first pixel driving circuit and the second pixel driving circuit also include a storage capacitor, a fourth transistor as a data writing transistor, and a fifth transistor as a light-emitting control transistor, respectively. The gate electrode of the fourth transistor is connected to the scan signal line, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor, the gate electrode of the fifth transistor is connected to the light emission control line, the first electrode of the fifth transistor is connected to the second plate of the storage capacitor, and the second electrode of the fifth transistor is connected to the first electrode of the third transistor. The light-emitting control line is located in the first conductive layer.

11. The display substrate according to claim 10, wherein, The first pixel driving circuit and the second pixel driving circuit further include a sixth transistor as a light-emitting control transistor and a seventh transistor as a reset transistor, respectively. The gate electrode of the sixth transistor is connected to the light-emitting control line, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, the first light-emitting device or the second light-emitting device is connected to the second electrode of the sixth transistor, the gate electrode of the seventh transistor is connected to the reset signal line, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor. The second initialization signal line is located in the second conductive layer.

12. The display substrate according to claim 11, wherein, In a first direction parallel to the substrate, the second initialization signal line, the reset signal line, the first initialization signal line, and the scan signal line for the same first pixel driving circuit or second pixel driving circuit are arranged sequentially.

13. The display substrate according to claim 10, wherein, The second transistor includes an active layer and two gate electrodes, the active layer being a semiconductor material layer located between the first conductive layer and the substrate. The active layer includes a first portion, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the two gate electrodes on the substrate. The second conductive layer includes a shielding pattern, wherein the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the shielding pattern on the substrate.

14. The display substrate according to claim 13, wherein, The occlusion pattern is integrally connected to the first initialization signal line.

15. The display substrate according to claim 13, wherein, The semiconductor material layer includes a semiconductor pattern that connects the active layer of the second transistor and the active layer of the first transistor. The orthographic projection of the semiconductor pattern on the substrate overlaps with the orthographic projection of the occlusion pattern on the substrate.

16. The display substrate according to claim 9, wherein, The first and second terminals of the first transistor, the first and second terminals of the second transistor, and the first and second terminals of the third transistor are located in a third conductive layer, which is located on the side of the second conductive layer away from the substrate.

17. The display substrate according to claim 16, wherein, The first power signal line is located in the fourth conductive layer, which is located on the side of the third conductive layer away from the substrate.

18. The display substrate according to claim 17, wherein, The data signal line is located in the fourth conductive layer.

19. The display substrate according to claim 16, wherein, The third conductive layer further includes a connection portion located between the second electrode of the first transistor and the gate electrode of the third transistor. The first power signal line also includes a protrusion. The orthographic projection of the connecting portion on the substrate overlaps with the orthographic projection of the protrusion on the substrate.

20. The display substrate according to claim 19, wherein, The orthographic projection of the connecting portion on the substrate is located within the orthographic projection of the protrusion on the substrate.

21. The display substrate according to claim 9, wherein, The spacing between the patterns of the third conductive layer of the first pixel driving circuit and the second pixel driving circuit located in adjacent rows is 7.0 micrometers to 10.0 micrometers.

22. The display substrate according to any one of claims 2-5, wherein, In the plurality of first pixel driving circuits and plurality of second pixel driving circuits in at least one set of pixel circuit groups, two first pixel driving circuits are provided between every two adjacent second pixel driving circuits.

23. A display device comprising the display substrate according to any one of claims 1-22.

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