Semiconductor device

Abstract

A semiconductor device can include a first receiver configured to receive a chip select signal from a receive node coupled to a termination resistor and configured to generate a first internal chip select signal, a command pulse generation circuit configured to generate a command pulse for entering a self-refresh operation based on an internal command address and the first internal chip select signal, and an operation control circuit configured to generate a resistor value change signal that adjusts a value of the termination resistor when the semiconductor device enters the self-refresh operation based on the command pulse.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0163829, filed with the Korean Intellectual Property Office on November 24, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device capable of adjusting the value of a termination resistor during a self-refresh operation. Background Technology

[0004] In semiconductor devices, DRAM is a type of volatile memory where data stored in memory cells is lost after a predetermined period of time, requiring a refresh operation to re-store the data. DRAM can perform a self-refresh operation by automatically generating commands for the refresh operation within it, thus periodically performing the refresh operation.

[0005] A semiconductor device may include an ODT (on-chip termination) circuit for matching external impedance with internal impedance, thereby improving signal integrity. Summary of the Invention

[0006] In one embodiment, a semiconductor device may include: a first receiver configured to receive a chip select signal from a receiving node coupled to a terminating resistor, and configured to generate a first internal chip select signal; a command pulse generation circuit configured to generate a command pulse for entering a self-refresh operation based on an internal command address and the first internal chip select signal; and an operation control circuit configured to generate a resistor value change signal that adjusts the value of the terminating resistor when the semiconductor device enters a self-refresh operation based on the command pulse.

[0007] In another embodiment, a semiconductor device may include: an operation control circuit configured to generate a resistor value change signal when the level of a chip select signal changes to cause the semiconductor device to enter a self-refresh operation; and an ODT (on-chip termination) circuit including a termination resistor coupled to a receiving node receiving the chip select signal, and configured to adjust the value of the termination resistor based on the resistor value change signal. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of an electronic system according to an embodiment.

[0009] Figure 2 It is shown Figure 1 A block diagram showing the configuration of the semiconductor device.

[0010] Figure 3 It is shown Figure 2A diagram illustrating an example of an ODT (On-Chip Termination) circuit.

[0011] Figure 4 It is shown Figure 3 The circuit diagram shown is an example of an internal setting code generation circuit.

[0012] Figure 5 It is shown Figure 3 The circuit diagram shows another example of the internal setting code generation circuit.

[0013] Figure 6 It is shown Figure 2 The circuit diagram shown is an example of the first receiver.

[0014] Figure 7 It is shown Figure 2 The circuit diagram shown is an example of a second receiver.

[0015] Figure 8 It is shown Figure 2 A diagram illustrating an example of a command pulse generation circuit.

[0016] Figure 9 It is shown Figure 2 The block diagram shown is an example of an operation control circuit.

[0017] Figure 10 It is shown Figure 9 The circuit diagram shown is an example of a self-refresh signal generation circuit.

[0018] Figure 11 It is shown Figure 9 The circuit diagram shown is an example of an internal self-refresh signal generation circuit.

[0019] Figure 12 It is shown Figure 9 The circuit diagram shown is an example of an enable signal generation circuit.

[0020] Figure 13 It is shown Figure 9 The circuit diagram shown is an example of a flag generation circuit.

[0021] Figure 14 It is shown Figure 9 The circuit diagram shown is an example of a signal generation circuit where the resistor value changes.

[0022] Figures 15 to 18 It is used to describe by Figure 2 The timing diagram shows the operations performed by the semiconductor device. Detailed Implementation

[0023] In the following description of the embodiments, the term "preset" means that the value of the parameter is predetermined when it is used in a process or algorithm. According to the embodiments, the value of the parameter can be set at the start of the process or algorithm or when the process or algorithm is executed.

[0024] Terms such as "first" and "second" used to distinguish various parts are not limited to parts. For example, the first part can be called the second part, and vice versa.

[0025] When a component is referred to as "coupled" or "connected" to another component, it can mean that these components can be directly coupled or connected to each other, or coupled or connected to each other through another component placed between them. On the other hand, when a component is referred to as "directly coupled" or "directly connected" to another component, it can mean that these components are directly coupled or connected to each other without another component placed between them.

[0026] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal with a "logic high level" is different from a signal with a "logic low level". For example, when a signal with a first voltage corresponds to a "logic high level", a signal with a second voltage can correspond to a "logic low level". According to an embodiment, a "logic high level" can be set to a voltage higher than a "logic low level". According to an embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, according to an embodiment, a signal with a logic high level can be set to a logic low level, and a signal with a logic low level can be set to a logic high level.

[0027] The teachings of this disclosure will be described in more detail below through embodiments. These embodiments are merely illustrative of the teachings of this disclosure, and the scope of this disclosure is not limited thereto.

[0028] Embodiments of this disclosure relate to a semiconductor device capable of adjusting the value of a termination resistor during a self-refresh operation.

[0029] Figure 1 This is a block diagram illustrating the configuration of the electronic system 100 according to an embodiment. (As shown) Figure 1As shown, the electronic system 100 may include a controller 110 and a semiconductor device 120. The controller 110 can send a chip select signal CS_n to the semiconductor device 120 via a first transmission line 130_1. The controller 110 can send a command address CA to the semiconductor device 120 via a second transmission line 130_2. The controller 110 can send a clock CK to the semiconductor device 120 via a third transmission line 130_3. The semiconductor device 120 may be implemented as a memory device. The semiconductor device 120 can receive the chip select signal CS_n, the command address CA, and the clock CK from the controller 110, and can perform a self-refresh operation or a normal operation. The normal operation may include various internal operations, such as write operations, read operations, activation operations, and precharge operations.

[0030] Controller 110 may include a chip select signal transmitter (CS_nTX) 111 configured to drive and output a chip select signal CS_n. Controller 110 can set the level of the chip select signal CS_n through the chip select signal transmitter 111. Controller 110 can change the level of the chip select signal CS_n from a preset level to a first target level, causing the semiconductor device 120 to enter a self-refresh operation. Then, controller 110 can change the level of the chip select signal CS_n back to the preset level after a preset period of time. In this embodiment, the preset period of time can be set to one cycle of clock CK. However, in this embodiment, the preset period of time can be set to various periods of time. After a delay time has elapsed since the semiconductor device 120 has entered the self-refresh operation, controller 110 can change the level of the chip select signal CS_n from the preset level to a second target level to control the power consumed by the semiconductor device 120. The delay time represents the time required for the input of the interrupt command address CA when the semiconductor device 120 enters the self-refresh operation. The difference between the preset level and the second target level can be set to a value greater than the difference between the preset level and the first target level.

[0031] The controller 110 can change the level of the chip selection signal CS_n from the second target level to a preset level, so that the semiconductor device 120 ends the self-refresh operation.

[0032] After a delay period has elapsed since the semiconductor device 120 has completed its self-refresh operation, the controller 110 can change the level of the chip selection signal CS_n from a preset level to a first target level, causing the semiconductor device 120 to recognize the end of the self-refresh operation. Then, after a preset time period, the controller 110 can change the level of the chip selection signal CS_n back to the preset level. The end delay period represents the time required for the semiconductor device 120 to stably recognize that the self-refresh operation has ended.

[0033] Semiconductor device 120 may include ODT (On-Chip Termination) circuitry 203, a chip select signal receiver (CS_n RX) 205, and operation control circuitry 217. ODT circuitry 203 may include a termination resistor (not shown) and a termination driver (not shown) configured to adjust the value of the termination resistor. Chip select signal receiver 205 may receive a chip select signal CS_n from a node coupled to the termination resistor included in ODT circuitry 203.

[0034] When the level of the chip selection signal CS_n changes from a preset level to a first target level, causing the semiconductor device to enter self-refresh operation, the operation control circuit 217 can generate a resistor value change signal. Figure 2 The RTT_C signal is used to adjust the value of the termination resistor included in the ODT circuit 203. The ODT circuit 203 can adjust the value of the termination resistor by controlling the drive capability of the termination driver based on the resistor value change signal RTT_C. Therefore, after a delay time has elapsed since the semiconductor device 120 has entered self-refresh operation, the semiconductor device 120 can stably control the level of the chip select signal CS_n, which transitions from a preset level to a second target level. Therefore, the semiconductor device 120 can prevent malfunctions caused by level changes in the chip select signal CS_n during self-refresh operation.

[0035] When the level of the chip selection signal CS_n changes from a preset level to a second target level after a delay time following the self-refresh operation of the semiconductor device 120, the operation control circuit 217 can activate the first receiver of the chip selection signal receiver 205 ( Figure 2 (207) Switch to the second receiver of chip select signal receiver 205 ( Figure 2 (209), and can disable the terminating resistor included in the ODT circuit 203. Therefore, the semiconductor device 120 can reduce the power consumed during the period of performing self-refresh operation.

[0036] When the level of the chip selection signal CS_n changes from the second target level to the preset level after the self-refresh operation is completed, the operation control circuit 217 can activate the second receiver of the chip selection signal receiver 205. Figure 2 209) Switch to the first receiver of chip select signal receiver 205 ( Figure 2 207), and enable the terminating resistor included in the ODT circuit 203.

[0037] Figure 2 It is shown Figure 1The diagram shows a block diagram of the configuration of the semiconductor device 120. As shown in Figure 2, the semiconductor device 120 may include a mode register 201, an ODT circuit 203, a chip select signal receiver 205, a command address receiver (CA RX) 211, a clock receiver (CK RX) 213, a command pulse generation circuit (COMMAND PULSE GEN) 215, an operation control circuit 217, and internal circuitry 219.

[0038] Mode register 201 can store and output setting code OP. Setting code OP can have a termination resistor included in ODT circuit 203 for setting ( Figure 3 The logic level combination of the RTT value.

[0039] The ODT circuit 203 may include a terminating resistor coupled to the receiver node nd_RX of the receiver chip selection signal CS_n. Figure 3 The ODT circuit 203 can enable the termination resistor RTT during the period when the enable signal EN is activated. The ODT circuit 203 may include a termination driver. Figure 3 The termination driver 223 is configured to adjust the value of the termination resistor RTT. The ODT circuit 203 can adjust the value of the termination resistor RTT by controlling the drive capability of the termination driver 223 based on the setting code OP and the resistor value change signal RTT_C. When the resistor value change signal RTT_C is deactivated, the ODT circuit 203 can set the value of the termination resistor RTT according to the logic level combination of the setting code OP. When the resistor value change signal RTT_C is activated, the ODT circuit 203 can set the value of the termination resistor RTT to a preset value. In different embodiments, the preset value can be set to various values. For example, when the resistor value change signal RTT_C is activated, the ODT circuit 203 can reduce the drive capability of the termination driver 223 to a value lower than when the resistor value change signal RTT_C is deactivated, thereby setting the value of the termination resistor RTT to a high value. In other words, the driving capability of the termination driver 223 can be adjusted by activating the resistor value change signal RTT_C, so as to stably control the level change of the chip selection signal CS_n. The following will refer to... Figure 3 Describe in detail the configuration and operation of ODT circuit 203.

[0040] The chip select signal receiver 205 may include a first receiver (FIRST RX) 207 and a second receiver (SECOND RX) 209, which are configured to receive signals from a termination resistor included in the ODT circuit 203. Figure 3The receiving node nd_RX, coupled to the RTT (Receiving Time Tolerance), receives the chip select signal CS_n. The level of the chip select signal CS_n can be set between the supply voltage VDD and the ground voltage VSS. The supply voltage VDD and the ground voltage VSS can be applied from power pads (not shown). In this embodiment, the preset level of the chip select signal CS_n can be set to the level of the supply voltage VDD, the first target level of the chip select signal CS_n can be set between the level of the supply voltage VDD and half of the supply voltage VDD, and the second target level of the chip select signal CS_n can be set to the level of the ground voltage VSS. This is only one embodiment, and the preset level, the first target level, and the second target level of the chip select signal CS_n can be set to various levels in different embodiments.

[0041] The first receiver 207 can receive the chip select signal CS_n from the receiving node nd_RX and generate a first internal chip select signal ICS1 based on the enable signal EN and the reference voltage VREF_CS. The first receiver 207 can be enabled during the period when the enable signal EN is activated. The first receiver 207 can set the logic level of the first internal chip select signal ICS1 by comparing the level of the chip select signal CS_n with the level of the reference voltage VREF_CS during the period when the enable signal EN is activated. The level of the reference voltage VREF_CS can be set between a preset level and a first target level. For example, when the level of the chip select signal CS_n changes from the preset level to the first target level, causing the semiconductor device to enter a self-refresh operation, the first receiver 207 can set the logic level of the first internal chip select signal ICS1 to the preset logic level. As another example, when the level of the chip select signal CS_n changes from the preset level to the second target level after a delay following the semiconductor device having entered a self-refresh operation, the first receiver 207 can set the logic level of the first internal chip select signal ICS1 to the preset logic level. For example, when the level of the chip select signal CS_n changes from a preset level to a first target level after an end delay time following the completion of the self-refresh operation, the first receiver 207 can set the logic level of the first internal chip select signal ICS1 to the preset logic level. In this embodiment, the preset logic level can be set to a logic low level. However, in different embodiments, the preset logic level can be set to a logic high level. The first receiver 207 can be implemented as a differential amplifier, which amplifies the difference between the level of the chip select signal CS_n and the level of the reference voltage VREF_CS and drives the output node that outputs the first internal chip select signal ICS1. The following will refer to... Figure 6 The configuration and operation of the first receiver 207 are described in detail.

[0042] The second receiver 209 can receive the chip select signal CS_n from the receiving node nd_RX and generate a second internal chip select signal ICS2 based on the self-refresh signal SREF. The second receiver 209 can be enabled during the period when the self-refresh signal SREF is activated. During the period when the self-refresh signal SREF is activated, the second receiver 209 can set the logic level of the second internal chip select signal ICS2 according to the level of the chip select signal CS_n. For example, when the level of the chip select signal CS_n changes from a preset level to a second target level after a delay time following the semiconductor device entering self-refresh operation, the second receiver 209 can change the logic level of the second internal chip select signal ICS2 from a first logic level to a second logic level. As another example, when the level of the chip select signal CS_n changes from a second target level to a preset level, causing the semiconductor device to end the self-refresh operation, the second receiver 209 can change the logic level of the second internal chip select signal ICS2 from a second logic level to a first logic level. In this embodiment, the first logic level and the second logic level can be set to logic high and logic low levels, respectively. However, in different implementations, the first logic level and the second logic level can be set to logic low and logic high, respectively. The second receiver 209 can be implemented as a CMOS (Complementary Metal-Oxide-Semiconductor) buffer, which drives the output node of the second internal chip select signal ICS2 according to the level of the chip select signal CS_n. The second receiver 209, implemented as a CMOS buffer, can have lower power consumption than the first receiver 207, which is implemented as a differential amplifier. Reference will be made below. Figure 7 The configuration and operation of the second receiver 209 are described in detail.

[0043] Command address receiver 211 can receive command address CA and generate internal command address ICA. Command address receiver 211 can buffer command address CA and output the buffered command address as internal command address ICA.

[0044] Clock receiver 213 can receive clock CK and generate internal clock ICK. Clock receiver 213 can buffer clock CK and output the buffered clock as internal clock ICK.

[0045] The command pulse generation circuit 215 can generate a command pulse SREP from the internal command address ICA based on the first internal chip select signal ICS1, synchronized with the internal clock ICK. When the first internal chip select signal ICS1 has a preset logic level, the command pulse generation circuit 215 can generate the command pulse SREP for entering the self-refresh operation by decoding the internal command address ICA, which has a combination of logic levels for entering the self-refresh operation. The following will refer to... Figure 8The configuration and operation of the command pulse generation circuit 215 are described in detail.

[0046] The operation control circuit 217 can generate a self-refresh signal SREF, an internal self-refresh signal ISREF, a resistor value change signal RTT_C, and an enable signal EN based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. The self-refresh signal SREF can be activated until the semiconductor device ends its self-refresh operation after entering the self-refresh phase. The internal self-refresh signal ISREF can be activated until an end delay time has elapsed after the semiconductor device ends its self-refresh operation. The resistor value change signal RTT_C can be activated to terminate the terminating resistor included in the ODT circuit 203. Figure 3 The value of RTT is adjusted to a preset value. The enable signal EN can be activated to enable the first receiver 207 and the termination resistor RTT included in the ODT circuit 203.

[0047] The operation control circuit 217 can control the activation state of the self-refresh signal SREF and the internal self-refresh signal ISREF based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. When the semiconductor device enters a self-refresh operation based on the command pulse SREP, the operation control circuit 217 can activate the self-refresh signal SREF and the internal self-refresh signal ISREF. The operation control circuit 217 can enable the second receiver 209 based on the activated self-refresh signal SREF. When the logic level of the second internal chip select signal ICS2 changes from the second logic level to the first logic level after the self-refresh operation ends, the operation control circuit 217 can deactivate the self-refresh signal SREF. The operation control circuit 217 can disable the second receiver 209 based on the deactivated self-refresh signal SREF. When the first internal chip select signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is deactivated after the self-refresh operation ends, the operation control circuit 217 can deactivate the internal self-refresh signal ISREF. In other words, when the first internal chip selection signal ICS1 has a preset logic level after the end delay time following the completion of the self-refresh operation, the operation control circuit 217 can deactivate the internal self-refresh signal ISREF.

[0048] The operation control circuit 217 can control the activation state of the resistor value change signal RTT_C based on the command pulse SREP and the second internal chip selection signal ICS2. When the semiconductor device enters self-refresh operation based on the command pulse SREP, the operation control circuit 217 can activate the resistor value change signal RTT_C. That is, when the semiconductor device enters self-refresh operation, the operation control circuit 217 can activate the terminating resistor included in the ODT circuit 203 based on the activated resistor value change signal RTT_C. Figure 3 The value of the RTT (Resistor Value Change Signal) is adjusted to a preset value. When the logic level of the second internal chip select signal ICS2 changes from the first logic level to the second logic level, the operation control circuit 217 can deactivate the resistor value change signal RTT_C. That is, after a delay time has elapsed since the semiconductor device has entered self-refresh operation, the operation control circuit 217 can set the value of the termination resistor RTT based on the deactivated resistor value change signal RTT_C according to the logic level combination of the setting code OP. Therefore, in order to stably control the level change of the chip select signal CS_n after the semiconductor device enters self-refresh operation, when the semiconductor device enters self-refresh operation, the operation control circuit 217 can adjust the value of the termination resistor RTT coupled to the chip select signal receiver 205 that receives the chip select signal CS_n. This prevents malfunctions caused by level changes of the chip select signal CS_n during self-refresh operation.

[0049] The operation control circuit 217 can control the activation state of the enable signal EN based on the command pulse SREP, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. When the first internal chip select signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is activated, the operation control circuit 217 can deactivate the enable signal EN. That is, after a delay time has elapsed since the semiconductor device entered self-refresh operation, the operation control circuit 217 can disable the first receiver 207 and the terminating resistor included in the ODT circuit 203 based on the deactivated enable signal EN. Figure 3Therefore, after a delay has elapsed since the semiconductor device has entered the self-refresh operation, the operation control circuit 217 can switch the first receiver 207 of the chip select signal receiver 205 to the second receiver 209 of the chip select signal receiver 205, and can disable the terminating resistor RTT coupled to the chip select signal receiver 205, thereby reducing the power consumed during the self-refresh operation period. When the logic level of the second internal chip select signal ICS2 changes from the second logic level to the first logic level after the self-refresh operation ends, the operation control circuit 217 can activate the enable signal EN. That is, when the self-refresh operation has ended, the operation control circuit 217 can enable the terminating resistor RTT and the first receiver 207 based on the activated enable signal EN.

[0050] Internal circuitry 219 may include multiple memory cells (not shown). Internal circuitry 219 may perform refresh operations on multiple memory cells during the period when the internal self-refresh signal ISREF is activated.

[0051] Figure 3 It is shown Figure 2 A diagram illustrating an example of the ODT circuit 203 is shown. Figure 3 As shown, the ODT circuit 203 may include an internal setup code generation circuit (IOP GEN) 221, a termination driver 223, and a termination resistor RTT.

[0052] The internal setting code generation circuit 221 can generate an internal setting code IOP based on the setting code OP and the resistor value change signal RTT_C. When the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit 221 can output the setting code OP as the internal setting code IOP. That is, when the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit 221 can generate an internal setting code IOP with the same logic level combination as the setting code OP. For example, when the resistor value change signal RTT_C is deactivated, the internal setting code generation circuit 221 can set the logic level combination of the internal setting code IOP to "H, H, H", which is equal to the logic level combination of the setting code OP. When the resistor value change signal RTT_C is activated, the internal setting code generation circuit 221 can set the combination of the internal setting code IOP to a preset combination. In different embodiments, the preset logic level combination can be set to various combinations. For example, when the resistor value change signal RTT_C is activated, the internal setting code generation circuit 221 can set the logic level combination of the internal setting code IOP to "H, L, L", regardless of the logic level combination of the setting code OP. (Refer to the following...) Figure 4 and Figure 5Describe the configuration and operation method of the internal setting code generation circuit 221.

[0053] Termination driver 223 may include switching elements 223_1, 223_2, and 223_3. In different embodiments, the number of switching elements may be set to various values. Switching element 223_1 may be coupled between a terminal of the supply voltage VDD and an internal node nd11. Switching element 223_2 may be coupled between a terminal of the supply voltage VDD and an internal node nd12. Switching element 223_3 may be coupled between a terminal of the supply voltage VDD and an internal node nd13. In different embodiments, one end of each switching element may be coupled to a terminal of the ground voltage VSS. The logic level combination of the internal set code IOP can determine whether to turn on the switching elements 223_1 to 223_3 included in termination driver 223. For example, when the logic level combination of the internal set code IOP is "H, H, H", all switching elements 223_1 to 223_3 can be turned on. For example, when the logic level combination of the internal setting code IOP is "H, L, L", switch element 223_1 can be turned on, while switch elements 223_2 and 223_3 can be turned off. That is to say, the driving capability of the termination driver 223 can be adjusted according to the logic level combination of the internal setting code IOP.

[0054] The terminating resistor RTT may include resistive elements R1, R2, and R3. The number of resistive elements can vary in different implementations. In different implementations, the resistance values ​​of resistive elements R1, R2, and R3 can be set to various values. Resistor element R1 may be coupled between the internal node nd11 and the receiving node nd_RX of the receiving chip select signal CS_n. Resistor element R2 may be coupled between the receiving node nd_RX and the internal node nd12. Resistor element R3 may be coupled between the receiving node nd_RX and the internal node nd13. The value of the terminating resistor RTT can be adjusted according to whether the switching elements 223_1 to 223_3 are turned on. The terminating resistor RTT can be enabled during the period when the enable signal EN is activated. More specifically, when the enable signal EN is activated, resistive elements R1 to R3 can be enabled and can have their own resistance values. When the enable signal EN is deactivated, resistive elements R1 to R3 can be disabled to remain in a high impedance (High-Z) state.

[0055] Figure 4 It is shown Figure 3 The circuit diagram shown is an example of the internal setting code generation circuit 221. Figure 4As shown, the internal set code generation circuit 221A may include NOR gates 221A_1, 221A_2, and 221A_3, and inverters 221A_4, 221A_5, and 221A_6. When the resistor value change signal RTT_C is deactivated to a logic low level, NOR gate 221A_1 and inverter 221A_4 can buffer the first bit OP of the set code. <1> Furthermore, the output buffer bits are used as the first bit of the internal set code (IOP). <1> When the resistor value change signal RTT_C is activated to a logic high level, the NOR gate 221A_1 and the inverter 221A_4 can convert the first bit of the internal set code IOP. <1> Set to logic high. The operation of NOR gate 221A_2 and inverter 221A_5, as well as the operation of NOR gate 221A_3 and inverter 221A_6, can be implemented in the same way as NOR gate 221A_1 and inverter 221A_4.

[0056] Figure 5 It is shown Figure 3 The circuit diagram shows another example of the internal setting code generation circuit 221. (See diagram for another example.) Figure 5 As shown, the internal setting code generation circuit 221B may include inverters 221B_1, 221B_5, 221B_6, and 221B_7, and NAND gates 221B_2, 221B_3, and 221B_4. Inverter 221B_1 can invert and buffer the resistor value change signal RTT_C, and can output an inverted and buffered signal as the inverted resistor value change signal RTT_CB. When the inverted resistor value change signal RTT_CB is at a logic high level, NAND gate 221B_2 and inverter 221B_5 can buffer the first bit OP of the setting code. <1> Furthermore, the output buffer bits are used as the first bit of the internal set code (IOP). <1> When the inverting resistor value change signal RTT_CB is at a logic low level, NAND gate 221B_2 and inverter 221B_5 can release the first bit of the internal set code IOP. <1> Set to logic low. The operations of NAND gate 221B_3 and inverter 221B_6, as well as NAND gate 221B_4 and inverter 221B_7, are implemented in the same way as NAND gate 221B_2 and inverter 221B_5.

[0057] Figure 6 It is shown Figure 2 The circuit diagram of an example of the first receiver 207 is shown. Figure 6 As shown, the first receiver 207 may include a charge supply circuit 231 and a charge release circuit 233.

[0058] The charge supply circuit 231 may include PMOS transistors 231_1 and 231_2. PMOS transistor 231_1 may be coupled between the terminal of the supply voltage VDD and the internal node nd21. PMOS transistor 231_1 can supply charge to the internal node nd21 according to the voltage level of the internal node nd21. PMOS transistor 231_2 may be coupled between the terminal of the supply voltage VDD and the output node nd22. PMOS transistor 231_2 can supply charge to the output node nd22, which outputs the first internal chip select signal ICS1, according to the voltage level of the internal node nd21.

[0059] The charge release circuit 233 may include NMOS transistors 233_1, 233_2, and 233_3. NMOS transistor 233_1 may be coupled between internal nodes nd21 and nd23 and is turned on according to the chip select signal CS_n. NMOS transistor 233_2 may be coupled between output node nd22 and internal node nd23 and is turned on according to the reference voltage VREF_CS. NMOS transistor 233_3 may be coupled between the ground voltage VSS terminal and internal node nd23. When the enable signal EN is activated to a logic high level, NMOS transistor 233_3 can release the charge from internal node nd23. When the enable signal EN has a logic high level and the chip select signal CS_n has a level higher than the reference voltage VREF_CS, the charge release circuit 233 can increase the amount of charge released from internal node nd21 to be greater than the amount of charge released from output node nd22. Therefore, output node nd22, which outputs the first internal chip select signal ICS1, can be driven to a logic high level. When the enable signal EN is at a logic high level and the chip select signal CS_n is at a level lower than the reference voltage VREF_CS, the charge release circuit 233 can increase the amount of charge released from the output node nd22 to be greater than the amount of charge released from the internal node nd21. Therefore, the output node nd22, which outputs the first internal chip select signal ICS1, can be driven to a logic low level.

[0060] Figure 7 It is shown Figure 2 The circuit diagram of an example of the second receiver 209 is shown. Figure 7 As shown, the second receiver 209 may include a first driving circuit 241 and a second driving circuit 243.

[0061] The first driving circuit 241 may include PMOS transistors 241_1 and 241_2, and NMOS transistors 241_3 and 241_4. PMOS transistor 241_1 may be coupled between the supply voltage VDD terminal and PMOS transistor 241_2, and can be turned on according to the logic level of the inverted self-refresh signal SREFB. The inverted self-refresh signal SREFB can be generated by inverting and buffering the self-refresh signal SREF. PMOS transistor 241_2 may be coupled between PMOS transistor 241_1 and the internal node nd31, and can be turned on according to the level of the chip select signal CS_n. When both PMOS transistors 241_1 and 241_2 are turned on according to both the inverted self-refresh signal SREFB and the chip select signal CS_n, PMOS transistors 241_1 and 241_2 can drive the internal node nd31 to a logic high level. NMOS transistor 241_3 can be coupled between the ground voltage VSS terminal and NMOS transistor 241_4, and can be turned on according to the logic level of the self-refresh signal SREF. NMOS transistor 241_4 can be coupled between internal node nd31 and NMOS transistor 241_3, and can be turned on according to the level of the chip select signal CS_n. When both NMOS transistors 241_3 and 241_4 are turned on according to both the self-refresh signal SREF and the chip select signal CS_n, NMOS transistors 241_3 and 241_4 can drive internal node nd31 to a logic low level.

[0062] The second driving circuit 243 may include a PMOS transistor 243_1 and an NMOS transistor 243_2. The PMOS transistor 243_1 may be coupled between the terminal supplying the voltage VDD and the output node nd32, which outputs the second internal chip select signal ICS2. When the internal node nd31 is driven to a logic low level, the PMOS transistor 243_1 can drive the output node nd32 to a logic high level. The NMOS transistor 243_2 may be coupled between the terminal ground voltage VSS and the output node nd32. When the internal node nd31 is driven to a logic high level, the NMOS transistor 243_2 can drive the output node nd32 to a logic low level.

[0063] Figure 8 It is shown Figure 2 A diagram illustrating an example of the command pulse generation circuit 215. (See diagram for example.) Figure 8 As shown, the command pulse generation circuit 215 may include a first latch circuit (LAT) 251, a second latch circuit (LAT) 253, and a command decoder 255.

[0064] The first latch circuit 251 can latch the internal command address ICA synchronously with the internal clock ICK, and output the latched internal command address ICA as the latch command address ICA_LAT.

[0065] The second latch circuit 253 can latch the first internal chip select signal ICS1 synchronously with the internal clock ICK, and output the latched first internal chip select signal ICS1 as the latch chip select signal ICS_LAT.

[0066] Command decoder 255 can generate a command pulse SREP by decoding the latch command address ICA_LAT based on the latch chip select signal ICS_LAT. More specifically, when the latch chip select signal ICS_LAT has a preset logic level, command decoder 255 can generate a command pulse SREP by decoding the latch command address ICA_LAT which has a combination of logic levels for entering the self-refresh operation.

[0067] Figure 9 It is shown Figure 2 A block diagram of an example of the operation control circuit 217 is shown. Figure 9 As shown, the operation control circuit 217 may include a self-refresh control circuit 260 and an internal operation control circuit 270.

[0068] The self-refresh control circuit 260 may include a self-refresh signal generation circuit (SREF GEN) 261 and an internal self-refresh signal generation circuit (ISREF GEN) 263. The self-refresh control circuit 260 may generate a self-refresh signal SREF and an internal self-refresh signal ISREF based on a command pulse SREP, a first internal chip selection signal ICS1, and a second internal chip selection signal ICS2.

[0069] The self-refresh signal generation circuit 261 can generate a self-refresh signal SREF based on the command pulse SREP and the second internal chip selection signal ICS2. The self-refresh signal generation circuit 261 can activate the self-refresh signal SREF synchronously with the deactivation time of the command pulse SREP, which is activated to enter the self-refresh operation. When the logic level of the second internal chip selection signal ICS2 changes from the second logic level to the first logic level after the self-refresh operation ends, the self-refresh signal generation circuit 261 can deactivate the self-refresh signal SREF. The following will refer to... Figure 10 The configuration and operation of the self-refresh signal generation circuit 261 are described in detail.

[0070] The internal self-refresh signal generation circuit 263 can generate an internal self-refresh signal ISREF based on the command pulse SREP, the self-refresh signal SREF, and the first internal chip selection signal ICS1. The internal self-refresh signal generation circuit 263 can activate the internal self-refresh signal ISREF synchronously with the deactivation time of the command pulse SREP, which is activated to enter the self-refresh operation. When the first internal chip selection signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is deactivated, the internal self-refresh signal generation circuit 263 can deactivate the internal self-refresh signal ISREF. That is, when the first internal chip selection signal ICS1 has a preset logic level after an end delay time following the end of the self-refresh operation, the internal self-refresh signal generation circuit 263 can deactivate the internal self-refresh signal ISREF. The following will refer to... Figure 11 The configuration and operation of the internal self-refresh signal generation circuit 263 are described in detail.

[0071] The internal operation control circuit 270 may include an enable signal generation circuit (EN GEN) 271, a flag generation circuit (FLAG GEN) 273, and a resistor value change signal generation circuit (RTT_C GEN) 275. The internal operation control circuit 270 may generate the enable signal EN and the resistor value change signal RTT_C based on the self-refresh signal SREF, the first internal chip selection signal ICS1, and the second internal chip selection signal ICS2.

[0072] The enable signal generation circuit 271 can generate the enable signal EN based on the self-refresh signal SREF, the flag FLAG, the first internal chip select signal ICS1, and the second internal chip select signal ICS2. The flag FLAG can be activated to indicate that the enable signal EN is deactivated, and can also be deactivated to indicate that the enable signal EN is activated. When the self-refresh signal SREF is deactivated, the enable signal generation circuit 271 can activate the enable signal EN. When the first internal chip select signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is activated, the enable signal generation circuit 271 can deactivate the enable signal EN. That is, when the first internal chip select signal ICS1 has a preset logic level after a delay time following the semiconductor device entering self-refresh operation, the enable signal generation circuit 271 can deactivate the enable signal EN. When the logic level of the second internal chip select signal ICS2 changes from a second logic level to a first logic level when the flag FLAG is activated, the enable signal generation circuit 271 can activate the enable signal EN. In other words, when the logic level of the second internal chip select signal ICS2 changes from the second logic level to the first logic level after the self-refresh operation ends, based on the flag indicating that the enable signal EN has been deactivated, the enable signal generation circuit 271 can activate the enable signal EN. The following will refer to... Figure 12 The configuration and operation of the enable signal generation circuit 271 are described in detail.

[0073] The flag generation circuit 273 can generate a flag based on the enable signal EN and the second internal chip select signal ICS2. When the enable signal EN is deactivated, the second internal chip select signal ICS2 has a second logic level, the flag generation circuit 273 can activate the flag to indicate that the enable signal EN is deactivated. When the enable signal EN is activated, the flag generation circuit 273 can deactivate the flag to indicate that the enable signal EN is activated. (Refer to the following...) Figure 13 The configuration and operation of the flag generation circuit 273 are described in detail.

[0074] The resistor value change signal generation circuit 275 can generate a resistor value change signal RTT_C based on the self-refresh signal SREF and the flag FLAG. When the self-refresh signal SREF is activated while the flag FLAG is deactivated, the resistor value change signal generation circuit 275 can activate the resistor value change signal RTT_C. That is, when the self-refresh signal SREF is activated based on the flag FLAG indicating that the enable signal EN is activated, the resistor value change signal generation circuit 275 can activate the resistor value change signal RTT_C. When the flag FLAG is activated, the resistor value change signal generation circuit 275 can deactivate the resistor value change signal RTT_C. In other words, the resistor value change signal generation circuit 275 can deactivate the resistor value change signal RTT_C based on the flag FLAG indicating that the enable signal EN is deactivated. The following will refer to... Figure 14 Provide a detailed description of the configuration and operation of the resistor value changing signal generation circuit 275.

[0075] Figure 10 It is shown Figure 9 The circuit diagram shows an example of the self-refresh signal generation circuit 261. Figure 10 As shown, the self-refresh signal generation circuit 261 may include a first pulse generation circuit 281 and a first activation control circuit 283.

[0076] When the logic level of the second internal chip select signal ICS2 changes from logic low to logic high after the self-refresh operation ends, the first pulse generation circuit 281 can generate a first self-refresh end pulse SPXP1 with a logic low level. The first pulse generation circuit 281 can be implemented as inverters 281_1, 281_2, and 281_3 and a NAND gate 281_4.

[0077] The first activation control circuit 283 can control the activation state of the self-refresh signal SREF based on the first self-refresh end pulse SRXP1 and the command pulse SREP for entering the self-refresh operation. The first activation control circuit 283 can activate the self-refresh signal SREF to a logic high level synchronously with the time point at which the command pulse SREP, which is activated to a logic high level, is deactivated to a logic low level. When the first self-refresh end pulse SRXP1 has a logic low level, the first activation control circuit 283 can deactivate the self-refresh signal SREF to a logic low level. The first activation control circuit 283 may include inverters 283_1 and 283_5, and NAND gates 283_2, 283_3, and 283_4. Inverter 283_1 can invert and buffer the command pulse SREP, and output the inverted and buffered pulse to internal node nd41. When internal node nd41 is driven to a logic low level, NAND gates 283_2 and 283_3 can drive internal node nd42 to a logic high level. When the first self-refresh end pulse SRXP1 is at a logic low level, NAND gates 283_2 and 283_3 can drive internal node nd42 to a logic low level. NAND gates 283_2 and 283_3 can also initialize internal node nd42 to a logic low level during the initialization operation based on the reset signal RSTB, which is at a logic low level. When internal node nd41 is driven to a logic low level, NAND gate 283_4 and inverter 283_5 can set the self-refresh signal SREF to a logic low level. When internal node nd41 is driven to a logic high level, NAND gate 283_4 and inverter 283_5 can buffer the signal of internal node nd42 and output the buffered signal as the self-refresh signal SREF.

[0078] Figure 11 It is shown Figure 9 The circuit diagram shown is an example of the internal self-refresh signal generation circuit 263. Figure 11 As shown, the internal self-refresh signal generation circuit 263 may include a second pulse generation circuit 291 and a second activation control circuit 293.

[0079] When the first internal chip select signal ICS1 is at a logic low level during the period when the self-refresh signal SREF is deactivated to a logic low level, the second pulse generation circuit 291 can generate a second self-refresh end pulse SRXP2 with a logic low level. The second pulse generation circuit 291 can be implemented as inverters 291_1 and 291_2 and NAND gate 291_3.

[0080] The second activation control circuit 293 can control the activation state of the internal self-refresh signal ISREF based on the second self-refresh end pulse SRXP2 and the command pulse SREP for entering the self-refresh operation. The second activation control circuit 293 can activate the internal self-refresh signal ISREF to a logic high level synchronously with the time point at which the command pulse SREP, which is activated to a logic high level, is deactivated to a logic low level. When the second self-refresh end pulse SRXP2 has a logic low level, the second activation control circuit 293 can deactivate the internal self-refresh signal ISREF to a logic low level. The second activation control circuit 293 may include inverters 293_1 and 293_5 and NAND gates 293_2, 293_3 and 293_4. The operation method of the second activation control circuit 293 can be... Figure 10 The operation of the first activation control circuit 283 shown is implemented in the same way.

[0081] Figure 12 It is shown Figure 9 The circuit diagram shows an example of the enable signal generation circuit 271. Figure 12 As shown, the enable signal generation circuit 271 may include a third pulse generation circuit 301 and a third activation control circuit 303.

[0082] When the logic level of the second internal chip select signal ICS2 changes from logic low to logic high after the self-refresh operation ends, based on the flag indicating that the enable signal EN is deactivated (which has a logic high level), the third pulse generation circuit 301 can generate a third self-refresh end pulse SRXP3 with a logic low level. The third pulse generation circuit 301 can be implemented as inverters 301_1, 301_2, 301_3, and 301_5, and NAND gates 301_4 and 301_6.

[0083] The third activation control circuit 303 can control the activation state of the enable signal EN based on the self-refresh signal SREF, the first internal chip select signal ICS1, and the third self-refresh end pulse SRXP3. The third activation control circuit 303 can activate the enable signal EN to a logic high level during the period when the self-refresh signal SREF is deactivated to a logic low level. When the first internal chip select signal ICS1 is at a logic low level during the period when the self-refresh signal SREF is activated to a logic high level, the third activation control circuit 303 can deactivate the enable signal EN to a logic low level. When the third self-refresh end pulse SRXP3 is at a logic low level, the third activation control circuit 303 can activate the enable signal EN to a logic high level. The third activation control circuit 303 may include NAND gates 303_1, 303_3, and 303_4, and inverters 303_2, 303_5, and 303_6. When the self-refresh signal SREF or the third self-refresh end pulse SRXP3 is at a logic low level, NAND gate 303_1 and inverter 303_2 can drive internal node nd61 to a logic low level. When internal node nd61 is driven to a logic low level, NAND gates 303_3 and 303_4 can drive internal node nd62 to a logic high level. When both the self-refresh signal SREF and the third self-refresh end pulse SRXP3 are at a logic high level, NAND gate 303_1 and inverter 303_2 can drive internal node nd61 to a logic high level. When internal node nd61 is driven to a logic high level and the first internal chip select signal ICS1 is at a logic low level, NAND gates 303_3 and 303_4 can drive internal node nd62 to a logic low level. NAND gates 303_3 and 303_4 can initialize internal node nd62 to a logic high level during initialization operation based on the reset signal RSTB, which is at a logic low level. Inverters 303_5 and 303_6 can buffer the signal of the internal node nd62 and output the buffered signal as the enable signal EN.

[0084] Figure 13 It is shown Figure 9 The circuit diagram shown is an example of the flag generation circuit 273. Figure 13 As shown, the flag generation circuit 273 may include a fourth pulse generation circuit 311 and a fourth activation control circuit 313.

[0085] The fourth pulse generation circuit 311 can generate the internal pulse IPUL based on the enable signal EN and the second internal chip selection signal ICS2. When the enable signal EN is activated to a logic high level, the fourth pulse generation circuit 311 can drive the internal pulse IPUL to a logic low level. When the enable signal EN is deactivated to a logic low level and the second internal chip selection signal ICS2 is at a logic low level, the fourth pulse generation circuit 311 can drive the internal pulse IPUL to a logic high level. The fourth pulse generation circuit 311 can be implemented as a NOR gate 311_1.

[0086] The fourth activation control circuit 313 can control the activation state of the flag based on the enable signal EN and the internal pulse IPUL. When the enable signal EN is activated to a logic high level, the fourth activation control circuit 313 can deactivate the flag to a logic low level. When the internal pulse IPUL is at a logic high level, the fourth activation control circuit 313 can activate the flag to a logic high level. The fourth activation control circuit 313 may include inverters 313_1, 313_4, and 313_5, and NAND gates 313_2 and 313_3. When the enable signal EN is at a logic high level, inverter 313_1 can drive the internal node nd71 to a logic low level. When the internal node nd71 is driven to a logic low level, NAND gates 313_2 and 313_3 can drive the internal node nd72 to a logic high level. When the internal pulse IPUL is at a logic high level, inverter 313_4 can drive the internal node nd73 to a logic low level. When internal node nd73 is driven to logic low, NAND gates 313_2 and 313_3 can drive internal node nd72 to logic low. Inverter 313_5 can invert and buffer the signal of internal node nd72, and output the inverted and buffered signal as a flag.

[0087] Figure 14 It is shown Figure 9 The circuit diagram shown is an example of a resistor value changing signal generation circuit 275. Figure 14 As shown, the resistor value change signal generation circuit 275 may include inverters 275_1 and 275_3 and a NAND gate 275_2. Inverter 275_1 can generate an inverted flag FLAGB by inverting and buffering a flag FLAG. The inverted flag FLAGB can have a logic high level to indicate an enable signal ( Figure 9 The enable signal (EN) is activated. The inverted flag (FLAB) can be logic low to indicate that the enable signal (EN) is deactivated. When the self-refresh signal (SREF) is activated to a logic high level and the inverted flag (FLAB) is logic high to indicate that the enable signal (EN) is deactivated. Figure 9When the enable signal EN is activated, NAND gate 275_2 and inverter 275_3 can activate the resistor value change signal RTT_C to a logic high level. When the inverting flag FLAGB has a logic low level to indicate that the enable signal EN is deactivated, NAND gate 275_2 and inverter 275_3 can deactivate the resistor value change signal RTT_C to a logic low level.

[0088] Figure 15 It is used to describe when Figure 2 The timing diagram shows the operations performed when the semiconductor device 120 enters a self-refresh operation. For example... Figure 15 As shown, the semiconductor device 120 can be controlled by the controller ( Figure 1 (110) Receive clock CK, chip select signal CS_n, and command address CA. The preset level of chip select signal CS_n can be set to the level of supply voltage VDD, the first target level of chip select signal CS_n can be set between the level of supply voltage VDD and half of the level of supply voltage VDD, and the second target level of chip select signal CS_n can be set to the level of ground voltage VSS.

[0089] In step S11, when the level of the chip select signal CS_n changes from a preset level to a first target level, causing the semiconductor device to enter a self-refresh operation, the first receiver 207 can set the first internal chip select signal ICS1 to a preset logic level by comparing the level of the chip select signal CS_n with the level of the reference voltage VREF_CS.

[0090] In step S13, when the first internal chip selection signal ICS1 has a preset logic level, the command pulse generation circuit 215 can generate a command pulse SREP from the command address CA which has a combination of logic levels for entering the self-refresh operation.

[0091] In step S15, the operation control circuit 217 can activate the self-refresh signal SREF and the internal self-refresh signal ISREF based on the command pulse SREP. The operation control circuit 217 can enable the second receiver 209 based on the activated self-refresh signal SREF. In step S17, the operation control circuit 217 can activate the resistor value change signal RTT_C based on the activated self-refresh signal SREF, used to change the termination resistor ( Figure 3 The RTT value is adjusted to the preset value.

[0092] Figure 16 It is used to describe when in Figure 2 The timing diagram shows the operations performed by the semiconductor device 120 after a delay time td1 following a self-refresh operation.

[0093] In step S21, when the level of the chip select signal CS_n changes from a preset level to a second target level after a delay time td1 after the semiconductor device has entered the self-refresh operation, the first receiver 207 can set the first internal chip select signal ICS1 to a preset logic level by comparing the level of the chip select signal CS_n with the level of the reference voltage VREF_CS.

[0094] In step S23, when the first internal chip selection signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is activated, the operation control circuit 217 can deactivate the enable signal EN to disable the first receiver 207 and the termination resistor. Figure 3 Therefore, after a delay time td1 has elapsed since the semiconductor device has entered self-refresh operation, the operation control circuit 217 can switch the first receiver 207 of the chip select signal receiver 205 to the second receiver 209 of the chip select signal receiver 205.

[0095] In step S25, when the level of the chip selection signal CS_n changes from a preset level to a second target level after a delay time td1 after the semiconductor device has entered the self-refresh operation, the second receiver 209 can change the logic level of the second internal chip selection signal ICS2 from the first logic level to the second logic level.

[0096] In step S27, when the logic level of the second internal chip selection signal ICS2 changes from the first logic level to the second logic level during the period when the enable signal EN is deactivated, the operation control circuit 217 can activate the flag ( Figure 9 (FLAG). In step S29, when the flag is activated, the operation control circuit 217 can deactivate the resistor value change signal RTT_C to terminate the resistor (FLAG). Figure 3 The value of RTT is set to the value set by the mode register 201.

[0097] Figure 17 It is used to describe when Figure 2 The timing diagram shows the operations performed when the semiconductor device 120 finishes its self-refresh operation.

[0098] In step S31, when the level of the chip selection signal CS_n changes from the second target level to the preset level, causing the semiconductor device to end the self-refresh operation, the second receiver 209 can change the logic level of the second internal chip selection signal ICS2 from the second logic level to the first logic level.

[0099] In step S33, when the logic level of the second internal chip selection signal ICS2 changes from the second logic level to the first logic level, the operation control circuit 217 can deactivate the self-refresh signal SREF. The operation control circuit 217 can disable the second receiver 209 based on the deactivated self-refresh signal SREF. Furthermore, in step S33, when the logic level of the second internal chip selection signal ICS2 changes from the second logic level to the first logic level, the operation control circuit 217 can, based on the activated flag (… Figure 9 The FLAG signal activates the enable signal EN to enable the first receiver 207 and the termination resistor. Figure 3 (RTT). Therefore, when the semiconductor device finishes its self-refresh operation, the operation control circuit 217 can switch the second receiver 209 of the chip select signal receiver 205 to the first receiver 207 of the chip select signal receiver 205.

[0100] In step S35, when the enable signal EN is activated, the operation control circuit 217 can deactivate the activated flag FLAG.

[0101] Figure 18 It is used to describe when in Figure 2 The timing diagram shows the operations performed by the semiconductor device 120 after it has entered a self-refresh operation and after an end delay time td2.

[0102] In step S41, when the level of the chip select signal CS_n changes from a preset level to a first target level after an end delay time td2 following the completion of the self-refresh operation of the semiconductor device, the first receiver 207 can compare the level of the chip select signal CS_n with the level of the reference voltage VREF_CS and set the first internal chip select signal ICS1 to a preset logic level.

[0103] In step S43, when the first internal chip selection signal ICS1 has a preset logic level during the period when the self-refresh signal SREF is deactivated, the operation control circuit 217 can deactivate the internal self-refresh signal ISREF.

[0104] As described above, the semiconductor device according to this embodiment can adjust the value of the terminating resistor coupled to the receiver receiving the chip selection signal when the semiconductor device enters a self-refresh operation, thereby stably controlling the level change of the chip selection signal and preventing malfunctions caused by level changes of the chip selection signal during the self-refresh operation. Furthermore, after a delay time has elapsed since the semiconductor device entered the self-refresh operation, the semiconductor device can switch the receiver receiving the chip selection signal and disable the terminating resistor coupled to the receiver receiving the chip selection signal, thereby reducing the power consumed during the self-refresh operation.

[0105] According to some implementations, when a semiconductor device enters a self-refresh operation, the semiconductor device can adjust the value of the terminating resistor coupled to the receiver that receives the chip select signal to stably control the level change of the chip select signal, thereby preventing malfunctions caused by the level change of the chip select signal during the self-refresh operation.

[0106] Furthermore, after a delay has elapsed since the semiconductor device entered self-refresh operation, the semiconductor device can switch the receiver that receives the chip select signal and disable the terminating resistor coupled to the receiver that receives the chip select signal, thereby reducing the power consumed during the self-refresh operation period.

[0107] Although some embodiments of this teaching have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions and substitutions are possible without departing from the scope and spirit of this teaching as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The first receiver receives a chip selection signal from a receiving node coupled to a terminating resistor and generates a first internal chip selection signal. The command pulse generation circuit generates a command pulse for entering the self-refresh operation based on the internal command address and the first internal chip selection signal. as well as The operation control circuit generates a resistor value change signal that adjusts the value of the termination resistor when the semiconductor device enters the self-refresh operation based on the command pulse; Specifically, when the level of the chip selection signal changes from a preset level to a first target level so that the semiconductor device enters the self-refresh operation, the first receiver sets the logic level of the first internal chip selection signal to the preset logic level.

2. The semiconductor device of claim 1, further comprising an on-chip terminated ODT circuit, the ODT circuit including the termination resistor. in, The ODT circuit: When the resistor value change signal is activated, the value of the terminating resistor is set to a preset value, and When the resistor value change signal is deactivated, the value of the terminating resistor is set to the value set by the mode register.

3. The semiconductor device according to claim 1, wherein, The first receiver is implemented as a differential amplifier, which amplifies the difference between the level of the chip selection signal and the level of the reference voltage, and drives the output node that outputs the first internal chip selection signal. The reference voltage level is set to be between the preset level and the first target level.

4. The semiconductor device according to claim 1, wherein, When the first internal chip selection signal has the preset logic level, the command pulse generation circuit generates the command pulse by decoding the internal command address having a combination of logic levels for entering the self-refresh operation.

5. The semiconductor device according to claim 1, wherein, After a delay following the semiconductor device's self-refresh operation, when the level of the chip selection signal changes from the preset level to the second target level, the first receiver sets the logic level of the first internal chip selection signal to the preset logic level. The difference between the preset level and the second target level is set to be greater than the difference between the preset level and the first target level.

6. The semiconductor device according to claim 5, wherein, The operation control circuit: When the semiconductor device enters the self-refresh operation based on the command pulse, the self-refresh signal is activated, and During the period when the self-refresh signal is activated, when the first internal chip select signal has the preset logic level, the termination resistor and the first receiver are disabled.

7. The semiconductor device of claim 1, further comprising a second receiver, the second receiver receiving the chip selection signal from the receiving node and generating a second internal chip selection signal.

8. The semiconductor device according to claim 7, wherein, The second receiver is implemented as a complementary metal-oxide-semiconductor (CMOS) buffer, which drives the output node of the second internal chip selection signal according to the level of the chip selection signal.

9. The semiconductor device according to claim 7, wherein, The operation control circuit enables the second receiver when the semiconductor device enters the self-refresh operation based on the command pulse.

10. The semiconductor device according to claim 7, wherein, When the level of the chip selection signal changes from the preset level to the second target level after a delay time following the self-refresh operation of the semiconductor device, the second receiver changes the logic level of the second internal chip selection signal from the first logic level to the second logic level.

11. The semiconductor device according to claim 10, wherein, When the logic level of the second internal chip selection signal changes from the first logic level to the second logic level, the operation control circuit deactivates the resistor value change signal.

12. The semiconductor device according to claim 10, wherein, When the level of the chip selection signal changes from the second target level to the preset level so that the semiconductor device ends the self-refresh operation, the second receiver changes the logic level of the second internal chip selection signal from the second logic level to the first logic level.

13. The semiconductor device according to claim 12, wherein, When the logic level of the second internal chip selection signal changes from the second logic level to the first logic level, the operation control circuit enables the terminating resistor and the first receiver.

14. The semiconductor device according to claim 12, wherein, When the logic level of the second internal chip selection signal changes from the second logic level to the first logic level, the operation control circuit disables the second receiver.

15. A semiconductor device, comprising: The operation control circuit generates a resistor value change signal when the level of the chip selection signal changes to cause the semiconductor device to enter self-refresh operation. as well as The on-chip termination ODT circuit includes a termination resistor coupled to a receiving node that receives the chip select signal, and adjusts the value of the termination resistor based on the resistor value change signal; wherein, when the level of the chip select signal changes from a preset level to a first target level so that the semiconductor device enters the self-refresh operation, the operation control circuit activates the resistor value change signal.

16. The semiconductor device according to claim 15, wherein, When the resistor value change signal is activated, the ODT circuit adjusts the value of the terminating resistor from the value set by the mode register to a preset value.

17. The semiconductor device according to claim 15, wherein, When the level of the chip selection signal changes from the preset level to the second target level, causing the semiconductor device to enter the self-refresh operation, the operation control circuit deactivates the resistor value change signal. The difference between the preset level and the second target level is set to be greater than the difference between the preset level and the first target level.

18. The semiconductor device according to claim 17, wherein, When the resistor value change signal is deactivated, the ODT circuit sets the value of the terminating resistor to the value set by the mode register.

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