Single photon avalanche photodiode and method for manufacturing the same

Abstract

The application provides a single photon avalanche photodiode and a preparation method thereof. The photodiode comprises a semiconductor substrate, a deep trench region extending from a first main surface of the semiconductor substrate to the inside of the semiconductor substrate, a cathode region comprising a first cathode part arranged on the first main surface of the semiconductor substrate and a second cathode part arranged on the outer circumferential side of the deep trench region and extending to the inside of the semiconductor substrate along the deep trench region, a buffer region comprising a first buffer part arranged on the outer circumferential side and below the first cathode part and a second buffer part arranged on the outer circumferential side of the second cathode part, a contact area of the buffer region and the cathode region forming an avalanche region, an anode region arranged on the upper part of the semiconductor substrate, and a photoelectric signal conversion region arranged in the inside of the semiconductor substrate. The single photon avalanche photodiode has the advantage of low time jitter, and the time-of-flight sensor adopting the single photon avalanche photodiode has high ranging accuracy.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of sensors, and particularly relates to a single-photon avalanche photodiode with low time jitter in a time-of-flight sensor device and a preparation method thereof. BACKGROUND

[0002] A time-of-flight sensor is an important part of a ranging device, which can capture three-dimensional (3D) distance information of a target object and obtain a 3D image; and is widely used in behavior analysis, monitoring, automatic driving of a car, artificial intelligence, machine vision perception and image 3D enhancement.

[0003] A time-of-flight sensor measures the travel time of light from a light source emission end to a target object reflection and then to a sensor receiving end by using a time-of-flight method, so as to determine distance information of the target object.

[0004] A time-of-flight sensor can directly obtain the travel time of light, which is called a direct time-of-flight sensor; the direct time-of-flight sensor uses a single-photon avalanche photodiode to detect a light pulse signal; the single-photon avalanche photodiode converts a received light signal into a photoelectric charge in a photoelectric signal conversion zone, the photoelectric charge moves to an avalanche zone to trigger the single-photon avalanche photodiode to generate an avalanche, a high current signal generated by the avalanche triggers a time-to-digital converter to record the time of a time period from emission to acceptance of the light pulse signal, and then distance information is inferred in combination with light speed data.

[0005] However, the existing single-photon avalanche photodiode has a serious time jitter problem, which greatly reduces the ranging accuracy of the time-of-flight sensor detection.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a single-photon avalanche photodiode and a preparation method thereof, which are used to solve the problem that the existing single-photon avalanche photodiode has a serious time jitter problem, thereby greatly reducing the ranging accuracy of the time-of-flight sensor detection.

[0008] To achieve the above and other related objectives, the present invention provides a single-photon avalanche photodiode, comprising: a semiconductor substrate including a first main surface and a second main surface opposite to each other; a deep trench region extending from the first main surface of the semiconductor substrate into the interior of the semiconductor substrate, the deep trench region being filled with a filler; a cathode region including a first cathode portion disposed on the first main surface of the semiconductor substrate and a second cathode portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate; a buffer zone including a first buffer portion disposed on the outer periphery and below the first cathode portion and a second buffer portion disposed on the outer periphery of the second cathode portion, the contact area between the buffer zone and the cathode region forming an avalanche region; an anode region disposed on the upper part of the semiconductor substrate, located on the outer periphery of the first buffer portion; and a photoelectric signal conversion region disposed below the first buffer portion and on the outer periphery of the second buffer portion.

[0009] Optionally, the width of the deep trench region is 0.1 micrometer to 0.3 micrometers, and the depth is greater than or equal to 0.5 micrometers. The filling material in the deep trench region includes one of oxides, nitrides, polycrystalline silicon, and metals.

[0010] Optionally, the thickness of the cathode region is greater than or equal to 0.1 micrometers, and the ion doping concentration is greater than or equal to 1e18atom / cm. 3 The doped ions include one or a mixture of two of the following: arsenic ions and phosphorus ions.

[0011] Optionally, the width of the anode region is greater than or equal to 0.1 micrometers, the depth is greater than or equal to 0.1 micrometers, and the ion doping concentration is greater than or equal to 1e18 atom / cm. 3 The doping ions include boron ions; and / or, the thickness of the buffer is 0.05 μm to 0.3 μm, and the ion doping concentration is 1e15 atom / cm³. 3 ~1e19atom / cm 3 The doped ions include boron ions.

[0012] Optionally, a first voltage is applied to the cathode region, and a second voltage is applied to the anode region. The difference between the first voltage and the second voltage is greater than or equal to the avalanche voltage of the single-photon avalanche photodiode.

[0013] Optionally, it further includes a pixel isolation region disposed in the semiconductor substrate below the anode region, and the anode region is in contact with the buffer. The pixel isolation region is an ion-doped isolation region with the same doping type as the buffer, and the doping concentration of the pixel isolation region is greater than the doping concentration of the buffer, so as to form an additional driving electric field for the movement of photoelectric charges in the semiconductor substrate toward the buffer.

[0014] Optionally, the single-photon avalanche photodiode receives light signals via either a first principal surface incident or a second principal surface incident; and / or, the planar structure of the deep trench region includes one of a polygon, a circle, and an ellipse.

[0015] Optionally, each of the single-photon avalanche photodiodes includes two or more deep trench regions, which are centrally or axially symmetrically distributed in the single-photon avalanche photodiode.

[0016] Optionally, the semiconductor substrate has a target region, wherein the horizontal distance from the photoelectric charge generated in the target region to the second buffer portion is less than the vertical distance from the photoelectric charge to the first buffer portion, wherein the upper edge of the target region extends from the center of the second cathode portion in the vertical direction to the bottom edge of the semiconductor substrate on the corresponding side.

[0017] The present invention also provides a time-of-flight sensor comprising a single-photon avalanche photodiode as described in any of the above claims.

[0018] The present invention also provides a ranging device comprising the time-of-flight sensor described above.

[0019] This invention also provides a method for fabricating a single-photon avalanche photodiode, the method comprising the steps of: providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to each other, forming a photoelectric signal conversion region and an anode region in the semiconductor substrate; forming a deep trench region in the semiconductor substrate; implanting first doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region using a first tilted ion implantation process to form a buffer zone, the buffer zone including a first buffer portion disposed on the first main surface of the semiconductor substrate and a second buffer portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate; implanting second doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region using a second tilted ion implantation process, the implantation depth being less than the implantation depth of the first doped ions, to form a cathode region in the buffer zone, the cathode region including a first cathode portion disposed on the first main surface of the semiconductor substrate and a second cathode portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate, the contact area between the buffer zone and the cathode region forming an avalanche region; and forming a filler in the deep trench region.

[0020] Optionally, implanting first doped ions into the first main surface of the semiconductor substrate and the sidewall of the deep trench region by the first tilted ion implantation process includes: forming a protective layer on the surface of the semiconductor substrate and the surface of the deep trench region; performing multiple first tilted ion implantations into the first main surface of the semiconductor substrate and the sidewall of the deep trench region, wherein the semiconductor substrate is rotated by an angle between adjacent first tilted ion implantations to ensure that the first doped ions are uniformly distributed on the sidewall of the deep trench region.

[0021] Optionally, during two consecutive first tilted ion implantations, the semiconductor substrate is rotated by an angle of α, and the first tilted ion implantation is performed on the first main surface of the semiconductor substrate and the sidewall of the deep trench region a number of times, with the same ion implantation dose and energy each time, where n is a positive integer greater than or equal to 2, and the product of n and α is 360 degrees.

[0022] Optionally, implanting second doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region by the second tilted ion implantation process includes: performing multiple second tilted ion implantations into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region, wherein the semiconductor substrate is rotated by an angle between adjacent second tilted ion implantations to ensure that the second doped ions are uniformly distributed on the sidewalls of the deep trench region.

[0023] Optionally, during two consecutive second tilted ion implantations, the semiconductor substrate is rotated by an angle of β, and the first tilted ion implantation is performed on the first main surface of the semiconductor substrate and the sidewall of the deep trench region a number of times, with the same ion implantation dose and energy each time, where k is a positive integer greater than or equal to 2, and the product of k and β is 360 degrees.

[0024] Optionally, the angle between the ion implantation direction of the first tilted ion implantation process and the second tilted ion implantation process and the first main surface of the semiconductor substrate is 2 to 15 degrees.

[0025] As described above, the single-photon avalanche photodiode and its fabrication method of the present invention have the following beneficial effects:

[0026] The single-photon avalanche photodiode of this invention has an avalanche region extending into the semiconductor substrate. This provides a closer avalanche region within the semiconductor substrate for charge carriers generated in the photoelectric signal conversion region, which is relatively far from the surface avalanche region. This allows charge carriers to rapidly move to the avalanche region within the semiconductor substrate, triggering photodiode avalanche and generating a high avalanche current signal. The single-photon avalanche photodiode of this invention has the advantage of low timing jitter, and time-of-flight sensors using this single-photon avalanche photodiode exhibit high ranging accuracy. Attached Figure Description

[0027] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0028] Figure 1 The diagram shows a cross-sectional structure of a single-photon avalanche photodiode.

[0029] Figure 2 The diagram shown is a cross-sectional structural schematic of a first embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0030] Figure 3 The diagram shown is a planar structural schematic of a first embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0031] Figure 4 The diagram shown is a planar structural schematic of a second embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0032] Figure 5 The diagram shown is a cross-sectional structural schematic of a second embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0033] Figure 6 The diagram shown is a planar structural schematic of a third embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0034] Figure 7 The diagram shown is a planar structural schematic of a fourth embodiment of the single-photon avalanche photodiode according to an embodiment of the present invention.

[0035] Figure 8 The diagram shown is a planar structural schematic of a fifth embodiment of the single-photon avalanche photodiode of the present invention.

[0036] Figure 9 The diagram shown is a planar structural schematic of a sixth embodiment of the single-photon avalanche photodiode of the present invention.

[0037] Figure 10 The diagram shows a method for fabricating a single-photon avalanche photodiode according to an embodiment of the present invention, and a structural schematic diagram of the process steps for generating the deep trench region in the embodiment.

[0038] Figure 11 The diagram shows a method for fabricating a single-photon avalanche photodiode according to an embodiment of the present invention, including a structural schematic of the first tilted ion implantation process step in the embodiment.

[0039] Figure 12The diagram shows a method for fabricating a single-photon avalanche photodiode according to an embodiment of the present invention, including a structural schematic of the second tilted ion implantation process step in the embodiment.

[0040] Figure 13 The diagram shows a method for fabricating a single-photon avalanche photodiode according to an embodiment of the present invention, and a structural schematic diagram of the process steps for filling the deep trench region in the embodiment.

[0041] Figure 14 The diagram shows a method for fabricating a single-photon avalanche photodiode according to an embodiment of the present invention, and a structural schematic diagram of the process steps for generating deep trenches in the embodiment.

[0042] Component designation explanation

[0043] Cathode regions 101 and 201

[0044] 2011 First Cathode Section

[0045] 2012 Second Cathode Section

[0046] 102, 202 Anode Zones

[0047] Buffers 103 and 203

[0048] 2031 First Buffer Section

[0049] 2032 Second Buffer Section

[0050] 104, 204 photoelectric signal conversion areas

[0051] 105 and 205 pixel isolation areas

[0052] 206, 207, 208, 209, 210, Deep trench area 211, 212, 213

[0054] 200 Avalanche Zone

[0055] 21 Protective Layer

[0056] 22 Protective Layer

[0057] 23 Photoresist Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0060] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0061] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0062] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0063] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] Figure 1 The diagram shows a direct time-of-flight sensor structure using a single-photon avalanche photodiode. Figure 1 In the diagram, 101 is the cathode region connected to voltage Vn, 102 is the anode region connected to voltage Vp, 103 is the buffer layer, 104 is the photoelectric signal conversion region, and 105 is the pixel isolation region. When the voltage difference between voltage Vn and voltage Vp reaches the avalanche voltage, the charge near the avalanche region can trigger an avalanche to generate a high current signal.

[0066] like Figure 1As shown, light enters from one side of the photoelectric signal conversion region 104. The incoming light may be converted into charge at point A, or at points B, C, or D. The conversion location from light to charge signal has random statistical uncertainty. Charge converted at points A or B is farther from the avalanche zone and takes longer to reach it; while charge converted at points C or D takes shorter to reach the avalanche zone. Therefore, the charges at points A and B, and the charges at points C and D, will trigger avalanches and generate avalanche signals at different times, thus causing jitter in the sensor's detection time.

[0067] Direct time-of-flight sensors collect optical pulse signals with relatively long wavelengths, typically near-infrared light, such as 940nm. Single-photon avalanche photodiodes (SPADs) have low conversion efficiency for near-infrared light, resulting in a thicker photoelectric signal conversion region (104), for example, 10 micrometers. This thicker region exacerbates time jitter, reducing the sensor's distance detection accuracy. Therefore, minimizing SPAD time jitter is crucial.

[0068] Based on the above, such as Figure 2 As shown, this embodiment provides a single-photon avalanche photodiode, which includes a semiconductor substrate, a deep trench region 206, a cathode region 201, a buffer region 203, and an anode region 202.

[0069] The semiconductor substrate includes a first principal surface and a second principal surface opposite to each other. The semiconductor substrate may be, for example, a semiconductor material such as silicon, germanium, or germanium-silicon.

[0070] like Figure 2 As shown, the deep trench region 206 extends from the first main surface of the semiconductor substrate into the interior of the semiconductor substrate, and the deep trench region 206 is filled with a filler. In one embodiment, the width of the deep trench region 206 is 0.1 micrometers to 0.3 micrometers, and the depth is greater than or equal to 0.5 micrometers. It should be noted that the width of the deep trench region 206 is specifically expressed as the shortest dimension among all dimensions passing through the center of the deep trench region 206. The filler in the deep trench region 206 includes one of oxides, nitrides, polysilicon, and metals. For example, the oxide can be silicon dioxide, and the nitride can be silicon nitride.

[0071] like Figure 2 As shown, the cathode region 201 includes a first cathode portion 2011 disposed on a first main surface of the semiconductor substrate and a second cathode portion 2012 disposed on the outer periphery of the deep trench region 206 and extending along the deep trench region 206 into the interior of the semiconductor substrate. In one embodiment, the thickness of the cathode region 201 is greater than or equal to 0.1 micrometers, and the ion doping concentration is greater than or equal to 1e18atom / cm.3 The doping ions include one or a mixture of arsenic and phosphorus ions. In one embodiment, the cathode region 201 is an N+ type cathode region 201, which is externally connected to a high voltage Vn. The cathode region 201 in this embodiment has a high concentration, which is beneficial for maintaining a substantially consistent potential between the first cathode portion 2011 and the second cathode portion 2022 when Vn is applied to the surface after the cathode region 201 extends into the semiconductor substrate along with the deep trench region 206.

[0072] like Figure 2 As shown, the buffer zone 203 includes a first buffer zone 2031 disposed on the outer periphery and below the first cathode portion 2011, and a second buffer zone 2032 disposed on the outer periphery of the second cathode portion 2012. The contact area between the buffer zone 203 and the cathode region 201 forms an avalanche region 200. In one embodiment, the thickness of the buffer zone 203 is 0.05 micrometers to 0.3 micrometers, and the ion doping concentration is 1e15 atom / cm³. 3 ~1e19atom / cm 3 The doped ions include boron ions.

[0073] like Figure 2 As shown, the anode region 202 is disposed on the upper part of the semiconductor substrate, located on the outer periphery of the first buffer portion 2031; in one embodiment, the width of the anode region 202 is greater than or equal to 0.1 micrometers, the depth is greater than or equal to 0.1 micrometers, the ion doping concentration is greater than or equal to 1e18atom / cm3, and the doped ions include boron ions. In one embodiment, the anode region 202 is a P+ type anode region 202, which is externally connected to a low voltage Vp.

[0074] like Figure 2 As shown, the photoelectric signal conversion region 204 is disposed below the first buffer portion 2031 and on the outer periphery of the second buffer portion 2032. The photoelectric signal conversion region 204 is used to receive optical signals and convert them into photoelectric charge signals. In one embodiment, the photoelectric signal conversion region 204 can be a P-type epitaxial layer on a semiconductor substrate, with a maximum P-type ion concentration of 2e15 atom / cm³. 3 In another embodiment, the photoelectric signal conversion region 204 can also be an N-type region, with a maximum N-type ion concentration of 1e16 atom / cm³. 3 .

[0075] In one embodiment, the cathode region 201 is externally connected to a first voltage, and the anode region 202 is externally connected to a second voltage. The difference between the first voltage and the second voltage is greater than or equal to the avalanche voltage of the single-photon avalanche photodiode. For example, in this example, the N+ type cathode region 201 is externally connected to a high voltage Vn, and the P+ type anode region 202 is externally connected to a low voltage Vp. The difference between the two is at least the avalanche voltage Vbd of the single-photon avalanche photodiode, for example, 25V.

[0076] In one embodiment, the semiconductor substrate has a target region. The horizontal distance from the photoelectric charge generated in the target region to the second buffer portion 2032 is less than the vertical distance from the photoelectric charge to the first buffer portion 2031. The upper edge of the target region extends from the vertical center of the second cathode portion 2012 to the bottom edge of the corresponding semiconductor substrate. For example, in one example, in a longitudinal cross-sectional view, the target region can be regarded as a triangular structure. The vertical center of the second cathode portion 2012 forms one vertex of the triangle, and the outer edges of the bottom of the semiconductor substrates on both sides (e.g., near the pixel isolation region 205) form the other two vertices of the triangle. This allows the photoelectric charge in the target region to reach the avalanche region through the second buffer portion 2032, thereby reducing the timing jitter of the single-photon avalanche photodiode.

[0077] In one embodiment, the single-photon avalanche photodiode further includes a pixel isolation region 205 disposed in the semiconductor substrate below the anode region 202. The pixel isolation region 205 isolates single-photon avalanche photodiodes of adjacent pixels, preventing photoelectric charge crosstalk. The anode region 202 is in contact with the buffer zone 203. The pixel isolation region 205 is an ion-doped isolation region with the same doping type as the buffer zone 203, and the doping concentration of the pixel isolation region 205 is greater than that of the buffer zone. This creates an additional driving electric field for the movement of photoelectric charges from the semiconductor substrate to the buffer zone 203, thereby facilitating photoelectric charge avalanche. In one embodiment, the pixel isolation region 205 is a P-type ion-doped region, where the P-type ion is a boron ion.

[0078] In one embodiment, the single-photon avalanche photodiode receives optical signals via either a first principal surface incidence or a second principal surface incidence.

[0079] In one embodiment, the planar structure of the deep trench region 206 includes one of polygonal, circular, and elliptical shapes. Each single-photon avalanche photodiode may contain two or more deep trench regions 206, which are centrally or axially symmetrically distributed in the single-photon avalanche photodiode.

[0080] Figure 3 This is a schematic diagram of a single-photon avalanche photodiode in this embodiment. The deep trench region 206 is located at the center. The outer periphery of the deep trench region 206 is the cathode region 201. The outer periphery of the cathode region 201 is the buffer zone 203. The outer periphery of the buffer zone 203 is the anode region 202. Below the buffer zone 203 is the pixel isolation region 205. Figure 3 The deep trench area 206 shown has a square planar structure.

[0081] Figure 3 The square deep groove area 206 shown can also be circular, such as... Figure 4 As shown. Figure 3 and Figure 4 In the schematic diagram of the planar structure shown, the structure of the deep trench region 206 can also be rectangular, other polygonal, elliptical, or other regular shapes (not shown in the schematic diagram).

[0082] Figure 5 The cross-sectional structure shown is an embodiment in which two deep trench regions 208 and 209 are provided in the single-photon avalanche photodiode. Figure 5 The cathode region 201, anode region 202, buffer zone 203, photoelectric signal conversion region 204, and pixel isolation region 205 in the illustrated embodiment are... Figure 2 In the illustrated embodiment, the corresponding zone attributes are the same. Figure 5 The two deep trench areas 208 and 209 shown are... Figure 2 The deep trench region 206 shown has the same properties.

[0083] Figure 6 As shown Figure 5 A schematic diagram of the planar structure corresponding to the cross-sectional structure. For example... Figure 6 As shown, the distances from the upper edge and the lower edge of the cathode region 201 of the two deep trench regions 208 and 209 are equal. The distance from the left edge of the cathode region 201 of the deep trench region 208 is equal to the distance from the right edge of the cathode region 201 of the deep trench region 209, and is also equal to the distance between the two deep trench regions 208 and 209. This makes the distance from the charge converted by light at any position inside the photoelectric signal conversion region to the avalanche region relatively short, reducing the time jitter of the single-photon avalanche photodiode.

[0084] Figure 6 The schematic diagram shown contains two deep trench regions 208 and 209. Other single-photon avalanche photodiodes can also contain four deep trench regions, such as... Figure 7 The diagram shown is a plan view. Figure 7As shown, the four deep trench regions 210, 211, 212, and 213 are evenly distributed. The properties of the four deep trench regions 210, 211, 212, and 213 in this embodiment are similar to... Figure 2 The deep trench region 206 shown has the same attributes. For example... Figure 7 As shown, the deep trench regions 210 and 211 are equidistant from the upper edge of the cathode region 201, and the deep trench regions 212 and 213 are equidistant from the lower edge of the cathode region 201; the deep trench regions 210 and 212 are equidistant from the left edge of the cathode region 201, and the deep trench regions 211 and 213 are equidistant from the right edge of the cathode region 201; the deep trench regions 210, 211, 212, and 213 are equidistant from each other and are evenly distributed in region 201.

[0085] Figure 6 The deep trench areas 208 and 209 shown are square in shape, but they can also be circular, such as... Figure 8 As shown, Figure 8 The deep trench areas 208 and 209 shown are... Figure 6 The deep trench regions 208 and 209 shown have the same properties. Deep trench regions 208 and 209 can also be rectangular, polygonal, elliptical or other regular shapes (not shown in the schematic diagram).

[0086] Figure 7 The deep trench areas 210, 211, 212, and 213 shown are square in shape, but they can also be circular, such as... Figure 9 As shown, Figure 9 The deep trench regions 210, 211, 212, and 213 shown are... Figure 7 The deep trench regions 210, 211, 212, and 213 shown have the same properties. The deep trench regions 210, 211, 212, and 213 can also be rectangular, polygonal, elliptical, or other regular shapes (not shown in the schematic diagram).

[0087] Figures 2 to 8 The embodiments shown depict one, two, or four deep trench regions. The embodiments of the present invention are not limited to these examples. Figures 2 to 8 In the illustrated embodiment, the deep trench area may also be three or other quantities.

[0088] This embodiment also provides a time-of-flight sensor, which includes a single-photon avalanche photodiode as described in the above embodiment.

[0089] This embodiment also provides a ranging device, which includes the time-of-flight sensor as described in the above embodiment. The ranging device can be applied, for example, to fields such as analysis, monitoring, autonomous driving, artificial intelligence, machine vision perception, and 3D image enhancement.

[0090] like Figures 10 to 14As shown, this embodiment also provides a method for fabricating a single-photon avalanche photodiode. The method includes the following steps: providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to each other; forming a photoelectric signal conversion region 204 and an anode region 202 in the semiconductor substrate; forming a deep trench region 206 in the semiconductor substrate; implanting first doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region 206 through a first tilted ion implantation process to form a buffer zone 203, the buffer zone 203 including a first buffer portion 2031 disposed on the first main surface of the semiconductor substrate and a buffer portion 2031 disposed on the outer periphery of the deep trench region 206 and extending along the deep trench region 206 to the sidewalls of the deep trench region 206. The semiconductor substrate contains a second buffer region 2032; second doped ions are implanted into the first main surface of the semiconductor substrate and the sidewall of the deep trench region 206 using a second tilted ion implantation process, with the implantation depth being less than that of the first doped ions, to form a cathode region 201 in the buffer region 203. The cathode region 201 includes a first cathode portion 2011 disposed on the first main surface of the semiconductor substrate and a second cathode portion 2012 disposed on the outer periphery of the deep trench region 206 and extending along the deep trench region 206 into the interior of the semiconductor substrate. The contact area between the buffer region 203 and the cathode region 201 forms an avalanche region 200; and a filler is formed in the deep trench region 206.

[0091] In one embodiment, the width of the deep trench region 206 is 0.1 micrometers to 0.3 micrometers, and the depth is greater than or equal to 0.5 micrometers.

[0092] In one embodiment, implanting first doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region 206 by a first tilted ion implantation process includes: forming a protective layer on the surface of the semiconductor substrate and the surface of the deep trench region 206; performing multiple first tilted ion implantations into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region 206, wherein during two adjacent first tilted ion implantations, the semiconductor substrate is rotated by an angle to ensure that the first doped ions are uniformly distributed on the sidewalls of the deep trench region 206.

[0093] In one embodiment, during two consecutive first tilted ion implantations, the semiconductor substrate is rotated by an angle of α, and the number of first tilted ion implantations to the first main surface of the semiconductor substrate and the sidewall of the deep trench region 206 is n times, with the same ion implantation dose and energy each time, where n is a positive integer greater than or equal to 2, and the product of n and α is 360 degrees.

[0094] In one embodiment, implanting second doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region 206 by a second tilted ion implantation process includes: performing multiple second tilted ion implantations into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region 206, wherein the semiconductor substrate is rotated by an angle between adjacent second tilted ion implantations to ensure that the second doped ions are uniformly distributed on the sidewalls of the deep trench region 206.

[0095] In one embodiment, the angle of rotation of the semiconductor substrate during two consecutive second tilted ion implantations is β, and the number of first tilted ion implantations to the first main surface of the semiconductor substrate and the sidewall of the deep trench region 206 is k, with the same ion implantation dose and energy each time, where k is a positive integer greater than or equal to 2, and the product of k and β is 360 degrees.

[0096] In one embodiment, the angle between the ion implantation direction of the first tilted ion implantation process and the second tilted ion implantation process and the first main surface of the semiconductor substrate is 2 to 15 degrees. For example, this angle can be adjusted and selected according to the top opening size of the deep trench, the sidewall tilt angle, etc.

[0097] In one embodiment, a pixel isolation region 205 is further formed in the semiconductor substrate. The pixel isolation region 205 is disposed below the anode region 202 and is used to isolate the single-photon avalanche photodiodes of adjacent pixels to prevent photoelectric charge crosstalk.

[0098] In a specific implementation, the fabrication method of the single-photon avalanche photodiode includes the following steps:

[0099] First, the deep trench region is formed on the semiconductor substrate using a dry etching method, such as... Figure 10 As shown. The specific steps are as follows: a protective layer 21 is deposited on the surface of the semiconductor substrate. The material of the protective layer 21 is an oxide, a nitride, or a combination of both. The thickness of the protective layer 21 is 0.01 micrometers to 0.2 micrometers. Then, photoresist 23 is spin-coated, developed, and plasma etched. The depth of etching on the semiconductor substrate is at least 0.5 micrometers. After etching, the photoresist 23 is cleaned to remove the protective layer 21.

[0100] Next, the buffer 203 is generated, as follows: Figure 11As shown. The specific steps are as follows: an oxide protective layer 22 is formed on the surface of the semiconductor substrate and the surface of the deep trench region by oxidation. The thickness of the oxide protective layer 22 is 0.01 micrometers. Ion implantation is then performed, using boron ions or boron fluoride ions. The ion implantation direction is tilted between 2 and 15 degrees, and a total of four ion implantations are performed, with the same ion implantation dose each time. The rotation angle of the semiconductor substrate relative to the carrier between adjacent ion implantations is 90 degrees. Alternatively, a total of eight ion implantations can be performed, with the same ion implantation dose each time, and the rotation angle of the semiconductor substrate relative to the carrier between adjacent ion implantations is 45 degrees. In the embodiments of this invention, the boron ion implantation energy can be 130–160 keV, and the boron fluoride ion implantation energy can be 350–450 keV.

[0101] Next, the N+ type cathode region 201 is generated, as follows: Figure 12 As shown. The specific steps are as follows: ion implantation is performed, using arsenic ions or phosphorus ions. The ion implantation direction is tilted at 2 to 15 degrees, and a total of four ion implantations are performed, with the same ion implantation dose each time. The rotation angle of the semiconductor substrate relative to the carrier between adjacent ion implantations is 90 degrees. Alternatively, a total of eight ion implantations can be performed, with the same ion implantation dose each time, and the rotation angle of the semiconductor substrate relative to the carrier between adjacent ion implantations is 45 degrees. In the embodiments of the present invention, the energy of arsenic ion implantation can be 170 to 190 keV, and the energy of phosphorus ion implantation can be 80 to 100 keV.

[0102] The next step is to fill the deep trench area, such as... Figure 13 As shown. The specific steps are as follows: a filler material is deposited using a chemical vapor deposition method. The filler material can be an oxide, such as silicon dioxide or titanium dioxide, or a nitride, such as silicon nitride, or polycrystalline silicon or a metal, such as aluminum or copper.

[0103] The next step is to planarize the surface of the semiconductor substrate, such as... Figure 14 As shown, a chemical mechanical polishing process can be used to remove the unwanted material layer on the surface of a semiconductor substrate. This material is the material layer generated when filling deep trench regions.

[0104] As described above, the single-photon avalanche photodiode and its fabrication method of the present invention have the following beneficial effects:

[0105] The single-photon avalanche photodiode of this invention has an avalanche region 200 extending into the semiconductor substrate. This provides a closer avalanche region 200 within the semiconductor substrate for charge carriers generated in the photoelectric signal conversion region 204, which is relatively far from the surface avalanche region 200. This allows the charge carriers to rapidly move to the avalanche region 200 within the semiconductor substrate, triggering photodiode avalanche and generating a high avalanche current signal. The single-photon avalanche photodiode of this invention has the advantage of low timing jitter, and time-of-flight sensors using this single-photon avalanche photodiode exhibit high ranging accuracy.

[0106] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A single-photon avalanche photodiode, characterized in that, The single-photon avalanche photodiode includes: A semiconductor substrate, comprising a first principal surface and a second principal surface opposite to each other; A deep trench region extends from the first main surface of the semiconductor substrate into the interior of the semiconductor substrate, and the deep trench region is filled with a filler. The cathode region includes a first cathode portion disposed on a first main surface of the semiconductor substrate and a second cathode portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate; The buffer zone includes a first buffer portion disposed on the outer periphery and below the first cathode portion and a second buffer portion disposed on the outer periphery of the second cathode portion, wherein the contact area between the buffer zone and the cathode portion forms an avalanche zone; The anode region is disposed on the upper part of the semiconductor substrate, located on the outer periphery of the first buffer portion; The photoelectric signal conversion area is located below the first buffer section and on the outer periphery of the second buffer section.

2. The single-photon avalanche photodiode according to claim 1, characterized in that: The width of the deep trench region is 0.1 micrometer to 0.3 micrometers, and the depth is greater than or equal to 0.5 micrometers. The filling material in the deep trench region includes one of oxides, nitrides, polycrystalline silicon, and metals.

3. The single-photon avalanche photodiode according to claim 1, characterized in that: The thickness of the cathode region is greater than or equal to 0.1 micrometers, and the ion doping concentration is greater than or equal to 1e18atom / cm. 3 The doped ions include one or a mixture of two of the following: arsenic ions and phosphorus ions.

4. The single-photon avalanche photodiode according to claim 1, characterized in that: The anode region has a width greater than or equal to 0.1 micrometers, a depth greater than or equal to 0.1 micrometers, and an ion doping concentration greater than or equal to 1e18 atom / cm². 3 The doping ions include boron ions; and / or, the thickness of the buffer is 0.05 μm to 0.3 μm, and the ion doping concentration is 1e15 atom / cm³. 3 ~1e19 atom / cm 3 The doped ions include boron ions.

5. The single-photon avalanche photodiode according to claim 1, characterized in that: The cathode region is connected to a first voltage, and the anode region is connected to a second voltage. The difference between the first voltage and the second voltage is greater than or equal to the avalanche voltage of the single-photon avalanche photodiode.

6. The single-photon avalanche photodiode according to claim 1, characterized in that: It also includes a pixel isolation region disposed in the semiconductor substrate below the anode region, and the anode region is in contact with the buffer. The pixel isolation region is an ion-doped isolation region with the same doping type as the buffer, and the doping concentration of the pixel isolation region is greater than the doping concentration of the buffer, so as to form an additional driving electric field for the movement of photoelectric charges in the semiconductor substrate to the buffer.

7. The single-photon avalanche photodiode according to claim 1, characterized in that: The single-photon avalanche photodiode receives light signals via either a first principal surface incident or a second principal surface incident; and / or, the planar structure of the deep trench region includes one of a polygon, a circle, and an ellipse.

8. The single-photon avalanche photodiode according to claim 1, characterized in that: Each of the single-photon avalanche photodiodes includes two or more deep trench regions, which are centrally or axially symmetrically distributed in the single-photon avalanche photodiode.

9. The single-photon avalanche photodiode according to any one of claims 1-8, characterized in that: The semiconductor substrate has a target region, and the horizontal distance from the photoelectric charge generated in the target region to the second buffer portion is less than the vertical distance from the photoelectric charge to the first buffer portion. The upper edge of the target region extends from the center of the second cathode portion in the vertical direction to the bottom edge of the semiconductor substrate on the corresponding side.

10. A time-of-flight sensor, characterized in that, The time-of-flight sensor comprises a single-photon avalanche photodiode as described in any one of claims 1 to 9.

11. A ranging device, characterized in that, The ranging device includes the time-of-flight sensor as described in claim 10.

12. A method for fabricating a single-photon avalanche photodiode as described in any one of claims 1-9, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a first main surface and a second main surface opposite to each other, and a photoelectric signal conversion region and an anode region are formed in the semiconductor substrate; A deep trench region is formed in the semiconductor substrate; A first doped ion is implanted into the first main surface of the semiconductor substrate and the sidewall of the deep trench region using a first tilted ion implantation process to form a buffer zone. The buffer zone includes a first buffer portion disposed on the first main surface of the semiconductor substrate and a second buffer portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate. A second doped ion is implanted into the first main surface of the semiconductor substrate and the sidewall of the deep trench region using a second tilted ion implantation process. The implantation depth is less than that of the first doped ion implantation depth to form a cathode region in the buffer zone. The cathode region includes a first cathode portion disposed on the first main surface of the semiconductor substrate and a second cathode portion disposed on the outer periphery of the deep trench region and extending along the deep trench region into the interior of the semiconductor substrate. The contact area between the buffer zone and the cathode region forms an avalanche zone. A filler is formed in the deep trench area.

13. The method for fabricating a single-photon avalanche photodiode according to claim 12, characterized in that: Implanting first doped ions onto the first main surface of the semiconductor substrate and the sidewalls of the deep trench region using a first tilted ion implantation process includes: A protective layer is formed on the surface of the semiconductor substrate and the surface of the deep trench region; Multiple first tilted ion implantations are performed on the first main surface of the semiconductor substrate and the sidewalls of the deep trench region. During two adjacent first tilted ion implantations, the semiconductor substrate is rotated by an angle to ensure that the first doped ions on the sidewalls of the deep trench region are evenly distributed.

14. The method for fabricating a single-photon avalanche photodiode according to claim 13, characterized in that: During two consecutive first tilted ion implantations, the semiconductor substrate rotates by an angle of α, and the number of first tilted ion implantations to the first main surface of the semiconductor substrate and the sidewall of the deep trench region is n. Each ion implantation dose and energy are the same, where n is a positive integer greater than or equal to 2, and the product of n and α is 360 degrees.

15. The method for fabricating a single-photon avalanche photodiode according to claim 12, characterized in that: Implanting second doped ions into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region using a second tilted ion implantation process includes: performing multiple second tilted ion implantations into the first main surface of the semiconductor substrate and the sidewalls of the deep trench region, wherein the semiconductor substrate is rotated by an angle between adjacent second tilted ion implantations to ensure that the second doped ions are uniformly distributed on the sidewalls of the deep trench region.

16. The method for fabricating a single-photon avalanche photodiode according to claim 15, characterized in that: During two consecutive second tilted ion implantations, the semiconductor substrate rotates by an angle of β, and the first tilted ion implantation is performed on the first main surface of the semiconductor substrate and the sidewall of the deep trench region a number of times, with the same ion implantation dose and energy each time, where k is a positive integer greater than or equal to 2, and the product of k and β is 360 degrees.

17. The method for fabricating a single-photon avalanche photodiode according to any one of claims 12-16, characterized in that: The angle between the ion implantation direction of the first tilted ion implantation process and the second tilted ion implantation process and the first main surface of the semiconductor substrate is 2 to 15 degrees.

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