Scanning control circuit and driving method, display substrate, display panel and device

Abstract

A scanning control circuit is applied to a display panel including Q display areas. The scanning control circuit includes Q gate initialization signal lines, Q light-emitting initialization signal lines, and Q scanning control sub-circuits. Each scanning control sub-circuit corresponds to a display area. The scanning control sub-circuit includes a gate scanning control unit and a light-emitting scanning control unit. Each gate scanning control unit is coupled to a gate initialization signal line. The gate scanning control unit is configured to be turned on or off under the control of a gate initialization signal from the gate initialization signal line to drive the corresponding display area to display or not display. Each light-emitting scanning control unit is coupled to a light-emitting initialization signal line. The light-emitting scanning control unit is configured to be turned on or off under the control of a light-emitting initialization signal from the light-emitting initialization signal line to drive the corresponding display area to display or not display.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a scanning control circuit and driving method, a display substrate, a display panel, and a device. Background Art

[0002] With the advancement of display technology, the semiconductor component technology at the core of display devices has also made significant progress. Organic Light Emitting Diodes (OLEDs), as current-mode light-emitting devices, are increasingly being used in high-performance display devices due to their self-luminescence, fast response, wide viewing angle, and ability to be fabricated on flexible substrates. Currently, with the development of flexible OLED displays, the form factors of display devices are becoming increasingly diverse. Among them, foldable display devices have become a symbol of the R&D capabilities of major manufacturers. Summary of the Invention

[0003] In one aspect, a scan control circuit is provided. The scan control circuit is applied to a display panel, the display panel including Q display areas, where Q ≥ 2 and Q is an integer. The scan control circuit includes 2Q initialization signal lines and Q scan control sub-circuits. Of the 2Q initialization signal lines, Q are gate initialization signal lines and Q are light-emission initialization signal lines. Each scan control sub-circuit corresponds to a display area. The scan control sub-circuit includes a gate scan control unit and a light-emission scan control unit. Each gate scan control unit is coupled to a gate initialization signal line, with different gate scan control units coupled to different gate initialization signal lines. The gate scan control unit is configured to be turned on or off under the control of a gate initialization signal from the gate initialization signal line to drive the corresponding display area to display or not display. Each light-emission scan control unit is coupled to a light-emission initialization signal line, with different light-emission scan control units coupled to different light-emission initialization signal lines. The light-emission scan control unit is configured to be turned on or off under the control of a light-emission initialization signal from the light-emission initialization signal line to drive the corresponding display area to display or not display.

[0004] In some embodiments, the gate scan control units and the light emitting scan control units in the same scan control subcircuit are arranged in parallel along a first direction; the Q display areas are arranged in parallel along a second direction; the first direction is substantially perpendicular to the second direction; the gate scan control units in the Q scan control subcircuits are arranged in parallel along the second direction, and the light emitting scan control units in the Q scan control subcircuits are arranged in parallel along the second direction.

[0005] In some embodiments, Q = 2. The two gate initialization signal lines extend along the second direction and are respectively disposed on opposite sides of the gate scan control unit. The two light emitting initialization signal lines extend along the second direction and are respectively disposed on opposite sides of the light emitting scan control unit.

[0006] In some embodiments, in each scan control sub-circuit, the gate scan control unit is closer to the corresponding display area than the light emitting scan control unit.

[0007] In some embodiments, the gate scan control unit includes multiple stages of cascaded gate shift registers, wherein the first S stages of gate shift registers are coupled to a gate initialization signal line, where S ≥ 1 and S is an integer. And / or, the light scan control unit includes multiple stages of cascaded light shift registers, wherein the first S stages of light shift registers are coupled to a light initialization signal line, where S ≥ 1 and S is an integer.

[0008] In another aspect, a display substrate is provided. The display substrate includes Q display areas, where Q ≥ 2 and Q is an integer. The display substrate includes a substrate and at least one scan control circuit disposed on the substrate. The scan control circuit includes 2Q initialization signal lines and Q scan control sub-circuits. Of the 2Q initialization signal lines, Q are gate initialization signal lines and Q are light-emission initialization signal lines. Each scan control sub-circuit corresponds to a display area. The scan control sub-circuit includes a gate scan control unit and a light-emission scan control unit. Each gate scan control unit is coupled to a gate initialization signal line, with different gate scan control units coupled to different gate initialization signal lines. The gate scan control unit is configured to be turned on or off under the control of a gate initialization signal from the gate initialization signal line to drive the corresponding display area to display or not display. Each light-emission scan control unit is coupled to a light-emission initialization signal line, with different light-emission scan control units coupled to different light-emission initialization signal lines. The light-emission scan control unit is configured to be turned on or off under the control of a light-emission initialization signal from the light-emission initialization signal line to drive the corresponding display area to display or not display.

[0009] In some embodiments, the display substrate includes a first display area and a second display area arranged side by side along a second direction. The scan control circuit includes a first scan control subcircuit corresponding to the first display area, a second scan control subcircuit corresponding to the second display area, and a first gate initialization signal line and a second gate initialization signal line. The first scan control subcircuit includes a first gate scan control unit, and the second scan control subcircuit includes a second gate scan control unit. The first gate initialization signal line is coupled to the first gate scan control unit, and the second gate initialization signal line is coupled to the second gate scan control unit.

[0010] The scan control subcircuit also includes a first gate voltage signal line, a second gate voltage signal line, a first gate clock signal line and a second gate clock signal line coupled to the gate scan control unit; along a first direction and from the inner side to the outer side of the display area, the second gate initialization signal line, the second gate voltage signal line, the first gate voltage signal line, the first gate clock signal line, the second gate clock signal line and the first gate initialization signal line are arranged in sequence, and the first gate scan control unit and the second gate scan control unit are located between the second gate initialization signal line and the first gate voltage signal line.

[0011] In some embodiments, the scan control circuit includes a second scan control subcircuit and a second gate initialization signal line, the second scan control subcircuit including a second gate scan control unit; the second gate scan control unit includes a plurality of cascaded second gate shift registers arranged in parallel along the second direction, each second gate shift register including a second gate input transistor. The second scan control subcircuit also includes S second gate initial connection lines, each corresponding to the first S stages of the second gate shift register; one end of each second gate initial connection line is coupled to the second gate initialization signal line, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register; S ≥ 1, and S is an integer.

[0012] In some embodiments, the scan control circuit includes a second scan control subcircuit, the second scan control subcircuit includes a second gate initial connection line, and the display substrate includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer sequentially arranged on the substrate. The second gate initial connection line includes at least one first connection segment and at least one second connection segment. The at least one first connection segment is located in the source-drain conductive layer. The orthographic projection of the first connection segment on the substrate is separated from the orthographic projection of any signal line in the second scan control subcircuit on the substrate. At least one second connection segment is located in the semiconductor layer. The orthographic projection of the second connection segment on the substrate is separated from the orthographic projection of any signal line in the second scan control subcircuit on the substrate. The resistivity of the second connection segment is greater than the resistivity of the first connection segment.

[0013] In some embodiments, the scan control circuit includes a second gate initialization signal line and a second gate voltage signal line. The second gate initialization connection line further includes at least one third connection segment, the at least one third connection segment being located in the first gate conductive layer or the second gate conductive layer; an orthographic projection of the third connection segment on the substrate intersects an orthographic projection of at least one of the second gate initialization signal line and the second gate voltage signal line on the substrate.

[0014] In some embodiments, the second gate initial connection line includes a plurality of sequentially connected connection segments; the source-drain conductive layer includes a plurality of first connection patterns, each first connection pattern electrically connecting two adjacent connection segments of the second gate initial connection line through a via.

[0015] In some embodiments, the scan control circuit includes a second gate initialization signal line and a second gate voltage signal line. The second scan control subcircuit includes a second gate scan control unit, the second gate scan control unit includes a second gate shift register, and the second gate shift register includes a second gate input transistor. The second gate initial connection line includes a first connection segment, a second connection segment, and a third connection segment connected in sequence. The orthographic projection of the third connection segment on the substrate intersects with the orthographic projections of the second gate voltage signal line and the second gate initialization signal line on the substrate. The end of the first connection segment away from the third connection segment is coupled to the corresponding second gate input transistor, and the end of the third connection segment away from the first connection segment is coupled to the second gate initialization signal line.

[0016] In some embodiments, the second gate initial connection line extends substantially along the first direction and is located between two adjacent stages of gate shift registers.

[0017] In some embodiments, the display substrate includes a source-drain conductive layer, and the second scan control subcircuit further includes a plurality of second gate connection lines, each corresponding to a second gate shift register of each stage except the first S stage. One end of each second gate connection line is coupled to the output end of the second gate shift register of the previous stage, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register. The plurality of second gate connection lines are located in the source-drain conductive layer.

[0018] In some embodiments, the scan control circuit includes a first gate scan control subcircuit and a first gate initialization signal line, wherein the first gate scan control subcircuit includes a first gate scan control unit. The first gate scan control unit includes a plurality of cascaded first gate shift registers arranged in parallel along the second direction, each first gate shift register including a first gate input transistor. The first scan control subcircuit also includes S first gate initialization connection lines, each corresponding to the first gate shift registers of the preceding S stages. One end of each first gate initialization connection line is coupled to the first gate initialization signal line, and the other end is coupled to the first gate input transistor of the corresponding first gate shift register.

[0019] In some embodiments, the display substrate includes a first display area and a second display area arranged side by side along a second direction. The scan control circuit includes a first scan control subcircuit corresponding to the first display area, a second scan control subcircuit corresponding to the second display area, and a first light-emission initialization signal line and a second light-emission initialization signal line. The first scan control subcircuit includes a first light-emission scan control unit, and the second scan control subcircuit includes a second light-emission scan control unit. The first light-emission initialization signal line is coupled to the first light-emission scan control unit, and the second light-emission initialization signal line is coupled to the second light-emission scan control unit.

[0020] The scan control subcircuit further includes a plurality of light-emission initialization signal lines, a first sub-light-emission voltage signal line, a second sub-light-emission voltage signal line, a second light-emission voltage signal line, a first light-emission clock signal line, and a second light-emission clock signal line, coupled to the light-emission scan control unit. The second light-emission initialization signal line, the first sub-light-emission voltage signal line, the second sub-light-emission voltage signal line, the second sub-light-emission voltage signal line, the first light-emission clock signal line, the second light-emission clock signal line, and the first light-emission initialization signal line are arranged in sequence along a first direction, from the inner side of the display area to the outer side. The first light-emission scan control unit and the second light-emission scan control unit are located between the first sub-light-emission voltage signal line and the first light-emission clock signal line.

[0021] In some embodiments, the second light-emission scanning control unit includes a plurality of cascaded second light-emission shift registers arranged in parallel along the second direction, each second light-emission shift register including a second light-emission input transistor. The second light-emission control subcircuit also includes S second light-emission initialization connection lines, each corresponding to the first S second light-emission shift registers. One end of each second light-emission initialization connection line is coupled to the second light-emission initialization signal line, and the other end is coupled to the second light-emission input transistor of the corresponding second light-emission shift register; S ≥ 1, and S is an integer.

[0022] In some embodiments, the display substrate includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source / drain conductive layer sequentially disposed on the substrate. The second light-emission initial connection line includes at least one fourth connection segment, at least one fifth connection segment, and at least one sixth connection segment. The at least one fourth connection segment is located in the source / drain conductive layer. The orthographic projection of the fourth connection segment on the substrate is separated from the orthographic projection of any signal line in the second light-emission control subcircuit on the substrate. The at least one fifth connection segment is located in the semiconductor layer. The orthographic projection of the fifth connection segment on the substrate is separated from the orthographic projection of any signal line in the second light-emission control subcircuit on the substrate; wherein the resistivity of the fifth connection segment is greater than the resistivity of the fourth connection segment. The at least one sixth connection segment is located in the first gate conductive layer or the second gate conductive layer. The orthographic projection of the sixth connection segment on the substrate intersects the orthographic projection of at least one of the second light-emission initialization signal line, the first sub-light-emission voltage signal line, and the second light-emission voltage signal line on the substrate.

[0023] In some embodiments, the second initial light-emitting connection line includes a plurality of sequentially connected connection segments, and the source-drain conductive layer includes a plurality of second connection patterns, each second connection pattern electrically connecting two adjacent connection segments of the second initial light-emitting connection line through a via hole.

[0024] In some embodiments, the second light-emitting initial connection line includes a fourth connection segment, a first sixth connection segment, a fifth connection segment, and a second sixth connection segment, which are sequentially connected. The orthographic projection of the first sixth connection segment on the substrate intersects the orthographic projection of the second light-emitting voltage signal line on the substrate. The orthographic projection of the second sixth connection segment on the substrate intersects the orthographic projections of both the first sub-light-emitting voltage signal line and the second light-emitting initialization signal line on the substrate. The end of the fourth connection segment away from the second sixth connection segment is coupled to the corresponding second light-emitting input transistor, and the end of the second sixth connection segment away from the fourth connection segment is coupled to the second light-emitting initialization signal line.

[0025] In another aspect, a display panel is provided. The display panel includes the display substrate described in any of the above embodiments and a control integrated circuit. The control integrated circuit is coupled to multiple initialization signal lines in a scan control circuit of the display substrate. The control integrated circuit is configured to transmit a first initialization signal to the initialization signal lines corresponding to display areas not required for display, thereby turning off the scan control sub-circuits corresponding to the display areas not required for display; and to transmit a second initialization signal to the initialization signal lines corresponding to display areas required for display, thereby turning on the scan control sub-circuits corresponding to the display areas required for display.

[0026] In another aspect, a display device is provided, which includes the display panel described in any one of the above embodiments.

[0027] In some embodiments, the display device is foldable along a boundary line between adjacent display areas.

[0028] In yet another aspect, a method for driving a scan control circuit is provided. The method for driving a scan control circuit is applicable to the scan control circuit described in any of the above embodiments. The method includes: when a target display area of ​​a display panel does not need to display, an initialization signal line coupled to a scan control subcircuit corresponding to the target display area provides a first initialization signal to the scan control subcircuit to turn off the scan control subcircuit. When the target display area needs to display, the initialization signal line coupled to the scan control subcircuit corresponding to the target display area provides a second initialization signal to the scan control subcircuit to turn on the scan control subcircuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] Figure 1A is a structural diagram of a display device according to some embodiments;

[0031] Figure 1B is a partial cross-sectional view of a display panel according to some embodiments;

[0032] Figure 2 is a diagram of a driving architecture of a display panel according to some embodiments;

[0033] Figure 3 is a structural diagram of a scan control circuit of a display panel according to some embodiments;

[0034] Figure 4 is a structural diagram of another scan control circuit of a display panel according to some embodiments;

[0035] Figure 5 is an equivalent circuit diagram of a gate shift register according to some embodiments;

[0036] Figure 6 for Figure 5The driving timing diagram of the gate shift register shown;

[0037] Figure 7 is an equivalent circuit diagram of a light emitting shift register according to some embodiments;

[0038] Figure 8 for Figure 7 The driving timing diagram of the light-emitting scan control shift register shown;

[0039] Figure 9 A top view of some film layers of a gate scanning control unit according to some embodiments;

[0040] Figure 10 is a top view of other film layers of a gate scanning control unit according to some embodiments;

[0041] Figure 11 is a top view of some further film layers of a gate scan control unit according to some embodiments;

[0042] Figure 12 is a top view of some further film layers of a gate scanning control unit according to some embodiments;

[0043] Figure 13 is a top view of some further film layers of a gate scan control unit according to some embodiments;

[0044] Figure 14 A top view of some film layers of a light emitting scanning control unit according to some embodiments;

[0045] Figure 15 A top view of other film layers of a light emitting scanning control unit according to some embodiments;

[0046] Figure 16 is a top view of some further film layers of a light emitting scanning control unit according to some embodiments;

[0047] Figure 17 is a top view of some further film layers of the light emitting scanning control unit according to some embodiments;

[0048] Figure 18 is a top view of some further film layers of a light emitting scanning control unit according to some embodiments;

[0049] Figure 19 for Figure 12 The cross-sectional view at the section line DD' in ;

[0050] Figure 20 for Figure 17 The cross-sectional view at the section line FF' in FIG;

[0051] Figure 21 for Figure 12 The cross-section at section line EE' in FIG;

[0052] Figure 22 is a flowchart of a driving method of a scan control circuit according to some embodiments. DETAILED DESCRIPTION

[0053] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] Hereinafter, the terms "first," "second," and similar expressions are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0058] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0063] In the shift register provided in the embodiments of the present disclosure, the transistors used in the shift register may be thin film transistors (TFT), field effect transistors (MOS), or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0064] In the shift register provided in the embodiments of the present disclosure, the control electrode of each thin film transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0065] In the embodiments of the present disclosure, the capacitor may be a capacitive device fabricated separately through a process, for example, by fabricating specialized capacitive electrodes, each of which may be implemented through a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or implemented through the transistor itself and other devices or circuits, or through the parasitic capacitance between circuits within the circuit itself.

[0066] In the shift register provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0067] The "low voltage" in the shift register provided in the embodiments of the present disclosure refers to a voltage that can turn on the operated P-type transistor included therein, but cannot turn on the operated N-type transistor included therein (i.e., the N-type transistor is turned off); accordingly, the "high voltage" refers to a voltage that can turn on the operated N-type transistor included therein, but cannot turn on the operated P-type transistor included therein (i.e., the P-type transistor is turned off).

[0068] Figure 1A FIG. 1 is a structural diagram of a display device according to some embodiments. Figure 1AAs shown, some embodiments of the present disclosure provide a display device 1, which can be a television, a mobile phone, a computer, a laptop, a tablet computer, a car computer, etc.

[0069] The display device 1 includes at least two display areas A, and the display device 1 is foldable along a boundary line L between adjacent display areas A. In addition, at least one display area A may not display an image when other display areas A display an image.

[0070] For example, Figure 1A As shown, the display device 1 includes a first display area A1 and a second display area A2, and the first display area A1 and the second display area A2 are folded along a boundary line L. The first display area A1 and the second display area A2 can display images simultaneously; alternatively, when the first display area A1 displays an image, the second display area A2 does not display an image; alternatively, when the second display area A2 displays an image, the first display area A1 does not display an image.

[0071] It should be noted that the boundary line L can be a transitional bending area, and the bending area can also be used for display. The bending area can be provided with a hinge or other device to achieve bending or flattening of the screen.

[0072] like Figure 1A As shown, the display device 1 includes a housing 10 , a display panel 20 disposed in the housing 10 , a circuit board, a display driver integrated circuit, and other electronic components.

[0073] The display panel 20 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., and the present disclosure does not make any specific limitation on this.

[0074] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 20 as an OLED display panel as an example.

[0075] In some embodiments, as Figure 2 As shown, the display panel 20 has a display area A and a peripheral area B disposed on at least one side of the display area A. Figure 2 In the example, the peripheral area B is arranged around the display area A.

[0076] See Figure 2In the display panel 20, sub-pixels P of multiple luminous colors are arranged in the display area A. The sub-pixels P of multiple luminous colors include at least a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first color, the second color, and the third color are three primary colors (for example, red, green, and blue).

[0077] Among them, such as Figure 1B As shown, the display panel 20 includes a display substrate 10 and an encapsulation layer 30 for encapsulating the display substrate 10 .

[0078] Here, the encapsulation layer 30 may be an encapsulation film or an encapsulation substrate.

[0079] In some embodiments, see Figure 1B and Figure 2 Each sub-pixel P includes a light-emitting device 15 and a pixel driving circuit 14 disposed on a substrate 21. The pixel driving circuit 14 includes multiple transistors. The transistor includes an active layer 235, a source electrode 265, a drain electrode 266, a gate electrode 235, and a gate insulating layer GI. The source electrode 265 and the drain electrode 266 are respectively in contact with the active layer 235. In a direction perpendicular to and away from the substrate 21, the light-emitting device 15 includes a first electrode 151, a light-emitting functional layer 152, and a second electrode 153.

[0080] For example, Figure 1B As shown, the first electrode 151 is the anode of the light emitting device 15, and the second electrode 153 is the cathode of the light emitting device 15. The first electrode 151 is electrically connected to the source 265 or the drain 266 of the transistor 141 serving as the driving transistor. Figure 1B In the figure, the first electrode 151 and the drain of the transistor 141 are electrically connected to each other.

[0081] In some embodiments, the light-emitting functional layer 152 includes only a light-emitting layer. In other embodiments, the light-emitting functional layer 152 includes, in addition to the light-emitting layer, at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0082] In some embodiments, as Figure 1B As shown, the display substrate 10 further includes a passivation layer PVX, which is disposed on a side of the pixel driving circuit 14 away from the substrate 21 .

[0083] In some embodiments, as Figure 1B As shown, the display substrate 10 further includes a first planar layer PLN. The first planar layer PLN1 is disposed on a side of the passivation layer PVX away from the substrate 21.

[0084] In some embodiments, as Figure 1B As shown, the display substrate 10 further includes a pixel defining layer PDL, the pixel defining layer PDL includes a plurality of opening areas, and one light emitting device 15 is disposed in one opening area.

[0085] In some embodiments, as Figure 1B As shown, the display substrate 10 further includes a buffer layer 111 , which is disposed between the pixel driving circuit 14 and the substrate 21 .

[0086] For ease of explanation, the above-mentioned multiple sub-pixels P are described in this disclosure as being arranged in a matrix. In this case, the sub-pixels P arranged in a row along the first direction X are referred to as sub-pixels P in the same row; and the sub-pixels P arranged in a column along the second direction Y are referred to as sub-pixels P in the same column.

[0087] See Figure 2 Each sub-pixel P includes a pixel driving circuit 200 for controlling the display of the sub-pixel P. The pixel driving circuits 200 located in the same row are coupled to the same gate scanning signal line GL and the same light-emitting scanning signal line EL, and the pixel driving circuits 200 located in the same column are coupled to the same data line DL.

[0088] Among them, the gate scanning signal line GL is used to transmit the gate scanning signal Gate to the pixel driving circuit 200; the light emitting scanning signal line EL is used to transmit the light emitting scanning signal EM to the pixel driving circuit 200; and the data line DL is used to transmit the data signal Data to the pixel driving circuit 200.

[0089] like Figure 2 As shown, the display panel 20 is provided with a scan control circuit 100 and a source driving circuit 300 in the peripheral area B.

[0090] In some embodiments, as Figure 2 As shown, the scan control circuit 100 includes a gate scan control unit 112 and a light scan control unit 113. The gate scan signal Gate comes from the gate scan control unit 112 coupled to the gate scan signal line GL, the light scan signal EM comes from the light scan control unit 113 coupled to the light scan signal line EL; the data signal Data comes from the source driver circuit 300 coupled to each data line DL.

[0091] It should be noted that the gate scanning control unit 112 and the light-emitting scanning control unit 113 can be integrated into one circuit, that is, each shift register of a scanning control unit 111 includes at least two output terminals, one of which outputs a gate scanning signal Gate and the other outputs a light-emitting scanning signal EM. This disclosure does not make detailed limitations here.

[0092] In some embodiments, as Figure 2 As shown, the scan control circuit 100 can be set on the side along the extension direction of the gate scan signal line GL, and the source driving circuit 300 can be set on the side along the extension direction of the data line DL to drive the pixel driving circuit 200 in the display panel 20 for display.

[0093] In some embodiments, see Figure 2 The scanning control circuit 100 is a GOA (Gate Driver on Array) circuit. This means that the scanning control circuit 100 is directly integrated into the array substrate of the display panel 20. This reduces the bezel size of the display panel 20, lowers the manufacturing cost of the display panel 20, and achieves a narrow-bezel design. The following embodiments are all described using the scanning control circuit 100 as a GOA circuit.

[0094] It should be noted that Figure 2 The following description takes the case where the scanning control circuit 100 is provided on one side of the peripheral area B of the display panel 20 and each gate scanning signal line GL and light-emitting scanning signal line EL is driven row by row from one side, ie, single-side driving as an example. Figure 3 and Figure 4 The following description takes the case where the scanning control circuits 100 are provided on both sides of the peripheral area B of the display panel 20 to sequentially drive the gate scanning signal lines GL and the light-emitting scanning signal lines EL row by row from both sides, ie, double-sided driving as an example.

[0095] In some embodiments, see Figure 2 and Figure 4 The scanning control circuit 100 includes a gate scanning control unit 112 and a light emitting scanning control unit 113. The gate scanning control unit 112 includes a multi-stage cascaded gate shift register (GRS1, GRS2...GRS(N)), and the light emitting scanning control unit 113 includes at least a multi-stage cascaded light emitting shift register (ERS1, ERS2...ERS(N)), where N is a positive integer.

[0096] It should be noted that each stage of gate shift register (GRS1, GRS2...GRS(N)) is coupled to at least one gate scanning signal line GL, and each stage of light emitting shift register (ERS1, ERS2...ERS(N)) is coupled to at least one light emitting scanning signal line EL. Figure 4In the figure, each gate shift register is coupled to a gate scanning signal line GL, and each light emitting shift register is coupled to a light emitting scanning signal line EL.

[0097] In some embodiments, see Figure 3 、 Figure 5 and Figure 7 For every two adjacent shift registers RS, the signal input terminal IPUT of the next shift register RS ​​is coupled to the output terminal OPUT of the previous shift register RS, and the signal input terminal IPUT of the first shift register RS1 is coupled to the corresponding initialization signal line STV.

[0098] In some related arts, the display device is a foldable display device including two display areas. In some scenarios, for example, when the foldable display device is in a folded state, one display area displays an image and the other display area displays a black screen.

[0099] However, the display area not used for displaying images does not stop refreshing and still displays a black screen. In other words, in this case, during a frame period, the display area not used for displaying images still charges the sub-pixels P in each row and performs normal row-by-row scanning, which not only generates excess power consumption but also wastes refresh time.

[0100] In order to solve the above problems, some embodiments of the present disclosure provide a scan control circuit 100. Figure 1A and Figure 2 The scanning control circuit 100 is applied to a display panel 20 including a plurality of display areas A. Figure 3 As shown, the scan control circuit 100 includes a plurality of initialization signal lines STV and a plurality of scan control sub-circuits 110. Each scan control sub-circuit 110 corresponds to one display area A.

[0101] The scan control subcircuit 110 includes at least one scan control unit 111. Each scan control unit 111 is coupled to an initialization signal line STV, with different scan control units 111 coupled to different initialization signal lines STV. The scan control unit 111 is configured to turn on or off under the control of an initialization signal from the initialization signal line STV, thereby driving the corresponding display area A to display or not display.

[0102] As can be seen from the above, each scan control sub-circuit 110 corresponds to a display area A, and the scan control unit 111 in each scan control sub-circuit 110 can be individually turned on or off under the control of an initialization signal from the initialization signal line STV to drive the corresponding display area A to display or not display. Based on this, when the above-mentioned scan control circuit 100 is applied to a display panel 20 including multiple display areas A, when the target display area of ​​the display panel 20 does not need to display, the initialization signal line STV coupled to the scan control sub-circuit 110 corresponding to the target display area can be controlled to provide a first initialization signal to the scan control sub-circuit 110 to turn off the scan control sub-circuit 110. This solves the problem in the related art where the display area A not used for displaying images still charges the rows of sub-pixels P included therein and performs normal row-by-row scanning, thereby reducing the waste of refresh time and lowering power consumption.

[0103] At the same time, the initialization signal line STV coupled to the scan control sub-circuit 110 corresponding to the other display area A can be controlled to provide a second initialization signal to the scan control sub-circuit 110 to turn on the scan control sub-circuit 110, thereby driving the other display area A to display normally. In addition, compared with the prior art, when any display area A of the display panel 20 is displayed, the number of corresponding refresh rows is reduced, the refresh frequency is high, the charging time is extended, and the display effect is better.

[0104] It should be noted that the target display area can be selected according to actual conditions, and this disclosure does not make any specific limitation here.

[0105] In some embodiments, as Figure 2 and Figure 4 As shown, the display panel 20 includes Q display areas A, and the scan control circuit 100 includes Q scan control sub-circuits 110 and 2Q initialization signal lines STV, where Q ≥ 2 and Q is an integer. Each scan control sub-circuit 110 includes a gate scan control unit 112 and a light scan control unit 113. The gate scan control unit 112 is configured to provide a gate scan signal Gate to the pixel drive circuit 200, and the light scan control unit 113 is configured to provide a light scan signal EM to the pixel drive circuit 200. Figure 2 and Figure 4 In the figure, Q=2 is taken as an example for illustration.

[0106] Among the 2Q initialization signal lines STV, Q are gate initialization signal lines GSTV, each gate scan control unit 112 is coupled to a gate initialization signal line GSTV, and each gate scan control unit 112 is turned on or off under the control of the gate initialization signal provided by the coupled gate initialization signal line GSTV; Q are light-emitting initialization signal lines ESTV, each light-emitting scan control unit 113 is coupled to a light-emitting initialization signal line ESTV, and each light-emitting scan control unit 113 is turned on or off under the control of the light-emitting initialization signal provided by the coupled light-emitting initialization signal line ESTV.

[0107] For example, see Figure 2 and Figure 4 The display panel 20 includes two display areas A, the scanning control circuit 100 includes two scanning control sub-circuits 110 and four initialization signal lines STV, each scanning control sub-circuit 110 includes a gate scanning control unit 112 and a light-emitting scanning control unit 113, the gate scanning control unit 112 is coupled to a gate initialization signal line GSTV, and the light-emitting scanning control unit 113 is coupled to a light-emitting initialization signal line ESTV.

[0108] In some embodiments, see Figure 2 The gate scan control unit 112 and the light emission scan control unit 113 in the same scan control subcircuit 110 are arranged in parallel along a first direction X, and the Q display areas A are arranged in parallel along a second direction Y. The first direction X is substantially perpendicular to the second direction Y. The gate scan control units 112 in multiple scan control subcircuits 110 are arranged in parallel along the second direction Y, and the light emission scan control units 113 in multiple scan control subcircuits 110 are arranged in parallel along the second direction Y. This arrangement allows the gate scan control units 112 and the light emission scan control units 113 to be neatly arranged, facilitating wiring layout and reducing the area occupied by the scan control circuit 100.

[0109] On this basis, see Figure 4 In the case where the display panel 20 includes two display areas A, the four initialization signal lines STV include two gate initialization signal lines GSTV and two light emitting initialization signal lines ESTV. Figure 12 As shown, two gate initialization signal lines GSTV ( Figure 12 GSTV1 and GSTV2) extend along the second direction Y and are respectively arranged on two opposite sides of the gate scanning control unit 112; Figure 17 As shown, two light emitting initialization signal lines ESTV ( Figure 17 The ESTV1 and ESTV2 in the figure extend along the second direction Y and are respectively disposed on two opposite sides of the light scanning control unit 113.

[0110] In some embodiments, as Figure 2 As shown, in each scan control sub-circuit 110, the gate scan control unit 112 is closer to the corresponding display area A than the light-emission scan control unit 113. In this case, the gate scan signal line GL coupled to the gate scan control unit 112 is shorter and has a lower load, which is beneficial to improving the stability of the gate scan signal Gate provided by the gate scan signal line GL to the pixel driving circuit 200.

[0111] In some embodiments, see Figure 3 The scanning control unit 111 includes a plurality of cascaded shift registers RS arranged in parallel along the second direction Y. The first S shift registers RS in the plurality of shift registers RS are coupled to an initialization signal line STV. Figure 3 In the figure, S=1 is taken as an example for illustration.

[0112] For example, Figure 3 、 Figure 5 and Figure 7 As shown, S=1, that is, in every two adjacent shift registers RS in the scan control unit 111, the signal input terminal IPUT of the first-stage shift register RS1 is coupled to the initialization signal terminal STV, and the signal input terminal IPUT of the next-stage shift register RS ​​is coupled to the output terminal OPUT of the previous-stage shift register RS.

[0113] It should be noted that, in the embodiment of the present disclosure, the cascade connection manner of the shift registers RS at each stage in the scan control unit 111 is not limited to this.

[0114] In some embodiments, as Figure 3 and Figure 4 As shown, the scanning control unit 111 is a gate scanning control unit 112. The gate scanning control unit 112 includes a plurality of cascaded gate shift registers GRS. The first S-stage gate shift registers GRS are coupled to a gate initialization signal line GSTV. Figure 4 In the figure, S=1 is taken as an example for illustration.

[0115] In some embodiments, as Figure 3 and Figure 4 As shown, the scanning control unit 111 is a light emitting scanning control unit 113 , which includes a plurality of cascaded light emitting shift registers ERS, wherein the first S-stage light emitting shift registers ERS are coupled to a light emitting initialization signal line ESTV. Figure 4 In the figure, S=1 is taken as an example for illustration.

[0116] The following combination Figure 5 and Figure 12, taking the gate shift register GRS including 7 transistors and 2 capacitors as an example, the circuit of the gate shift register GRS is schematically described. In the following description, the gate shift register GRS can be any one of the multi-stage gate shift registers included in the gate scan control unit 112.

[0117] It should be noted that, in this article, the first gate clock signal terminal and the subsequent first gate clock signal line use the same symbol "GCK", the second gate clock signal terminal and the subsequent second gate clock signal line use the same symbol "GCB", the first gate voltage signal terminal and the subsequent first gate voltage signal line use the same symbol "GVGL", and the second gate voltage signal terminal and the subsequent second gate voltage signal line use the same symbol "GVGH". This is only for the convenience of description and does not mean that they are the same components or signals.

[0118] like Figure 5 As shown, the gate shift register GRS includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0119] A control electrode of the first transistor T1 is coupled to the first gate clock signal terminal GCK, a first electrode of the first transistor T1 is coupled to the signal input terminal IPUT, and a second electrode of the first transistor T1 is coupled to the first node N1.

[0120] A control electrode of the second transistor T2 is coupled to the first node N1 , a first electrode of the second transistor T2 is coupled to the first gate clock signal terminal GCK, and a second electrode of the second transistor T2 is coupled to the second node N2 .

[0121] A control electrode of the third transistor T3 is coupled to the first gate clock signal terminal GCK, a first electrode of the third transistor T3 is coupled to the first gate voltage signal terminal GVGL, and a second electrode of the third transistor T3 is coupled to the second node N2.

[0122] A control electrode of the fourth transistor T4 is coupled to the second node N2 , a first electrode of the fourth transistor T4 is coupled to the second gate voltage signal terminal GVGH and the first plate of the first capacitor C1 , and a second electrode of the fourth transistor T4 is coupled to the output terminal OPUT.

[0123] A control electrode of the fifth transistor T5 is coupled to the third node N3 , a first electrode of the fifth transistor T5 is coupled to the second gate clock signal terminal GCB, and a second electrode of the fifth transistor T5 is coupled to the output terminal OPUT and the first plate of the second storage capacitor C2 .

[0124] A control electrode of the sixth transistor T6 is coupled to the second node N2 , a first electrode of the sixth transistor T6 is coupled to the second gate voltage signal terminal GVGH, and a second electrode of the sixth transistor T6 is coupled to the fourth node N4 .

[0125] A control electrode of the seventh transistor T7 is coupled to the second gate clock signal terminal GCB, a first electrode of the seventh transistor T7 is coupled to the fourth node N4, and a second electrode of the seventh transistor T7 is coupled to the first node N1.

[0126] A control electrode of the eighth transistor T8 is coupled to the first gate voltage signal terminal GVGL, a first electrode of the eighth transistor T8 is coupled to the first node N1 , and a second electrode of the eighth transistor T8 is coupled to the third node N3 .

[0127] A first plate of the first capacitor C1 is coupled to the first electrode and the second gate voltage signal terminal GVGH of the fourth transistor T4 , and a second plate of the first capacitor C1 is coupled to the second node N2 .

[0128] A first plate of the second capacitor C2 is coupled to the second electrode of the fifth transistor T4 , and a second plate of the first capacitor C1 is coupled to the third node N3 .

[0129] It should be noted that, in a multi-stage cascaded gate shift register GRS, when an S-stage gate shift register GRS is cascaded, for two adjacent groups of S-stage gate shift registers GRS, the first gate clock signal terminal GCK of the gate shift register GRS of the upper group and the second gate clock signal terminal GCB of the gate shift register GRS of the lower group are coupled to the same gate clock signal line; the second gate clock signal terminal GCB of the gate shift register GRS of the upper group and the first gate clock signal terminal GCK of the gate shift register GRS of the lower group are coupled to the same gate clock signal line. For example, the first gate clock signal terminal GCK of the gate shift register GRS of the upper group is coupled to the first gate clock signal line GCK; the second gate clock signal terminal GCB of the gate shift register GRS of the upper group is coupled to the second gate clock signal line GCB; the first gate clock signal terminal GCK of the gate shift register GRS of the lower group is coupled to the second gate clock signal line GCB, and the second gate clock signal terminal GCB of the gate shift register GRS of the lower group is coupled to the first gate clock signal line GCK.

[0130] It should be noted that Figure 5 In the circuit shown, nodes N1, N2 and N3 do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0131] like Figures 9 to 12As shown, the circuit of the gate shift register GRS is formed by etching and stacking the required pattern film layers layer by layer, and finally forming the following Figure 5 The individual transistors in the equivalent circuit shown.

[0132] like Figure 9 As shown, a semiconductor layer ACT is first formed. The material of the semiconductor layer ACT includes amorphous silicon, single crystal silicon, polycrystalline silicon, or metal oxide semiconductor material; for example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO) or zinc oxide (ZnO), but the present disclosure is not limited thereto. The semiconductor layer ACT includes Figure 5 The active layer 225 of each transistor in the equivalent circuit shown (see Figure 12 and Figure 19 ).

[0133] like Figure 10 As shown, a first gate conductive layer Gt1 is formed on the semiconductor layer ACT. The first gate conductive layer Gt1 overlaps the semiconductor layer ACT to form a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The material of the first gate conductive layer Gt1 includes a conductive metal; for example, the material of the first gate conductive layer Gt1 includes at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. The first gate conductive layer Gt1 includes Figure 5 The gate 235 of each transistor and the first plate of the capacitor in the equivalent circuit shown (see Figure 12 and Figure 21 ).

[0134] In some embodiments, a first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate conductive layer Gt1 (see Figure 19 and Figure 21 ), the first gate insulating layer GI1 is used to electrically insulate the semiconductor layer ACT from the first gate conductive layer Gt1. The material of the first gate insulating layer GI1 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the first gate insulating layer GI1 includes silicon dioxide, but the present disclosure is not limited thereto.

[0135] like Figure 11 As shown, a second gate conductive layer Gt2 is formed on the first gate conductive layer Gt1. The overlapped portion of the second gate conductive layer Gt2 and the first gate conductive layer Gt1 forms a first capacitor C1 and a second capacitor C2, respectively. The material of the second gate conductive layer Gt2 includes a conductive metal; for example, the material of the second gate conductive layer Gt2 includes at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. The second gate conductive layer Gt2 includes Figure 5The second plate of the capacitor in the equivalent circuit shown (see Figure 12 ).

[0136] In some embodiments, a second gate insulating layer GI2 is disposed between the first gate conductive layer Gt1 and the second gate conductive layer Gt2 (see Figure 19 The material of the second gate insulating layer GI2 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the second gate insulating layer GI2 includes silicon dioxide, but the present disclosure is not limited thereto.

[0137] like Figure 12 As shown, a source-drain conductive layer SD is formed on the second gate conductive layer Gt2. The source-drain conductive layer SD includes a gate initialization signal line GSTV, a first gate voltage signal line GVGL, a second gate voltage signal line GVGH, a first gate clock signal line GCK, and a second gate clock signal line GCB. The material of the source-drain conductive layer SD includes a conductive metal; for example, the material of the source-drain conductive layer SD includes at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. The source-drain conductive layer SD includes Figure 5 The signal lines in the equivalent circuit shown (see Figure 12 ).

[0138] It should be noted that, see Figure 12 and Figure 19 Each signal line, transistor, and capacitor is electrically connected to the source / drain conductive layer SD through a via HL, achieving electrical connection through the source / drain conductive layer SD. For example, when the first gate conductive layer Gt1 is electrically connected to the source / drain conductive layer SD, the via HL penetrates the ILD and the second gate insulating layer GI2. For another example, when the semiconductor layer ACT is electrically connected to the source / drain conductive layer SD, the via HL penetrates the ILD, the first gate insulating layer GI1, and the second gate insulating layer GI2.

[0139] In some embodiments, an interlayer dielectric layer ILD (see Figure 19 The material of the interlayer dielectric layer ILD includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide; for example, the material of the second gate insulating layer GI2 includes silicon dioxide, but the present disclosure is not limited thereto.

[0140] Figure 6 for Figure 5 The timing diagram of the gate shift register GRS is shown below. The input phase P1 and the output phase P2 of the gate shift register GRS are described in detail below by taking the transistor as a P-type transistor as an example, which does not limit the protection of the present disclosure.

[0141] Among them, "low voltage" can turn on the P-type transistor, but cannot turn on the N-type transistor (that is, the N-type transistor is turned off); "high voltage" can turn on the N-type transistor, but cannot turn on the P-type transistor (that is, the P-type transistor is turned off).

[0142] It should be noted that the embodiments of the present disclosure include but are not limited to the above. For example, one or more thin-film transistors in the gate shift register GRS circuit provided in the embodiments of the present disclosure may also be N-type transistors. It is only necessary to connect the electrodes of the selected thin-film transistors in accordance with the electrodes of the corresponding thin-film transistors in the embodiments of the present disclosure, and to provide the corresponding high voltage or low voltage at the corresponding voltage terminals.

[0143] Illustratively, in the following description, “0” represents a low voltage and “1” represents a high voltage.

[0144] In the input phase P1, see Figure 6 , IPUT=0, GCK=0, GCB=1, OPUT=1.

[0145] In this case, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned on, the seventh transistor T7 is turned off, and the output terminal OPUT outputs a high-voltage gate scan signal Gate to control the gate signal terminal of the corresponding pixel driving circuit 200 to be turned off.

[0146] In the output stage P2, see Figure 6 , IPUT=1, GCK=1, GCB=0, OPUT=0.

[0147] In this case, the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are all turned on, the first transistor T1, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are all turned off, and the output terminal OPUT outputs a low-voltage gate scan signal Gate to control the gate signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0148] The following combination Figure 7 and Figure 17 Taking the light emitting shift register ERS including 12 transistors and 3 capacitors as an example, the circuit of the light emitting shift register ERS is schematically described. In the following description, the light emitting shift register ERS can be any one of the multi-stage light emitting shift registers included in the light emitting scan control unit 113.

[0149] It should be noted that, in this article, the first light-emitting clock signal terminal and the subsequent first light-emitting clock signal line use the same symbol "ECK", the second light-emitting clock signal terminal and the subsequent second light-emitting clock signal line use the same symbol "ECB", the first light-emitting voltage signal terminal and the subsequent first light-emitting voltage signal line use the same symbol "EVGL", and the second light-emitting voltage signal terminal and the subsequent second light-emitting voltage signal line use the same symbol "EVGH". This is only for the convenience of description and does not mean that they are the same components or signals.

[0150] like Figure 7 As shown, the light emitting shift register ERS includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0151] A control electrode of the first transistor T1 is coupled to the first light emitting clock signal terminal ECK, a first electrode of the first transistor T1 is coupled to the signal input terminal IPUT, and a second electrode of the first transistor T1 is coupled to the fourth node N4.

[0152] A control electrode of the second transistor T2 is coupled to the fourth node N4 , a first electrode of the second transistor T2 is coupled to the first light emitting clock signal terminal ECK, and a second electrode of the second transistor T2 is coupled to the fifth node N5 .

[0153] A control electrode of the third transistor T3 is coupled to the first light-emitting clock signal terminal ECK, a first electrode of the third transistor T3 is coupled to the first light-emitting voltage signal terminal GVGL, and a second electrode of the third transistor T3 is coupled to the fifth node N5.

[0154] A control electrode of the fourth transistor T4 is coupled to the second light emitting clock signal terminal ECB, a first electrode of the fourth transistor T4 is coupled to the sixth node N6, and a second electrode of the fourth transistor T4 is coupled to the fourth node N4.

[0155] A control electrode of the fifth transistor T5 is coupled to the fifth node N5 , a first electrode of the fifth transistor T5 is coupled to the second light emitting voltage signal terminal VGH, and a second electrode of the fifth transistor T5 is coupled to the sixth node N6 .

[0156] A control electrode of the sixth transistor T6 is coupled to the seventh node N7 , a first electrode of the sixth transistor T6 is coupled to the second light emitting clock signal terminal ECB, and a second electrode of the sixth transistor T6 is coupled to the eighth node N8 .

[0157] A control electrode of the seventh transistor T7 is coupled to the second light emitting clock signal terminal ECB, a first electrode of the seventh transistor T7 is coupled to the eighth node N8, and a second electrode of the seventh transistor T7 is coupled to the ninth node N9.

[0158] A control electrode of the eighth transistor T8 is coupled to the fourth node N4 , a first electrode of the eighth transistor T8 is coupled to the second light emitting voltage signal terminal VGH, and a second electrode of the eighth transistor T8 is coupled to the ninth node N9 .

[0159] A control electrode of the ninth transistor T9 is coupled to the ninth node N9 , a first electrode of the ninth transistor T9 is coupled to the second light emitting voltage signal terminal VGH and the first plate of the third capacitor C3 , and a second electrode of the ninth transistor T9 is coupled to the output terminal OPUT.

[0160] A control electrode of the tenth transistor T10 is coupled to the tenth node N10 , a first electrode of the tenth transistor T10 is coupled to the first light-emitting voltage signal terminal VGL, and a second electrode of the tenth transistor T10 is coupled to the output terminal OPUT.

[0161] A control electrode of the eleventh transistor T11 is coupled to the first light emitting voltage signal terminal VGL, a first electrode of the eleventh transistor T11 is coupled to the fifth node N5 , and a second electrode of the eleventh transistor T11 is coupled to the seventh node N7 .

[0162] A control electrode of the twelfth transistor T12 is coupled to the first light emitting voltage signal terminal VGL, a first electrode of the twelfth transistor T12 is coupled to the fourth node N4 , and a second electrode of the twelfth transistor T12 is coupled to the tenth node N10 .

[0163] A first plate of the first capacitor C1 is coupled to the seventh node N7 , and a second plate of the first capacitor C1 is coupled to the eighth node N8 .

[0164] A first plate of the second capacitor C2 is coupled to the second light emitting clock signal terminal ECB, and a second plate of the second capacitor C2 is coupled to the tenth node N10.

[0165] A first plate of the third capacitor C3 is coupled to the first electrode of the ninth transistor T9 and the second light emitting voltage signal terminal VGH, and a second plate of the third capacitor C3 is coupled to the ninth node N9.

[0166] It should be noted that, in a multi-stage cascaded light-emitting shift register ERS, when S-stage light-emitting shift registers ERS are cascaded, in two adjacent groups of S-stage light-emitting shift registers ERS, the first light-emitting clock signal terminal ECK of the light-emitting shift register ERS of the upper group and the second light-emitting clock signal terminal ECB of the light-emitting shift register ERS of the lower group are coupled to the same light-emitting clock signal line; and the second light-emitting clock signal terminal ECB of the light-emitting shift register ERS of the upper group and the first light-emitting clock signal terminal ECK of the light-emitting shift register ERS of the lower group are coupled to the same light-emitting clock signal line. For example, the first light-emitting clock signal terminal ECK of the light-emitting shift register ERS of the upper group is coupled to the first light-emitting clock signal line ECK; the second light-emitting clock signal terminal ECB of the light-emitting shift register ERS of the upper group is coupled to the second light-emitting clock signal line ECB; the first light-emitting clock signal terminal ECK of the light-emitting shift register ERS of the lower group is coupled to the second light-emitting clock signal line ECB, and the second light-emitting clock signal terminal ECB of the light-emitting shift register ERS of the lower group is coupled to the first light-emitting clock signal line ECK.

[0167] It should be noted that if Figure 7 In the circuit shown, nodes N4, N5, N6, N7, N8, N9 and N10 do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0168] like Figures 14 to 17 As shown, the circuit of the light emitting shift register ERS is formed by etching and stacking the required pattern film layers layer by layer. Figure 7 The individual transistors in the equivalent circuit shown.

[0169] like Figure 14 As shown, a semiconductor layer ACT is formed first. The semiconductor layer ACT of the light emitting shift register ERS can be made of the same material and in the same layer as the semiconductor layer ACT of the gate shift register ERS. The semiconductor layer ACT also includes Figure 7 The active layer 225 of each transistor in the equivalent circuit shown (see Figure 17 and Figure 21 ).

[0170] like Figure 15As shown, a first gate conductive layer Gt1 is formed on the semiconductor layer ACT. The first gate conductive layer Gt1 overlaps with the semiconductor layer ACT to form a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The first gate conductive layer Gt1 of the light emitting shift register ERS can be made of the same material and in the same layer as the first gate conductive layer Gt1 of the gate shift register ERS. The first gate conductive layer Gt1 also includes Figure 7 The gate 235 of each transistor and the first plate of the capacitor in the equivalent circuit shown (see Figure 17 and Figure 21 ).

[0171] In some embodiments, a first gate insulating layer GI1 is disposed between the semiconductor layer ACT and the first gate conductive layer Gt1 (see Figure 20 The first gate insulating layer GI1 of the light emitting shift register ERS can be made of the same material and in the same layer as the first gate insulating layer GI1 of the gate shift register ERS.

[0172] like Figure 16 As shown, a second gate conductive layer Gt2 is formed on the first gate conductive layer Gt1, and the overlapped portion of the second gate conductive layer Gt2 and the first gate conductive layer Gt1 respectively forms a first capacitor C1, a second capacitor C2 and a third capacitor C3. The second gate conductive layer Gt2 of the light emitting shift register ERS can be made of the same material and in the same layer as the second gate conductive layer Gt2 of the gate shift register ERS. The second gate conductive layer Gt2 also includes Figure 7 The second plate of the capacitor in the equivalent circuit shown (see Figure 17 ).

[0173] In some embodiments, a second gate insulating layer GI2 is disposed between the first gate conductive layer Gt1 and the second gate conductive layer Gt2 (see Figure 20 The second gate insulating layer GI2 of the light emitting shift register ERS can be made of the same material and in the same layer as the second gate insulating layer GI2 of the gate shift register ERS.

[0174] like Figure 17As shown, a source-drain conductive layer SD is formed on the second gate conductive layer Gt2, and the source-drain conductive layer SD includes a second light-emitting initialization signal line ESTV2, a first sub-light-emitting voltage signal line EVGL1, a second light-emitting voltage signal line EVGH, a second sub-light-emitting voltage signal line EVGL2, a first light-emitting clock signal line ECK, a second light-emitting clock signal line ECB, and a first light-emitting initialization signal line ESTV1. The source-drain conductive layer SD of the light-emitting shift register ERS can be made of the same material and in the same layer as the source-drain conductive layer SD of the gate shift register ERS. The source-drain conductive layer SD also includes Figure 7 The signal lines in the equivalent circuit shown (see Figure 17 ).

[0175] It should be noted that, see Figure 17 and Figure 20 Each signal line, transistor, and capacitor is electrically connected to the source / drain conductive layer SD through a via HL, achieving electrical connection through the source / drain conductive layer SD. For example, when the first gate conductive layer Gt1 is electrically connected to the source / drain conductive layer SD, the via HL penetrates the ILD and the second gate insulating layer GI2. For another example, when the semiconductor layer ACT is electrically connected to the source / drain conductive layer SD, the via HL penetrates the ILD, the first gate insulating layer GI1, and the second gate insulating layer GI2.

[0176] In some embodiments, an interlayer dielectric layer ILD (see Figure 20 The interlayer dielectric layer ILD of the light emitting shift register ERS can be made of the same material and in the same layer as the interlayer dielectric layer ILD of the gate shift register ERS.

[0177] Figure 8 for Figure 7 The timing diagram of the light emitting shift register ERS is shown below. Taking the transistors as P-type transistors as an example, the input phases P1 to P3 and the output phases P2 to P4 of the light emitting shift register ERS are described in detail, which does not limit the protection scope of the present disclosure.

[0178] It should be noted that the embodiments of the present disclosure include but are not limited to the above. For example, one or more thin-film transistors in the gate shift register GRS circuit provided in the embodiments of the present disclosure may also be N-type transistors. It is only necessary to connect the electrodes of the selected thin-film transistors in accordance with the electrodes of the corresponding thin-film transistors in the embodiments of the present disclosure, and to provide the corresponding high voltage or low voltage at the corresponding voltage terminals.

[0179] Among them, "low voltage" can turn on the P-type transistor, but cannot turn on the N-type transistor (that is, the N-type transistor is turned off); "high voltage" can turn on the N-type transistor, but cannot turn on the P-type transistor (that is, the P-type transistor is turned off).

[0180] Illustratively, in the following description, “0” represents a low voltage and “1” represents a high voltage.

[0181] In the input phase P3 to P5, refer to Figure 7 and Figure 8 .

[0182] Among them, in P3, IPUT=1, ECK=0, ECB=1, OPUT=0.

[0183] In this case, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all turned off, the output terminal OPUT does not output, and the light-emitting scanning signal EM received by the enable signal terminal of the corresponding pixel driving circuit 200 is the low-voltage light-emitting scanning signal EM of the previous frame stored in the capacitor externally connected between the light-emitting shift register RS ​​and the pixel driving circuit 200, so as to control the enable signal terminal of the corresponding pixel driving circuit 200 to be turned off.

[0184] In P4, IPUT=1, ECK=1, ECB=0, OPUT=1.

[0185] In this case, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the output terminal OPUT outputs a high-voltage light-emitting scanning signal EM to control the enable signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0186] In P5, IPUT=1, ECK=0, ECB=1, OPUT=1.

[0187] In this case, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the output terminal OPUT outputs a high-voltage light-emitting scanning signal EM to control the enable signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0188] In the output stage P4~P6, refer to Figure 10 and Figure 13 .

[0189] Among them, in P4, IPUT=1, ECK=1, ECB=0, OPUT=1.

[0190] In this case, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the output terminal OPUT outputs a high-voltage light-emitting scanning signal EM to control the enable signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0191] In P5, IPUT=1, ECK=0, ECB=1, OPUT=1.

[0192] In this case, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the output terminal OPUT outputs a high-voltage light-emitting scanning signal EM to control the enable signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0193] In P6, IPUT=0, ECK=1, ECB=0, OPUT=1.

[0194] In this case, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 are all turned on, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the output terminal OPUT outputs a high-voltage light-emitting scanning signal EM to control the enable signal terminal of the corresponding pixel driving circuit 200 to turn on.

[0195] It should be noted that in the embodiments of the present disclosure, the specific implementation of the gate shift register GRS and the light emitting shift register GRS is not limited to the above-described methods. They can be any implementation method, such as a conventional connection method well known to those skilled in the art, as long as the corresponding functions are achieved. The above examples do not limit the scope of protection of the present disclosure.

[0196] Some embodiments of the present disclosure provide a display substrate 2. Figure 2 As shown, the display substrate 2 includes a substrate 21 and at least one scanning control circuit 100 disposed on the substrate 21 . The scanning control circuit 100 is the scanning control circuit 100 of any of the above embodiments.

[0197] For example, see Figure 4 The display substrate 2 includes two scanning control circuits 100, which are arranged on opposite sides of the display substrate 2. The two scanning control circuits 100 drive each pixel driving circuit 200 row by row from both sides at the same time, that is, double-sided driving, to reduce the load and improve the display effect.

[0198] In some embodiments, as Figure 2 and Figure 4 As shown, each scan control sub-circuit 110 in the scan control circuit 100 includes a gate scan control unit 112 and a light emission scan control unit 113 .

[0199] On this basis, see Figure 12 The scan control subcircuit 110 also includes: a plurality of gate initialization signal lines GSTV, a first gate voltage signal line GVGL, a second gate voltage signal line GVGH, a first gate clock signal line GCK, and a second gate clock signal line GCB coupled to the gate scan control unit 112, and a plurality of light-emitting initialization signal lines ESTV, at least one first light-emitting voltage signal line EVGL, a second light-emitting voltage signal line EVGH, a first light-emitting clock signal line ECK, and a second light-emitting clock signal line ECB coupled to the light-emitting scan control unit 113.

[0200] Among them, the first gate clock signal line GCK and the second gate clock signal line GCB can refer to the timing diagram of the above-mentioned gate shift register GRS, and the present disclosure will not elaborate on them here; the signals transmitted by the first light-emitting clock signal line ECK and the second light-emitting clock signal line ECB can refer to the timing diagram of the above-mentioned light-emitting shift register ERS, and the present disclosure will not elaborate on them here.

[0201] It should be noted that the first gate voltage signal line GVGL is configured to transmit a DC operating level signal, for example, the first gate voltage signal line GVGL is configured to transmit a low-level signal; the second gate voltage signal line GVGH is configured to transmit a DC non-operating level signal, for example, the second gate voltage signal line GVGH is configured to transmit a high-level signal. Similarly, the first light-emitting voltage signal line EVGL is configured to transmit a DC operating level signal, for example, the first light-emitting voltage signal line EVGL is configured to transmit a low-voltage signal; the second light-emitting voltage signal line EVGH is configured to transmit a DC non-operating level signal, for example, the second light-emitting voltage signal line EVGH is configured to transmit a high-voltage signal.

[0202] In some embodiments, as Figure 4 As shown, the display substrate 2 has a first display area A1 and a second display area A2 arranged side by side along the second direction Y.

[0203] like Figure 4 As shown, the scan control circuit 100 includes a first scan control subcircuit 1101 corresponding to the first display area A1, and a second scan control subcircuit 1102 corresponding to the second display area A2. The first scan control subcircuit 1101 includes a first gate scan control unit 1121, and the second scan control subcircuit 1102 includes a second gate scan control unit 1122.

[0204] like Figure 12 As shown, the plurality of gate initialization signal lines GSTV include a first gate initialization signal line GSTV1 and a second gate initialization signal line GSTV2. The first gate initialization signal line GSTV1 is coupled to the first gate scan control unit 1121, and the second gate initialization signal line GSTV2 is coupled to the second gate scan control unit 1122.

[0205] like Figure 12 As shown, along the first direction X and from the inner side of the display area A to the outer side, the second gate initialization signal line GSTV2, the second gate voltage signal line GVGH, the first gate voltage signal line GVGL, the first gate clock signal line GCK, the second gate clock signal line GCB, and the first gate initialization signal line GSTV1 are arranged in sequence, and the first gate scan control unit 1121 and the second gate scan control unit 1122 are located between the second gate initialization signal line GSTV2 and the first gate voltage signal line GVGL.

[0206] It should be noted that the orthographic projection of the second gate voltage signal line GVGH on the substrate 21 can overlap with the orthographic projection of the first capacitor C1 and the second capacitor C2 in the gate shift register GRS on the substrate 21, and the area where the second gate voltage signal line GVGH overlaps with the first capacitor C1 and the second capacitor C2 in the gate shift register GRS can be directly connected to the via HL (see Figure 19 ) to achieve electrical connection and simplify wiring layout.

[0207] In some embodiments, see Figure 2 and Figure 12 In the case where the gate scan control unit 112 is closer to the corresponding display area A than the light scan control unit 113, the display panel 20 further includes a light test signal line Eout. The light test signal line Eout extends along the second direction Y and is located on a side of the second gate initialization signal line GSTV2 closer to the display area A. The light test signal line Eout is configured to transmit a light test signal during a test phase to determine whether there is a short circuit or open circuit problem.

[0208] In some embodiments, as Figure 4 As shown, the second gate scanning control unit 1122 includes a plurality of cascaded second gate shift registers arranged in parallel along the second direction Y, and each stage of the second gate shift register includes a second gate input transistor (the first transistor T1 mentioned in the above gate shift register).

[0209] On this basis, the second scan control subcircuit 1102 further includes S second gate initial connection lines 1103, each corresponding to the first S stages of the second gate shift register. One end of each second gate initial connection line 1103 is coupled to the second gate initialization signal line GSTV2, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register (the first transistor T1 mentioned in the gate shift register above). Where S ≥ 1, and S is an integer.

[0210] In some embodiments, see Figure 4 and Figure 13 The first gate scanning control unit 1121 includes a plurality of cascaded first gate shift registers arranged in parallel along the second direction Y, and each stage of the first gate shift register includes a first gate input transistor (the first transistor T1 mentioned in the above gate shift register).

[0211] On this basis, the first gate scan control unit 1121 further includes S first gate initial connection lines 1104, each corresponding to the first gate shift register of the first S stages. One end of each first gate initial connection line 1104 is coupled to the first gate initialization signal line GSTV1, and the other end is coupled to the first gate input transistor of the corresponding first gate shift register (the first transistor T1 mentioned in the gate shift register above). Where S ≥ 1, and S is an integer. Figure 12 In the figure, S=1 is taken as an example for illustration.

[0212] In some embodiments, as Figure 12 and Figure 17As shown, the display substrate 2 includes a semiconductor layer ACT, a first gate conductive layer Gt1, a second gate conductive layer Gt2 and a source-drain conductive layer SD which are sequentially arranged on a substrate 21.

[0213] Among them, see Figure 9 、 Figure 10 、 Figure 12 and Figure 21 The semiconductor layer ACT includes the active layer 225 of the transistor in the scan control circuit 100, the first gate conductive layer Gt1 includes the gate 235 of the transistor in the scan control circuit 100 and the first plate of the capacitor, and the second gate conductive layer Gt2 includes the second plate of the capacitor in the scan control circuit 100. The source-drain conductive layer SD includes the source 265 and drain 266 of the transistor in the scan control circuit 100 and various signal lines in the scan control circuit 100.

[0214] On this basis, if Figure 12 and Figure 19 As shown, the second gate initial connection line 1103 includes at least one first connection segment 251 and at least one second connection segment 221. The at least one first connection segment 251 is located in the source-drain conductive layer SD. The orthographic projection of the first connection segment 251 on the substrate 21 is separated from the orthographic projection of any signal line in the second scan control sub-circuit 1102 on the substrate 21. The at least one second connection segment 221 is located in the semiconductor layer ACT. The orthographic projection of the second connection segment 221 on the substrate 21 is separated from the orthographic projection of any signal line in the second scan control sub-circuit 1102 on the substrate 21. The resistivity of the second connection segment 221 is greater than that of the first connection segment 251 to reduce the risk of static electricity generated during the process causing a sudden change in the initialization signal provided by the second gate initialization signal line GSTV2.

[0215] It should be noted that the resistivity of the second connecting segment 221 being greater than the resistivity of the first connecting segment 251 can be controlled by the materials of the semiconductor layer ACT and the source / drain conductive layer SD. For example, the material of the semiconductor layer ACT includes at least one of low-temperature polysilicon, single crystal silicon, and a metal oxide, and the source / drain conductive layer SD includes at least one of copper, aluminum, and silver.

[0216] In some embodiments, see Figure 13The first gate initial connection line 1104 includes at least one seventh connection segment 252 and at least one eighth connection segment 222. The at least one seventh connection segment 252 is located in the source-drain conductive layer SD, and the orthographic projection of the seventh connection segment 252 on the substrate 21 is separated from the orthographic projection of any signal line in the first scan control sub-circuit 1101 on the substrate 21. The at least one eighth connection segment 222 is located in the semiconductor layer ACT, and the orthographic projection of the eighth connection segment 222 on the substrate 21 is separated from the orthographic projection of any signal line in the first scan control sub-circuit 1101 on the substrate 21. The resistivity of the eighth connection segment 222 is greater than that of the seventh connection segment 252, thereby reducing the risk of static electricity generated during the process causing a sudden change in the initialization signal provided by the first gate initialization signal line GSTV1.

[0217] In some embodiments, as Figure 12 and Figure 19 As shown, the second gate initial connection line 1103 further includes at least one third connection segment 231. The at least one third connection segment 231 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the third connection segment 231 on the substrate 21 intersects the orthographic projection of at least one of the second gate initialization signal line GSTV2 and the second gate voltage signal line GVGH on the substrate. It should be noted that the at least one third connection segment 231 is located in the first gate conductive layer Gt1 and is relatively far away from the source-drain conductive layer SD. Therefore, the signal transmitted by the third connection segment 231 is less susceptible to interference from parasitic capacitance. Figure 12 In the figure, at least one third connection segment 231 is located in the first gate conductive layer Gt1 as an example.

[0218] Illustratively, the second gate initial connection line 1103 includes a first connection segment 251, a second connection segment 221, and a third connection segment 231, which are connected in sequence. The orthographic projection of the third connection segment 231 on the substrate 21 intersects with the orthographic projections of the second gate voltage signal line GVGH and the second gate initialization signal line GSTV2 on the substrate 21. An end of the first connection segment 251 away from the third connection segment 231 is coupled to the corresponding second gate input transistor (the first transistor T1 mentioned in the gate shift register above), and an end of the third connection segment 231 away from the first connection segment 251 is coupled to the second gate initialization signal line GSTV2.

[0219] In this case, the third connection segment 231 can be formed in the first gate conductive layer Gt1 or the second gate conductive layer Gt2 so that the second gate initial connection line 1103 can be electrically connected to the second gate initialization signal line GSTV2 across the second gate voltage signal line GVGH.

[0220] In some embodiments, see Figure 13The first gate initial connection line 1104 further includes at least one ninth connection segment 232. The at least one ninth connection segment 232 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the ninth connection segment 232 on the substrate 21 intersects with the orthographic projection of at least one of the first gate initialization signal line GSTV1, the first gate clock signal line GCK, and the second gate clock signal line GCB on the substrate 21. It should be noted that the at least one ninth connection segment 232 is located in the first gate conductive layer Gt1 and is relatively far away from the source / drain conductive layer SD. Therefore, the signal transmitted by the ninth connection segment 232 is less susceptible to interference from parasitic capacitance. Figure 13 In the figure, at least one ninth connecting segment 232 is located in the first gate conductive layer Gt1 as an example.

[0221] Illustratively, the orthographic projection of the ninth connecting segment 232 on the substrate 21 intersects the orthographic projections of the first gate initialization signal line GSTV1, the first gate clock signal line GCK, and the second gate clock signal line GCB on the substrate 21. An end of the seventh connecting segment 252 remote from the ninth connecting segment 232 is coupled to the corresponding first gate input transistor (the first transistor T1 mentioned in the gate shift register above), and an end of the ninth connecting segment 232 remote from the seventh connecting segment 252 is coupled to the first gate initialization signal line GSTV1.

[0222] In this case, a ninth connection segment 232 can be formed on the first gate conductive layer Gt1 or the second gate conductive layer Gt2 so that the first gate initial connection line 1104 can cross the first gate clock signal line GCK, the second gate clock signal line GCB and the first gate initialization signal line GSTV1 to achieve electrical connection.

[0223] The connections between the multiple connection segments of the first gate initial connection line 1104 and the second gate initial connection line 1103 are all through via holes HL (see Figure 19 ) is realized, during the process, usually etching or laser drilling is performed from the source-drain conductive layer SD toward the substrate 21 side to form the via hole HL.

[0224] Based on this, in some embodiments, such as Figure 12 and Figure 19 The second gate initial connection line 1103 includes a plurality of sequentially connected connection segments, and the source-drain conductive layer SD includes a plurality of first connection patterns 257 . Each first connection pattern 257 electrically connects two adjacent connection segments of the second gate initial connection line 1103 through a via HL.

[0225] In some embodiments, see Figure 13 The first gate initial connection line 1104 includes a plurality of sequentially connected connection segments, the source-drain conductive layer SD includes a plurality of third connection patterns 259, each of which is connected through a via HL (see Figure 19 ) electrically connects two adjacent connection segments of the first gate initial connection line 1104.

[0226] In some embodiments, as Figure 12 As shown, the second gate initial connection line 1103 extends substantially along the first direction X and is located between two adjacent stages of gate shift registers GRS.

[0227] Among them, for the first stage second gate shift register of the second gate scanning control unit 1122, as shown in FIG. Figure 12 As shown, the corresponding second gate initial connection line 1103 is located between the last stage first gate shift register of the first gate scan control unit 1121 and the first stage second gate shift register of the second gate scan control unit 1122 .

[0228] If the first S-level second gate shift registers of the second gate scan control unit 1122 are coupled to the second gate initialization signal line GSTV2, the second gate initial connection lines 1103 corresponding to the remaining S-1-level second gate shift registers, except for the first-level second gate shift register, are located between two adjacent second gate shift registers.

[0229] In some embodiments, the first gate initial connection line 1104 extends substantially along the first direction X. For the first stage gate shift register of the first gate scanning control unit 1121, as shown in FIG. Figure 13 As shown, the corresponding first gate initial connection line 1104 is located at a side of the first stage gate shift register of the first gate scanning control unit 1121 away from the last stage first gate shift register.

[0230] If the first S-stage first gate shift registers of the first gate scan control unit 1121 are coupled to the first gate initialization signal line GSTV1, the first gate initial connection lines 1104 corresponding to the remaining S-1-stage first gate shift registers, except for the first-stage first gate shift register, are located between two adjacent first gate shift registers.

[0231] In some embodiments, as Figure 4 、 Figure 5 and Figure 12 As shown, the second scan control sub-circuit 1102 further includes a plurality of second gate connection lines 253. The plurality of second gate connection lines 253 correspond to the second gate shift registers of the other stages except the first S stage. One end of each second gate connection line 253 is coupled to the output terminal OPUT of the second gate shift register of the previous stage, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register. The plurality of second gate connection lines 253 can be located in the source-drain conductive layer SD.

[0232] In some embodiments, as Figure 4 、 Figure 5 and Figure 13 As shown, the first scan control subcircuit 1101 further includes a plurality of first gate connection lines 254, each corresponding to a first gate shift register of each stage except the first S stage. One end of each first gate connection line 254 is coupled to the output terminal OPUT of the first gate shift register of the previous stage, and the other end is coupled to the first gate input transistor of the corresponding first gate shift register. The plurality of first gate connection lines 254 can be located in the source-drain conductive layer SD.

[0233] In some embodiments, as Figure 4 and Figure 17 As shown, the scanning control circuit 100 includes a first light-emitting control subcircuit 1105 corresponding to the first display area A1, and a second light-emitting control subcircuit 1106 corresponding to the second display area A2. The first light-emitting control subcircuit 1105 includes a first light-emitting scanning control unit 1131, and the second light-emitting control subcircuit 1106 includes a second light-emitting scanning control unit 1132.

[0234] See 4 and Figure 17 The plurality of light-emission initialization signal lines ESTV include a first light-emission initialization signal line ESTV1 and a second light-emission initialization signal line ESTV2. The first light-emission initialization signal line ESTV1 is coupled to the first light-emission scan control unit 1131, and the second light-emission initialization signal line ESTV2 is coupled to the second light-emission scan control unit 1132. The at least one first light-emission voltage signal line EVGL includes a first sub-light-emission voltage signal line EVGL1 and a second sub-light-emission voltage signal line EVGL2.

[0235] like Figure 17 As shown, along the first direction X, and from the inner side of the display area A to the outer side ( Figure 17 The second light-emitting initialization signal line ESTV2, the first sub-light-emitting voltage signal line EVGL1, the second light-emitting voltage signal line EVGH, the second sub-light-emitting voltage signal line EVGL2, the first light-emitting clock signal line ECK, the second light-emitting clock signal line ECB, and the first light-emitting initialization signal line ESTV1 are arranged in sequence, and the first light-emitting scan control unit 1131 and the second light-emitting scan control unit 1132 are located between the first sub-light-emitting voltage signal line EVGL1 and the first light-emitting clock signal line ECK.

[0236] It should be noted that the orthographic projection of the second sub-light emitting voltage signal line EVGL2 on the substrate 21 can overlap with the orthographic projection of the second capacitor C2 in the light emitting shift register ERS on the substrate 21, and the area where the second sub-light emitting voltage signal line EVGL2 overlaps with the second capacitor C2 in the light emitting shift register ERS can be directly connected to the substrate 21 through the via HL (see Figure 20 ) to achieve electrical connection and simplify wiring layout.

[0237] In addition, the orthographic projection of the second light emitting voltage signal line EVGH on the substrate 21 can overlap with the orthographic projection of the third capacitor C3 in the light emitting shift register ERS on the substrate 21, and the area where the second light emitting voltage signal line EVGH overlaps with the third capacitor C3 in the light emitting shift register ERS can be directly connected to the substrate 21 through the via hole HL (see Figure 20 ) to achieve electrical connection and simplify wiring layout.

[0238] In some embodiments, as Figure 17 As shown, the second light-emitting scanning control unit 1132 includes a plurality of cascaded second light-emitting shift registers arranged in parallel along the second direction Y, and each stage of the second light-emitting shift register includes a second light-emitting input transistor (the first transistor T1 mentioned in the above light-emitting shift register).

[0239] On this basis, the second light-emission control subcircuit 1106 further includes S second light-emission initial connection lines 1107, each corresponding to the first S stages of the second light-emission shift register. One end of each second light-emission initial connection line 1107 is coupled to the second light-emission initialization signal line ESTV2, and the other end is coupled to the second light-emission input transistor (the first transistor T1 mentioned in the light-emission shift register) of the corresponding second light-emission shift register. Where S ≥ 1, and S is an integer. Figure 17 In the figure, S=1 is taken as an example for illustration.

[0240] In some embodiments, see Figure 17 The first light-emitting scanning control unit 1131 includes a plurality of cascaded first light-emitting shift registers arranged in parallel along the second direction Y, and each stage of the first light-emitting shift register includes a first light-emitting input transistor (the first transistor T1 mentioned in the above light-emitting shift register).

[0241] On this basis, if Figure 18 As shown, the first light-emission scanning control unit 1131 also includes S first light-emission initial connection lines 1108, each corresponding to the first light-emission shift register of the first S stage. One end of each first light-emission initial connection line 1108 is coupled to the first light-emission initialization signal line ESTV1, and the other end is coupled to the first light-emission input transistor of the corresponding first light-emission shift register (the first transistor T1 mentioned in the light-emission shift register above). Where S ≥ 1, and S is an integer.

[0242] In some embodiments, as Figure 17 and Figure 21As shown, the second light-emitting initial connection line 1107 includes at least one fourth connection segment 255 and at least one fifth connection segment 223. The at least one fourth connection segment 255 is located in the source-drain conductive layer SD, and the orthographic projection of the fourth connection segment 255 on the substrate 21 is separated from the orthographic projection of any signal line in the second light-emitting control subcircuit 1106 on the substrate 21. At least one fifth connection segment 223 is located in the semiconductor layer ACT, and the orthographic projection of the fifth connection segment 223 on the substrate 21 is separated from the orthographic projection of any signal line in the second light-emitting control subcircuit 1106 on the substrate 21. The resistivity of the fifth connection segment 223 is greater than that of the fourth connection segment 255, so as to reduce the risk of static electricity generated during the process causing a sudden change in the initialization signal provided by the second light-emitting initialization signal line ESTV2.

[0243] It should be noted that the resistivity of the fifth connecting segment 223 being greater than the resistivity of the fourth connecting segment 255 can be achieved by the materials of the semiconductor layer ACT and the source / drain conductive layer SD. For example, the material of the semiconductor layer ACT includes at least one of low-temperature polysilicon, single crystal silicon, and a metal oxide, and the source / drain conductive layer SD includes at least one of copper, aluminum, and silver.

[0244] In some embodiments, see Figure 18 The first light-emitting initial connection line 1108 includes at least one tenth connection segment 256 and at least one eleventh connection segment 224. The at least one tenth connection segment 256 is located in the source-drain conductive layer SD, and the orthographic projection of the tenth connection segment 256 on the substrate 21 is separated from the orthographic projection of any signal line in the first scan control sub-circuit 1101 on the substrate 21. The at least one eleventh connection segment 224 is located in the semiconductor layer ACT, and the orthographic projection of the eleventh connection segment 224 on the substrate 21 is separated from the orthographic projection of any signal line in the first scan control sub-circuit 1101 on the substrate 21. The resistivity of the eleventh connection segment 224 is greater than the resistivity of the tenth connection segment 256, so as to reduce the risk of static electricity generated during the process causing a sudden change in the initialization signal provided by the first light-emitting initialization signal line ESTV1.

[0245] In some embodiments, as Figure 17 and Figure 21As shown, the second light-emitting initial connection line 1107 further includes at least one sixth connection segment 233. The at least one sixth connection segment 233 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the sixth connection segment 233 on the substrate 21 intersects the orthographic projection on the substrate of at least one of the second light-emitting initialization signal line ESTV2, the first sub-light-emitting voltage signal line EVGL1, and the second light-emitting voltage signal line EVGH. It should be noted that the at least one sixth connection segment 233 is located in the first gate conductive layer Gt1, which is relatively far from the source-drain conductive layer SD. Therefore, the signal transmitted by the sixth connection segment 233 is less susceptible to interference from parasitic capacitance. Figure 17 In the figure, at least one sixth connection segment 233 is located in the first gate conductive layer Gt1 as an example for illustration.

[0246] For example, Figure 17 and Figure 21 As shown, the second light-emitting initial connection line 1107 includes a fourth connection segment 255, a first sixth connection segment 2331, a fifth connection segment 223, and a second sixth connection segment 2332, which are connected in sequence. The orthographic projection of the first sixth connection segment 2331 on the substrate 21 intersects with the orthographic projection of the second light-emitting voltage signal line EVGH on the substrate 21; the orthographic projection of the second sixth connection segment 2332 on the substrate 21 intersects with the orthographic projections of the first sub-light-emitting voltage signal line EVGL1 and the second light-emitting initialization signal line ESTV2 on the substrate 21. The end of the fourth connection segment 255 away from the second sixth connection segment 2332 is coupled to the corresponding second light-emitting input transistor (the first transistor T1 mentioned in the light-emitting shift register above), and the end of the second sixth connection segment 2332 away from the fourth connection segment 255 is coupled to the second light-emitting initialization signal line ESTV2.

[0247] In this case, two sixth connection segments 233 can be made on the first gate conductive layer Gt1 or the second gate conductive layer Gt2, so that the second gate initial connection line 1103 can cross the second light-emitting voltage signal line EVGH, the first sub-light-emitting voltage signal line EVGL1 and the second light-emitting initialization signal line ESTV2 to achieve electrical connection.

[0248] In some embodiments, see Figure 18The first light-emitting initial connection line 1108 further includes at least one twelfth connection segment 234. The at least one twelfth connection segment 234 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the twelfth connection segment 234 on the substrate 21 intersects with the orthographic projection of at least one of the first light-emitting initialization signal line ESTV1, the first light-emitting clock signal line ECK, the second light-emitting clock signal line ECB, and the second sub-light-emitting voltage signal line EVGL2 on the substrate 21. It should be noted that the at least one twelfth connection segment 234 is located in the first gate conductive layer Gt1 and is relatively far away from the source-drain conductive layer SD. Therefore, the signal transmitted by the twelfth connection segment 234 is less susceptible to interference from parasitic capacitance. Figure 18 The example in which at least one twelfth connecting segment 234 is located in the first gate conductive layer Gt1 is used for illustration.

[0249] For example, Figure 18 As shown, the orthographic projection of the twelfth connecting segment 234 on the substrate 21 intersects the orthographic projections of the first light-emission initialization signal line ESTV1, the first light-emission clock signal line ECK, the second light-emission clock signal line ECB, and the second sub-light-emission voltage signal line EVGL2 on the substrate 21. The end of the tenth connecting segment 256 away from the twelfth connecting segment 234 is coupled to the corresponding first light-emission input transistor (the first transistor T1 mentioned in the light-emission shift register above), and the end of the twelfth connecting segment 234 away from the tenth connecting segment 256 is coupled to the first light-emission initialization signal line ESTV1.

[0250] In this case, the twelfth connecting segment 234 can be made in the first gate conductive layer Gt1 or the second gate conductive layer Gt2, so that the first light-emitting initial connection line 1108 can cross the second sub-light-emitting voltage signal line EVGL2, the first light-emitting clock signal line ECK, the second light-emitting clock signal line ECB and the first light-emitting initialization signal line ESTV1 to achieve electrical connection.

[0251] The connections between the multiple connection segments of the first initial light-emitting connection line 1108 and the second initial light-emitting connection line 1107 are all through via holes HL (see Figure 20 ) is realized, during the process, usually etching or laser drilling is performed from the source-drain conductive layer SD toward the substrate 21 side to form the via hole HL.

[0252] Based on this, in some embodiments, such as Figure 17 and Figure 20 As shown, the second initial light-emitting connection line 1107 includes multiple connection segments connected in sequence, and the source-drain conductive layer SD includes multiple second connection patterns 258. Each second connection pattern 258 electrically connects two adjacent connection segments of the second initial light-emitting connection line 1107 through a via HL.

[0253] In some embodiments, as Figure 18 As shown, the first initial light-emitting connection line 1108 includes a plurality of sequentially connected connection segments, the source-drain conductive layer SD includes a plurality of fourth connection patterns 260, each of which is connected to the source-drain conductive layer SD by a via hole HL (see FIG. Figure 20 ) electrically connects two adjacent connection segments of the first light-emitting initial connection line 1108.

[0254] In some embodiments, see Figure 17 The second initial light-emitting connection line 1107 extends substantially along the first direction X and is located between two adjacent light-emitting shift registers ERS.

[0255] Among them, for the first-level second light-emitting shift register of the second light-emitting scan control unit 1132, its corresponding second light-emitting initial connection line 1107 is located between the last-level first light-emitting shift register of the first light-emitting scan control unit 1131 and the first-level second light-emitting shift register of the second light-emitting scan control unit 1132.

[0256] If the first S-level second light-emitting shift registers of the second light-emitting scanning control unit 1132 are coupled to the second light-emitting initialization signal line ESTV2, the second light-emitting initial connection lines 1107 corresponding to the remaining S-1-level second light-emitting shift registers, except for the first-level second light-emitting shift register, are located between two adjacent second light-emitting shift registers.

[0257] In some embodiments, see Figure 18 The first initial light-emitting connection line 1108 extends substantially along the first direction X. For the first-stage light-emitting shift register of the first light-emitting scan control unit 1131 , the corresponding first initial light-emitting connection line 1108 is located on a side of the first-stage light-emitting shift register of the first light-emitting scan control unit 1131 away from the last-stage first light-emitting shift register.

[0258] If the first S-level first light-emitting shift registers of the first light-emitting scanning control unit 1131 are coupled to the first light-emitting initialization signal line ESTV1, except for the first-level first light-emitting shift register, the first light-emitting initial connection lines 1108 corresponding to the remaining S-1-level first light-emitting shift registers are located between two adjacent first light-emitting shift registers.

[0259] In some embodiments, see Figure 4 、 Figure 7 and Figure 17The second scan control subcircuit 1102 further includes a plurality of second light-emitting connection lines 261, each corresponding to a second light-emitting shift register of each stage except the first S stage. One end of each second light-emitting connection line 261 is coupled to the output terminal OPUT of the second light-emitting shift register of the previous stage, and the other end is coupled to the second light-emitting input transistor of the corresponding second light-emitting shift register.

[0260] Among them, such as Figure 17 As shown, the second light-emitting connection line 261 may include at least one thirteenth connection segment 262 and at least one fourteenth connection segment 241. The thirteenth connection segment 262 is located in the source-drain conductive layer SD. The orthographic projection of the thirteenth connection segment 262 on the substrate 21 is separated from the orthographic projection of any signal line in the second scan control sub-circuit 1101 on the substrate 21. The fourteenth connection segment 241 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the fourteenth connection segment 241 on the substrate 21 intersects the orthographic projection of the second light-emitting voltage signal line EVGH on the substrate 21 and the orthographic projection of the signal line coupled to the gate scan control unit 112 on the substrate 21. Figure 17 The fourteenth connecting segment 241 located in the second gate conductive layer Gt2 is taken as an example for illustration.

[0261] In addition, one end of the thirteenth connecting segment 262 away from the fourteenth connecting segment 241 is coupled to the second light-emitting input transistor of the corresponding second light-emitting shift register, and the fourteenth connecting segment 241 is coupled to the output end OPUT of the previous second light-emitting shift register.

[0262] It should be noted that the fourteenth connecting segment 241 also crosses the gate scanning unit to be electrically connected to the pixel driving circuit.

[0263] In some embodiments, see Figure 4 、 Figure 7 and Figure 18 The first scan control subcircuit 1101 further includes a plurality of first light-emitting connection lines 263, each corresponding to a first light-emitting shift register of each stage except the first S stage. One end of each first light-emitting connection line 263 is coupled to the output terminal OPUT of the first light-emitting shift register of the previous stage, and the other end is coupled to the first light-emitting input transistor of the corresponding first light-emitting shift register.

[0264] Among them, such as Figure 18As shown, the second light-emitting connection line 263 may include at least one fifteenth connection segment 264 and at least one sixteenth connection segment 242. The fifteenth connection segment 264 is located in the source-drain conductive layer SD. The orthographic projection of the fifteenth connection segment 264 on the substrate 21 is separated from the orthographic projection of any signal line in the second scan control sub-circuit 1101 on the substrate 21. The sixteenth connection segment 242 is located in the first gate conductive layer Gt1 or the second gate conductive layer Gt2. The orthographic projection of the sixteenth connection segment 242 on the substrate 21 intersects the orthographic projection of the second light-emitting voltage signal line EVGH on the substrate 21 and the orthographic projection of the signal line coupled to the gate scan control unit 112 on the substrate 21. Figure 18 The sixteenth connecting segment 242 located in the second gate conductive layer Gt2 is taken as an example for illustration.

[0265] In addition, one end of the fifteenth connecting segment 264 away from the sixteenth connecting segment 242 is coupled to the second light-emitting input transistor of the corresponding second light-emitting shift register, and the sixteenth connecting segment 242 is coupled to the output end OPUT of the previous second light-emitting shift register.

[0266] It should be noted that the sixteenth connecting segment 242 also crosses the gate scanning control unit 122 and is coupled to the corresponding pixel driving circuit 200 .

[0267] Some embodiments of the present disclosure provide a display panel 20. Figure 2 、 Figure 3 and Figure 4 As shown, the display panel 20 includes a display substrate 2 and a control integrated circuit 3 as in any of the above embodiments. It should be noted that the control integrated circuit 3 can be a timing control chip.

[0268] The control integrated circuit 3 is coupled to a plurality of initialization signal lines STV in the scan control circuit 100 of the display substrate 2. The control integrated circuit 3 is configured to transmit a first initialization signal to the initialization signal lines STV corresponding to the display areas A that do not need to display, thereby turning off the scan control sub-circuits 110 corresponding to the display areas A that do not need to display; and to transmit a second initialization signal to the initialization signal lines STV corresponding to the display areas A that do need to display, thereby turning on the scan control sub-circuits 110 corresponding to the display areas A that do need to display.

[0269] In some embodiments, when at least two adjacent display areas A need to be displayed, along the second direction Y, in the two adjacent display areas A, the second initialization signal transmitted by the initialization signal line STV corresponding to the next display area A is the same as the signal output by the last output terminal OPUT of the scanning control subcircuit 110 corresponding to the previous display area A, so as to realize the common display of the two adjacent display areas A.

[0270] Some embodiments of the present disclosure also provide a display device 1. Figure 1A As shown, the display device 1 includes a display panel 20 as described in any of the above embodiments.

[0271] In some embodiments, the display device 1 can be folded along the boundary line between adjacent display areas A.

[0272] Some embodiments of the present disclosure also provide a driving method of a scanning control circuit, which is applied to the scanning control circuit of any of the above embodiments. Figure 22 As shown, the driving method includes S1 and S2.

[0273] S1, when the target display area of ​​the display panel 20 does not need to display, the initialization signal line STV coupled to the scan control sub-circuit 110 corresponding to the target display area provides a first initialization signal to the scan control sub-circuit 110 to turn off the scan control sub-circuit 110.

[0274] In the above steps, the signal input terminal of the first transistor of the first stage shift register of the scan control subcircuit 110 corresponding to the target display area is turned off under the control of the first initialization signal, so that the corresponding scan control subcircuit 110 is turned off.

[0275] S2 , when the target display area needs to display, the initialization signal line STV coupled to the scan control sub-circuit 110 corresponding to the target display area provides a second initialization signal to the scan control sub-circuit 110 to turn on the scan control sub-circuit 110 .

[0276] In the above steps, the signal input terminal of the first transistor of the first stage shift register of the scan control subcircuit 110 corresponding to the target display area is turned on under the control of the second initialization signal, so that the corresponding scan control subcircuit 110 is turned on.

[0277] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: The device comprises Q display areas, where Q=2; the Q display areas include a first display area and a second display area arranged in parallel along a second direction; and the display substrate comprises: substrate; At least one scanning control circuit is provided on the substrate, wherein the scanning control circuit comprises: 2Q initialization signal lines, wherein Q of the 2Q initialization signal lines are gate initialization signal lines and Q are light-emitting initialization signal lines; Q scan control sub-circuits, each scan control sub-circuit corresponding to a display area; the scan control sub-circuit includes: a gate scanning control unit, each gate scanning control unit being coupled to a gate initialization signal line, and different gate scanning control units being coupled to different gate initialization signal lines; the gate scanning control unit being configured to be turned on or off under the control of a gate initialization signal from the gate initialization signal line, so as to drive the corresponding display area to display or not display; a light-emitting scanning control unit, each light-emitting scanning control unit being coupled to a light-emitting initialization signal line, and different light-emitting scanning control units being coupled to different light-emitting initialization signal lines; the light-emitting scanning control unit being configured to turn on or off under the control of a light-emitting initialization signal from the light-emitting initialization signal line, so as to drive the corresponding display area to display or not display; The two gate initialization signal lines extend along the second direction, and one gate initialization signal line is arranged on a side of the light emitting scanning control unit away from the display area, and the other gate initialization signal line is arranged on a side of the light emitting scanning control unit close to the display area; The two light emitting initialization signal lines extend along the second direction, and one of the light emitting initialization signal lines is arranged on a side of the light emitting scanning control unit away from the display area, and the other light emitting initialization signal line is arranged on a side of the light emitting scanning control unit close to the display area; The scanning control circuit includes: a first scanning control subcircuit corresponding to the first display area, a second scanning control subcircuit corresponding to the second display area, and a first light-emitting initialization signal line and a second light-emitting initialization signal line; The first scan control subcircuit includes a first light-emitting scan control unit, and the second scan control subcircuit includes a second light-emitting scan control unit; the first light-emitting initialization signal line is coupled to the first light-emitting scan control unit, and the second light-emitting initialization signal line is coupled to the second light-emitting scan control unit; The scan control subcircuit also includes a plurality of light-emitting initialization signal lines, a first sub-light-emitting voltage signal line, a second sub-light-emitting voltage signal line, a second light-emitting voltage signal line, a first light-emitting clock signal line and a second light-emitting clock signal line coupled to the light-emitting scan control unit; along a first direction and from the inner side of the display area to the outer side, the second light-emitting initialization signal line, the first sub-light-emitting voltage signal line, the second light-emitting voltage signal line, the second sub-light-emitting voltage signal line, the first light-emitting clock signal line, the second light-emitting clock signal line and the first light-emitting initialization signal line are arranged in sequence; the first light-emitting scan control unit and the second light-emitting scan control unit are located between the first sub-light-emitting voltage signal line and the first light-emitting clock signal line; the light-emitting scan control unit includes a ninth transistor, the first electrode of the ninth transistor is connected to the second light-emitting voltage signal line, and the second electrode of the ninth transistor is coupled to the output end.

2. The display substrate according to claim 1, wherein: comprising a first display area and a second display area arranged in parallel along a second direction, wherein the scan control circuit comprises: a first scan control subcircuit corresponding to the first display area, a second scan control subcircuit corresponding to the second display area, and a first gate initialization signal line and a second gate initialization signal line; The first scan control subcircuit includes a first gate scan control unit, and the second scan control subcircuit includes a second gate scan control unit; the first gate initialization signal line is coupled to the first gate scan control unit, and the second gate initialization signal line is coupled to the second gate scan control unit; The scan control subcircuit also includes a first gate voltage signal line, a second gate voltage signal line, a first gate clock signal line, and a second gate clock signal line coupled to the gate scan control unit; along a first direction and from the inner side to the outer side of the display area, the second gate initialization signal line, the second gate voltage signal line, the first gate voltage signal line, the first gate clock signal line, the second gate clock signal line, and the first gate initialization signal line are arranged in sequence, and the first gate scan control unit and the second gate scan control unit are located between the second gate initialization signal line and the first gate voltage signal line.

3. The display substrate according to claim 1, wherein The scan control circuit includes a second scan control subcircuit and a second gate initialization signal line, the second scan control subcircuit includes a second gate scan control unit; the second gate scan control unit includes a plurality of cascaded second gate shift registers arranged in parallel along the second direction, each stage of the second gate shift register includes a second gate input transistor; The second scanning control sub-circuit further includes: S second gate initial connection lines, each corresponding to the first S stage second gate shift register; one end of each second gate initial connection line is coupled to the second gate initialization signal line, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register; S≥1, and S is an integer.

4. The display substrate according to claim 1, wherein The scan control circuit includes a second scan control subcircuit, the second scan control subcircuit includes a second gate initial connection line, and the display substrate includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer sequentially disposed on the substrate; The second gate initial connection line includes: at least one first connecting segment located in the source-drain conductive layer; an orthographic projection of the first connecting segment on the substrate is separated from an orthographic projection of any signal line in the second scan control subcircuit on the substrate; at least one second connecting segment located in the semiconductor layer; an orthographic projection of the second connecting segment on the substrate is separated from an orthographic projection of any signal line in the second scan control subcircuit on the substrate; The resistivity of the second connecting section is greater than the resistivity of the first connecting section.

5. The display substrate according to claim 4, wherein: The scanning control circuit includes a second gate initialization signal line and a second gate voltage signal line; the second gate initial connection line also includes: At least one third connecting segment is located in the first gate conductive layer or the second gate conductive layer; the orthographic projection of the third connecting segment on the substrate intersects with the orthographic projection of at least one of the second gate initialization signal line and the second gate voltage signal line on the substrate.

6. The display substrate according to claim 4, wherein: The second gate initial connection line includes a plurality of connection segments connected in sequence; The source-drain conductive layer includes a plurality of first connection patterns, and each first connection pattern electrically connects two adjacent connection segments of the second gate initial connection line through a via hole.

7. The display substrate according to claim 4, wherein: The scan control circuit includes a second gate initialization signal line and a second gate voltage signal line; the second scan control sub-circuit includes a second gate scan control unit, the second gate scan control unit includes a second gate shift register, and the second gate shift register includes a second gate input transistor; The second gate initial connection line includes a first connection segment, a second connection segment and a third connection segment connected in sequence; An orthographic projection of the third connecting segment on the substrate intersects with an orthographic projection of the second gate voltage signal line and the second gate initialization signal line on the substrate; One end of the first connection segment away from the third connection segment is coupled to the corresponding second gate input transistor, and one end of the third connection segment away from the first connection segment is coupled to the second gate initialization signal line.

8. The display substrate according to claim 4, wherein: The second gate initial connection line extends substantially along the first direction and is located between two adjacent stages of gate shift registers.

9. The display substrate according to claim 3, wherein: Including a source-drain conductive layer, the second scan control sub-circuit further includes: a plurality of second gate connection lines, each corresponding to a second gate shift register of each stage except the first S stage; one end of each second gate connection line is coupled to the output end of the second gate shift register of the previous stage, and the other end is coupled to the second gate input transistor of the corresponding second gate shift register; The plurality of second gate connection lines are located in the source-drain conductive layer.

10. The display substrate according to any one of claims 3 to 9, wherein: The scanning control circuit includes a first gate scanning control subcircuit and a first gate initialization signal line, the first gate scanning control subcircuit includes a first gate scanning control unit; the first gate scanning control unit includes a plurality of cascaded first gate shift registers arranged in parallel along the second direction, each stage of the first gate shift register including a first gate input transistor; The first scanning control sub-circuit further includes: S first gate initial connection lines correspond to the first S stage first gate shift registers respectively; one end of each first gate initial connection line is coupled to the first gate initialization signal line, and the other end is coupled to the first gate input transistor of the corresponding first gate shift register.

11. The display substrate according to claim 1, wherein The second light emitting scanning control unit includes a plurality of cascaded second light emitting shift registers arranged in parallel along the second direction, and each stage of the second light emitting shift register includes a second light emitting input transistor; The second light emitting control subcircuit further includes: S second light-emitting initial connection lines correspond to the first S stages of the second light-emitting shift registers respectively; one end of each second light-emitting initial connection line is coupled to the second light-emitting initialization signal line, and the other end is coupled to the second light-emitting input transistor of the corresponding second light-emitting shift register; S≥1, and S is an integer.

12. The display substrate according to claim 11, wherein: It includes a semiconductor layer, a first gate conductive layer, a second gate conductive layer and a source-drain conductive layer which are sequentially arranged on the substrate; The second initial light-emitting connection line includes: at least one fourth connecting segment located in the source-drain conductive layer; an orthographic projection of the fourth connecting segment on the substrate is separated from an orthographic projection of any signal line in the second light-emitting control subcircuit on the substrate; at least one fifth connecting segment located in the semiconductor layer; an orthographic projection of the fifth connecting segment on the substrate is separated from an orthographic projection of any signal line in the second light-emitting control subcircuit on the substrate; wherein the resistivity of the fifth connecting segment is greater than the resistivity of the fourth connecting segment; At least one sixth connecting segment is located in the first gate conductive layer or the second gate conductive layer; the orthographic projection of the sixth connecting segment on the substrate intersects with the orthographic projection of at least one of the second light-emitting initialization signal line, the first sub-light-emitting voltage signal line, and the second light-emitting voltage signal line on the substrate.

13. The display substrate according to claim 12, wherein: The second initial light-emitting connection line includes a plurality of connection segments connected in sequence; The source-drain conductive layer includes a plurality of second connection patterns, and each second connection pattern electrically connects two adjacent connection segments of the second light-emitting initial connection line through a via hole.

14. The display substrate according to claim 12 or 13, wherein: The second initial light-emitting connection line includes a fourth connection segment, a first sixth connection segment, a fifth connection segment and a second sixth connection segment connected in sequence; The orthographic projection of the first sixth connecting segment on the substrate intersects with the orthographic projection of the second light-emitting voltage signal line on the substrate; The orthographic projection of the second sixth connecting segment on the substrate intersects with the orthographic projections of the first sub-light-emitting voltage signal line and the second light-emitting initialization signal line on the substrate; One end of the fourth connection segment away from the second sixth connection segment is coupled to the corresponding second light-emitting input transistor, and one end of the second sixth connection segment away from the fourth connection segment is coupled to the second light-emitting initialization signal line.

15. The display substrate according to claim 1, wherein The gate scanning control unit and the light emitting scanning control unit in the same scanning control subcircuit are arranged in parallel along a first direction; the Q display areas are arranged in parallel along a second direction; the first direction is substantially perpendicular to the second direction; The gate scanning control units in the Q scanning control sub-circuits are arranged in parallel along the second direction, and the light emitting scanning control units in the Q scanning control sub-circuits are arranged in parallel along the second direction.

16. The display substrate according to claim 1, wherein In each scan control sub-circuit, the gate scan control unit is closer to the corresponding display area than the light emitting scan control unit.

17. The display substrate according to claim 1, wherein The gate scanning control unit includes a plurality of cascaded gate shift registers, wherein the first S-stage gate shift registers are coupled to a gate initialization signal line, S≥1, and S is an integer; and / or, The light-emitting scanning control unit includes a plurality of cascaded light-emitting shift registers, wherein the first S-stage light-emitting shift registers are coupled to a light-emitting initialization signal line, where S≥1 and S is an integer.

18. A display panel, characterized in that: include: The display substrate according to any one of claims 1 to 17; A control integrated circuit is coupled to multiple initialization signal lines in the scanning control circuit of the display substrate; the control integrated circuit is configured to transmit a first initialization signal to the initialization signal line corresponding to the display area that does not need to be displayed, so as to turn off the scanning control sub-circuit corresponding to the display area that does not need to be displayed; and transmit a second initialization signal to the initialization signal line corresponding to the display area that needs to be displayed, so as to turn on the scanning control sub-circuit corresponding to the display area that needs to be displayed.

19. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

20. The display device according to claim 19, wherein The display device is foldable along a boundary line between adjacent display areas.

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