Storage component testing method and system, storage medium, and electronic device

Abstract

The application discloses a kind of storage assembly test method and system, storage medium and electronic equipment.The method comprises: in the case where receiving the first instruction sent by host, using the test parameter carried by first instruction to carry out the compatible test of main equipment and the slave equipment to be tested;Wherein, at least including: the first storage assembly corresponding to secure digital card and the second storage assembly corresponding to embedded memory on the slave equipment to be tested;In the process of carrying out the compatible test of main equipment and the slave equipment to be tested corresponding, the numerical set corresponding to multiple preset target parameters of main equipment is determined, and the numerical allowable range supported by the slave equipment to be tested for each parameter in multiple preset target parameters is determined;According to numerical set and numerical allowable range, it is determined whether the first storage assembly and / or second storage assembly in main equipment and the slave equipment to be tested is compatible.Solve the problem that the test efficiency of whether the storage assembly and other equipment are compatible in the prior art is lower.

Description

Technical Field

[0001] This invention relates to the field of testing, and more specifically, to a method and system for testing storage components, a storage medium, and an electronic device. Background Technology

[0002] Currently, TF cards (Trans-flash Card, generally referring to Micro SD cards) are widely used in various occasions. Due to the different types of mobile devices and different application scenarios, the compatibility test of TF cards is becoming increasingly severe.

[0003] The current common method involves inserting a card into a device to obtain the status information of the device under test. This requires finding a matching device, performing the operation once to obtain the status information, and then determining whether it meets expectations. This testing method cannot verify the compatibility performance of a large number of SD cards (Secure Digital Memory Card / SD card) and eMMC (Embedded Multi Media Card) in a single test. It requires numerous repetitive tests and cannot automatically evaluate the optimal compatibility of TF cards, SD cards, and eMMC cards. This consumes a significant amount of manpower and time, resulting in low testing efficiency.

[0004] There is currently no effective solution to the problem of low testing efficiency for compatibility issues between storage components and other devices in existing technologies. Summary of the Invention

[0005] This invention provides a method and system for testing storage components, a storage medium, and an electronic device, to at least solve the problem of low testing efficiency for compatibility of storage components with other devices in the prior art.

[0006] According to one aspect of the present invention, a storage component testing method is provided, comprising: upon receiving a first instruction sent by a host, performing a compatibility test between a master device and a slave device under test using test parameters carried by the first instruction; wherein the slave device under test includes at least: a first storage component corresponding to a security digital card and a second storage component corresponding to an embedded memory, and the master device is a device for adapting to the slave device; during the compatibility test between the master device and the slave device under test, determining a set of values ​​corresponding to multiple preset target parameters of the master device, and determining the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters; and determining whether the master device and the first storage component and / or the second storage component in the slave device under test are compatible based on the set of values ​​and the allowable range of values.

[0007] According to another aspect of the present invention, a storage component testing system is also provided, comprising: a host, configured to send a first instruction to a bridging chip; a bridging chip, configured to perform a compatibility test between a master device and a slave device under test using test parameters carried by the first instruction, wherein during the compatibility test between the master device and the slave device under test, the chip determines a set of values ​​corresponding to a plurality of preset target parameters of the master device, and determines a range of allowed values ​​supported by the slave device under test for each of the plurality of preset target parameters; a protocol analyzer, configured to normalize the set of values ​​corresponding to the plurality of preset target parameters existing in the master device, and map the normalization result to the range of allowed values, so as to determine whether the master device and a first storage component and / or a second storage component in the slave device under test are compatible based on the set of values ​​and the range of allowed values; a slave device under test, configured to install a first storage component corresponding to a security digital card to be tested and a second storage component corresponding to an embedded memory; and a master device, configured to adapt to the slave device.

[0008] According to another aspect of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the method in any of the method embodiments at runtime.

[0009] According to another aspect of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to perform the method in any of the above-described method embodiments through the computer program.

[0010] In this embodiment of the invention, upon receiving a first instruction from the host, a compatibility test between the master device and the slave device under test is performed using test parameters carried by the first instruction. The slave device under test includes at least a first storage component corresponding to a secure digital card and a second storage component corresponding to an embedded memory. During the compatibility test between the master device and the slave device under test, a set of values ​​corresponding to multiple preset target parameters of the master device is determined, as well as the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters is determined. Based on the set of values ​​and the allowable range of values, it is determined whether the first storage component and / or the second storage component in the master device and the slave device under test are compatible. That is, by establishing a connection between the master device and the slave device under test, and installing a secure digital card and an embedded memory in the slave device under test, compatibility testing of the secure digital card and the embedded memory is achieved within the same device. This reduces the number of repeated tests, significantly improves the efficiency of the compatibility test, and solves the problem of low testing efficiency for compatibility between storage components and other devices in the prior art. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0012] Figure 1 This is a hardware structure block diagram of a target terminal according to an embodiment of the present invention, which describes a storage component testing method.

[0013] Figure 2 This is a flowchart of a storage component testing method according to an embodiment of the present invention;

[0014] Figure 3 This is a schematic diagram of the structure corresponding to the test method for compatibility screening of parallel signal SD cards and eMMC according to an optional embodiment of the present invention;

[0015] Figure 4 A flowchart illustrating the process of obtaining the compatibility range of the device under test according to an optional embodiment of the present invention;

[0016] Figure 5 A flowchart illustrating how a protocol analyzer acquires master device information according to an optional embodiment of the present invention;

[0017] Figure 6 This is a schematic diagram of the structure of a storage component testing device according to an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] The method embodiments provided in this application can be executed on a target terminal, mobile terminal, or similar computing device. Taking running on a target terminal as an example, Figure 1 This is a hardware structure block diagram of the target terminal for a storage component testing method according to an embodiment of the present invention. Figure 1 As shown, the target terminal 10 may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. Optionally, the target terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the target terminal described above. For example, the target terminal 10 may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 Equivalent functions or ratios shown Figure 1 The functions shown have more different configurations.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the storage component testing method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the target terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the target terminal 10. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0023] Alternatively, as an alternative implementation method, such asFigure 2 As shown, the above-mentioned storage component testing methods include:

[0024] Step S202: Upon receiving a first instruction from the host, a compatibility test between the master device and the slave device under test is performed using the test parameters carried by the first instruction; wherein the slave device under test includes at least: a first storage component corresponding to a security digital card and a second storage component corresponding to an embedded memory; the master device is a device for adapting to the slave device;

[0025] Step S204: During the compatibility test between the master device and the slave device under test, determine the set of values ​​corresponding to multiple preset target parameters of the master device, and determine the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters.

[0026] Step S206: Determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the set of values ​​and the allowable range of values.

[0027] Through the above steps, upon receiving a first instruction from the host, the compatibility test between the master device and the slave device under test is performed using the test parameters carried by the first instruction. The slave device under test includes at least a first storage component corresponding to a secure digital card and a second storage component corresponding to an embedded memory. During the compatibility test between the master device and the slave device under test, the numerical set corresponding to multiple preset target parameters of the master device is determined, as well as the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters is determined. Based on the numerical set and the allowable range of values, the compatibility between the first storage component and / or the second storage component in the master device and the slave device under test is determined. That is, by establishing a connection between the master device and the slave device under test, and installing a secure digital card and an embedded memory in the slave device under test, compatibility testing of the secure digital card and the embedded memory is achieved within the same device. This reduces the number of repeated tests, greatly improves the efficiency of the compatibility test, and solves the problem of low testing efficiency for compatibility between storage components and other devices in the prior art.

[0028] Understandably, in practical applications, the host (which can be understood as a computer) and the master device are not the same device. The slave device refers to the SD card and EMMC under test. The slave device is installed on the bridge chip. After the bridge chip is connected to the host, the host sends the mode, voltage, and frequency to be tested to test the slave device and obtain the sampling point frequencies that the slave device can support. This provides a reference for the master device to adapt the slave device and ensure the effectiveness of compatibility.

[0029] In one exemplary embodiment, performing compatibility testing between the master device and the slave device under test using test parameters carried by a first instruction includes: establishing a communication connection between the master device and the slave device under test via a bridging chip; wherein the bridging chip is connected to the master device via a first target interface and the bridging chip is connected to the slave device under test via a second target interface; the first instruction is used to carry test parameters, the test parameters including at least: the transmission mode during master device communication, the signal voltage during master device communication, the signal frequency during master device communication, and the sampling points during master device communication; when the bridging chip receives the first instruction sent by the master device, performing compatibility testing between the master device and the slave device under test using the test parameters carried by the first instruction.

[0030] In practical applications, the host connects to the bridge chip via a USB interface and sends the mode, voltage, and frequency to be tested via write buffer commands. The bridge chip sets the relevant states according to the received data and begins testing (tests include power-on, read, and write operations). By adjusting different sampling points, the range of sampling points supported by the slave device under that mode, voltage, and frequency is determined. Simultaneously, the host continuously sends read buffer commands. If the slave device completes the test, it uploads the sampling point information (including high and low points). The host then sends the next set of test samples again via write buffer commands, repeating the above steps until the test is complete.

[0031] Understandably, the above read buffer instruction is mainly used to obtain the sampling information and test data information determined in the bridge chip in real time.

[0032] Optionally, determining whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the set of values ​​and the allowable range of values ​​includes the following steps:

[0033] Step 302: Upload the set of values ​​and the allowed range of values ​​to the protocol analyzer;

[0034] Step 304: Determine the relative positional relationship between the target mapping point corresponding to the set of values ​​fed back by the protocol analyzer and the target mapping range corresponding to the allowable range of values;

[0035] Step 306: Determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the relative positional relationship.

[0036] It should be noted that, in order to better align with practical applications, after obtaining the numerical set and allowable range, the protocol analyzer needs to normalize the coordinates of the allowable range corresponding to the device under test and calculate the coordinates (r, θ, φ) of each point in the three-dimensional spherical coordinate system. Simultaneously, based on the normalization parameters, it calculates the target coordinates of the numerical set corresponding to the master device in the graph. Points in the three-dimensional spherical coordinate system whose angular coordinates are close to the target coordinates are selected for comparison. If the radii corresponding to the target coordinates are all much smaller than the radius of the selected points, it indicates compatibility; if there are very close points, compatibility is questionable; if the radii corresponding to the target coordinates are all larger than the target coordinates, it indicates incompatibility.

[0037] By following the steps above, compatibility can be assessed using quantitative methods. This allows for a broad evaluation of the compatibility between newly introduced master and slave devices, improving the efficiency of compatibility assessment when a single storage device has a large number of devices that need to be adapted, and reducing the latency of compatibility determination.

[0038] There are multiple ways to determine whether the master device and the first storage component and / or the second storage component in the slave device under test are compatible based on the relative positional relationship in step S206 above. In one optional embodiment, it can be implemented by the following scheme: when the relative positional relationship indicates that the target mapping point is in the target area of ​​the target mapping range, the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is determined to be compatible, wherein the target area is the central area of ​​the target mapping range; when the relative positional relationship indicates that the target mapping point is outside the target area of ​​the target mapping range but within the target mapping range, the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is determined to be suspected compatible; when the relative positional relationship indicates that the target mapping point is outside the target mapping range, the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is determined to be incompatible.

[0039] It should be noted that, in order to improve the accuracy of data comparison, a protocol analyzer can be used to obtain the voltage, frequency, sampling point and mode used during master device communication. This point can be mapped to the slave device support range diagram. If it is clearly within the diagram, it means that it should be compatible; if it is on the edge or very close to the edge, it means that compatibility is questionable; if it is clearly outside the diagram, it means that it is not compatible.

[0040] As an optional implementation, determining the numerical set corresponding to multiple preset target parameters of the master device during the compatibility test between the master device and the slave device under test includes: parsing the first instruction sent by the host to obtain the test parameters corresponding to the compatibility test; determining the actual values ​​of the test parameters at different test stages to obtain the numerical set corresponding to multiple preset target parameters of the master device.

[0041] Optionally, determining the allowable range of values ​​supported by the slave device under test for each of the plurality of preset target parameters includes: determining the data transmission parameters corresponding to the security digital card and the embedded memory installed in the slave device under test; obtaining the transmission information supported by the slave device under test at different sampling points; and determining the allowable range of values ​​supported by the slave device under test for each of the plurality of preset target parameters based on the data transmission parameters and the transmission information.

[0042] It is understandable that by obtaining a three-dimensional scatter plot of the maximum voltage, frequency, and sampling points supported by a slave device in a certain mode, the range enclosed by connecting adjacent data in the scatter plot can be considered as the range of voltage, frequency, and sampling points supported by the slave device in the corresponding mode. This allows for the evaluation of the compatibility of different slave devices in the same mode.

[0043] It should be noted that the comparison of data values ​​between the master and slave devices is determined using a protocol analyzer. The protocol analyzer is used to obtain the voltage, frequency, and sampling point range of the master device, where the master device refers to the device adapted to the slave device. The voltage, frequency, and supported sampling point ranges of both the master and slave devices are obtained during the testing process. The voltage, frequency, and sampling points of the master device are normalized using a calculation program and then mapped to the slave device's supported range. If they fall within the slave device's supported range graph, compatibility is determined.

[0044] To better understand the technical solutions of the embodiments and optional embodiments of the present invention, the process of the above-described storage component testing method is explained below with reference to examples, but it is not intended to limit the technical solutions of the embodiments of the present invention.

[0045] In related technologies, after connecting the relay via FPC, the list of expansion cards is obtained, and the connection between the smart device and the expansion card is switched according to the device to obtain the status information of the expansion card, thereby determining the compatibility of the expansion card, which simplifies the testing process and improves efficiency.

[0046] However, the above-mentioned patented technology has the following risks: After the smart device obtains the memory card status information, it generates a test report based on the comparison between the predicted result and the current test result. It cannot automatically assess compatibility. For new main controllers, testing must be carried out again. Expansion cards are tested on the corresponding smart devices, but different SD cards and eMMC need to be tested on different smart devices, which requires redesigning the test plan and also requires a large number of devices to provide the test environment.

[0047] Another related method is to send test signals to independent circuits through a test board. Therefore, it can only test the integrity of the supported protocol and cannot assess the compatibility of the protocol.

[0048] Furthermore, the compatibility of SD cards and eMMC is affected by the signal voltage, sampling point, frequency, and transmission mode supported by the master device. Although the protocol specifies the communication voltage, frequency, and sampling point, different master devices may have voltage offsets and frequency variations, sometimes leading to incompatibility between master and slave devices.

[0049] It should be noted that changes in any of these three parameters can lead to a decrease in the tolerance of the other two. This is particularly evident as the frequency increases, the device's tolerance for sampling points decreases significantly. In other words, the three parameters are correlated. Therefore, without considering other parameters, a compatibility conclusion cannot be drawn based on a single parameter within a given range. A new evaluation method is needed to make this judgment.

[0050] As an optional implementation, a test method for compatibility screening of parallel signal SD cards and eMMC is provided to quantitatively evaluate the compatibility of master and slave devices. By acquiring the voltage, frequency, and sampling point information of the master device, after the host sends a test command, the bridging chip sets the corresponding state according to the received test command to perform the test. After the test, the range of voltage, frequency, and sampling points supported by the device under test is obtained, thereby evaluating the compatibility of the device under test. This test method can broadly evaluate the compatibility of the device under test and reduce repeated testing.

[0051] Optional, Figure 3 This is a schematic diagram of the structure corresponding to the test method for compatibility screening of parallel signal SD cards and eMMC according to an optional embodiment of the present invention, including the following:

[0052] The host 32, the bridge chip 34, and the slave device under test 36, wherein the slave device under test 36 includes: a switch chip 40, an SD card 42, and an eMMC 44;

[0053] It should be noted that the eMMC is connected to the switch chip via an interface socket, and the SD card and eMMC on the switch chip can be flexibly replaced according to actual testing needs. The host can be a computer host or other devices with data storage requirements. This application does not impose too many restrictions on this.

[0054] As an optional implementation method, the specific implementation of the above method is as follows:

[0055] Optional, Figure 4 A flowchart for obtaining the compatibility range of the device under test according to an optional embodiment of the present invention; including the following steps:

[0056] Step 1: The host connects to the bridge chip via a USB interface and sends the mode, voltage, and frequency to be tested via the write buffer command;

[0057] Step 2: The bridging chip (i.e., the bridge chip) sets the relevant status according to the received data and begins testing (the test includes power-on, read, write, etc.);

[0058] Step 3: By adjusting different sampling points, determine the range of sampling points supported by the device under this mode, voltage, and frequency.

[0059] Step 4: If the test is completed from the device, the information of the sampling points (including high and low points) will be uploaded. Then the host will send the next set of test samples again through the write buffer command and repeat the above steps until the test is completed.

[0060] It should be noted that during the test, the host will continuously send read buffer commands, and by completing the above test, a three-dimensional scatter plot of the maximum voltage, frequency and sampling points supported by the slave device in this mode can be obtained. The range enclosed by connecting adjacent data in the scatter plot can be considered as the range of voltage, frequency and sampling points supported by the slave device in the corresponding mode. This allows us to evaluate the compatibility of different slave devices in the same mode.

[0061] Optional, Figure 5 A flowchart illustrating how a protocol analyzer acquires master device information according to an optional embodiment of the present invention; including the following steps:

[0062] A protocol analyzer or oscilloscope obtains master device information from the bridge chip via a data interface. This information determines the voltage, frequency, sampling point, and mode used by the master device during communication. The analyzer then identifies the corresponding coordinates in the data coordinate system and maps this point to the slave device support range diagram. If the point is clearly within the diagram, it indicates compatibility; if it's on the edge or very close to the edge, compatibility is questionable; and if it's clearly outside the diagram, it indicates incompatibility.

[0063] Optionally, the specific comparison method is as follows: Normalize the coordinates of the device corresponding to the supported range and calculate the coordinates (r, θ, φ) of each point in the three-dimensional spherical coordinate system. At the same time, calculate the coordinates of the main device in the three-dimensional spherical coordinate system based on the normalization parameters. Select points with similar angular coordinates for comparison. If the radii are all much smaller than the radius of the selected points, it indicates compatibility; if there are very close points, it indicates that compatibility is questionable; if they are all larger, it indicates that incompatibility is not possible.

[0064] Optionally, the coordinate normalization method is as follows: Normalize the values ​​of each dimension of the device coordinate points obtained from the test, and record the normalization parameters (|x|). max ,|y| max ,|z| max The normalization formula is as follows: x'=x / |X| max Map the normalized coordinate points to a three-dimensional spherical coordinate system. The formula is as follows:

[0065]

[0066]

[0067]

[0068] The coordinates of the main device in the three-dimensional spherical coordinate system are calculated based on the normalization parameters. Points with similar angular coordinates are selected for comparison. This process includes: normalizing the coordinates of the main device using the normalization parameters and performing coordinate system transformation to obtain the coordinate system parameters of the main device in the graph; selecting points with similar angular coordinates (with relevant thresholds set) for comparison to draw conclusions.

[0069] That is, by using the above method, the exhaustive method is used to obtain the voltage, frequency, and sampling point range that the slave device can operate at, and the normalized spherical coordinate system is used to evaluate whether the master and slave devices are compatible.

[0070] The above embodiments provide a testing method for compatibility screening of parallel signal SD cards and eMMC. By evaluating the operation of slave devices at different voltages, frequencies, and sampling points, the method assesses the allowable range of voltages, frequencies, and sampling points supported by the slave devices. Then, by measuring the voltage, frequency, and sampling points of the master device during operation, the compatibility between the slave and master devices is determined. Using quantitative methods to evaluate compatibility allows for a broad assessment of the compatibility between newly introduced master and slave devices. This process can be automated. Furthermore, it can provide compatibility assessments for situations where a single storage device has a large number of devices requiring adaptation. Compared to existing technologies, it offers higher accuracy and utilization, broadening its application scenarios.

[0071] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0073] According to another aspect of the present invention, a storage component testing system for implementing the above-described storage component testing method is also provided. For example... Figure 6 As shown, the system includes:

[0074] Host 62 is used to send the first instruction to the bridge chip;

[0075] The bridging chip 64 is used to perform compatibility testing between the master device and the slave device under test using test parameters carried by the first instruction. During the compatibility test between the master device and the slave device under test, the chip determines the set of values ​​corresponding to multiple preset target parameters of the master device and the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters.

[0076] Protocol analyzer 66 is used to normalize the set of values ​​corresponding to multiple preset target parameters in the master device, and map the normalization result to the allowable range of values, so as to determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test according to the set of values ​​and the allowable range of values.

[0077] The device under test 68 is used to install the first storage component corresponding to the security digital card to be tested for compatibility and the second storage component corresponding to the embedded memory.

[0078] The master device 70 is used to adapt the slave device.

[0079] The system described above, upon receiving a first instruction from the host, uses the test parameters carried by the first instruction to perform compatibility testing between the master device and the slave device under test. The slave device under test includes at least a first storage component corresponding to a secure digital card and a second storage component corresponding to an embedded memory. During the compatibility testing, the system determines the numerical set corresponding to multiple preset target parameters of the master device and the allowable range of values ​​supported by the slave device for each of these preset target parameters. Based on the numerical set and allowable range, the system determines whether the first and / or second storage components in the master device and the slave device under test are compatible. This is achieved by establishing a connection between the master device and the slave device under test, and by installing a secure digital card and an embedded memory in the slave device under test. This allows for compatibility testing of the secure digital card and the embedded memory within the same device, reducing the number of repeated tests and significantly improving the efficiency of compatibility testing. This solves the problem of low testing efficiency for compatibility testing of storage components with other devices in existing technologies.

[0080] In an exemplary embodiment, the bridging chip 64 is further configured to establish a communication connection between the host and the slave device under test; wherein the bridging chip is connected to the host through a first target interface and the bridging chip is connected to the slave device under test through a second target interface; the first instruction is used to carry test parameters, the test parameters including at least: the transmission mode during master device communication, the signal voltage during master device communication, the signal frequency during master device communication, and the sampling point during master device communication; when the bridging chip receives the first instruction sent by the host, it uses the test parameters carried by the first instruction to perform compatibility testing between the master device and the slave device under test.

[0081] Optionally, the protocol analyzer 66 is further configured to acquire the target data value set corresponding to the slave device, normalize the coordinates according to different data dimensions, record the normalization parameters corresponding to the coordinate normalization, and map the multiple first coordinate points corresponding to the coordinate normalization to a three-dimensional spherical coordinate system; use the normalization parameters to transform the data value set, determine the second coordinate point corresponding to the data value set in the three-dimensional spherical coordinate system, acquire the target first coordinate point within a preset threshold range of the second coordinate point, generate a relative positional relationship, and determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the relative positional relationship.

[0082] For example, the coordinates of the slave device's corresponding support range are normalized, and the coordinates (r, θ, φ) of each point in the three-dimensional spherical coordinate system are calculated. Simultaneously, the coordinates of the master device in the same three-dimensional spherical coordinate system are calculated based on the normalization parameters. Points with similar angular coordinates are selected for comparison. If the radii of all points are much smaller than the radius of the selected points, compatibility is indicated; if very close points exist, compatibility is questionable; if all are larger, incompatibility is not possible. Optionally, the specific method for coordinate normalization is as follows: Normalize the values ​​of each dimension of the slave device's coordinate points obtained from the test, and record the normalization parameters (|x|). max ,|y| max ,|z| max The normalization formula is as follows: x'=x / |X| max Map the normalized coordinate points to a three-dimensional spherical coordinate system. The formula is as follows:

[0083]

[0084]

[0085]

[0086] The coordinates of the main device in the three-dimensional spherical coordinate system are calculated based on the normalization parameters. Points with similar angular coordinates are selected for comparison. This process includes: normalizing the coordinates of the main device using the normalization parameters and performing coordinate system transformation to obtain the coordinate system parameters of the main device in the graph; and comparing points with similar angular coordinates (with relevant thresholds set) to draw a conclusion, i.e., the relative positional relationship.

[0087] Optionally, the bridging chip 64 is further configured to upload the set of values ​​and the allowable range of values ​​to the protocol analyzer; determine the relative positional relationship between the target mapping point corresponding to the set of values ​​fed back by the protocol analyzer and the target mapping range corresponding to the allowable range of values; and determine whether the master device and the first storage component and / or the second storage component in the slave device under test are compatible based on the relative positional relationship.

[0088] In an optional embodiment, the bridging chip 64 is further configured to: determine that the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is compatible when the relative positional relationship indicates that the target mapping point is in the target area of ​​the target mapping range, wherein the target area is the central area of ​​the target mapping range; determine that the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is suspected to be compatible when the relative positional relationship indicates that the target mapping point is outside the target area of ​​the target mapping range but within the target mapping range; and determine that the compatibility result between the master device and the first storage component and / or the second storage component in the slave device under test is incompatible when the relative positional relationship indicates that the target mapping point is outside the target mapping range.

[0089] As an optional implementation, the bridging chip 64 is further configured to parse the first instruction sent by the host to obtain the test parameters corresponding to the compatibility test; determine the actual values ​​of the test parameters at different test stages to obtain a set of values ​​corresponding to multiple preset target parameters of the host device.

[0090] Optionally, the bridging chip 64 is further configured to determine the data transmission parameters corresponding to the security digital card and the embedded memory installed in the slave device under test; obtain the transmission information supported by the slave device under test at different sampling points; and determine the allowable range of values ​​supported by the slave device under test for each of the plurality of preset target parameters based on the data transmission parameters and the transmission information.

[0091] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0092] Embodiments of the present invention also provide a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0093] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0094] S1. Upon receiving a first instruction from the host, perform a compatibility test between the master device and the slave device under test using the test parameters carried by the first instruction; wherein, the slave device under test includes at least: a first storage component corresponding to the security digital card and a second storage component corresponding to the embedded memory;

[0095] S2. During the compatibility test between the master device and the slave device under test, determine the set of values ​​corresponding to multiple preset target parameters of the master device, and determine the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters.

[0096] S3. Determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the set of values ​​and the allowable range of values.

[0097] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0098] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0099] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0100] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0101] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0102] S1. Upon receiving a first instruction from the host, perform a compatibility test between the master device and the slave device under test using the test parameters carried by the first instruction; wherein, the slave device under test includes at least: a first storage component corresponding to the security digital card and a second storage component corresponding to the embedded memory;

[0103] S2. During the compatibility test between the master device and the slave device under test, determine the set of values ​​corresponding to multiple preset target parameters of the master device, and determine the allowable range of values ​​supported by the slave device under test for each of the multiple preset target parameters.

[0104] S3. Determine whether the master device is compatible with the first storage component and / or the second storage component in the slave device under test based on the set of values ​​and the allowable range of values.

[0105] Optionally, in this embodiment, those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0106] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0107] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0108] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed client can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between units or modules, and may be electrical or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0112] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A memory component testing method, comprising: Comprise: In the case of receiving the first instruction sent by the host, using the test parameters carried by the first instruction to perform compatibility test of the host device and the slave device to be tested; wherein, the slave device to be tested comprises at least: the first storage component corresponding to the secure digital card and the second storage component corresponding to the embedded memory, and the host device is a device adapted to the slave device; In the process of performing the compatibility test of the host device and the slave device to be tested, the value set corresponding to a plurality of preset target parameters of the host device is determined, and the value range allowed by the slave device to be tested for each parameter in the plurality of preset target parameters is determined; According to the value set and the value range, it is determined whether the host device and the first storage component and / or the second storage component in the slave device to be tested are compatible; According to the value set and the value range, it is determined whether the host device and the first storage component and / or the second storage component in the slave device to be tested are compatible, comprising: Upload the value set and the value range to the protocol analyzer; determine the relative positional relationship between the target mapping point corresponding to the value set and the target mapping range corresponding to the value range feedback by the protocol analyzer; In the case that the relative positional relationship indicates that the target mapping point is in the target area of the target mapping range, it is determined that the compatibility result of the host device and the first storage component and / or the second storage component in the slave device to be tested is compatible, wherein the target area is the central range area in the target mapping range; In the case that the relative positional relationship indicates that the target mapping point is outside the target area of the target mapping range and is in the target mapping range, it is determined that the compatibility result between the host device and the first storage component and / or the second storage component in the slave device to be tested is suspected compatible; In the case that the relative positional relationship indicates that the target mapping point is outside the target mapping range, it is determined that the compatibility result of the host device and the first storage component and / or the second storage component in the slave device to be tested is incompatible.

2. The method of claim 1, wherein, Using the test parameters carried by the first instruction to perform the compatibility test of the host device and the slave device to be tested, comprising: The communication connection between the host and the slave device to be tested is established through the bridge chip; wherein, the bridge chip connects the host through the first target interface, and the bridge chip connects the slave device to be tested through the second target interface; the first instruction is used to carry the test parameters, and the test parameters at least include: transmission mode during host communication, signal voltage during host communication, signal frequency during host communication, and sampling point during host communication; In the case that the bridge chip receives the first instruction sent by the host, using the test parameters carried by the first instruction to perform the compatibility test of the host device and the slave device to be tested.

3. The method of claim 1, wherein, In the process of performing the compatibility test of the host device and the slave device to be tested, the value set corresponding to a plurality of preset target parameters of the host device is determined, comprising: perform instruction analysis on the first instruction sent by the host to obtain a test parameter corresponding to the compatibility test; determine actual values of the test parameter in different test stages to obtain a value set corresponding to a plurality of preset target parameters of the host device.

4. The method of claim 1, wherein, determine a value range supported by the to-be-tested slave device for each parameter in the plurality of preset target parameters, including: determine data transmission parameters corresponding to the secure digital card and the embedded memory installed in the to-be-tested slave device; obtain transmission information supported by the to-be-tested slave device at different sampling points; determine the value range supported by the to-be-tested slave device for each parameter in the plurality of preset target parameters according to the data transmission parameters and the transmission information.

5. A memory component testing system, comprising: including: a host, configured to send a first instruction to a bridge chip; the bridge chip, configured to perform a compatibility test of a host device and a to-be-tested slave device using a test parameter carried in the first instruction, determine a value set corresponding to a plurality of preset target parameters of the host device in the process of performing the compatibility test of the host device and the to-be-tested slave device, and determine a value range supported by the to-be-tested slave device for each parameter in the plurality of preset target parameters; a protocol analyzer, configured to perform normalization processing on the value set corresponding to the plurality of preset target parameters in the host device, map a normalization processing result to the value range, and determine whether the host device and a first storage component and / or a second storage component in the to-be-tested slave device are compatible according to the value set and the value range; a to-be-tested slave device, configured to install a first storage component corresponding to a secure digital card to be executed for a compatibility test and a second storage component corresponding to an embedded memory; a host device, configured to adapt to the slave device; the bridge chip, further configured to upload the value set and the value range to the protocol analyzer; determine a relative positional relationship between a target mapping point corresponding to the value set fed back by the protocol analyzer and a target mapping range corresponding to the value range; in a case where the relative positional relationship indicates that the target mapping point is in a target area of the target mapping range, determine that a compatibility result of the host device and the first storage component and / or the second storage component in the to-be-tested slave device is compatible, wherein the target area is a central range area in the target mapping range; in a case where the relative positional relationship indicates that the target mapping point is outside the target area of the target mapping range and is within the target mapping range, determine that the compatibility result between the host device and the first storage component and / or the second storage component in the to-be-tested slave device is suspected compatible; in a case where the relative positional relationship indicates that the target mapping point is outside the target mapping range, determine that the compatibility result of the host device and the first storage component and / or the second storage component in the to-be-tested slave device is incompatible.

6. The system of claim 5, wherein, The protocol analyzer is further configured to perform coordinate normalization on a target data value set corresponding to the slave device according to different data dimensions, record a normalization parameter corresponding to the coordinate normalization, and map a plurality of first coordinate points corresponding to the coordinate normalization to a three-dimensional spherical coordinate system; convert the data value set using the normalization parameter, determine a second coordinate point of the data value set in the three-dimensional spherical coordinate system, obtain a target first coordinate point within a preset threshold range of the second coordinate point, generate a relative position relationship, and determine whether the master device is compatible with the first storage component and / or the second storage component in the to-be-tested slave device according to the relative position relationship.

7. A computer readable storage medium, characterized in that, The computer-readable storage medium comprises a stored program, wherein the program performs the method described in any one of claims 1 to 4 when executed.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method described in any one of claims 1 to 4 by using the computer program.

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