Memristor array operation circuit

Abstract

The present disclosure provides a memristor array operation circuit, comprising: a basic storage module comprising a plurality of basic storage units, each basic storage unit comprising a first memristor and a first transistor connected to each other; a preprocessing module comprising a plurality of common-gate amplifiers connected to the first transistor, and an output current of the plurality of common-gate amplifiers being outputted in a collective manner; and a biasing module for providing a bias voltage for the preprocessing module; wherein the first transistor is configured to receive control information, the preprocessing module is configured to read an output current of the basic storage unit to obtain resistance information of the first memristor; and the control information and the resistance information are subjected to a multiply-accumulate operation in the preprocessing module. The present disclosure expands the resistance difference between the high resistance state and the low resistance state of the memristor, improves the parallelism of the memristor array read operation, and improves the operation energy efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and in particular to a memristor array operational circuit. Background Technology

[0002] With the rapid development of artificial intelligence technology and the dramatic increase in data scale, the von Neumann computing architecture based on traditional Complementary Metal Oxide Semiconductor (CMOS) is severely constrained by the "memory wall," making it unable to efficiently support massive data transmission and matrix-vector product calculations. Memristors, whose conductance can be adjusted by external excitation, are considered the fourth basic device besides resistors, capacitors, and inductors. They possess advantages such as non-volatility, low power consumption, good miniaturization, and compatibility with CMOS processes. They can efficiently support parallel and analog computing, making them one of the preferred devices for realizing "in-memory computing" architectures based on this new device, and thus have high research value and application prospects.

[0003] The traditional method for performing multiply-accumulate calculations based on memristors is to interconnect the memristors in a cross array. The memristors on the cross nodes are programmed to be in a high-resistance or low-resistance state according to the design requirements. By applying a read voltage on the row line, according to Kirchhoff's current law and Ohm's law, the read voltage and the current generated by the memristor are accumulated on the column line, thereby realizing the multiply-accumulate operation.

[0004] Due to limitations in current memristor manufacturing processes and the inherent randomness of the devices, memristor resistance values ​​exhibit significant deviations, with little difference between high and low resistance states—a small window size, sometimes less than an order of magnitude. The method of generating and summing currents by directly applying a read voltage to the memristor for multiplication and accumulation cannot guarantee computational accuracy, suffers from coarse granularity, and limited parallelism, typically not exceeding 20. Furthermore, voltage-mode operation tends to lead to high energy consumption, and uncontrolled currents can easily alter the memristor's resistance value. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the existing technical problems, this disclosure provides a memristor array operational circuit, which at least partially solves the above-mentioned technical problems.

[0007] (II) Technical Solution

[0008] This disclosure provides a memristor array operational circuit, comprising: a basic storage module including multiple basic storage cells, each basic storage cell including a first memristor and a first transistor interconnected; a preprocessing module including multiple common-gate amplifiers connected to the first transistor, and the output currents of the multiple common-gate amplifiers being aggregated and output; and a bias module for providing a bias voltage to the preprocessing module; wherein the first transistor is used to receive control information, the preprocessing module is used to read the output current of the basic storage cells to obtain the resistance information of the first memristor; and the control information and the resistance information are multiplied and accumulated in the preprocessing module.

[0009] Optionally, the basic storage cell includes 1T1R, 2T1R and 2T2R structures; wherein R is a first memristor and T is a first transistor; in the 2T1R structure, one first transistor is used for read operation and the other first transistor is used for write operation.

[0010] Optionally, the common-gate amplifier is used to amplify the resistance difference between the high-resistance state and the low-resistance state of the first memristor; wherein, when the first memristor is in the low-resistance state and the first transistor is turned on, the output current of the common-gate amplifier is not suppressed; when the first memristor is in the high-resistance state, the output current of the common-gate amplifier is suppressed.

[0011] Optionally, the common-gate amplifier includes a single-transistor common-gate amplifier and a dual-transistor common-source common-gate amplifier.

[0012] Optionally, the bias module includes: a plurality of second transistors, each of which is connected to a first transistor and a common-gate amplifier; a third transistor, connected to the plurality of second transistors, for providing a bias voltage to the plurality of second transistors; and a fourth transistor, connected to the plurality of common-gate amplifiers, for providing a bias voltage to the plurality of common-gate amplifiers.

[0013] Optionally, the bias module further includes: a plurality of replicated memory cells; wherein each replicated memory cell includes a second memristor and a fifth transistor interconnected, the second memristor being in a low-resistance state; the fifth transistor is connected to a fourth transistor, and some of the fourth transistors are connected to a third transistor; or different fifth transistors are connected to the third transistor and the fourth transistor respectively.

[0014] Optionally, the bias module may further include a reference current source for providing a reference current to the bias module.

[0015] Optionally, the number of basic storage units ranges from 2 to 128.

[0016] Optionally, the memristor array operation circuit further includes: multiple bit rows and multiple word columns; wherein, the basic storage cell is located at the intersection of the bit row and the word column; the first memristor is connected to the bit row, the first transistor is connected to the word column, and the first transistor receives control information through the word column.

[0017] (III) Beneficial Effects

[0018] Compared with the prior art, the memristor array operational circuit provided in this disclosure has at least the following characteristics:

[0019] Beneficial effects:

[0020] (1) This disclosure realizes the multiplication and accumulation operation of control information and memristor resistance information through multiple basic storage units and corresponding common-gate amplifiers. The common-gate amplifier can expand the resistance difference between the high-resistance state and the low-resistance state of the memristor, improve the parallelism of memristor array reading and computing, and improve computing efficiency.

[0021] (2) This disclosure strengthens the relationship between the output current of the preprocessing module and the reference current of the bias module by using a bias module designed in mirror image with the basic storage cell and the common gate amplifier, thereby weakening the characteristic fluctuations of the basic storage cell device itself and improving the accuracy of the operation.

[0022] (3) The present invention adopts a current-mode reading method, which ensures the configuration stability of the memristor and reduces the operational power consumption of the memristor array. Attached Figure Description

[0023] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A circuit diagram of a memristor array operational circuit according to an embodiment of the present disclosure is shown schematically.

[0025] Figure 2 A circuit diagram of a memristor array operational circuit according to another embodiment of the present disclosure is shown schematically.

[0026] Figures 3A-3C A circuit diagram of a basic memory cell according to an embodiment of the present disclosure is shown schematically;

[0027] Figure 4 A schematic diagram of a memristor array operational circuit according to an embodiment of the present disclosure is shown.

[0028] Figure 5 The transient simulation results of a basic memory cell according to an embodiment of the present disclosure are illustrated schematically.

[0029] Figures 6A-6FThe distribution of the convergent current is illustrated schematically in several typical cases according to embodiments of the present disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0031] It should be noted that similar or identical parts are referred to by the same reference numerals in the accompanying drawings or description. The technical features of the various embodiments exemplified in the specification can be freely combined to form new solutions without conflict. Furthermore, each claim can stand alone as an embodiment, or the technical features in the various claims can be combined to form new embodiments. In the drawings, the shape or thickness of the embodiments may be enlarged and indicated in a simplified or convenient manner. Moreover, elements or implementations not shown or described in the drawings are those known to those skilled in the art. Additionally, although this document provides examples of parameters containing specific values, it should be understood that the parameters need not be exactly equal to the corresponding values, but can approximate the corresponding values ​​within acceptable error tolerances or design constraints.

[0032] Unless there are technical obstacles or contradictions, the various embodiments described above in this disclosure can be freely combined to form other embodiments, all of which are within the protection scope of this disclosure.

[0033] Although this disclosure has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to illustrate preferred embodiments of this disclosure and should not be construed as limiting the disclosure. The dimensions in the drawings are merely illustrative and should not be construed as limiting the disclosure.

[0034] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

[0035] Figure 1 A circuit diagram of a memristor array operational circuit according to an embodiment of the present disclosure is shown schematically. Figure 2 A circuit diagram of a memristor array operational circuit according to another embodiment of the present disclosure is shown schematically.

[0036] According to embodiments of this disclosure, such as Figure 1 and Figure 2As shown, the memristor array operational circuit includes, for example, a basic storage module A, comprising multiple basic storage cells 101, each basic storage cell 101 including a first memristor 1011 and a first transistor 1012 interconnected. A preprocessing module B includes multiple common-gate amplifiers 1021, the common-gate amplifiers 1021 being connected to the first transistors 1012, and a summed output (I) of the output currents of the multiple common-gate amplifiers 1021. out The bias module C provides a bias voltage to the preprocessing module B. The first transistor 1012 receives control information, and the preprocessing module B reads the output current of the basic storage unit 101 to obtain the resistance value of the first memristor 1011. The control information and the resistance value are multiplied and accumulated in the preprocessing module B.

[0037] For ease of explanation, LRS indicates that the memristor is in a low-resistance state, and HRS indicates that the memristor is in a high-resistance state.

[0038] For example, the number of basic storage units 101 is n, where n is a positive integer. The first memristor 1011 corresponds to w1, w2, ..., w n The first transistor 1012 corresponds to MT1, MT2, ..., MT n The input control signals of the first transistor 1012 correspond to x1, x2, ..., x1, x2, ..., x3 respectively. n The common-gate amplifiers 1021 correspond to MP1, MP2, ..., MP2 respectively. n Each basic storage cell 101 corresponds to a common-gate amplifier 1021, forming a branch. The common-gate amplifier 1021 can read the resistance value information of the low-resistance state LRS or high-resistance state HRS stored in the basic storage cell 101, and output currents I1, I2, ..., I... n The information read by each branch is expressed in the form of n branches, which output currents I1, I2, ..., I... n Based on Kirchhoff's current law, I1, I2, ..., I n I is obtained by accumulating in the form of single-point aggregation. out This enables the accumulation of information read from multiple basic storage units 101.

[0039] For example, the input to the first memristor 1011 is a fixed small current, which will not affect the resistance value of the memristor. The resistance value information of the low-resistance state or high-resistance state stored in the first memristor 1011 can be regarded as 1 bit of weighted information w. n The control signal connected to the gate of the first transistor 1012 can be regarded as a 1-bit input control information x. n 1 bit weight information w n and 1 bit control information x nOne-bit multiplication can be directly implemented using the basic storage unit 101. n *x n Combined with preprocessing module B, it can be integrated into a binary array multiplication and accumulation operation ∑w n *x n This enables the realization of the basic operational unit for morphological operations in artificial neural networks.

[0040] According to embodiments of this disclosure, the basic memory cell 101 includes, for example, 1T1R, 2T1R, and 2T2R structures. Here, R is a first memristor 1011, and T is a first transistor 1012. In the 2T1R structure, one first transistor 1012 is used for read operations, and the other first transistor 1012 is used for write operations.

[0041] Figures 3A-3C A circuit diagram of a basic storage unit according to an embodiment of the present disclosure is shown schematically.

[0042] For example, such as Figure 3A As shown, the basic memory cell 101 consists of a first memristor 1011 and a first transistor 1012 forming a "1T1R" structure. Alternatively, as... Figure 3B As shown, the basic storage cell 101 consists of two first memristors 1011 and two first transistors 1012 forming a "2T2R" structure. Alternatively, as... Figure 3C As shown, the basic storage cell 101 consists of a first memristor 1011 and two first transistors 1012 forming a "2T1R" structure.

[0043] Since the voltage and current magnitudes differ during read and write operations, the basic memory cell 101 can employ a 2T1R structure to improve the matching performance of the first transistor 1012. One of the first transistors 1012 is used for reading, and the other is used for writing. During read operations, the current in each branch is relatively small, allowing the use of smaller transistors. Conversely, during write operations, the current in each branch is relatively large, necessitating the use of larger transistors. Using different transistors for read and write operations within the same basic memory cell 101 maximizes transistor utilization and reduces hardware costs.

[0044] According to embodiments of this disclosure, the common-gate amplifier 1021 can be used to amplify the resistance difference between the high-resistance state and the low-resistance state of the first memristor 1011. Specifically, when the first memristor 1011 is in the low-resistance state and the first transistor 1012 is turned on, the output current of the common-gate amplifier 1021 is not suppressed. When the first memristor 1011 is in the high-resistance state, the output current of the common-gate amplifier 1021 is suppressed.

[0045] For example, the output current I of the common-gate amplifier 1021n The fundamental current I is when the first memristor 1011 is in a low-resistance state (or "1"). n =I u When the first memristor 1011 is in a high-resistance state (or "0"), the current is suppressed and approaches 0, i.e., I0. n =0. Where, I u This represents the current in one branch of the bias circuit.

[0046] For example, the number of basic memory cells (equivalent to parallelism), n, ranges from 2 to 128. Under current memristor manufacturing processes, memristors exhibit characteristics such as a small resistance difference between high and low resistance states (even less than one order of magnitude), and a large resistance deviation distribution. In practical operation, this is not conducive to simple convergence of array readout currents, nor to achieving high-parallelism array computation (parallelism n is limited to n < 20). However, by amplifying the resistance difference between the high and low resistance states of the first memristor 1011 in the basic memory cell 101 using a common-gate amplifier 1021, high-parallelism computation of the memristor array can be achieved, with parallelism n reaching 128, thereby improving the energy efficiency of artificial neural network-type computation.

[0047] For example, common-gate amplifiers include single-transistor common-gate amplifiers and dual-transistor common-source common-gate amplifiers. Among them, dual-transistor common-source common-gate amplifiers have superior characteristics, enabling higher transconductance with a more economical circuit area.

[0048] According to embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the bias module C includes, for example, a plurality of second transistors 1031, each connected to a first transistor 1012 and a common-gate amplifier 1021. A third transistor 1041, connected to the plurality of second transistors 1031, is used to provide a bias voltage to the plurality of second transistors 1031. And a fourth transistor 1042, connected to the plurality of common-gate amplifiers 1021, is used to provide a bias voltage to the plurality of common-gate amplifiers 1021.

[0049] For example, the second transistor 1031 corresponds to MN1, MN2, ..., MN, respectively. n The third transistor 1041 corresponds to MN. ref0 The fourth transistor 1042 corresponds to MP. ref0 and MP ref1 MN ref0 with MN1, MN2,...,MN n Connected to it and providing a bias voltage. MP ref0 and MP ref1 With MP1, MP2, ..., MP nConnect them and provide them with a bias voltage.

[0050] According to embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the bias module C further includes, for example, a plurality of replicated memory cells 105; wherein each replicated memory cell 105 includes a second memristor 1051 and a fifth transistor 1052 interconnected, the second memristor 1051 being in a low-resistance state. The fifth transistor 1052 is connected to a fourth transistor 1042, and a portion of the fourth transistor 1042 is connected to a third transistor 1041. Alternatively, different fifth transistors 1052 are connected to the third transistor 1041 and the fourth transistor 1042 respectively.

[0051] For example, all second memristors 1051 are in a low-resistance state (represented by "1"), making each replicated memory cell 105 in a conducting state. One of the replicated memory cells 105 is connected to MP. ref0 Connected to another copy storage unit 105, and MP ref1 Connected, and MP ref1 With MN ref0 Connected.

[0052] It is understandable that the multiple second transistors 1031 are equivalent to mirror circuits of preprocessing module B, and the multiple replicated memory cells 105 are equivalent to mirror circuits of basic memory module A. This mirror circuit design strengthens the proportional relationship between the output current of the common-gate amplifier 1021 and the currents of each branch in bias module C, while weakening the impact of fluctuations in the characteristics of the devices themselves in basic memory module A on operational accuracy. Furthermore, the design of multiple branches in bias module C reduces the current deviation of a single branch in preprocessing module B, ensuring the output currents I1, I2, ..., I of the first memristor 1011 in the low-resistance state. n The accuracy is high, and the output current approaches 0 in the high-resistivity state.

[0053] It should be noted that MP can be removed. ref1 This allows another copy storage unit 105 to be connected to MN. ref0 Direct connection. The number of second transistors 1031 corresponds to the number of common-gate amplifiers 1021, while the number of replica memory cells 105 may be the same as or different from the number of basic memory cells 101.

[0054] According to embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the bias module may further include, for example, a reference current source 106, for providing a reference current I to the bias module C. ref .

[0055] For example, the reference current Iref It can be provided externally or through the integration of a constant current source. Reference current I ref This is the sum of the currents in each branch of the bias module C.

[0056] According to embodiments of this disclosure, the memristor array operation circuit further includes, for example, multiple bitlines and multiple wordlines. A basic storage unit 101 is located at the intersection of the bitlines and wordlines. A first memristor 1011 is connected to the bitlines, and a first transistor 1012 is connected to the wordlines. The first transistor 1012 receives control information through the wordlines.

[0057] For example, the top electrode of the first memristor 1011 is connected to the bitlines of the memristor array, the bottom electrode of the first memristor 1011 is connected to the drain of the first transistor 1012, the gate of the first transistor 1012 is connected to the wordlines of the memristor array, and the source of the first transistor 1012 is connected to the sourcelines of the memristor array. The basic memory cells 101 are all located at the intersections of the bitlines and wordlines of the memristor array; therefore, the memristor array can also be called a memristor crossover array. The memristor array operational circuit disclosed herein can be effectively combined with conventional memristor arrays, reducing the design complexity of peripheral circuits.

[0058] Figure 4 A schematic diagram of a memristor array operational circuit according to an embodiment of the present disclosure is shown.

[0059] To verify the calculation accuracy of the memristor array read circuit provided in this embodiment, the following was performed: Figure 4 The circuit was simulated.

[0060] According to embodiments of this disclosure, such as Figure 4 As shown, the basic memory cell 101 is, for example, a 2T1R structure. The common-gate amplifier 1021 is, for example, a dual-transistor common-source common-gate amplifier. In the basic memory module A, for example, 128 basic memory cells 101 are provided. In this embodiment, I ref For example, 8μA. For example, the resistance state of the first memristor 1011 is modeled as follows: the high resistance state distribution of the first memristor 1011 is (mean 69.8kΩ, variance 11.85kΩ), and the low resistance state distribution is (mean 8.38kΩ, variance 100.74Ω).

[0061] Figure 5 The transient simulation results of a basic memory cell according to an embodiment of the present disclosure are illustrated schematically.

[0062] For example, the basic storage cell 101 is first simulated to verify the difference in output of the first memristor 1011 under high and low resistance states. Figure 5 As shown, where DXB <3> For the input signal applied to the basic storage unit 101, MP0A <3> The output current I of the basic storage unit 101 out When the first memristor 1011 is written to a low-impedance state, and the input control signal is low (i.e., the first transistor 1012 in the basic memory cell 101 is turned on), the stable output current of this branch is I. out =I u (In this embodiment, the mirror design method selects I for example) u =4μA); When the input is high, i.e., the transistor in the basic memory cell is off, the stable output current of this branch is less than 30nA. When the first memristor 1011 is programmed to a high impedance state, when the input control signal is low, i.e., the first transistor 1012 in the basic memory cell 101 is on, the stable output current of this branch is still less than 30nA.

[0063] To further verify that the memristor array read circuit has a high tolerance for memristor matching accuracy and to ensure the circuit's calculation accuracy, Figure 1 Monte Carlo simulation was performed on the circuit. The number of sampling points was set to 32, for example, i.e., MC = 32.

[0064] Figures 6A-6F The distribution of the convergent current is illustrated schematically in several typical cases according to embodiments of the present disclosure.

[0065] According to embodiments of this disclosure, such as Figure 6A As shown, for example, in a memristor array operational circuit composed of 128 basic memory cells 101 under a CMOS 180nm process, when all 128 first memristors 1011 in the memristor array are written in a high-resistivity state, the ideal converged current is 0A, and the actual converged current ITOT∈(0, 1.75)μA. Figure 6B As shown, in the case where one first memristor 1011 in the memristor array is in a low-resistance state and the remaining 127 first memristors 1011 are in a high-resistance state, the ideal converged current is 4μA, and the actual converged current ITOT∈(4.5, 5.5)μA. Figure 6C As shown, with 16 first memristors 1011 in the memristor array in a low-resistance state and the remaining 112 first memristors 1011 in a high-resistance state, the ideal converged current is 64 μA, and the actual converged current ITOT∈(64, 65.5) μA. Figure 6DAs shown, with 64 first memristors 1011 in the memristor array in a low-resistance state and the remaining 64 first memristors 1011 in a high-resistance state, the ideal converged current is 256 μA, and the actual converged current ITOT∈(255, 258) μA. Figure 6E As shown, when 127 first memristors 1011 in the memristor array are in a low-resistance state and the remaining first memristor 1011 is in a high-resistance state, the ideal converged current is 508 μA, and the actual converged current ITOT∈(506, 510) μA. Figure 6F As shown, when all 128 first memristors 1011 in the memristor array are in a low-resistance state, the ideal converged current is 512μA, and the actual converged current ITOT∈(510,514)μA.

[0066] Simulation results show that, in the current-mode-based memristor array provided in this embodiment, the first memristor 1011 in the basic storage unit 101 exhibits a two-order-of-magnitude difference in calculated current between its high-resistance and low-resistance states. In contrast, the memristor circuit model used in related technologies shows a difference of less than one order of magnitude between high and low resistance states, and when using a traditional voltage-applied method for calculation, the difference in calculated current between the high-resistance and low-resistance states is also less than one order of magnitude. The array read / write circuit provided in this embodiment solves the problem of small differences between the high and low resistance states of the memristor from a circuit design perspective.

[0067] Furthermore, the current-mode-based memristor array provided in this embodiment, when the number of basic storage cells 101 integrated in the array is as high as 128, still shows no overlap in the converged current results, demonstrating good distinguishability. This proves that the designed array read / write circuit has high parallelism and ensures computational accuracy.

[0068] Furthermore, since the output current of each branch is only 0-30nA or 0-4μA, the operating current of the memristor in this embodiment is significantly reduced compared to the traditional voltage application method, which improves the resistance stability of the memristor device. Therefore, the memristor array reading circuit provided in this disclosure has low power consumption characteristics.

[0069] In summary, this disclosure presents a memristor array operational circuit. Through multiple basic storage cells and corresponding common-gate amplifiers, it achieves multiplication and accumulation operations between control information and memristor resistance information. Furthermore, the common-gate amplifiers can extend the resistance difference between the high-resistance and low-resistance states of the memristor, improving the parallelism of memristor array read operations and enhancing operational efficiency.

[0070] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to a specific order or hierarchy.

[0071] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in understanding this disclosure. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect their actual size, scale, or actual positional relationships.

[0072] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, this disclosure is in a state of having fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of this disclosure.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. The term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as "including" is used as a conjunction in the claims. The use of any term "or" in the specification or claims is intended to mean "non-exclusive or."

[0074] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A memristor array operation circuit, comprising: The application relates to a memory device, comprising: a basic storage module comprising a plurality of basic storage units, each of the basic storage units comprising a first memristor and a first transistor connected with each other; a preprocessing module comprising a plurality of common-gate amplifiers, the common-gate amplifiers being connected with the first transistors, and output currents of the common-gate amplifiers being output in total; a biasing module for providing a bias voltage for the preprocessing module; wherein the first transistors are used for receiving control information, the preprocessing module is used for reading output currents of the basic storage units to obtain resistance value information of the first memristors; the control information and the resistance value information are subjected to a multiply-accumulate operation in the preprocessing module; the common-gate amplifiers are used for amplifying a resistance value difference between a high resistance state and a low resistance state of the first memristors; in the case that the first memristors are in the low resistance state and the first transistors are turned on, the output currents of the common-gate amplifiers are not inhibited; in the case that the first memristors are in the high resistance state, the output currents of the common-gate amplifiers are inhibited.

2. The circuit of claim 1, wherein, The basic storage units comprise 1T1R, 2T1R and 2T2R structures; wherein R is the first memristor, and T is the first transistor; in the structure of the 2T1R, one of the first transistors is used for read operation, and the other of the first transistors is used for write operation.

3. The circuit of claim 1, wherein, The common-gate amplifiers comprise single-tube common-gate amplifiers and double-tube common-source common-gate amplifiers.

4. The circuit of claim 1, wherein, The biasing module comprises: a plurality of second transistors, the second transistors being connected with the first transistors respectively and connected with the common-gate amplifiers; a third transistor connected with the plurality of second transistors and used for providing a bias voltage for the plurality of second transistors; and a fourth transistor connected with the plurality of common-gate amplifiers and used for providing a bias voltage for the plurality of common-gate amplifiers.

5. The circuit of claim 4, wherein, The biasing module further comprises: a plurality of copy storage units; wherein each of the copy storage units comprises a second memristor and a fifth transistor connected with each other, the second memristor being in a low resistance state; the fifth transistors are connected with the fourth transistors, and part of the fourth transistors are connected with the third transistors; or different fifth transistors are connected with the third transistors and the fourth transistors respectively.

6. The circuit of claim 1, wherein, The biasing module further comprises: a reference current source for providing a reference current for the biasing module.

7. The circuit of claim 1, wherein, The number of the basic storage units ranges from 2 to 128.

8. The circuit of claim 1, wherein, The application further comprises: a plurality of bit rows and a plurality of word columns; wherein the basic storage units are arranged at intersection points of the bit rows and the word columns; the first memristors are connected with the bit rows, the first transistors are connected with the word columns, and the first transistors receive the control information through the word columns.

Images