A wafer-level packaging structure for multiple heterogeneous chips

Abstract

This invention relates to a wafer-level packaging structure for multiple heterogeneous chips, comprising interconnected first and second remolded wafers. The first remolded wafer includes multiple first chips, and the second remolded wafer includes multiple second chips, wherein the first and second chips are different. By molding the first and second chips into two remolded wafers and bonding the two remolded wafers, up to dozens of heterogeneous chips can be connected between the two remolded wafers. Moreover, the heterogeneous chips are directly connected through electrodes on the chips, greatly increasing the number of interconnections between computing chips and interface chips, improving bandwidth, and shortening communication links.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a wafer-level packaging structure for multiple heterogeneous chips. Background Technology

[0002] Wafer-level packaging (WLP) refers to performing most or all of the packaging and testing procedures directly on the wafer, followed by dicing to create individual components. WLP packaging offers advantages such as smaller package size and better electrical performance, and is currently widely used in packaging applications for low-pin-count consumer ICs. For example, Chinese patent CN 114823592 A discloses a system-on-a-chip (SoC) structure and its fabrication method. This SoC structure is a wafer-level packaging structure, including a wafer substrate, integrated circuit chips, a system configuration board, and a system heat dissipation module.

[0003] However, existing wafer-level packaging structures have limitations such as a limited number of wafer-level multi-chip connections, a limited number of wafer-level inter-chip interconnects, limited wafer-level inter-chip bandwidth, and the need to use adapter boards, substrates, or PCBs. Furthermore, they have long communication paths between wafer-level chips. In addition, there are also problems such as long power supply paths and poor heat dissipation. Summary of the Invention

[0004] To address at least some of the aforementioned problems in the prior art, the present invention provides a wafer-level packaging structure for multiple heterogeneous chips, comprising interconnected first and second remolded wafers, wherein the first remolded wafer includes a plurality of first chips and the second remolded wafer includes a plurality of second chips, wherein the first chips and the second chips are different.

[0005] Furthermore, the first reshaped wafer and the second reshaped wafer are connected by a hybrid bonding between the electrodes on the front side of the first chip and the electrodes on the front side of the second chip.

[0006] The first chip in the first remolded wafer and the second chip in the second remolded wafer are interconnected in a staggered manner. One of the second chips is electrically connected to a plurality of adjacent first chips. The first chip is electrically connected to adjacent first chips through metal lines inside the second chip, and the second chip is electrically connected to adjacent second chips through metal lines inside the first chip.

[0007] Furthermore, the first remolded wafer also includes a first molding layer for molding multiple first chips, wherein the electrodes on the front side of the first chips are exposed in the first molding layer;

[0008] The second remolded wafer also includes a second molding layer that encapsulates a plurality of second chips, wherein the electrodes on the front side of the second chips and the back side of the second chips are exposed by the second molding layer.

[0009] Furthermore, the first chip is a computing chip or a storage chip;

[0010] The second chip is an interface chip.

[0011] Furthermore, the second chip has a through-silicon via (TSV) that penetrates the second chip, with one end connected to the electrode of the second chip and the other end exposed on the back of the second chip.

[0012] Furthermore, it also includes:

[0013] The first interconnect layer is disposed on the back side of the second remolded wafer and is electrically connected to the through-silicon via.

[0014] A substrate, the front side of which is connected to the back side of the second remolded wafer via bumps, wherein the front side of the substrate has a second wiring layer, the back side has a third wiring layer, and the bumps connect the first wiring layer and the second wiring layer; and

[0015] A heat pipe heat dissipation module includes a first microchannel on the back side of a second reshaped wafer, a second microchannel on the front side of a substrate, and a heat pipe housed in a channel formed by the combination of the first and second microchannel grooves. The heat pipe is located in the gap between the bumps, and the diameter of the heat pipe is equal to the sum of the depth of the first microchannel groove, the depth of the second microchannel groove, the thickness of the first redistribution layer, the thickness of the second redistribution layer, and the height of the bumps.

[0016] Furthermore, it also includes a vertical power supply module, which is connected to the back of the substrate via BGA solder balls, wherein the BGA solder balls include ground solder balls and power solder balls, and the vertical power supply module includes:

[0017] A circuit board having a fourth wiring layer on its front side, the circuit board having vertical metal traces electrically connected to the fourth wiring layer, and the circuit board being electrically connected to the substrate via BGA solder balls.

[0018] The second-stage voltage regulation module is located on the back of the circuit board and is electrically connected to the longitudinal metal traces in the circuit board.

[0019] A power connector that is electrically connected to the second-stage voltage regulation module;

[0020] PCB board, which is electrically connected to the power connector; and

[0021] The first-stage voltage regulation module is electrically connected to the PCB board.

[0022] Furthermore, the vertical power supply module also includes:

[0023] A second heat dissipation module, connected to the voltage regulation module, has pre-drilled holes; and

[0024] A passive device that is electrically connected to the PCB board.

[0025] Furthermore, the power connector is electrically connected to the second-stage voltage regulation module via a circuit through a reserved hole in the second heat dissipation module;

[0026] The first side of the second-stage voltage regulation module is connected to the circuit board, and its second side is connected to the second heat dissipation module; the first side and the second side of the second voltage regulation module are opposite to each other.

[0027] The first side of the second heat dissipation module is connected to the second side of the second-stage voltage regulation module, the second side of the second heat dissipation module is connected to the power connector, and the first side and the second side of the second heat dissipation module are opposite to each other.

[0028] Furthermore, the circuit board has a built-in isolation layer, which together with two adjacent longitudinal metals form a capacitor.

[0029] The present invention has at least the following beneficial effects: The wafer-level packaging structure for multiple heterogeneous chips disclosed herein encapsulates a computing chip and an interface chip into two remolded wafers, and bonds the two remolded wafers together. This allows for the connection of up to dozens of heterogeneous chips within the two remolded wafers, with the heterogeneous chips directly connected via electrodes on the chips. This significantly increases the number of interconnections between the computing chip and the interface chip, from hundreds to hundreds of thousands, increasing bandwidth from GB / s to TB / s and shortening communication links. The wafer-level packaging structure uses a vertical power supply structure, shortening the power supply path length. Three heat dissipation modules are arranged at different locations within the wafer-level packaging structure, with the central heat pipe heat dissipation module directly contacting the chip to achieve efficient heat dissipation near the heat source, improving the heat dissipation effect. Furthermore, the heat pipe does not require inlet and outlet ports; the liquid circulates internally, and the heat pipe utilizes liquid evaporation and condensation cycles to achieve the most efficient heat transfer method, enabling rapid heat dissipation for the chip and providing excellent heat dissipation performance. Attached Figure Description

[0030] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope.

[0031] Figure 1 A schematic diagram of a wafer-level packaging structure for a multi-heterogeneous chip according to an embodiment of the present invention is shown;

[0032] Figure 2 A schematic diagram of a reshaped wafer of multiple heterogeneous chips according to an embodiment of the present invention is shown;

[0033] Figure 3 A schematic vertical cross-sectional view of a second reshaped wafer and substrate according to an embodiment of the present invention is shown;

[0034] Figure 4 A vertical cross-sectional schematic diagram of a heat pipe cooling module according to an embodiment of the present invention is shown;

[0035] Figure 5 A cross-sectional schematic diagram of a heat pipe cooling module according to an embodiment of the present invention is shown;

[0036] Figure 6 A schematic diagram of a vertical power supply module according to an embodiment of the present invention is shown;

[0037] Figure 7 A schematic diagram illustrating the working principle of a heat pipe is shown; and

[0038] Figure 8 The process of fabricating a wafer-level packaging structure for multiple heterogeneous chips according to an embodiment of the present invention is illustrated. Detailed Implementation

[0039] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0040] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0041] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0042] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0043] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0044] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0046] Figure 1 A schematic diagram of a wafer-level packaging structure for a multi-heterogeneous chip according to an embodiment of the present invention is shown. Figure 2 A schematic diagram of a reshaped wafer of multiple heterogeneous chips according to an embodiment of the present invention is shown. Figure 3 A schematic vertical cross-sectional view of a second reshaped wafer and substrate according to an embodiment of the present invention is shown. Figure 4 A vertical cross-sectional schematic diagram of a heat pipe cooling module according to an embodiment of the present invention is shown. Figure 5 A cross-sectional schematic diagram of a heat pipe cooling module according to an embodiment of the present invention is shown.

[0047] like Figure 1 and 2 As shown, a wafer-level packaging structure for multiple heterogeneous chips includes a first remolded wafer 1, a second remolded wafer 2, a substrate 3, a heat pipe heat dissipation module, a first heat dissipation module 4, and a vertical power supply module 5.

[0048] The first remolded wafer 1 and the second remolded wafer 2 are interconnected. The first remolded wafer 1 includes a plurality of first chips 11, and the second remolded wafer 2 includes a plurality of second chips 21. The first remolded wafer 1 also includes a first molding compound (not shown) encapsulating the plurality of first chips 11, wherein the electrodes on the front side of the first chips 11 are exposed in the first molding compound. The second remolded wafer 2 also includes a second molding compound (not shown) encapsulating the plurality of second chips 21, wherein the electrodes on the front side of the second chips 21 and the back side of the second chips 21 are exposed in the second molding compound. The first chips 11 and the second chips 21 are different types of chips. In one embodiment of the present invention, the first chip is a computing chip, and the second chip is an interface chip. In other embodiments of the present invention, the first chip may also be a memory chip (HBM or DDR). By adopting a heterogeneous integration approach, multiple chips with different functions are vertically integrated to achieve functional integration.

[0049] The first remolded wafer 1 and the second remolded wafer 2 are connected via hybrid bonding, wherein the electrodes on the front side of the first chip 11 are bonded to the electrodes on the front side of the second chip 21. Hybrid bonding eliminates the need for microbumps, reducing the interconnect pitch to below 10μm and decreasing the interconnect width and spacing, thereby increasing interconnect density. Increased interconnect density leads to improved interconnect bandwidth. Vertical electrode bonding between chips reduces the interconnect length between heterogeneous chips, further enhancing interconnect bandwidth. Direct connection between heterogeneous chips via on-chip electrodes significantly increases the number of interconnects between computing chips and interface chips, reaching hundreds of thousands of interconnects, resulting in bandwidth of TB / s. Traditionally, connections between heterogeneous chips are achieved through PCB traces; in the above wafer-level packaging structure, hybrid bonding of heterogeneous chip electrodes replaces this traditional PCB trace connection method, greatly reducing the number of external I / O connections.

[0050] The first chip 11 in the first remolded wafer 1 and the second chip 21 in the second remolded wafer 2 are interconnected in a staggered manner, with one of the second chips 21 electrically connected to a plurality of adjacent first chips 11 via hybrid electrode bonding. In this embodiment, one second chip 21 is bonded to four adjacent first chips 11 via hybrid electrode bonding. The first chip 11 can be electrically connected to any three other first chips 11 via metal wires inside the second chip 21, and the second chip 21 can be electrically connected to adjacent second chips 21 via metal wires inside the first chip 11. By using the method of heterogeneous chip staggered interconnection, one second chip 21 can control four nearby first chips 11. By using the second chip 21, the length of the horizontal connection between the first chips 11 can be reduced.

[0051] The second chip 21 has a through-silicon via 22 that penetrates the second chip 21, with one end connected to the electrode of the second chip and the other end exposed on the back side of the second chip. The back side of the second chip has a first microchannel groove.

[0052] The first heat dissipation module 4 is disposed on the back side of the first remolded wafer 1 and is used for chip heat dissipation. The first heat dissipation module 4 can be a heat dissipation structure in the form of a metal heat sink or a microfluidic channel.

[0053] A first redistribution layer (not shown) is disposed on the back side of the second remolded wafer and electrically connected to a through-silicon via.

[0054] The substrate has a second wiring layer (not shown) on the front side and a third wiring layer (not shown) on the back side, wherein the second wiring layer is electrically connected to the bumps and the third wiring layer is electrically connected to the BGA solder balls.

[0055] Bump 6 electrically connects the first super-wiring layer to the second super-wiring layer on the front side of the substrate. The front side of the substrate is connected to the back side of the second remolded wafer 2 via bump 6.

[0056] like Figures 3 to 5 As shown, the heat pipe cooling module 7 includes a first microchannel groove 23 on the back side of the second remolded wafer 2, a second microchannel groove 31 on the front side of the substrate 3, and a heat pipe 71 housed in a channel formed by the combination of the first and second microchannel grooves. The diameter of the heat pipe 71 is equal to the sum of the depth of the first microchannel groove 23, the depth of the second microchannel groove 31, the thickness of the first redistribution layer, the thickness of the second redistribution layer, and the height of the bumps 6, so that the heat pipe 71 can be just accommodated in the channel. The heat pipe 71 is arranged longitudinally on the front side of the substrate 3 and is located in the gap between the bumps 6. Preferably, the heat pipe is located at 1 / 2 of the bump gap, without affecting the arrangement of the bumps. The heat pipe directly contacts the second chip, improving the heat dissipation effect.

[0057] The substrate 3 also includes passive components such as capacitors, inductors, and resistors. The capacitors are MIM capacitors, which include a lower electrode, a dielectric layer, and an upper electrode. The capacitors, inductors, and resistors are electrically connected to each other and to the second and third wiring layers.

[0058] The substrate 3 is connected to the vertical power supply module 5 via BGA solder balls 8, wherein the BGA solder balls 8 are electrically connected to the third wiring layer on the back of the substrate. The BGA solder balls 8 include ground solder balls and power solder balls.

[0059] Figure 6 A schematic diagram of a vertical power supply module according to an embodiment of the present invention is shown.

[0060] like Figure 6 As shown, the vertical power supply module 5 includes a circuit board 51, a second-stage voltage regulation module 52, a second heat dissipation module 53, a power connector 54, a PCB board 55, a first-stage voltage regulation module 56, and passive components 57.

[0061] Circuit board 51 is electrically connected to substrate 3 via BGA solder balls 8. A fourth wiring layer 58 is arranged on the front side of circuit board 51. The BGA solder balls 8 connect the fourth wiring layer 58 to the third wiring layer of substrate 3. The fourth wiring layer 58 on the surface of circuit board 51 improves the connectivity with solder balls of different pitches.

[0062] The circuit board 51 has a vertical metal trace 59, which electrically connects the fourth wiring layer 58 and the second-stage voltage regulation module 52. The vertical metal trace 59 runs through the circuit board 51 and is electrically connected to the fourth wiring layer 58 and the second-stage voltage regulation module 52. The vertical metal trace 59 can be a metal tube, such as a copper tube, to increase current carrying capacity. The metal tube can be hollow inside to enhance heat dissipation and reduce the effects of thermal expansion and contraction. By directly connecting the vertical metal trace in the circuit board to the corresponding ground BGA / power BGA, the length of the power trace is reduced, thereby reducing the resistance and voltage drop on the power supply. The circuit board has a built-in isolation layer 60, which uses two adjacent vertical metal traces as the upper and lower plates of a capacitor, forming a MIM capacitor. Power integrity is improved by integrating passive components such as capacitors into the circuit board.

[0063] The second-stage voltage regulation module 52 is disposed on the back of the circuit board 51 and is electrically connected to the vertical metal trace 59 in the circuit board 51. The first side of the second-stage voltage regulation module 52 is connected to the circuit board 51, and its second side is connected to the second heat dissipation module 53, with the first side and the second side of the second-stage voltage regulation module 52 facing each other. The second heat dissipation module 53 can be a heat dissipation structure in the form of a metal heat sink or a microchannel.

[0064] The second heat dissipation module 53 has a pre-drilled hole 531. The power connector 54 is electrically connected to the second-stage voltage regulation module 52 via a circuit through the pre-drilled hole. The pre-drilled hole 531 can also be used to fix mechanical components. The first side of the second heat dissipation module 53 is connected to the second side of the second-stage voltage regulation module 52, and the second side of the second heat dissipation module 53 is connected to the power connector 54. The first side and the second side of the second heat dissipation module 53 are opposite to each other.

[0065] The second side of the PCB board 55 is connected to the power connector 54, and the PCB board 55 is electrically connected to the power connector 54. The first-stage voltage regulation module 56 and multiple passive components 57 are electrically connected to both sides of the PCB board 55, with the multiple components located on both sides of the first-stage voltage regulation module 56.

[0066] Here, the power connector 54 serves to bring out the I / O pins related to the functional interface from the circuit board to connect to various external boards, thereby improving flexibility.

[0067] The first-stage voltage regulation module 56 and the second-stage voltage regulation module 52 are vertically connected via power connector 54. This vertical connection enables multi-stage voltage regulation. The first-stage voltage regulation module 56 is connected to an external DC power input and is soldered onto a small PCB board with passive components such as capacitors using double-sided mounting. The second-stage voltage regulation module provides the large current required by the chip at the specified voltage. It is connected to the back of circuit board 51 via PCB soldering in a matrix arrangement. By integrating the voltage regulation modules onto circuit board 51 and using vertical power supply, the trace length of the power path is reduced. This wafer-level package structure integrates a vertical power supply module and incorporates components that improve power integrity.

[0068] When current flows through the power supply network, a portion of the applied voltage will drop in the power transmission network according to Ohm's law. The amount of voltage drop is V = IR. With the current I remaining constant, the voltage drop can be reduced by decreasing the resistance. The vertical power supply module described above uses a vertical connection to reduce the length of the power and ground wires, thereby reducing the resistance value and thus reducing the voltage drop.

[0069] The manufacturing method of the above-mentioned heat pipe heat dissipation module includes:

[0070] Step 1: Fabricate a first microchannel trench on the back side of the second remolded wafer. The first microchannel trench is formed on the back side of the second remolded wafer using an etching method. The second remolded wafer includes multiple second chips and a second molding layer that encapsulates the second chips. The electrodes on the front side of the second chips and the back side of the second chips expose the second molding layer. The front side of the second remolded wafer is the surface with electrodes, and the back side of the second remolded wafer is opposite to the front side.

[0071] Step 2: Fabricate a second microchannel trench on the front side of the substrate. The second microchannel trench is formed on the front side of the substrate by etching, wherein the number, width, and spacing of the second microchannel trench are the same as those of the first microchannel trench.

[0072] Step 3: Connect the second remolded wafer and the substrate, wherein the second microchannel trench is aligned with the first microchannel trench to form a channel. The second remolded wafer and the substrate are connected by connecting the bumps to the second redistribution layer on the front side of the substrate.

[0073] Step 4: Insert the heat pipe into the channel. The diameter of the heat pipe is equal to the sum of the depth of the first microchannel groove, the depth of the second microchannel groove, the thickness of the first redistribution layer, the thickness of the second redistribution layer, and the height of the bumps, so that the heat pipe can be just accommodated in the channel. The heat pipe is arranged longitudinally on the front side of the substrate and is located in the gap between the bumps. Preferably, the heat pipe is located at 1 / 2 of the bump gap, without affecting the arrangement of the bumps. The heat pipe directly contacts the second chip, improving the heat dissipation effect.

[0074] Figure 7 A schematic diagram illustrating the working principle of a heat pipe is shown.

[0075] The working principle of a heat pipe is as follows:

[0076] The chip transfers heat to a heat pipe, which then dissipates the heat. For example... Figure 7 As shown, a heat pipe consists of a container and a capillary-structured core. Functionally, the heat pipe is divided into an evaporation section, a condensation section, and an insulation section between them. In the evaporation section, the working fluid inside the core is heated and evaporates, carrying away heat—the latent heat of vaporization of the working fluid. The vapor flows from the central channel to the condensation section of the heat pipe, condenses into liquid, and releases latent heat. Under capillary action, the liquid flows back to the evaporation section. This process forms a closed loop, transferring a large amount of heat from the evaporation section to the condensation section.

[0077] When the evaporation section is below and the condensation section is above, with the heat pipe placed vertically, the return flow of the working liquid can be satisfied by gravity, eliminating the need for a capillary-structured wick. This type of heat pipe without a porous wick is called a thermosiphon. In the above encapsulation structure, the heat pipe is placed horizontally and uses a capillary-structured wick.

[0078] Compared to microfluidic cooling structures, heat pipes do not require inlet and outlet ports; the liquid circulates internally. The evaporation of the working fluid in a heat pipe absorbs a significant amount of heat, while condensation releases heat. Utilizing this evaporation and condensation cycle achieves the most efficient heat transfer. Heat pipes are heat transfer devices that employ this method, possessing a thermal conductivity thousands of times that of copper. This phase-change heat transfer rapidly dissipates heat from the heat source to other areas, thus relieving heat loss.

[0079] Figure 8 The process of fabricating a wafer-level packaging structure for multiple heterogeneous chips according to an embodiment of the present invention is illustrated.

[0080] like Figure 8 As shown, the fabrication method of the wafer-level packaging structure for multiple heterogeneous chips includes:

[0081] Step 1 involves providing multiple first chips and multiple second chips that have passed testing. Both the first and second chips have electrodes on their front sides. The first and second chips are different types of chips. In one embodiment of the invention, the first chip is a computing chip, and the second chip is an interface chip. In other embodiments of the invention, the first chip can also be a memory chip (HBM or DDR).

[0082] Step 2: Multiple first chips are molded to form a first remolded wafer, and multiple second chips are molded to form a second remolded wafer. The electrodes on the front side of the first chips and the electrodes on the front side of the second chips are not molded.

[0083] Step 3 involves hybrid bonding of the first and second reshaped wafers, wherein the electrodes on the front side of the first chip are bonded to the electrodes on the front side of the second chip. Hybrid bonding eliminates the need for microbumps, reducing the interconnect pitch to below 10 μm and decreasing the interconnect width and spacing, thereby increasing interconnect density. Increased interconnect density leads to improved interconnect bandwidth. Vertical electrode bonding between chips reduces the interconnect length between heterogeneous chips, further enhancing interconnect bandwidth. The first chip in the first reshaped wafer and the second chip in the second reshaped wafer are interconnected in a staggered manner, with one second chip electrically connected to multiple adjacent first chips via hybrid electrode bonding. In this embodiment, one second chip is hybrid-bonded to four adjacent first chips. The first chip can be electrically connected to any three other first chips via metal lines inside the second chip, and the second chip can be electrically connected to adjacent second chips via metal lines inside the first chip. This method of staggered heterogeneous chip connection allows one second chip to control four nearby first chips. By using the second chip, the length of horizontal connections between first chips can be reduced.

[0084] Step 4: Thin the back side of the second reshaped wafer to expose the back side of the second chip.

[0085] Step 5: Fabricate through-silicon vias (TSVs) on the back side of the second chip. First, form TSVs on the back side of the second chip by etching. Then, fill the TSVs with metal to make them conductive. The TSVs are electrically connected to the electrodes on the front side of the second chip.

[0086] Step 6: Fabricate the first microchannel groove on the back side of the second reshaped wafer.

[0087] Step 7: Deploy a first super-wiring layer on the back side of the second remolded wafer, wherein the first super-wiring layer is electrically connected to a through-silicon via.

[0088] Step 8: Arrange bumps on the surface of the first overlay layer opposite to the second reshaped wafer.

[0089] Step 9: Fabricate a second microchannel groove on the front side of the substrate. The second microchannel groove has the same number, width, and spacing as the first microchannel groove.

[0090] Step 10: Arrange a second wiring layer and a third wiring layer on the front and back sides of the substrate, respectively.

[0091] Step 11: Arrange BGA solder balls on the surface of the third wiring layer facing away from the substrate.

[0092] Step 12 involves connecting the bumps to the second redistribution layer on the front side of the substrate to connect the second remolded wafer and the substrate. After the second remolded wafer and the substrate are connected, the second microchannel trench is aligned with the first microchannel trench to form a channel.

[0093] Step 13: Insert the heat pipe into the channel. The diameter of the heat pipe is equal to the sum of the depth of the first microchannel groove, the depth of the second microchannel groove, the thickness of the first redistribution layer, the thickness of the second redistribution layer, and the height of the bumps, so that the heat pipe can be just accommodated in the channel. The heat pipe is arranged longitudinally on the front side of the substrate and is located in the gap between the bumps. Preferably, the heat pipe is located at 1 / 2 of the bump gap, without affecting the arrangement of the bumps. The heat pipe directly contacts the second chip, improving the heat dissipation effect.

[0094] Step 14: Arrange capacitors in the circuit board and arrange a fourth wiring layer on the front side of the circuit board. The fourth wiring layer is electrically connected to the capacitors. Grooves are etched into the circuit board, and two opposing metal tubes are arranged on the inner wall of each groove as the upper and lower plates of the capacitor. Insulating material is then arranged within the grooves to form an isolation layer, forming a MIM (Metal Injection Molding) capacitor. The metal tubes can be, for example, cuboids. The metal tubes, serving as vertical metal traces in the circuit board, increase current carrying capacity. The interior of the metal tubes can be hollow to enhance heat dissipation and reduce the effects of thermal expansion and contraction.

[0095] Step 15: Arrange a second-stage voltage regulation module on the back of the circuit board. The first side of the second-stage voltage regulation module is connected to the back of the circuit board, and the second-stage voltage regulation module is electrically connected to the capacitors in the circuit board.

[0096] Step 16: Connect the circuit board to the substrate by connecting the fourth wiring layer on the front side of the circuit board to the BGA solder balls.

[0097] Step 17: A first heat dissipation module is mounted on the back side of the first remolded wafer, and a second heat dissipation module is mounted on the second side of the second-stage voltage regulation module, away from the circuit board. The second side of the second-stage voltage regulation module is opposite to the first side. The second heat dissipation module has pre-drilled holes. The first side of the second heat dissipation module is connected to the second side of the second-stage voltage regulation module.

[0098] Step 18: Arrange a power connector on the second side of the second heat dissipation module, away from the second-stage voltage regulation module. The first side of the second heat dissipation module is opposite to the second side. The power connector is electrically connected to the second-stage voltage regulation module via a circuit through a pre-drilled hole in the second heat dissipation module. The first side of the power connector is connected to the second side of the second heat dissipation module.

[0099] Step 19: Arrange the PCB board on the second side of the power connector away from the second heat dissipation module.

[0100] Step 20: Arrange the first-stage voltage regulation module and passive components on both sides of the PCB board. Multiple passive components are located around the first-stage voltage regulation module. Passive components include capacitors, inductors, and other devices.

[0101] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A wafer-level packaging structure for multiple heterogeneous chips, characterized in that, The first reshaped wafer and the second reshaped wafer are interconnected. The first reshaped wafer includes a plurality of first chips, and the second reshaped wafer includes a plurality of second chips, wherein the first chips and the second chips are different. The second chip has a through-silicon via (TSV) that penetrates the second chip, with one end connected to the electrode of the second chip and the other end exposed on the back of the second chip. The first interconnect layer is disposed on the back side of the second remolded wafer and is electrically connected to the through-silicon via. The substrate has a front side connected to the back side of the second reshaped wafer via bumps, wherein the front side of the substrate has a second wiring layer and the back side has a third wiring layer, and the bumps connect the first wiring layer and the second wiring layer. as well as A heat pipe heat dissipation module includes a first microchannel groove on the back side of a second remolded wafer, a second microchannel groove on the front side of a substrate, and a heat pipe housed in a channel formed by the combination of the first and second microchannel grooves. The heat pipe is located in the gap between the bumps, and the diameter of the heat pipe is equal to the sum of the depth of the first microchannel groove, the depth of the second microchannel groove, the thickness of the first redistribution layer, the thickness of the second redistribution layer, and the height of the bumps. A vertical power supply module is connected to the back of the substrate via BGA solder balls, wherein the BGA solder balls include ground solder balls and power solder balls. The vertical power supply module includes: A circuit board having a fourth wiring layer on its front side, the circuit board having vertical metal traces electrically connected to the fourth wiring layer, and the circuit board being electrically connected to the substrate via BGA solder balls. The second-stage voltage regulation module is located on the back of the circuit board and is electrically connected to the longitudinal metal traces in the circuit board. A power connector that is electrically connected to the second-stage voltage regulation module; PCB board, which is electrically connected to the power connector; and The first-stage voltage regulation module is electrically connected to the PCB board.

2. The wafer-level packaging structure for multiple heterogeneous chips according to claim 1, characterized in that, The first remolded wafer and the second remolded wafer are connected by a hybrid bonding between the electrodes on the front side of the first chip and the electrodes on the front side of the second chip. The first chip in the first remolded wafer and the second chip in the second remolded wafer are interconnected in a staggered manner. One of the second chips is electrically connected to a plurality of adjacent first chips. The first chip is electrically connected to adjacent first chips through metal lines inside the second chip, and the second chip is electrically connected to adjacent second chips through metal lines inside the first chip.

3. The wafer-level packaging structure for multiple heterogeneous chips according to claim 1, characterized in that, The first remolded wafer also includes a first molding layer for molding multiple first chips, wherein the electrodes on the front side of the first chips are exposed in the first molding layer; The second remolded wafer also includes a second molding layer that encapsulates a plurality of second chips, wherein the electrodes on the front side of the second chips and the back side of the second chips are exposed by the second molding layer.

4. The wafer-level packaging structure for multiple heterogeneous chips according to claim 1, characterized in that, The first chip is a computing chip or a storage chip; The second chip is an interface chip.

5. The wafer-level packaging structure for multiple heterogeneous chips according to claim 1, characterized in that, The vertical power supply module also includes: A second heat dissipation module, connected to the voltage regulation module, has pre-drilled holes; and A passive device that is electrically connected to the PCB board.

6. The wafer-level packaging structure for multiple heterogeneous chips according to claim 5, characterized in that, The power connector is electrically connected to the second-stage voltage regulation module via a circuit through a reserved hole in the second heat dissipation module. The first side of the second-stage voltage regulation module is connected to the circuit board, and its second side is connected to the second heat dissipation module. The first side and the second side of the second-stage voltage regulation module are opposite to each other. as well as The first side of the second heat dissipation module is connected to the second side of the second-stage voltage regulation module, the second side of the second heat dissipation module is connected to the power connector, and the first side and the second side of the second heat dissipation module are opposite to each other.

7. The wafer-level packaging structure for multiple heterogeneous chips according to claim 1, characterized in that, The circuit board has a built-in isolation layer, which together with two adjacent vertical metals form a capacitor.

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