Vertical two-dimensional field effect device and method of manufacturing the same

Abstract

The application provides a vertical two-dimensional field effect device and a manufacturing method thereof. The method comprises the following steps: according to the pattern design of the vertical two-dimensional field effect device, a first forming mask and a first etching mask are arranged on the surface of a substrate and cross each other, the width of the first forming mask is equal to the thickness of a field effect tube unit, the interval of the first etching mask is equal to the length of the field effect tube unit, a first recess with a first depth is formed by first etching; the remaining parts of the lower parts of the first forming mask and the first etching mask form a vertical field effect device prototype and a tension skeleton respectively; a second recess with a second depth is formed by second etching, and a post-processing process is performed to form a source, a gate and a drain. The vertical two-dimensional field effect device obtained by the above method comprises a field effect tube with a vertical plane shape on a substrate, the upper end and the lower end of the field effect tube are respectively a source or a drain, the gate is arranged between the source and the drain, and the periphery of the final field effect tube is filled with a first insulating material.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their manufacturing technology, and particularly to a vertical two-dimensional field-effect device and its manufacturing method. Background Technology

[0002] Traditional field-effect devices are horizontally mounted on a substrate, meaning that the source, gate, and drain of the field-effect device are all horizontally laid on the silicon substrate. They have mature manufacturing processes to produce. During the manufacturing process, due to the large area of ​​support provided by the silicon substrate, the device height is small, resulting in good structural stability during the process and preventing instability and deformation that could affect quality and yield.

[0003] However, the laying process occupies a large area of ​​the silicon substrate, thus reducing the number and density of distributions per unit area, which affects the integration of semiconductors and is not conducive to miniaturization. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention provides a vertical two-dimensional field-effect device, comprising: a substrate;

[0005] A field-effect transistor unit includes multiple field-effect transistors arranged in an array in a vertical direction perpendicular to the substrate;

[0006] The field-effect transistor includes a source, a gate, and a drain. The source and drain are located at the upper or lower end of the field-effect transistor, respectively. The gate is located between the source and the drain. The gate is annular in a horizontal direction parallel to the substrate. The periphery of the field-effect transistor is filled with a first insulating material.

[0007] Optionally, a silicon layer is provided on the outer side of the annular gate, and a second insulating material is filled between the silicon layer and the annular gate.

[0008] Optionally, the first insulating material and the second insulating material are different materials.

[0009] Optionally, the first insulating material is silicon nitride, and the second insulating material is silicon oxide.

[0010] Optionally, the first insulating material and the second insulating material are the same material.

[0011] Optionally, the substrate is provided with a conductive connection layer for connecting adjacent field-effect transistors.

[0012] Optionally, the conductive connection layer is a silicide or a cobalt-containing silicide material.

[0013] The present invention also provides a method for manufacturing a vertical two-dimensional field-effect device, comprising the following steps:

[0014] S10, based on the pattern design of the vertical two-dimensional field-effect device, sets an intersecting first forming mask and a first etching mask on the substrate surface. The width of the first forming mask is equal to the thickness of the field-effect transistor unit, and the spacing of the first etching mask is equal to the length of the field-effect transistor unit. The first etching is performed to form a first groove of a first depth. The remaining part at the bottom of the first forming mask forms the prototype of the vertical field-effect device. The remaining part at the bottom of the first etching mask forms a tension skeleton.

[0015] S20 Remove the first forming mask, fill the first insulating material into the first groove and perform a leveling process;

[0016] S30 removes the first etch mask, sets a second etch mask in the area other than the first etch mask, performs a second etch to form a second groove of a second depth, and then performs a post-processing process to form the source, gate and drain.

[0017] Optionally, in step S10, the first forming mask is configured as a plurality of strips arranged in parallel and spaced apart from each other.

[0018] Optionally, in step S20, before filling the first groove, an oxidation treatment is performed, and after the oxidation treatment, the oxide layer at the bottom of the first groove is removed. Then, a conductor material infiltration treatment is performed on the bottom of the first groove, thereby forming a conductive connection layer connecting adjacent field-effect transistor units on the substrate.

[0019] Optionally, the conductor material is a silicide or a cobalt-containing silicide.

[0020] Optionally, in step S20, before filling the first groove, the first depth is divided into three height segments along the vertical direction and doped with different densities. The doping density of the upper and lower height segments is higher than that of the middle height segment. The middle height segment forms the gate prototype, while the upper and lower height segments form the source prototype or the drain prototype, respectively.

[0021] Optionally, the first forming mask and the first etching mask are arranged in a right-angled cross shape, and the second forming mask and the second etching mask are arranged in a right-angled cross shape.

[0022] Optionally, in step S30, the post-processing includes:

[0023] S31 performs an oxidation treatment on the second groove, then fills the second groove with the first insulating material and performs a leveling treatment;

[0024] S33 sets a second forming mask in addition to the original first forming mask position, and performs a third etching to remove the first insulating material and oxide layer to form a third groove with a third depth, the third depth including an upper height section and a middle height section;

[0025] S35 After filling the third groove with the second insulating material and leveling it, a fourth etching is performed to remove the second insulating material to form a fourth groove with a fourth depth, the fourth depth including the upper height section; a first insulating material film layer is provided on the side wall of the fourth groove;

[0026] S37 forms a gate slot by etching the middle height section of the fourth groove, oxidizes the sidewall of the gate slot to form a second insulating material, and fills the gate slot with metal to form a ring gate.

[0027] S39 uses the first insulating material to fill the fourth groove.

[0028] The present invention discloses a vertical two-dimensional field-effect device and its manufacturing method. During manufacturing, according to the pattern design of the vertical two-dimensional field-effect device, a first forming mask and a first etching mask are intersecting on the surface of a substrate. The width of the first forming mask is equal to the thickness of the field-effect transistor unit, and the spacing of the first etching mask is equal to the length of the field-effect transistor unit. A first etching is performed to form a first groove of a first depth, which is not less than the total height of the vertically arranged source, gate, and drain electrodes. This allows the portion of the first forming mask to form a prototype of the vertical field-effect device. Due to the retention of the first etching mask position, a tensioned skeleton structure is formed at both ends of the prototype of the vertical field-effect device, enabling the prototype of the vertical field-effect device to achieve high-quality manufacturing even when the device is tall. The thickness and width are relatively large, and the upright planar shape can be maintained without falling over before filling. The first forming mask is removed, and the first insulating material is filled into the first groove and leveled. The filled first insulating material is tightly squeezed against the vertical field effect device prototype from both sides. At this time, the first etching mask is removed, and a second etching mask is set in the area other than the first etching mask. A second etching is performed to form a second groove with a second depth. The second depth is greater than the first depth. That is, the tension skeleton structure at both ends of the previously retained vertical field effect device prototype is removed. Since there is filling on both sides, the removal of the tension skeleton structure will not affect the vertical field effect device prototype. Then, the post-processing process is performed to form the source, gate and drain. This method allows for the fabrication of vertical two-dimensional field-effect devices with nanometer-scale thickness. The vertical two-dimensional field-effect device includes a substrate and a field-effect transistor unit with multiple field-effect transistors arranged vertically and perpendicularly to the substrate. Each field-effect transistor includes a source, a gate, and a drain, with the upper and lower ends being the source or drain, respectively. The gate is located between the source and drain, and both ends and sides are filled with a first insulating material. Because the field-effect device is vertically arranged, it occupies a very small substrate area, thus allowing for the arrangement of more devices per unit area, increasing the device's integration and performance.

[0029] In this invention, a vertical two-dimensional FET is intentionally created on a Si substrate, with its source / gate and drain stacked vertically on the silicon substrate, to increase the integration level of conventional MOS or FINFET devices, improve device performance (device response speed - RCdelay, increase operating current, reduce device impedance), and provide a wide-channel device.

[0030] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0033] Figure 1 This is a three-dimensional schematic diagram of a vertical two-dimensional field-effect device according to an embodiment of the present invention;

[0034] Figure 2 This is a flowchart illustrating a manufacturing method for a vertical two-dimensional field-effect device according to an embodiment of the present invention.

[0035] Figure 3 This is a flowchart of the post-processing technology used in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0036] Figure 4 This is a planar schematic diagram of step S10 in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0037] Figure 5 for Figure 4 Schematic diagram of cross-section a-a' of the doping treatment in the example;

[0038] Figure 6 This is a cross-sectional schematic diagram of step a-a' of the oxidation treatment and conductive connection layer formation steps in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0039] Figure 7 This is a cross-sectional schematic diagram of step a-a', where the first groove is filled with the first insulating material after the formation of the conductive connection layer, according to an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0040] Figure 8This is a planar schematic diagram of the second etching step for forming the second groove in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0041] Figure 9 for Figure 8 Schematic diagram of the b-b' section of the embodiment;

[0042] Figure 10 for Figure 8 A schematic diagram of the c-c' section of the embodiment;

[0043] Figure 11 This is a cross-sectional schematic diagram of the second groove oxidation treatment step b-b' in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0044] Figure 12 This is a cross-sectional schematic diagram of step b-b', which is the second groove filling step of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0045] Figure 13 This is a cross-sectional schematic diagram of the second groove oxidation treatment step c-c' in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0046] Figure 14 This is a cross-sectional schematic diagram of step c-c', which is the second groove filling step of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0047] Figure 15 A schematic diagram of the second forming mask and the second etching mask set up for an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0048] Figure 16 This is a schematic diagram of the etching process used to form the third groove in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0049] Figure 17 for Figure 16 A schematic diagram of the b-b' cross-section of the third groove etched in the embodiment;

[0050] Figure 18 for Figure 16 A schematic diagram of the c-c' cross-section of the third groove etched in the embodiment;

[0051] Figure 19 This is a cross-sectional schematic diagram of step b-b', the third groove filling step of the manufacturing method of the vertical two-dimensional field-effect device of the present invention, which is an embodiment of the manufacturing method of the present invention.

[0052] Figure 20 This is a schematic diagram of the cross-section of the fourth groove a-a' formed by etching in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0053] Figure 21 This is a schematic diagram of the cross-section of the fourth groove b-b' formed by etching in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0054] Figure 22 This is a schematic diagram of the cross-section of the gate slot a-a' formed by etching in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0055] Figure 23 This is a schematic diagram of the cross-section of the gate groove b-b' formed by etching in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention;

[0056] Figure 24 This is a schematic cross-sectional view of step a-a', which is the gate slot oxidation treatment to form the second insulating material in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0057] Figure 25 This is a schematic cross-sectional view of step b-b', which is the gate slot oxidation treatment to form the second insulating material in an embodiment of the manufacturing method of the vertical two-dimensional field-effect device of the present invention.

[0058] Figure 26 This is a schematic cross-sectional view of step a-a', which is a method embodiment of manufacturing a vertical two-dimensional field-effect device of the present invention, to form an annular gate by filling the gate slot with metal.

[0059] Figure 27 This is a schematic cross-sectional view of step b-b', which is a method for manufacturing a vertical two-dimensional field-effect device according to the present invention, involving the gate slot metal filling to form an annular gate.

[0060] Figure 28 This is a cross-sectional schematic diagram of step b-b', the fourth groove filling step of the manufacturing method of the vertical two-dimensional field-effect device of the present invention. Detailed Implementation

[0061] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0062] like Figure 1 As shown, this embodiment of the invention provides a vertical two-dimensional field-effect device, substrate 2;

[0063] A field-effect transistor unit includes a plurality of field-effect transistors 1 arranged in an array in a vertical direction perpendicular to the substrate;

[0064] The field-effect transistor 1 includes a source, a gate 11, and a drain. The source and drain 12 are located at the upper or lower end of the field-effect transistor, respectively. The gate 11 is located between the source and the drain. The gate 11 is annular in a horizontal direction parallel to the substrate 2. The periphery of the field-effect transistor 1 is filled with a first insulating material 3.

[0065] The working principle and beneficial effects of the above technical solution are as follows: The vertical two-dimensional field-effect device of this solution includes a field-effect transistor unit containing multiple field-effect transistors. The field-effect transistors include a source, a gate, and a drain, which are arranged vertically and perpendicular to the substrate. The upper and lower ends are the source and drain, respectively, and the gate is located between the source and drain. The periphery of the field-effect transistor (including both ends and both sides) is filled with a first insulating material, which can generally be silicon nitride. Since the field-effect device is arranged vertically, it occupies a very small substrate area. Therefore, more devices can be arranged per unit area, increasing the integration and performance of the device.

[0066] In one embodiment, such as Figure 26 As shown, a silicon layer 111 is provided on the outer side of the ring gate 113, and a second insulating material 112 is filled between the silicon layer 111 and the ring gate 113; wherein,

[0067] The first insulating material 3 and the second insulating material 112 are different materials; the first insulating material 3 can be silicon nitride, while the second insulating material 112 can be silicon oxide.

[0068] or

[0069] The first insulating material 3 and the second insulating material 112 are made of the same material.

[0070] The working principle and beneficial effects of the above technical solution are as follows: This solution provides a gate structure for a vertical two-dimensional field-effect device, with an intermediate silicon crystal layer and a second insulating material and a ring gate disposed around the silicon crystal layer. Conductivity is achieved through the ring gate. The second insulating material is in close contact with the silicon crystal layer, and the ring gate is in close contact with the second insulating material. The silicon crystal layer, the second insulating material, and the ring gate are all perpendicular to the substrate. This structure ensures that the gate has sufficient area, thereby guaranteeing the performance of the device.

[0071] In one embodiment, such as Figure 6-7 As shown, a conductive connection layer 16 is provided on the substrate 2 between the bottoms of each adjacent field-effect transistor 1. The conductive connection layer 16 is generally made of silicide or cobalt-containing silicide material.

[0072] The working principle and beneficial effects of the above technical solution are as follows: At the connection point between the substrate and the bottom of each adjacent field-effect transistor, a conductive connection layer is set to connect each adjacent field-effect transistor. The conductive connection layer is generally made of silicide or cobalt-containing silicide material to ensure the function of the device and form a whole field-effect transistor unit group.

[0073] like Figure 2 and Figure 4-5 and Figure 7-10As shown, this embodiment of the invention also provides a method for manufacturing a vertical two-dimensional field-effect device, including the following steps:

[0074] S10 Figure 4 As shown, according to the pattern design of a vertical two-dimensional field-effect device, a first forming mask 41 and a first etching mask 51 are intersecting on the surface of the substrate 2. The width of the first forming mask 41 is equal to the thickness of the field-effect transistor 1, and the spacing of the first etching masks 51 is equal to the length of the field-effect transistor 1. Figure 5 As shown, the first etching is performed to form a first groove 14 of a first depth; the remaining portion at the bottom of the first forming mask 41 forms a prototype of a vertical field-effect device; the remaining portion at the bottom of the first etching mask 51 forms a tension skeleton.

[0075] S20 removes the first forming mask, such as Figure 7 As shown, the first insulating material 17 is filled into the first groove 14 and then leveled.

[0076] S30 removes the first etch mask, such as Figure 8 As shown, a second etching mask 52 is provided in the area other than the first etching mask, such as... Figure 9 and Figure 10 As shown, a second etching is performed to form a second groove 18 of a second depth, and then a post-processing process is performed to form the source, gate and drain.

[0077] The working principle and beneficial effects of the above technical solution are as follows: In the manufacturing of field-effect devices, according to the graphic design of a vertical two-dimensional field-effect device, a first forming mask and a first etching mask are set on the substrate surface, intersecting each other. Generally, a right-angle intersection is chosen, meaning the first forming mask and the first etching mask are perpendicular to each other. The width of the first forming mask is equal to the thickness of the field-effect transistor unit. Multiple first forming masks can be arranged in parallel intervals. The spacing of the first etching masks is equal to the length of the field-effect transistor unit. At least two first etching masks are set and arranged in parallel intervals. The first etching is performed to form a first groove of a first depth, which is not less than the total height of the source, gate, and drain arranged vertically. This allows the portion of the first forming mask to form the prototype of a vertical field-effect device. Due to the retention of the first etching mask position, a tension skeleton structure is formed at both ends of the prototype of the vertical field-effect device, ensuring that even if the height and thickness of the prototype are relatively large, it can maintain an upright planar shape and will not collapse before filling. The first forming mask is removed, and the first groove is filled with a first insulating material and leveled. The first insulating material is tightly extruded onto the vertical field-effect device (VFET) prototype from both sides. Then, the first etch mask is removed, and a second etch mask is placed on the area excluding the first etch mask. A second etching is performed to form a second groove with a second depth greater than the first depth. This removes the tensioned framework structure at both ends of the previously retained VFET prototype. Since there is filler on both sides, the removal of the tensioned framework structure does not affect the VFET prototype. Post-processing is then performed to form the source, gate, and drain. In this way, a VFET with a thickness on the nanometer scale can be manufactured. A two-dimensional field-effect device (FET) is disclosed. This vertical two-dimensional FET includes a substrate and a FET unit with multiple FETs arranged vertically perpendicular to the substrate. Each FET includes a source, a gate, and a drain, with the upper and lower ends being the source or drain, respectively. The gate is located between the source and drain. Both ends and sides of the FET are filled with a first insulating material, which is typically silicon nitride. Because this FET is vertically arranged, it occupies a very small substrate area, thus allowing for the arrangement of more devices per unit area, increasing the device's integration density and performance.

[0078] In one embodiment, in step S10, as Figure 4 As shown, the first forming mask is configured as multiple strips arranged in parallel and spaced intervals; in step S20, as... Figure 6 and Figure 7As shown, before filling the first groove 14, an oxidation treatment is performed to form an oxide layer 15. After the oxidation treatment, the oxide layer at the bottom of the first groove is removed. Then, a conductor material infiltration treatment is performed on the bottom of the first groove 14. The metal used for infiltration treatment is generally powdered cobalt, thereby forming a conductive connection layer 16 connecting each adjacent field-effect transistor unit on the substrate 2. The conductive connection layer 16 is generally made of silicide or cobalt-containing silicide material, such as cobalt silicide.

[0079] The working principle and beneficial effects of the above technical solution are as follows: This solution sets up multiple field-effect transistors (FETs) on the same substrate, and all FETs are arranged vertically in parallel with intervals. The spacing between each adjacent FET can be the same as the spacing between traditional horizontally laid FET devices. Since its thickness is only at the nanometer level, it can greatly increase the number of FETs per unit area and improve the integration of the device. During fabrication, the vertical FET prototype is first oxidized to form an oxide layer. Then, the oxide layer at the bottom of the etching trench between adjacent FETs is removed, and a conductive material is used for infiltration treatment. Since the conductive material only reacts with pure silicon and does not interact with the second insulating material, silicon oxide can generally be selected as the second insulating material. Therefore, a conductive connection layer connecting each adjacent FET can be formed at the connection between the substrate and the bottom of each adjacent FET, ensuring the device function and forming a whole FET unit group.

[0080] In one embodiment, such as Figure 3 and Figure 11-28 As shown, in step S30, the post-processing technology includes:

[0081] S31 Figure 11 and 13 As shown, the second groove is subjected to an oxidation treatment, as follows: Figure 12 and 14 As shown, the first insulating material is then filled into the second groove and the surface is leveled.

[0082] S33 as Figure 15 As shown, a second forming mask 42 is provided at a location other than the original first forming mask position, such as... Figure 16-18 As shown, a third etching is performed to remove the first insulating material and oxide layer to form a third groove 181 with a third depth, the third depth including an upper height section and a middle height section;

[0083] S35 Figure 19 As shown, after the third groove 181 is filled with the second insulating material 182 and leveled, as Figure 20 and 21 As shown, a fourth etching is performed to remove the second insulating material 182 to form a fourth groove 183 with a fourth depth, the fourth depth including an upper height section; a first insulating material film layer 184 is provided on the sidewall of the fourth groove 183;

[0084] S37 Figure 22 and 23 As shown, the door groove 185 is formed by etching the middle height section of the fourth groove, as... Figure 24 and 25 As shown, the sidewall of the door groove 185 is oxidized to form a second insulating material 112, such as... Figure 26 and 27 As shown, a ring gate 113 is formed by filling the gate slot 185 with metal;

[0085] S39 Figure 28 As shown, the fourth groove 183 is filled with the first insulating material 17.

[0086] The working principle and beneficial effects of the above technical solution are as follows: This solution provides a post-processing technology for manufacturing vertical two-dimensional field-effect devices. Through multiple etching processes, the gate structure of the device is shaped, so that the gate includes a silicon crystal layer and a second insulating material and a ring gate symmetrically arranged on both sides of the silicon crystal layer. Conductivity is achieved through the ring gate. The second insulating material is in close contact with the silicon crystal layer, and the ring gate is in close contact with the second insulating material. The silicon crystal layer, the second insulating material and the ring gate are all perpendicular to the substrate. This structure ensures that the gate has sufficient area, thereby ensuring the performance of the device.

[0087] In one embodiment, such as Figure 4 As shown, the first forming mask 41 and the first etching mask 51 are arranged at a right-angle cross, as... Figure 15 As shown, the second forming mask 42 and the second etching mask 52 are arranged at right angles to each other.

[0088] The working principle and beneficial effects of the above technical solution are as follows: In the manufacturing process of vertical two-dimensional field-effect devices, the first forming mask and the first etching mask are arranged in a right-angle cross shape, and the second forming mask and the second etching mask are arranged in a right-angle cross shape. When manufacturing a device structure containing multiple field-effect transistors, the arrangement of multiple first forming masks and first etching masks forms a fishbone support shape. The retained part of the first etching mask is similar to the vertebrae of a fish. This structure ensures the effectiveness of the support during the process. The distance between two adjacent first etching masks can be determined according to the size of the field-effect transistors to ensure both support and the performance of the manufactured field-effect device.

[0089] In one embodiment, in step S20, as Figure 5 As shown, before filling the first groove, the first depth is divided into three height segments along the vertical direction and doped with different densities. The doping density of the upper and lower height segments is higher than that of the middle height segment. The middle height segment forms the gate prototype, while the upper and lower height segments form the source prototype or the drain prototype, respectively.

[0090] The working principle and beneficial effects of the above technical solution are as follows: This solution arranges the doping process before the first groove is filled. At this time, the prototype of the vertical field-effect device is fully exposed, and the process can be carried out simultaneously on both sides of the prototype of the vertical field-effect device, which increases the doping area and improves the doping efficiency. During doping, the first depth is divided into three height segments along the vertical direction for different density doping processes. The doping density of the upper and lower height segments is higher than that of the middle height segment, which ensures the quality and performance requirements of each part of the device. The gate prototype is formed in the middle height segment, and the source prototype or drain prototype is formed in the upper and lower height segments, respectively.

[0091] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for manufacturing a vertical two-dimensional field-effect device, characterized in that, Includes the following steps: S10, based on the pattern design of the vertical two-dimensional field-effect device, sets an intersecting first forming mask and a first etching mask on the substrate surface. The width of the first forming mask is equal to the thickness of the field-effect transistor unit, and the spacing of the first etching mask is equal to the length of the field-effect transistor unit. The first etching is performed to form a first groove of a first depth. The remaining portion at the bottom of the first forming mask forms the prototype of a vertical field-effect device; The remaining portion at the bottom of the first etch mask forms a tension skeleton; S20 Remove the first forming mask, fill the first insulating material into the first groove and perform a leveling process; S30 removes the first etch mask, sets a second etch mask in the area other than the first etch mask, performs a second etch to form a second groove of a second depth, and then performs a post-processing process to form the source, gate and drain.

2. The method for manufacturing a vertical two-dimensional field-effect device according to claim 1, characterized in that, In step S10, the first forming mask is configured as multiple strips arranged in parallel and spaced apart from each other.

3. The method for manufacturing a vertical two-dimensional field-effect device according to claim 1, characterized in that, In step S20, before filling the first groove, an oxidation treatment is performed. After the oxidation treatment, the oxide layer at the bottom of the first groove is removed. Then, a conductor material infiltration treatment is performed on the bottom of the first groove to form a conductive connection layer connecting adjacent field-effect transistor units on the substrate.

4. The method for manufacturing a vertical two-dimensional field-effect device according to claim 3, characterized in that, The conductor material is a silicide or a cobalt-containing silicide.

5. The method for manufacturing a vertical two-dimensional field-effect device according to claim 3, characterized in that, In step S20, before filling the first groove, the first depth is divided into three height segments along the vertical direction and doped with different densities. The doping density of the upper and lower height segments is higher than that of the middle height segment. The middle height segment forms the gate prototype, while the upper and lower height segments form the source prototype or the drain prototype, respectively.

6. The method for manufacturing a vertical two-dimensional field-effect device according to claim 1, characterized in that, The first forming mask and the first etching mask are arranged in a right-angled cross shape, and the second forming mask and the second etching mask are arranged in a right-angled cross shape.

7. The method for manufacturing a vertical two-dimensional field-effect device according to claim 1, characterized in that, In step S30, the post-processing includes: S31 performs an oxidation treatment on the second groove, then fills the second groove with the first insulating material and performs a leveling treatment; S33 sets a second forming mask in addition to the original first forming mask position, and performs a third etching to remove the first insulating material and oxide layer to form a third groove with a third depth, the third depth including an upper height section and a middle height section; S35 After filling the third groove with the second insulating material and leveling it, a fourth etching is performed to remove the second insulating material to form a fourth groove with a fourth depth, the fourth depth including the upper height section; a first insulating material film layer is provided on the side wall of the fourth groove; S37 forms a gate slot by etching the middle height section of the fourth groove, oxidizes the sidewall of the gate slot to form a second insulating material, and fills the gate slot with metal to form a ring gate. S39 uses the first insulating material to fill the fourth groove.

8. A vertical two-dimensional field-effect device, characterized in that, Manufactured by any one of the manufacturing methods of claims 1-7, comprising: a substrate; A field-effect transistor unit includes multiple field-effect transistors perpendicular to the substrate, and the multiple field-effect transistors are arranged in an array in a direction parallel to the substrate; The field-effect transistor includes a source, a gate, and a drain. The source and drain are located at the upper or lower end of the field-effect transistor, respectively. The gate is located between the source and the drain. The gate is annular in a horizontal direction parallel to the substrate. The periphery of the field-effect transistor is filled with a first insulating material.

9. The vertical two-dimensional field-effect device according to claim 8, characterized in that, A silicon crystal layer is provided on the outer side of the ring gate, and a second insulating material is filled between the silicon crystal layer and the ring gate.

10. The vertical two-dimensional field-effect device according to claim 9, characterized in that, The first insulating material and the second insulating material are different materials.

11. The vertical two-dimensional field-effect device according to claim 10, characterized in that, The first insulating material is silicon nitride, and the second insulating material is silicon oxide.

12. The vertical two-dimensional field-effect device according to claim 9, characterized in that, The first insulating material and the second insulating material are the same material.

13. The vertical two-dimensional field-effect device according to claim 8, characterized in that, The substrate has a conductive connection layer that connects adjacent field-effect transistors.

14. The vertical two-dimensional field-effect device according to claim 13, characterized in that, The conductive connection layer is a silicide or a cobalt-containing silicide material.

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