A fast level shifter circuit for power management chips

Abstract

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a fast level shifting circuit for power management chips. Background Technology

[0002] With the increasing maturity of power management technology, power management chips have become an indispensable part of electronic products. The level shifting circuit, as one of the core circuits of a power management chip, directly affects the chip's performance characteristics.

[0003] Figure 1 This is a traditional level-shifting circuit, mainly composed of a high-voltage NMOS transistor M1, a low-voltage PMOS transistor M2, a low-voltage NMOS transistor M3, a resistor R1, and a Zener diode Z1. When the input terminal IN is high, NMOS transistor M1 is turned on, and its drain voltage is pulled low. The Zener diode and resistor R1 are connected in parallel to prevent the drain voltage of NMOS transistor M1 from pulling down and causing the gate oxide layer of PMOS transistor M2 to break down. The output terminal OUT is high. When the input terminal IN is low, NMOS transistor M1 is turned off, and its drain voltage is pulled high. The output terminal OUT is low. Traditional level-shifting circuits have disadvantages such as high power consumption, long delay, and inconsistent rise and fall edge delays, which limits their application in high-precision systems. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above. It proposes a fast level shifting circuit for power management chips. The technical solution of this invention is as follows:

[0005] A fast level shifting circuit for a power management chip includes: a level shifting core circuit (1) and a low-delay path detection circuit (2), wherein the signal output terminal of the level shifting core circuit (1) is connected to the signal input terminal of the low-delay path detection circuit (2), and the signal output terminal of the low-delay path detection circuit (2) is connected to the signal input terminal of the level shifting core circuit (1); the level shifting core circuit (1) provides two control signals to the low-delay path detection circuit (2), and the low-delay path detection circuit (2) generates a high-voltage output signal at its output terminal.

[0006] Furthermore, the level shifting core circuit (1) includes: inverter inv1, inverter inv2, NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and resistor R1. The input terminal of inverter inv1 is connected to the circuit input terminal IN, and the output terminal of inverter inv1 is connected to the gate of NMOS transistor M1 and the inverter... The input terminal of inverter inv2 is connected to the inverter's input terminal, and the output terminal of inverter inv2 is connected to the gate of NMOS transistor M2. The source of PMOS transistor M5 is connected to the sources of PMOS transistors M6, M13, M9, M14, and M11, as well as the high-voltage power supply terminal VDDH. The gate of PMOS transistor M5 is connected to the drain of PMOS transistors M6, M4, M14, M8, M11, and M12, respectively. The drain of transistor M5 is connected to the source of PMOS transistor M3, the gate of PMOS transistor M6, the drain of PMOS transistor M13, the gate of PMOS transistor M9, the gate of NMOS transistor M10, and the drain of NMOS transistor M7. The gate of PMOS transistor M3 is connected to one end of resistor R1 and the gate of PMOS transistor M4. The other end of resistor R1 is connected to the substrate of NMOS transistor M7, the source of NMOS transistor M7, the gate of NMOS transistor M7, the source of NMOS transistor M10, the substrate of NMOS transistor M8, the source of NMOS transistor M8, the gate of NMOS transistor M8, and the drain of NMOS transistor M1. The source of transistor M2 is connected to the low power supply terminal VSSH in the high voltage domain. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor M1. The source of NMOS transistor M1 is connected to the source of NMOS transistor M2 and the external ground GND. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M2. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M10, the input of inverter inv3, and one input of NAND gate nand1. The drain of PMOS transistor M11 is connected to the drain of NMOS transistor M12, the input of inverter inv6, and one input of NAND gate nand2.

[0007] Furthermore, the low-delay path detection circuit (2) includes: inverters inv3, inv4, inv5, inv6, inv7, and inv8; NAND gates nand1, nand2, nand3, and nand4; wherein the output of inverter inv3 is connected to the input of inverter inv4; the output of inverter inv4 is connected to the input of inverter inv5; the output of inverter inv5 is connected to the other input of NAND gate nand1; and the output of NAND gate nand1 is connected to the gate of PMOS transistor M14. The gate of NAND gate M13 is connected to one input terminal of NAND gate NAND 3. The other input terminal of NAND gate NAND 3 is connected to the output terminal of NAND gate NAND 4 and the output terminal OUT of the circuit. The output terminal of NAND gate NAND 3 is connected to one input terminal of NAND gate NAND 4. The output terminal of inverter inv6 is connected to the input terminal of inverter inv7. The output terminal of inverter inv7 is connected to the input terminal of inverter inv8. The output terminal of inverter inv8 is connected to the other end of NAND gate NAND 2. The output terminal of NAND gate NAND 2 is connected to the gate of PMOS transistor M13 and the other input terminal of NAND gate NAND 4.

[0008] Furthermore, in the level shifting core circuit (1), the operating voltage of inverter inv1 and inverter inv2 is V. DD And below the VSSH voltage at the low power supply terminal of the high voltage domain. SSH and the voltage VDDH at the high-voltage power supply terminal. DDH V DDH -V SSH =5V, NMOS transistors M1, M2, M3, and M4 are all large-size high-voltage power transistors with a maximum drain-source withstand voltage greater than V. DDH Resistor R1 reduces the voltage V at the drain of PMOS transistor M5, i.e., node D. D Or the drain voltage V of PMOS transistor M6, i.e., node E. E Able to quickly from V DDH Reduced to V SSH PMOS transistors M13 and M14 are pull-up MOS transistors with a voltage V. D or voltage V E A diode implemented by NMOS transistors M7 and M8 with their gate, source, and substrate shorted can rapidly increase voltage V. D and V E Not lower than V SSH-0.7, thus ensuring that the voltage difference between the source and gate of PMOS transistors M5 and M6 is always less than their breakdown voltage, and the voltage difference between the source and gate of PMOS transistors M9 and M11 is always less than their breakdown voltage, ensuring the reliability of the circuit devices; when the input signal at the circuit input terminal IN changes from 0 to V DD At that time, the drain voltage V at node A of NMOS transistor M1 A Increase, voltage V D From V SSH Change to V DDH This causes the drain voltage V at node F of PMOS transistor M9 to increase. F From V DDH Change to V SSH Meanwhile, the drain voltage V at node B of NMOS transistor M2... B The gate-drain capacitance C of the large-size high-voltage power PMOS transistor M4 is reduced to the external ground GND potential. GD4 This causes the gate voltage V of the high-voltage power PMOS transistor M4, i.e., the node C voltage, to increase. C Decrease, and thus voltage V E Reduced to approximately V SSH Therefore, the drain voltage V of PMOS transistor M11, i.e., the node G voltage, is... G From V SSH Change to V DDH Similarly, when the input signal at the circuit input terminal IN changes from V... DD When the voltage becomes 0, NMOS transistor M1 is turned on, NMOS transistor M2 is turned off, and the voltage V... F From V SSH Change to V DDH Voltage V G From V DDH Change to V SSH .

[0009] Furthermore, in the low-delay path detection circuit (2), the operating power supply voltage of inverters inv3, inv4, inv5, inv6, inv7, inv8, NAND gate nand1, NAND gate nand2, NAND gate nand3, and NAND gate nand4 is the voltage V of the high-voltage domain power supply terminal VDDH. DDH and the operating ground voltage is the voltage V at the low power supply terminal of the high voltage domain, VSSH. SSH When the input signal at the circuit input terminal IN changes from 0 to the operating power supply voltage V of the inverter inv1 DD At that time, the drain voltage V at node F of PMOS transistor M9 F From V DDH Change to V SSHThe delay chain consisting of inverters inv3, inv4, and inv5 ensures that the output voltage of the NAND gate nand1 remains at V. DDH At the same time, the drain voltage V of PMOS transistor M11, i.e., the node G voltage, is... G From V SSH Change to V DDH The delay chain consisting of inverters inv6, inv7, and inv8 enables the output of the NAND gate NAND2 to generate a signal from V. DDH To V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv6, inv7, and inv8, thereby causing the voltage at the circuit output terminal OUT to change from V... SSH Change to V DDH The change is consistent with the change of the input signal at the input terminal IN; similarly, when the input signal at the circuit input terminal IN changes from V... DD When the value becomes 0, the output of the NAND gate NAND1 generates a value from V. DDH To V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv3, inv4, and inv5, and the output voltage of the NAND gate nand2 remains at V. DDH This causes the circuit output terminal OUT to change from V. DDH Change to V SSH It changes in accordance with the input signal at the input terminal IN.

[0010] Furthermore, when the input signal at the circuit input terminal IN changes from 0 to V... DD At that time, the circuit output terminal OUT also changes from V. SSH Change to V DDH V DD V is the operating power supply voltage for inverter inv1. SSH For the high voltage domain low power supply terminal VSSH voltage, V DDH For the high-voltage domain power supply terminal VDDH voltage, the delay from the input terminal IN to the output terminal OUT during this process is composed of the delay time T1 of inverter inv1, the delay time T2 of inverter inv2, the delay time T3 from the gate of NMOS transistor M2 to node E, the delay time T4 from node E to the output terminal of NAND gate nand2, and the delay time T5 from the output terminal of NAND gate nand2 to the circuit output terminal OUT. Among them, the delay time T3 accounts for the largest proportion. The transient enhancement resistor R1 and the gate-source capacitance and gate-drain capacitance of PMOS transistors M3 and M4 with large channel width-to-length ratio constitute a resistor-capacitor delay, which makes the node C voltage V C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the NMOS transistor M2 turning on, and the node B voltage V BThe voltage V drops rapidly and is coupled through the gate-drain capacitance of the PMOS transistor M4. C The gate-source voltage of PMOS transistor M4 is relatively low |V GS4 |=|V C -V E The current I4 is relatively large and operates in the saturation region; the diode implemented by the NMOS transistor M8 with its gate, source, and substrate shorted makes the voltage V... E The minimum value is not lower than V SSH -0.7, therefore the delay time T3 = C E (V DDH -V SSH +0.7) / I4, a large current I4 can effectively reduce the delay time T3, where C E Let be the parasitic capacitance of node E.

[0011] Furthermore, when the input signal at the circuit input terminal IN changes from V... DD When the voltage changes to 0, the circuit output terminal OUT also changes from the high voltage V. DDH Become low voltage V SSH V DD V is the operating power supply voltage for inverter inv1. SSH For the high voltage domain low power supply terminal VSSH voltage, V DDH For the high-voltage domain power supply terminal VDDH voltage, during this process, the delay from the input terminal IN to the output terminal OUT is mainly composed of the delay time T1 of the inverter inv1 and the delay time T from the gate of the NMOS transistor M1 to node D. 2b The delay time T from node D to the output of the NAND gate nand1 3b The delay time T from the output of the NAND gate nand1 to the circuit output OUT. 4b Composition, where the delay time T 2b The largest component, transient enhancement resistor R1, together with the gate-source and gate-drain capacitances of PMOS transistors M3 and M4 (which have large channel width-to-length ratios), constitutes a resistor-capacitor delay, causing the node C voltage V to... C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the NMOS transistor M1 turning on, and the node A voltage V A The voltage V drops rapidly and is coupled through the gate-drain capacitance of PMOS transistor M3. C The gate-source voltage of PMOS transistor M3 is relatively low |V GS3 |=|V C -V D The current I3 is relatively large and operates in the saturation region. The diode implemented by shorting the gate, source, and substrate of NMOS transistor M7 results in a voltage V... D The minimum value is not lower than V SSH -0.7, therefore the delay time T 2b =CD (V DDH -V SSH +0.7) / I3, a large current I3 can effectively reduce the delay time T. 2b , where C D Let be the parasitic capacitance of node D.

[0012] The advantages and beneficial effects of this invention are as follows:

[0013] This invention provides a fast level shifting circuit for power management chips, using resistor R1 to rapidly shift the voltage at the drain of PMOS transistor M5 or PMOS transistor M6 from V... DDH Reduced to V SSH To improve the transient characteristics of the circuit, shorten the voltage transition delay time, and reduce switching losses, PMOS transistors M13 and M14 are used to form pull-up MOS transistors, enabling the drain voltage of PMOS transistor M5 or M6 to rise rapidly, thus reducing switching losses. NMOS transistors M7 and M8, with their gate, source, and substrate shorted, are used to implement diodes, ensuring that the low potential of the drain voltage of PMOS transistor M5 and the drain voltage of PMOS transistor M6 is not lower than V. SSH -0.7, to ensure the reliability of circuit components, a delay chain structure is formed by inverters inv3-inv5 and inverters inv6-inv8. A down pulse signal is generated at the output of NAND gate nand1 or NAND gate nand2, which in turn generates a high voltage output signal at the circuit output OUT that is consistent with the change of the input signal at the input terminal IN, thereby realizing a high-performance fast level shift circuit. Attached Figure Description

[0014] Figure 1 This is an example of a traditional level shifting circuit schematic;

[0015] Figure 2 A schematic diagram of a fast level shifting circuit for a power management chip, according to a preferred embodiment of the present invention;

[0016] Figure 3 A simulation diagram of the characteristics of a fast level shifting circuit for a power management chip according to a preferred embodiment of the present invention when the input signal changes from 0V to 5V.

[0017] Figure 4 A simulation diagram of the characteristics of a fast level shifting circuit for a power management chip according to a preferred embodiment of the present invention when the input signal changes from 5V to 0V. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0019] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0020] In this embodiment, resistor R1 is used to allow the voltage at the drain of PMOS transistor M5 or PMOS transistor M6 to quickly change from V... DDH Reduced to V SSH To improve the transient characteristics of the circuit, shorten the voltage transition delay time, and reduce switching losses, PMOS transistors M13 and M14 are used to form pull-up MOS transistors, enabling the drain voltage of PMOS transistor M5 or M6 to rise rapidly, thus reducing switching losses. NMOS transistors M7 and M8, with their gate, source, and substrate shorted, are used to implement diodes, ensuring that the low potential of the drain voltage of PMOS transistor M5 and the drain voltage of PMOS transistor M6 is not lower than V. SSH -0.7, to ensure the reliability of circuit components, a delay chain structure is formed by inverters inv3-inv5 and inverters inv6-inv8. A down pulse signal is generated at the output of NAND gate nand1 or NAND gate nand2, which in turn generates a high voltage output signal at the circuit output OUT that is consistent with the change of the input signal at the input terminal IN, thereby realizing a high-performance fast level shift circuit.

[0021] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0022] Example

[0023] A fast level shifting circuit for power management chips, such as Figure 2 As shown, it includes a level shift core circuit 1 and a low-delay path detection circuit 2;

[0024] The signal output terminal of the level shift core circuit 1 is connected to the signal input terminal of the low-delay path detection circuit 2, and the signal output terminal of the low-delay path detection circuit 2 is connected to the signal input terminal of the level shift core circuit 1. The level shift core circuit 1 provides two control signals to the low-delay path detection circuit 2, and the low-delay path detection circuit 2 generates a high-voltage output signal at its output terminal.

[0025] As a preferred technical solution, such as Figure 2As shown, the level shifting core circuit 1 includes: inverter inv1, inverter inv2, NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and resistor R1. The input terminal of inverter inv1 is connected to the circuit input terminal IN, and the output terminal of inverter inv1 is connected to the gate of NMOS transistor M1 and the inverter inv2. The input terminal of inverter inv2 is connected to the inverter, and the output terminal of inverter inv2 is connected to the gate of NMOS transistor M2. The source of PMOS transistor M5 is connected to the sources of PMOS transistors M6, M13, M9, M14, and M11, as well as the high-voltage power supply terminal VDDH. The gate of PMOS transistor M5 is connected to the drain of PMOS transistors M6, M4, M14, M8, M11, and M12, respectively. The drain of transistor 5 is connected to the source of PMOS transistor M3, the gate of PMOS transistor M6, the drain of PMOS transistor M13, the gate of PMOS transistor M9, the gate of NMOS transistor M10, and the drain of NMOS transistor M7, respectively. The gate of PMOS transistor M3 is connected to one end of resistor R1 and the gate of PMOS transistor M4, respectively. The other end of resistor R1 is connected to the substrate of NMOS transistor M7, the source of NMOS transistor M7, the gate of NMOS transistor M7, the source of NMOS transistor M10, the substrate of NMOS transistor M8, the source of NMOS transistor M8, the gate of NMOS transistor M8, and the drain of NMOS transistor M12, respectively. The source of the PMOS transistor M3 is connected to the low power supply terminal VSSH of the high voltage domain. The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M1. The source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and the external ground GND. The drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M2. The drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10, the input of the inverter inv3, and one input of the NAND gate nand1. The drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M12, the input of the inverter inv6, and one input of the NAND gate nand2.

[0026] The low-delay path detection circuit 2 includes: inverters inv3, inv4, inv5, inv6, inv7, inv8, NAND gates nand1, nand2, nand3, and nand4. The output of inverter inv3 is connected to the input of inverter inv4, the output of inverter inv4 is connected to the input of inverter inv5, the output of inverter inv5 is connected to the other input of NAND gate nand1, and the output of NAND gate nand1 is connected to the gate of PMOS transistor M14 and... One input of NAND gate NAND3 is connected to the other input of NAND gate NAND3, which is connected to the output of NAND gate NAND4 and the output of the circuit OUT. The output of NAND gate NAND3 is connected to one input of NAND gate NAND4. The output of inverter inv6 is connected to the input of inverter inv7. The output of inverter inv7 is connected to the input of inverter inv8. The output of inverter inv8 is connected to the other end of NAND gate NAND2. The output of NAND gate NAND2 is connected to the gate of PMOS transistor M13 and the other input of NAND gate NAND4.

[0027] In the level shifting core circuit 1, inverters inv1 and inv2 form a low-voltage region circuit and convert the input signal at the circuit input terminal IN into two opposite signals. Its operating voltage is V. DD And the voltage V at the low power supply terminal of the high voltage domain is lower than VSSH. SSH and the voltage V at the high-voltage power supply terminal VDDH DDH V DDH -V SSH =5V, NMOS transistors M1, M2, M3, and M4 are all large-size high-voltage power transistors with a maximum drain-source withstand voltage greater than V. DDH PMOS transistors M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14, along with resistor R1, constitute a high-voltage circuit. During circuit operation, resistor R1 allows the voltage at the drain of PMOS transistor M5 (node ​​D) or the drain of PMOS transistor M6 (node ​​E) to quickly change from V0. DDH Reduced to V SSHThis improves the transient characteristics of the circuit, shortens the voltage transition delay time, and reduces switching losses. PMOS transistors M13 and M14 are pull-up MOS transistors, enabling a rapid rise in the drain voltage (node ​​D) of PMOS transistor M5 or the drain voltage (node ​​E) of PMOS transistor M6 during operation, thus reducing switching losses. Shorting the gate, source, and substrate of NMOS transistor M7 acts as a diode, causing the drain voltage V of PMOS transistor M5 (node ​​D) to rise rapidly. D Not lower than V SSH -0.7, the diode effect achieved by shorting the gate, source, and substrate of NMOS transistor M8 results in a voltage V at the drain (node ​​E) of PMOS transistor M6. E Not lower than V SSH -0.7 ensures that the voltage difference between the source and gate of PMOS transistors M5 and M6 is always less than their breakdown voltage, and the voltage difference between the source and gate of PMOS transistors M9 and M11 is always less than their breakdown voltage, thus ensuring the reliability of the circuit devices.

[0028] When the input signal at the circuit input terminal IN changes from 0 to V DD When NMOS transistor M1 is turned off, the voltage V at the drain of NMOS transistor M1 (i.e., node A) is... A As the voltage V at the drain (node ​​D) of PMOS transistor M5 increases, D From V SSH Change to V DDH This causes the drain voltage V of PMOS transistor M9 (i.e., node F) to increase. F From V DDH Change to V SSH At the same time, NMOS transistor M2 is turned on, and the voltage V at the drain of NMOS transistor M2 (i.e., node B) is... B The gate-drain capacitance C of the large-size high-voltage power PMOS transistor M4 is reduced to the external ground GND potential. GD4 This causes the gate (i.e., node C) voltage V of the high-voltage power PMOS transistor M4 to be... C This reduces the voltage V at the drain (node ​​E) of PMOS transistor M6. E Reduced to approximately V SSH Therefore, the drain voltage V of PMOS transistor M11 (i.e., node G) is... G From V SSH Change to V DDH Similarly, when the input signal at the circuit input terminal IN changes from V... DD When the voltage becomes 0, NMOS transistor M1 is turned on, NMOS transistor M2 is turned off, and the voltage V... F From V SSH Change to V DDH Voltage V G From V DDH Change to V SSH.

[0029] In the low-delay path detection circuit 2, the power supplies of inverters inv3, inv4, inv5, inv6, inv7, inv8, NAND gates nand1, nand2, nand3, and nand4 are all connected to the high-voltage power supply terminal VDDH, and the working ground is connected to the low-voltage power supply terminal VSSH. When the input signal at the circuit input terminal IN changes from 0 to VDDH... DD At that time, the voltage V F From V DDH Change to V SSH It maintains a high voltage V at the output of the NAND gate NAND1 through a delay chain consisting of inverters inv3, inv4, and inv5. DDH At the same time, voltage V G From V SSH Change to V DDH It uses a delay chain consisting of inverters inv6, inv7, and inv8 to generate a voltage from the high voltage V at the output of the NAND gate NAND2. DDH To low voltage V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv6, inv7, and inv8, thereby causing the circuit output OUT to drop from the low voltage V. SSH Transform into high voltage V DDH The change is consistent with the change of the input signal at the input terminal IN; similarly, when the input signal at the circuit input terminal IN changes from V... DD When the voltage becomes 0, the output of the NAND gate NAND1 generates a voltage from the high voltage V. DDH To low voltage V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv3, inv4, and inv5, and the output of the NAND gate nand2 is kept at a high voltage V. DDH This causes the circuit output terminal OUT to switch from high voltage V. DDH Become low voltage V SSH It changes in accordance with the input signal at the input terminal IN.

[0030] Furthermore, when the input signal at the circuit input terminal IN changes from 0 to V... DD At that time, the circuit output terminal OUT also changes from the low voltage V. SSH Transform into high voltage V DDHIn this process, the delay from input IN to output OUT is mainly composed of the delay time T1 of inverter inv1, the delay time T2 of inverter inv2, the delay time T3 from the gate of NMOS transistor M2 to node E, the delay time T4 from node E to the output of NAND gate nand2, and the delay time T5 from the output of NAND gate nand2 to the circuit output OUT. Among them, the delay time T3 accounts for the largest proportion. The transient enhancement resistor R1 and the gate-source capacitance and gate-drain capacitance of PMOS transistors M3 and M4 with large channel width-to-length ratio constitute a resistor-capacitor delay, which causes the voltage V at node C to be reduced. C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the input signal at the circuit input terminal IN changing from 0 to V. DD When NMOS transistor M2 is turned on, the voltage V at node B... B The voltage V at node C drops rapidly and is coupled through the gate-drain capacitance of PMOS transistor M4. C The low voltage causes PMOS transistor M4 to operate in the saturation region and its source voltage V E With gate voltage V C If there is a large difference, then the current I4 of PMOS transistor M4 is

[0031]

[0032] In the formula, μ p C represents hole mobility. ox V is the gate oxide capacitance per unit area, (W / L)4 is the channel width-to-length ratio of PMOS transistor M4, and V THP This is the threshold voltage of the high-voltage power PMOS transistor. Shorting the gate, source, and substrate of the NMOS transistor M8, which acts as a diode, ensures that the low potential at node E is not lower than V. SSH -0.7, therefore the delay time T3 is approximately...

[0033]

[0034] In the formula, C E Let |V| be the parasitic capacitance of node E. From equations (1) and (2), we can obtain that the large |V| E -V C It can obtain a large current I4, thereby effectively reducing the delay time T3.

[0035] When the input signal at the circuit input terminal IN changes from V... DD When the voltage changes to 0, the circuit output terminal OUT also changes from the high voltage V. DDH Become low voltage V SSH During this process, the delay from input IN to output OUT is mainly due to the delay time T1 of inverter inv1 and the delay time T from the gate of NMOS transistor M1 to node D. 2bThe delay time T from node D to the output of the NAND gate nand1 3b The delay time T from the output of the NAND gate nand1 to the circuit output OUT. 4b Composition, where the delay time T 2b The largest component, transient enhancement resistor R1, together with the gate-source and gate-drain capacitances of PMOS transistors M3 and M4 (which have a large channel width-to-length ratio), constitutes a resistor-capacitor delay, causing the voltage V at node C to... C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the input signal at the circuit input terminal IN from V... DD When the voltage becomes 0, NMOS transistor M1 turns on, and the voltage V at node A... A The voltage V at node C drops rapidly and is coupled through the gate-drain capacitance of PMOS transistor M3. C The low voltage causes PMOS transistor M3 to operate in the saturation region and its source voltage V D With gate voltage V C If there is a large difference, then the current I3 of PMOS transistor M3 is

[0036]

[0037] In the formula, (W / L)3 is the channel width-to-length ratio of PMOS transistor M3. The diode implemented by shorting the gate, source, and substrate of NMOS transistor M7 ensures that the low potential of node D is not lower than V. SSH -0.7, therefore the delay time T 2b Approximately

[0038]

[0039] In the formula, C D Let |V| be the parasitic capacitance of node D. From equations (3) and (4), we can obtain that the large |V|... D -V C It can obtain a large current I3, thereby effectively reducing the delay time T. 2b Meanwhile, in circuit design, T3 = T 2b T4 = T 3b And T2 + T5 = T 4b The relationship causes the input signal at the IN terminal to change from 0 to V. DD And the input signal from V DD The same delay applies when it becomes 0.

[0040] Figure 3This is a simulation curve of a fast level shifting circuit for a power management chip according to the present invention, when the input signal at the input terminal IN changes from 0 to 5V. The horizontal axis represents time t, and the vertical axis represents the input / output voltage waveform. The simulation results show that when the input signal at the input terminal IN changes from 0V to 5V, the circuit output terminal OUT receives an output signal that changes from 30V to 35V, and the delay between the output signal and the input signal is 1ns.

[0041] Figure 4 This is a simulation curve of a fast level shifting circuit for a power management chip according to the present invention, when the input signal at the input terminal IN changes from 5V to 0V. The horizontal axis represents time t, and the vertical axis represents the input / output voltage waveform. The simulation results show that when the input signal at the input terminal IN changes from 5V to 0V, the circuit output terminal OUT receives an output signal that changes from 35V to 30V, and the delay between the output signal and the input signal is 1ns.

[0042] In the above embodiments of this application, a fast level shifting circuit for a power management chip includes a level shifting core circuit and a low-delay path detection circuit. In this embodiment, resistor R1 is used to allow the voltage at the drain of PMOS transistor M5 or PMOS transistor M6 to quickly change from V... DDH Reduced to V SSH To improve the transient characteristics of the circuit, shorten the voltage transition delay time, and reduce switching losses, PMOS transistors M13 and M14 are used to form pull-up MOS transistors, enabling the drain voltage of PMOS transistor M5 or M6 to rise rapidly, thus reducing switching losses. NMOS transistors M7 and M8, with their gate, source, and substrate shorted, are used to implement diodes, ensuring that the low potential of the drain voltage of PMOS transistor M5 and the drain voltage of PMOS transistor M6 is not lower than V. SSH -0.7, to ensure the reliability of circuit components, a delay chain structure is formed by inverters inv3-inv5 and inverters inv6-inv8. A down pulse signal is generated at the output of NAND gate nand1 or NAND gate nand2, which in turn generates a high voltage output signal at the circuit output OUT that is consistent with the change of the input signal at the input terminal IN, thereby realizing a high-performance fast level shift circuit.

[0043] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0044] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A fast level shifting circuit for a power management chip, characterized in that, include: The circuit comprises a level-shifting core circuit (1) and a low-delay path detection circuit (2), wherein the signal output terminal of the level-shifting core circuit (1) is connected to the signal input terminal of the low-delay path detection circuit (2), and the signal output terminal of the low-delay path detection circuit (2) is connected to the signal input terminal of the level-shifting core circuit (1); the level-shifting core circuit (1) provides two control signals to the low-delay path detection circuit (2), and the low-delay path detection circuit (2) generates a high-voltage output signal at its output terminal; The level shifting core circuit (1) includes: inverter inv1, inverter inv2, NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and resistor R1. The input terminal of inverter inv1 is connected to the circuit input terminal IN, and the output terminal of inverter inv1 is connected to the gate of NMOS transistor M1 and the inverter inv2. The input terminal of inverter M2 is connected to the inverter's output terminal, which is connected to the gate of NMOS transistor M2. The source of PMOS transistor M5 is connected to the sources of PMOS transistors M6, M13, M9, M14, and M11, as well as the high-voltage power supply terminal VDDH. The gate of PMOS transistor M5 is connected to the drain of PMOS transistors M6, M4, M14, M8, M11, and M12, respectively. The drain of PMOS transistor M3 is connected to the source of PMOS transistor M3, the gate of PMOS transistor M6, the drain of PMOS transistor M13, the gate of PMOS transistor M9, the gate of NMOS transistor M10, and the drain of NMOS transistor M7, respectively. The gate of PMOS transistor M3 is connected to one end of resistor R1 and the gate of PMOS transistor M4, respectively. The other end of resistor R1 is connected to the substrate of NMOS transistor M7, the source of NMOS transistor M7, the gate of NMOS transistor M7, the source of NMOS transistor M10, the substrate of NMOS transistor M8, the source of NMOS transistor M8, the gate of NMOS transistor M8, and the drain of NMOS transistor M12, respectively. The source and the low power supply terminal VSSH of the high voltage domain are connected. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor M1. The source of NMOS transistor M1 is connected to the source of NMOS transistor M2 and the external ground GND. The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M2. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M10, the input of inverter inv3, and one input of NAND gate nand1. The drain of PMOS transistor M11 is connected to the drain of NMOS transistor M12, the input of inverter inv6, and one input of NAND gate nand2.

2. The fast level shifting circuit for a power management chip according to claim 1, characterized in that, The low-delay path detection circuit (2) includes: inverters inv3, inv4, inv5, inv6, inv7, inv8, NAND gates nand1, nand2, nand3, and nand4. The output of inverter inv3 is connected to the input of inverter inv4, the output of inverter inv4 is connected to the input of inverter inv5, and the output of inverter inv5 is connected to the other input of NAND gate nand1. The output of NAND gate nand1 is connected to the gate of PMOS transistor M14. The circuit is connected to one input of NAND gate NAND3, the other input of NAND gate NAND3 is connected to the output of NAND gate NAND4 and the output of the circuit OUT, the output of NAND gate NAND3 is connected to one input of NAND gate NAND4, the output of inverter inv6 is connected to the input of inverter inv7, the output of inverter inv7 is connected to the input of inverter inv8, the output of inverter inv8 is connected to the other end of NAND gate NAND2, and the output of NAND gate NAND2 is connected to the gate of PMOS transistor M13 and the other input of NAND gate NAND4.

3. The fast level shifting circuit for a power management chip according to claim 1, characterized in that, In the core circuit (1) for level shifting, the operating voltage of inverters inv1 and inv2 is V. DD And below the VSSH voltage at the low power supply terminal of the high voltage domain. SSH and the voltage VDDH at the high-voltage power supply terminal. DDH V DDH -V SSH =5V, NMOS transistors M1, M2, M3, and M4 are all large-size high-voltage power transistors with a maximum drain-source withstand voltage greater than V. DDH Resistor R1 reduces the voltage V at the drain of PMOS transistor M5, i.e., node D. D Or the drain voltage V of PMOS transistor M6, i.e., node E. E Able to quickly from V DDH Reduced to V SSH PMOS transistors M13 and M14 are pull-up MOS transistors with a voltage V. D or voltage V E A diode implemented by NMOS transistors M7 and M8 with their gate, source, and substrate shorted can rapidly increase voltage V. D and V E Not lower than V SSH -0.7, thus ensuring that the voltage difference between the source and gate of PMOS transistors M5 and M6 is always less than their breakdown voltage, and the voltage difference between the source and gate of PMOS transistors M9 and M11 is always less than their breakdown voltage, ensuring the reliability of the circuit devices; when the input signal at the circuit input terminal IN changes from 0 to V DD At that time, the drain voltage V at node A of NMOS transistor M1 A Increase, voltage V D From V SSH Change to V DDH This causes the drain voltage V at node F of PMOS transistor M9 to increase. F From V DDH Change to V SSH Meanwhile, the drain voltage V at node B of NMOS transistor M2... B The gate-drain capacitance C of the large-size high-voltage power PMOS transistor M4 is reduced to the external ground GND potential. GD4 This causes the gate voltage V of the high-voltage power PMOS transistor M4, i.e., the node C voltage, to increase. C Decrease, and thus voltage V E Reduced to approximately V SSH Therefore, the drain voltage V of PMOS transistor M11, i.e., the node G voltage, is... G From V SSH Change to V DDH Similarly, when the input signal at the circuit input terminal IN changes from V... DD When the voltage becomes 0, NMOS transistor M1 is turned on, NMOS transistor M2 is turned off, and the voltage V... F From V SSH Change to V DDH Voltage V G From V DDH Change to V SSH .

4. A fast level shifting circuit for a power management chip according to claim 3, characterized in that, In the low-delay path detection circuit (2), the operating power supply voltage of inverters inv3, inv4, inv5, inv6, inv7, inv8, NAND gate nand1, NAND gate nand2, NAND gate nand3, and NAND gate nand4 is the voltage V of the high-voltage domain power supply terminal VDDH. DDH and the operating ground voltage is the voltage V at the low power supply terminal of the high voltage domain, VSSH. SSH When the input signal at the circuit input terminal IN changes from 0 to the operating power supply voltage V of the inverter inv1 DD At that time, the drain voltage V at node F of PMOS transistor M9 F From V DDH Change to V SSH The delay chain consisting of inverters inv3, inv4, and inv5 ensures that the output voltage of the NAND gate nand1 remains at V. DDH At the same time, the drain voltage V of PMOS transistor M11, i.e., the node G voltage, is... G From V SSH Change to V DDH The delay chain consisting of inverters inv6, inv7, and inv8 enables the output of the NAND gate NAND2 to generate a signal from V. DDH To V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv6, inv7, and inv8, thereby causing the voltage at the circuit output terminal OUT to change from V... SSH Change to V DDH The change is consistent with the change of the input signal at the input terminal IN; similarly, when the input signal at the circuit input terminal IN changes from V... DD When the value becomes 0, the output of the NAND gate NAND1 generates a value from V. DDH To V SSH The lower pulse signal has a pulse width equal to the delay time of the delay chain consisting of inverters inv3, inv4, and inv5, and the output voltage of the NAND gate nand2 remains at V. DDH This causes the circuit output terminal OUT to change from V. DDH Change to V SSH It changes in accordance with the input signal at the input terminal IN.

5. A fast level shifting circuit for a power management chip according to claim 3 or 4, characterized in that, When the input signal at the circuit input terminal IN changes from 0 to V DD At that time, the circuit output terminal OUT also changes from V. SSH Change to V DDH V DD V is the operating power supply voltage for inverter inv1. SSH For the high voltage domain low power supply terminal VSSH voltage, V DDH For the high-voltage domain power supply terminal VDDH voltage, the delay from the input terminal IN to the output terminal OUT during this process is composed of the delay time T1 of inverter inv1, the delay time T2 of inverter inv2, the delay time T3 from the gate of NMOS transistor M2 to node E, the delay time T4 from node E to the output terminal of NAND gate nand2, and the delay time T5 from the output terminal of NAND gate nand2 to the circuit output terminal OUT. Among them, the delay time T3 accounts for the largest proportion. The transient enhancement resistor R1 and the gate-source capacitance and gate-drain capacitance of PMOS transistors M3 and M4 with large channel width-to-length ratio constitute a resistor-capacitor delay, which makes the node C voltage V C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the NMOS transistor M2 turning on, and the node B voltage V B The voltage V drops rapidly and is coupled through the gate-drain capacitance of the PMOS transistor M4. C The gate-source voltage of PMOS transistor M4 is relatively low |V GS4 |=|V C -V E The current I4 is relatively large and operates in the saturation region; the diode implemented by the NMOS transistor M8 with its gate, source, and substrate shorted makes the voltage V... E The minimum value is not lower than V SSH -0.7, therefore the delay time T3 = C E (V DDH -V SSH +0.7) / I4, a large current I4 can effectively reduce the delay time T3, where C E Let be the parasitic capacitance of node E.

6. A fast level shifting circuit for a power management chip according to claim 5, characterized in that, When the input signal at the circuit input terminal IN changes from V... DD When the voltage changes to 0, the circuit output terminal OUT also changes from the high voltage V. DDH Become low voltage V SSH V DD V is the operating power supply voltage for inverter inv1. SSH For the high voltage domain low power supply terminal VSSH voltage, V DDH For the high-voltage domain power supply terminal VDDH voltage, during this process, the delay from the input terminal IN to the output terminal OUT is mainly composed of the delay time T1 of the inverter inv1 and the delay time T from the gate of the NMOS transistor M1 to node D. 2b The delay time T from node D to the output of the NAND gate nand1 3b The delay time T from the output of the NAND gate nand1 to the circuit output OUT. 4b Composition, where the delay time T 2b The largest component, transient enhancement resistor R1, together with the gate-source and gate-drain capacitances of PMOS transistors M3 and M4 (which have large channel width-to-length ratios), constitutes a resistor-capacitor delay, causing the node C voltage V to... C There is a certain delay time between the high voltage domain low power supply voltage VSSH and the NMOS transistor M1 turning on, and the node A voltage V A The voltage V drops rapidly and is coupled through the gate-drain capacitance of PMOS transistor M3. C The gate-source voltage of PMOS transistor M3 is relatively low |V GS3 |=|V C -V D The current I3 is relatively large and operates in the saturation region; the diode implemented by the NMOS transistor M7 with its gate, source, and substrate shorted makes the voltage V... D The minimum value is not lower than V SSH -0.7, therefore the delay time T 2b =C D (V DDH -V SSH +0.7) / I3, a large current I3 can effectively reduce the delay time T. 2b , where C D Let be the parasitic capacitance of node D.

Images