High-speed flexible sampling rate conversion method and apparatus

Abstract

The application provides a high-speed flexible sampling rate conversion method and device, which comprises the following steps: resampling preprocessing of ADC sampling data to obtain resampling data; generating parallel NCO control signals according to an external timing error signal to determine input sample point indexes and filter coefficients of a parallel FIR filter; determining target data from the resampling data according to the input sample point indexes and inputting the target data into the parallel FIR filter; setting filter coefficients of the parallel FIR filter according to the filter coefficients; and shaping the effective parallel degree of the parallel FIR filter outputting the target data after the filter coefficient setting to a fixed parallel degree through a barrel shifter and outputting. Compared with the sampling rate conversion technology, the application reduces the system cost, is suitable for optical fiber transmission and other communication systems requiring large bandwidth and high speed, and can respond to the timing recovery error signal in real time and adjust the output data sampling rate.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a high-speed, flexible sampling rate conversion method and apparatus. Background Technology

[0002] With the rise of internet technology, especially the rapid development of emerging fields such as the Internet of Things, big data, and cloud computing, the amount of data carried by communication networks has increased exponentially. Line speeds have reached 100Gbps, 400Gbps, and even higher. This, in turn, places high demands on high-speed DACs (Digital-to-Analog Converters) and ADCs (Analog-to-Digital Converters). Because the sampling clock of a high-speed ADC is not synchronized with the transmitting clock, the ADC sampling point is not optimal. Furthermore, the high-speed ADC sampling clock itself has some jitter, which also introduces sampling point deviation. The chip system or hardware circuit must track the ADC sampling rate changes in real time to ensure communication system synchronization and meet the requirements of high-capacity, high-speed transmission.

[0003] Currently, sampling rate conversion typically uses fixed M / N fractional factors or rational number sampling rate conversion techniques. However, these techniques are only suitable for systems with the same clock source and are not suitable for real-time changes in the sampling rate caused by time-varying timing during timing recovery. Alternatively, frequency synthesis techniques can be used to make the ADC reference clock track and compensate for the timing error signal generated by the system, so that the input signal meets the sampling rate requirements. However, this method requires the use of a precise clock from frequency synthesis, which increases the system cost. Summary of the Invention

[0004] To address the shortcomings of existing sampling rate conversion techniques, this invention provides a high-speed, flexible sampling rate conversion method and apparatus.

[0005] In a first aspect, the present invention provides a high-speed flexible sampling rate conversion method, the high-speed flexible sampling rate conversion method comprising:

[0006] The ADC sampled data is preprocessed by resampling to obtain resampled data;

[0007] A parallel NCO control signal is generated based on the external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter.

[0008] The target data is determined from the resampled data based on the input sample point index, and the target data is input into the parallel FIR filter;

[0009] Set the filter coefficients for each FIR filter in the parallel FIR filter based on the filter coefficients;

[0010] The effective parallelism of the parallel FIR filter, whose filter coefficients have been set, is shaped to a fixed parallelism for the target data output by a barrel shifter and then output.

[0011] Optionally, the step of resampling the ADC sampled data to obtain resampled data includes:

[0012] The ADC sampling data with input parallelism of NPIS and clock domain of clk_A is passed through a parallel FIR filter to output data with parallel downsampling number of NPDS.

[0013] Data with parallelism of NPDS is processed by cross-clock domain CDC to obtain resampled data with clock domain clk_B, where the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B.

[0014] Optionally, the step of generating a parallel NCO control signal based on an external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter includes:

[0015] The value of nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution.

[0016] The parallel accumulation of the nco_step value and the external timing error signal timing_error yields NPOS+m parallel NCO control signals nco_seq, where m≥1 and NPOS+m is the maximum number of parallelisms of the parallel FIR filter.

[0017] The integer part nco_int#i of the i-th control signal nco_seq#i among the parallel NPOS+m NCO control signals nco_seq is used as the input sample point index of the i-th FIR filter;

[0018] The filter coefficients of the i-th FIR filter are obtained by looking up the filter entry in the filter table based on the fractional part of nco_seq#i, nco_dec#i.

[0019] Optionally, the step of finding the filter coefficients of the i-th FIR filter by looking up the filter table entry based on the fractional part nco_seq#i nco_dec#i includes:

[0020] The filter table entry is searched based on (num_phs*nco_dec#i) to determine the i-th FIR filter coefficient, where num_phs is the number of interpolated phases. The filter table entry is generated based on a preset tool and has a total of num_phs*fir_taps taps.

[0021] Optionally, the step of determining the target data from the resampled data based on the input sample point index includes:

[0022] The target data corresponding to the i-th FIR filter is determined from the resampled data based on the input sample point index nco_int#i of the i-th FIR filter. The corresponding formula is:

[0023] fir_in#i=smp_in[nco_int#i+fir_taps:nco_int#i+1]

[0024] Where fir_taps is the number of tap coefficients of the i-th FIR filter, smp_in is the concatenation of the current beat resampled data and the previous beat high fir_taps resampled data, and fir_in#i is the target data corresponding to the i-th FIR filter.

[0025] Secondly, the present invention also provides a high-speed flexible sampling rate conversion device, the high-speed flexible sampling rate conversion device comprising:

[0026] The preprocessing module is used to perform resampling preprocessing on the ADC sampled data to obtain resampled data;

[0027] The first determining module is used to generate a parallel NCO control signal based on the external timing error signal in order to determine the input sample point index and filter coefficients of the parallel FIR filter.

[0028] The second determination module is used to determine the target data from the resampled data according to the input sample point index, and input the target data into the parallel FIR filter;

[0029] The setting module is used to set the filter coefficients for each FIR filter in the parallel FIR filter according to the filter coefficients.

[0030] The shaping module is used to shape the effective parallelism of the parallel FIR filter with filter coefficients set for the target data to a fixed parallelism and then output it through a barrel shifter.

[0031] Optionally, the preprocessing module is used for:

[0032] The ADC sampling data with input parallelism of NPIS and clock domain of clk_A is passed through a parallel FIR filter to output data with parallel downsampling number of NPDS.

[0033] Data with parallelism of NPDS is processed by cross-clock domain CDC to obtain resampled data with clock domain clk_B, where the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B.

[0034] Optionally, the first determining module is used for:

[0035] The value of nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution.

[0036] The parallel accumulation of the nco_step value and the external timing error signal timing_error yields NPOS+m parallel NCO control signals nco_seq, where m≥1 and NPOS+m is the maximum number of parallelisms of the parallel FIR filter.

[0037] The integer part nco_int#i of the i-th control signal nco_seq#i among the parallel NPOS+m NCO control signals nco_seq is used as the input sample point index of the i-th FIR filter;

[0038] The filter coefficients of the i-th FIR filter are obtained by looking up the filter entry in the filter table based on the fractional part of nco_seq#i, nco_dec#i.

[0039] Optionally, the first determining module is used for:

[0040] The filter table entry is searched based on (num_phs*nco_dec#i) to determine the i-th FIR filter coefficient, where num_phs is the number of interpolated phases. The filter table entry is generated based on a preset tool and has a total of num_phs*fir_taps taps.

[0041] Optionally, a second determining module is used for:

[0042] The target data corresponding to the i-th FIR filter is determined from the resampled data based on the input sample point index nco_int#i of the i-th FIR filter. The corresponding formula is:

[0043] fir_in#i=smp_in[nco_int#i+fir_taps:nco_int#i+1]

[0044] Where fir_taps is the number of tap coefficients of the i-th FIR filter, smp_in is the concatenation of the current beat resampled data and the previous beat high fir_taps resampled data, and fir_in#i is the target data corresponding to the i-th FIR filter.

[0045] In this invention, the ADC sampled data undergoes resampling preprocessing to obtain resampled data; a parallel NCO control signal is generated based on an external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter; target data is determined from the resampled data based on the input sample point index and input into the parallel FIR filter; filter coefficients are set for each FIR filter in the parallel FIR filter according to the filter coefficients; and the effective parallelism of the parallel FIR filter outputting the target data is shaped to a fixed parallelism using a barrel shifter and then output. Compared with sampling rate conversion technology, this invention features a simpler main system digital domain clock scheme, eliminating the need for complex units such as frequency synthesis, thus reducing system costs; and the use of parallel processing technology effectively meets the requirements of high-bandwidth data processing, making it suitable for applications such as fiber optic transmission that require high bandwidth and high speed communication systems; it can respond to timing recovery error signals in real time, adjusting the output data sampling rate to ensure communication system synchronization. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating the first embodiment of the high-speed flexible sampling rate conversion method of the present invention;

[0047] Figure 2 This is a schematic diagram of resampling based on parallel NPDS FIR filters;

[0048] Figure 3 A schematic diagram for determining the NCO control signal nco_seq based on the external timing error signal;

[0049] Figure 4 A schematic diagram for determining the integer and fractional parts of the NCO control signal nco_seq based on the external timing error signal;

[0050] Figure 5 This is a schematic diagram of a scenario illustrating an embodiment of the high-speed flexible sampling rate conversion method of the present invention;

[0051] Figure 6 This is a functional module diagram of an embodiment of the high-speed flexible sampling rate conversion device of the present invention.

[0052] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0053] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0054] In a first aspect, embodiments of the present invention provide a high-speed, flexible sampling rate conversion method.

[0055] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the high-speed, flexible sampling rate conversion method of the present invention. Figure 1 As shown, high-speed, flexible sampling rate conversion methods include:

[0056] Step S10: Perform resampling preprocessing on the ADC sampled data to obtain resampled data;

[0057] In this embodiment, the line input becomes ADC sampled data after being sampled by the ADC; the ADC sampled data undergoes resampling preprocessing to become resampling data capable of accommodating a higher symbol rate. Specifically, whether to perform resampling preprocessing is determined based on the frequency relationship between the source clocks clk_A and clk_B. If the frequency of clk_A equals the frequency of clk_B, resampling preprocessing is not required. Otherwise, resampling preprocessing is performed, i.e., step S10 is executed.

[0058] Further, in one embodiment, step S10 includes:

[0059] Step S101: The ADC sampling data with input parallelism of parallel input sample number NPIS and clock domain of clk_A is passed through a parallel FIR filter to output data with parallel downsampling number NPDS.

[0060] In this embodiment, the core of the resampling preprocessing is the use of a low-pass FIR filter bank (i.e., a parallel FIR filter) to avoid aliasing during resampling. The line input becomes ADC sampled data after ADC sampling. The ADC sampled data with an input parallelism of NPIS (Number of Parallel Input Samples) is passed through a low-pass FIR filter bank to output data with a parallelism of NPDS (Number of Parallel Down Samples). This data is then processed by CDC (clock domain crossing) to transform the NPDS data output by the low-pass FIR filter bank to the clk_B clock domain, thus obtaining the resampled data.

[0061] Wherein, the resampling factor = NPIS / NPDS.

[0062] The resampling formula is as follows:

[0063]

[0064] In the formula, x and y are the input and output data of the parallel FIR filter in the resampling preprocessing, L and M are the upsampling and downsampling factors, L / M is the resampling factor, and h(n) is the anti-aliasing filter, which ensures that aliasing does not occur after resampling. This indicates rounding down to the nearest integer.

[0065] To facilitate hardware implementation, NPDS number of polyphase FIR filters are used in parallel to achieve resampling and anti-aliasing. It is assumed that each FIR filter has TAPS of tap coefficients. Based on the resampling factor L / M, a pre-generated FIR filter coefficient table, coeff_lut, is generated using Matlab. The coeff_lut table is user-programmable and used to configure the FIR filter coefficients. Simultaneously, NPDS number of FIR filter input data and tap coefficient index values ​​are generated.

[0066] The formulas for calculating the input data and coefficient index of each NPDS resampled FIR filter are as follows:

[0067] smp_select[NPDS-1:0]=floor(floo r(((0:NPDS-1)*NPIS / NPDS*L+0.5) / L)

[0068] coeff_select[NPDS-1:0]=floor((0:NPDS-1)*NPIS / NPDS*L+0.5)-floor(floor((0:NPDS-1)*NPIS / NPDS*L+0.5) / L)*L

[0069] Here, `smp_select` is an array of length `NPDS` indicating the indices of the NPDS FIR filter input ADC sampled data, and `coeff_select` is the index of the FIR filter coefficient table `coeff_lut`. Since the resampling factor in the resampling preprocessing is fixed, the `NPDS` `smp_select` and `coeff_select` values ​​can be stored internally in the hardware circuitry.

[0070] Reference Figure 2 , Figure 2 This is a schematic diagram illustrating resampling based on parallel NPDS FIR filters. (See diagram below.) Figure 2 As shown, to ensure the continuity of the FIR filter input data, the ADC sampling rate data smp_in_r[NPIS-1:NPIS-TAPS] from the previous cycle is concatenated with the ADC sampling rate data smp_in[NPIS-1:0] from the current cycle and used as the input for NPDS FIR filters. Based on each smp_select value, TAPS consecutive input ADC sampling data are selected. Simultaneously, based on the coeff_select value, TAPS coefficients are selected from the filter coefficient table entry coeff_lut and fed into the parallel NPDS FIR filters to achieve resampling preprocessing.

[0071] All of the above implementations are implemented in the clk_A clock domain.

[0072] Step S102: Perform cross-clock domain CDC processing on the data with parallelism of NPDS to obtain resampled data with clock domain clk_B, wherein the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B.

[0073] In this embodiment, the output data smp_out of the FIR filter bank with NPDS parallelism in the clk_A clock domain is adjusted by CDC to resampled data with NPIS parallelism in the clk_B clock domain. The CDC processing method is a known technique in the art and will not be described in detail here.

[0074] After the ADC sampled data is preprocessed by resampling, the sampling rate is reduced, thereby saving circuit power consumption.

[0075] Step S20: Generate a parallel NCO control signal based on the external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter.

[0076] In this embodiment, the resampled data obtained after fixed-multiple resampling preprocessing is used to determine the starting position of the input resampled data of the subsequent variable-sampling parallel FIR filter, and to determine the filter coefficients, based on the parallel NCO control signal nco_seq generated by the external timing error signal.

[0077] Further, in one embodiment, step S20 includes:

[0078] Step S201: Determine the value of nco_step based on the input sampling rate, the target sampling rate, and the phase resolution;

[0079] In this embodiment, the step value nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution. Specifically:

[0080] nco_step = 2^nco_bits * input sampling rate / target sampling rate.

[0081] Where nco_bits is the fixed-point bit width of nco_step. For example, if the input sampling rate is 1.33x and the target sampling rate is 2x, then...

[0082] Step S202: The nco_step value and the external timing error signal timing_error are accumulated in parallel to obtain NPOS+m parallel NCO control signals nco_seq, where m≥1 and NPOS+m is the maximum number of parallelisms of the parallel FIR filter.

[0083] In this embodiment, the nco_step value and the external timing error signal timing_error are accumulated in parallel to obtain parallel NPOS+m nco_seq values. The i-th nco_seq value is denoted by nco_seq#i, and the logic for generating nco_seq in parallel is as follows:

[0084] nco_seq=nco_step*(0:NPOS+m-1)+base_nco_step+timing_error

[0085] Where (0:NPOS+m-1) represents 0, 1, 2, ..., NPOS+m-1. The value of base_nco_step is determined based on whether the values ​​of nco_seq[NPOS-1] and nco_seq[NPOS+m-1] in the previous valid cycle overflow. Specifically, when nco_seq[NPOS-1] does not overflow, but nco_seq[NPOS+m-1] overflows, base_nco_step = mod(nco_seq[NPOS+m-1], 1); when nco_seq[NPOS-1] overflows, base_nco_step = mod(nco_seq[NPOS-1], 1). Simultaneously, the number of effective parallel FIR filters is determined based on whether nco_seq[NPOS-1] and nco_seq[NPOS+m-1] overflow.

[0086] NPOS (Number of Parallel Output Samples) represents the target output parallelism, and NPOS+m is the maximum number of parallel FIR filters, where m>=1. The specific value is related to the input clock clk_B offset and jitter. Note that this part of the implementation operates in the clk_B clock domain, and the target sampling rate / input sampling rate = NPOS / NPIS.

[0087] Reference Figure 3 , Figure 3 This is a schematic diagram for determining the NCO control signal nco_seq based on the external timing error signal.

[0088] Step S203: Use the integer part nco_int#i of the i-th control signal nco_seq#i among the parallel NPOS+m NCO control signals nco_seq as the input sample point index of the i-th FIR filter;

[0089] Step S204: Find the filter coefficients of the i-th FIR filter by looking up the filter table entry based on the fractional part nco_seq#i nco_dec#i.

[0090] In this embodiment, refer to Figure 4 , Figure 4 This diagram illustrates how to determine the integer and fractional parts of the NCO control signal nco_seq based on an external timing error signal.

[0091] Further, in one embodiment, step S204 includes:

[0092] The filter table entry is searched based on (num_phs*nco_dec#i) to determine the i-th FIR filter coefficient, where num_phs is the number of interpolated phases. The filter table entry is generated based on a preset tool and has a total of num_phs*fir_taps taps.

[0093] In this embodiment, the filter table entry is looked up according to (num_phs*nco_dec#i) to indicate the interpolated phase of the input resampled data of the i-th FIR filter, thereby determining the coefficients of each FIR filter. Here, num_phs is the number of interpolated phases. The filter table entry needs to be generated in advance using MATLAB or other tools, and has a total of num_phs*fir_taps taps.

[0094] Step S30: Determine the target data from the resampled data based on the input sample point index, and input the target data into the parallel FIR filter;

[0095] In this embodiment, the target data corresponding to each FIR filter is determined from the resampled data according to the input sample point index of each FIR filter, and then input into the corresponding FIR filter.

[0096] Furthermore, in one embodiment, the step of determining the target data from the resampled data based on the input sample point index includes:

[0097] The target data corresponding to the i-th FIR filter is determined from the resampled data based on the input sample point index nco_int#i of the i-th FIR filter. The corresponding formula is:

[0098] fir_in#i=smp_in[nco_int#i+fir_taps:nco_int#i+1]

[0099] Where fir_taps is the number of tap coefficients of the i-th FIR filter, smp_in is the concatenation of the current beat resampled data and the previous beat high fir_taps resampled data, and fir_in#i is the target data corresponding to the i-th FIR filter.

[0100] Parallel FIR filters are polyphase architectures. Each of the (NPOS+m) parallel sub-unit FIR filters receives fir_taps of consecutive input data and fir_taps of tap coefficients, performs multiplication and accumulation processing, and completes the parallel filtering function. Each sub-unit FIR filter has only fir_taps of taps, enabling high-speed processing through simple calculations.

[0101] Step S40: Set the filter coefficients for each FIR filter in the parallel FIR filter according to the filter coefficients.

[0102] In this embodiment, the filter coefficients of each FIR filter in the parallel FIR filter can be set according to the filter coefficients of each FIR filter in the parallel FIR filter determined in step S20.

[0103] Step S50: The effective parallelism of the parallel FIR filter with set filter coefficients for the target data is shaped to a fixed parallelism using a barrel shifter and then output.

[0104] In this embodiment, after the filter coefficients of each FIR filter in the parallel FIR filter are set, the effective parallelism of the target data output is shaped to a fixed parallelism by the barrel shifter and then output, thereby obtaining the variable sampling data.

[0105] In this embodiment, the ADC sampled data is preprocessed by resampling to obtain resampled data; a parallel NCO control signal is generated based on the external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter; the target data is determined from the resampled data based on the input sample point index and input into the parallel FIR filter; the filter coefficients of each FIR filter in the parallel FIR filter are set according to the filter coefficients; and the effective parallelism of the parallel FIR filter outputting the target data for the target data is shaped to a fixed parallelism using a barrel shifter and then output. Compared with sampling rate conversion technology, this embodiment has a simpler main system digital domain clock scheme, eliminating the need for complex units such as frequency synthesis, thus reducing system costs; and the use of parallel processing technology effectively meets the requirements of high-bandwidth data processing, making it suitable for communication system applications requiring high bandwidth and high speed, such as fiber optic transmission; it can respond to timing recovery error signals in real time, adjust the output data sampling rate, and ensure the synchronization of the communication system.

[0106] Furthermore, in one embodiment, reference is made to Figure 5 , Figure 5 This is a schematic diagram illustrating a scenario of an embodiment of the high-speed, flexible sampling rate conversion method of the present invention. For example... Figure 5As shown, clk_A and clk_B are clocks from the same source. clk_A is the ADC sampling data clock, and clk_B is the clock after resampling preprocessing. The clock frequency must satisfy clk_A >= clk_B. The line data undergoes resampling preprocessing to obtain resampled data, which is then input into the FIP filter for preprocessing. Specifically:

[0107] First, the ADC sampling data with an input parallelism of NPIS (Number of Parallel Input Samples) is passed through a low-pass FIR filter bank to output data with a parallelism of NPDS (Number of Parallel Down Samples). Then, it is processed by CDC (clock domain crossing). The filter output data with a parallelism of NPDS is transformed to the clk_B clock domain to become the final resampled data.

[0108] The data after fixed-multiple resampling preprocessing needs to determine the starting position of the input sampling data of the parallel FIR filter for subsequent variable sampling and the addressing coefficients of the table entries based on the parallel NCO control signal nco_seq generated by the external timing error signal.

[0109] The FIR coefficient table is looked up based on the addressing coefficients to indicate the interpolation phase of the input sampled data for the parallel FIR filter, thereby determining the coefficients of each FIR filter in the parallel FIR filter. The core of the parallel variable sampling filter is also a polyphase architecture. After receiving fir_taps of consecutive input data and fir_taps of tap coefficients, the parallel (NPOS+m) sub-unit FIR filters perform multiplication and accumulation processing to complete the parallel filtering function. Each sub-unit FIR filter has only fir_taps of taps, achieving high-speed processing through simple calculations.

[0110] The effective parallelism of the parallel filter output is shaped to a fixed NPOS parallelism output by a barrel shifter, i.e., output variable sampling data.

[0111] Secondly, embodiments of the present invention also provide a high-speed, flexible sampling rate conversion device.

[0112] In one embodiment, reference is made to Figure 6 , Figure 6 This is a functional module diagram of an embodiment of the high-speed flexible sampling rate conversion device of the present invention. Figure 6 As shown, the high-speed flexible sampling rate conversion device includes:

[0113] Preprocessing module 10 is used to perform resampling preprocessing on ADC sampled data to obtain resampled data;

[0114] The first determining module 20 is used to generate a parallel NCO control signal based on an external timing error signal in order to determine the input sample point index and filter coefficients of the parallel FIR filter.

[0115] The second determining module 30 is used to determine the target data from the resampled data according to the input sample point index, and input the target data into the parallel FIR filter;

[0116] Setting module 40 is used to set the filter coefficients of each FIR filter in the parallel FIR filter according to the filter coefficients.

[0117] Shaping module 50 is used to shape the effective parallelism of the parallel FIR filter with filter coefficients set for the target data to a fixed parallelism and output it through a barrel shifter.

[0118] Furthermore, in one embodiment, the preprocessing module 10 is used for:

[0119] The ADC sampling data with input parallelism of NPIS and clock domain of clk_A is passed through a parallel FIR filter to output data with parallel downsampling number of NPDS.

[0120] Data with parallelism of NPDS is processed by cross-clock domain CDC to obtain resampled data with clock domain clk_B, where the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B.

[0121] Furthermore, in one embodiment, the first determining module 20 is configured to:

[0122] The value of nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution.

[0123] The parallel accumulation of the nco_step value and the external timing error signal timing_error yields NPOS+m parallel NCO control signals nco_seq, where m≥1 and NPOS+m is the maximum number of parallelisms of the parallel FIR filter.

[0124] The integer part nco_int#i of the i-th control signal nco_seq#i among the parallel NPOS+m NCO control signals nco_seq is used as the input sample point index of the i-th FIR filter;

[0125] The filter coefficients of the i-th FIR filter are obtained by looking up the filter entry in the filter table based on the fractional part of nco_seq#i, nco_dec#i.

[0126] Furthermore, in one embodiment, the first determining module 20 is configured to:

[0127] The filter table entry is searched based on (num_phs*nco_dec#i) to determine the i-th FIR filter coefficient, where num_phs is the number of interpolated phases. The filter table entry is generated based on a preset tool and has a total of num_phs*fir_taps taps.

[0128] Furthermore, in one embodiment, the second determining module 30 is used for:

[0129] The target data corresponding to the i-th FIR filter is determined from the resampled data based on the input sample point index nco_int#i of the i-th FIR filter. The corresponding formula is:

[0130] fir_in#i=smp_in[nco_int#i+fir_taps:nco_int#i+1]

[0131] Where fir_taps is the number of tap coefficients of the i-th FIR filter, smp_in is the concatenation of the current beat resampled data and the previous beat high fir_taps resampled data, and fir_in#i is the target data corresponding to the i-th FIR filter.

[0132] The functions of each module in the high-speed flexible sampling rate conversion device correspond to the steps in the embodiment of the high-speed flexible sampling rate conversion method. Their functions and implementation processes will not be described in detail here.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0134] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0135] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of the present invention.

[0136] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A high-speed, flexible sampling rate conversion method, characterized in that, The high-speed, flexible sampling rate conversion method includes: The ADC sampling data with input parallelism of NPIS and clock domain of clk_A is passed through a parallel FIR filter to output data with parallel downsampling number of NPDS. Data with parallelism of NPDS is processed by cross-clock domain CDC to obtain resampled data with clock domain clk_B, where the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B. A parallel NCO control signal is generated based on the external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter. The target data is determined from the resampled data based on the input sample point index, and the target data is input into the parallel FIR filter; Set the filter coefficients for each FIR filter in the parallel FIR filter based on the filter coefficients; The effective parallelism of the parallel FIR filter, whose filter coefficients have been set, is shaped to a fixed parallelism for the target data using a barrel shifter and then output. The step of generating a parallel NCO control signal based on an external timing error signal to determine the input sample point index and filter coefficients of the parallel FIR filter includes: The value of nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution. , Define the bit width for nco_step; The parallel accumulation of the nco_step value and the external timing error signal timing_error yields NPOS+m parallel NCO control signals nco_seq, where m≥1, NPOS+m is the maximum number of parallelisms of the parallel FIR filter, and NPOS is the target output parallelism. The i-th control signal in nco_seq from the parallel NPOS+m NCO control signals integer part This is the index of the input sample point of the i-th FIR filter; according to decimal part The filter coefficients of the i-th FIR filter are obtained by looking up the filter table entry.

2. The high-speed flexible sampling rate conversion method as described in claim 1, characterized in that, According to decimal part The steps for finding the filter coefficients of the i-th FIR filter by looking up a filter entry in the filter table include: according to and The product lookup filter entry is used to determine the i-th FIR filter coefficient, where, The number of interpolated phases is determined by the filter table entries generated based on a preset tool, and there are a total of [number missing]. *fir_taps are the number of taps, where fir_taps is the number of tap coefficients for the i-th FIR filter.

3. The high-speed flexible sampling rate conversion method as described in claim 1, characterized in that, The step of determining the target data from the resampled data based on the input sample point index includes: Based on the input sample point index of the i-th FIR filter The target data corresponding to the i-th FIR filter is determined from the resampled data using the following formula: Where fir_taps is the number of tap coefficients of the i-th FIR filter, and smp_in is the concatenation of the current beat resampled data and the high fir_taps resampled data of the previous beat. Let be the target data corresponding to the i-th FIR filter.

4. A high-speed, flexible sampling rate conversion device, characterized in that, The high-speed flexible sampling rate conversion device includes: The preprocessing module is used to output data with parallel downsampling number NPDS and parallel input sample number NPIS and clock domain clk_A through a parallel FIR filter; and to perform cross-clock domain CDC processing on the data with parallel input sample number NPDS to obtain resampled data with clock domain clk_B, wherein the clock frequency of clk_A is greater than or equal to the clock frequency of clk_B. The first determining module is used to generate a parallel NCO control signal based on the external timing error signal in order to determine the input sample point index and filter coefficients of the parallel FIR filter. The second determination module is used to determine the target data from the resampled data according to the input sample point index, and input the target data into the parallel FIR filter; The setting module is used to set the filter coefficients for each FIR filter in the parallel FIR filter according to the filter coefficients. The shaping module is used to shape the effective parallelism of the parallel FIR filter with filter coefficients set for the target data to a fixed parallelism and then output it through a barrel shifter. The first determining module is used to generate a parallel NCO control signal based on an external timing error signal, in order to determine the input sample point index and filter coefficients of the parallel FIR filter, including: The value of nco_step is determined based on the input sampling rate, the target sampling rate, and the phase resolution. , Define the bit width for nco_step; The parallel accumulation of the nco_step value and the external timing error signal timing_error yields NPOS+m parallel NCO control signals nco_seq, where m≥1, NPOS+m is the maximum number of parallelisms of the parallel FIR filter, and NPOS is the target output parallelism. The i-th control signal in nco_seq from the parallel NPOS+m NCO control signals integer part This is the index of the input sample point of the i-th FIR filter; according to decimal part The filter coefficients of the i-th FIR filter are obtained by looking up the filter table entry.

5. The high-speed flexible sampling rate conversion device as described in claim 4, characterized in that, The first determining module is used for: according to and The product lookup filter entry is used to determine the i-th FIR filter coefficient, where, The number of interpolated phases is determined by the filter table entries generated based on a preset tool, and there are a total of [number missing]. *fir_taps are the number of taps, where fir_taps is the number of tap coefficients for the i-th FIR filter.

6. The high-speed flexible sampling rate conversion device as described in claim 4, characterized in that, The second determining module is used for: Based on the input sample point index of the i-th FIR filter The target data corresponding to the i-th FIR filter is determined from the resampled data using the following formula: Where fir_taps is the number of tap coefficients of the i-th FIR filter, and smp_in is the concatenation of the current beat resampled data and the high fir_taps resampled data of the previous beat. Let be the target data corresponding to the i-th FIR filter.

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