A low-distortion PAM-4 optical emitter

Abstract

This invention discloses a low-distortion PAM-4 optical transmitter, belonging to the field of optical transmitter technology, and solves the technical problem of nonlinearity in lasers. The invention includes a bias current source, a first thermometer code encoding circuit, a second thermometer code encoding circuit, a first equalization generation and data serialization circuit, a second equalization generation and data serialization circuit, a third equalization generation and data serialization circuit, a first output driving circuit, a second output driving circuit, a third output driving circuit, and a clock duty cycle correction circuit. The thermometer code encoding circuit encodes the two pairs of half-rate LSB and MSB code streams input from the transmitter into six half-rate unary code streams. These six half-rate unary code streams are then converted into three full-rate main-tap unary code streams and three full-rate equalization tap unary code streams by the equalization generation and serialization circuits. These are then converted into current by the output driving circuits and added at the output node to form an equalized PAM-4 signal.

Description

Technical Field

[0001] This invention relates to the field of optical emitter technology, and more specifically, to a low-distortion PAM-4 optical emitter. Background Technology

[0002] Fiber optic networks, with their advantages of high capacity, low loss, and low cost, are widely used in the construction of communication facilities such as data centers, access networks, and metropolitan area networks. The optical transmitter is a crucial component of a fiber optic network; it performs voltage-to-current conversion, amplitude amplification, and pre-distortion processing on the electrical signals output from the front-end communication module, thereby driving the laser to emit a low-distortion optical signal. The nonlinear characteristics of a laser can be divided into static nonlinearity and dynamic nonlinearity. The former refers to the nonlinear relationship between the laser's input current and output optical power, while the latter refers to the change in the laser's bandwidth with variations in the bias current. When a PAM-4 signal drives the laser, the static nonlinearity causes inconsistencies in the height of the three sub-eyes of the emitted optical signal, with the upper eye having the smallest height and the lower eye the largest; this phenomenon is called amplitude distortion. As the signal rate increases, the dynamic nonlinearity of the laser further exacerbates this amplitude distortion.

[0003] Traditional optical transmitter chips obtain the PAM-4 signal by adding the least significant bit (LSB) and most significant bit (MSB) bit streams. Therefore, the upper and lower eyelid heights of the optical signal are coupled and cannot be independently adjusted, making it difficult to solve the static nonlinearity problem of the laser. Traditional equalization methods also cannot address the dynamic nonlinearity problem of the laser. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to address the above-mentioned shortcomings of the prior art. The purpose of the present invention is to provide a low-distortion PAM-4 optical transmitter.

[0005] The technical solution of this invention is: a low-distortion PAM-4 optical transmitter, including a bias current source, and further including a first thermometer code encoding circuit, a second thermometer code encoding circuit, a first equalization generation and data serialization circuit, a second equalization generation and data serialization circuit, a third equalization generation and data serialization circuit, a first output driving circuit, a second output driving circuit, a third output driving circuit, and a clock duty cycle correction circuit.

[0006] The first group of four half-rate non-return-to-zero differential signals are input into the first thermometer code encoding circuit to obtain the first group of six half-rate unary NRZ differential signals. The first group of six half-rate unary NRZ differential signals are divided into three groups and input into the first equalization generation and data serialization circuit, the second equalization generation and data serialization circuit, and the third equalization generation and data serialization circuit, respectively.

[0007] The second group of four half-rate non-return-to-zero differential signals are input into the second thermometer code encoding circuit to obtain the second group of six half-rate unary NRZ differential signals. The second group of six half-rate unary NRZ differential signals are divided into three groups and input into the first equalization generation and data serialization circuit, the second equalization generation and data serialization circuit, and the third equalization generation and data serialization circuit, respectively.

[0008] The clock duty cycle correction circuit outputs control signals to the first equalization generation and data serialization circuit, the second equalization generation and data serialization circuit, and the third equalization generation and data serialization circuit, respectively.

[0009] The first equalization generation and data serialization circuit outputs the first set of full-rate main tap and equalization tap NRZ differential signals to the first output drive circuit; the second equalization generation and data serialization circuit outputs the second set of full-rate main tap and equalization tap NRZ differential signals to the second output drive circuit; and the third equalization generation and data serialization circuit outputs the third set of full-rate main tap and equalization tap NRZ differential signals to the third output drive circuit.

[0010] The first output driving circuit outputs a first current signal, the second output driving circuit outputs a second current signal, and the third output driving circuit outputs a third current signal. The output current of the bias current source subtracts the first, second, and third current signals to obtain a fourth current signal in PAM-4 format. The fourth current signal is input to the laser to drive it to emit a PAM-4 format optical signal.

[0011] As a further improvement, the first thermometer code encoding circuit and the second thermometer code encoding circuit have the same structure. The first thermometer code encoding circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NAND gate, a second NAND gate, a first NOR gate, and a second NOR gate. The output of the first NOT gate is connected to the first input of the second NOR gate, the first input of the fifth NOT gate, and the first input of the second NAND gate, respectively. The first input of the first NOR gate is connected to the first input of the third NOT gate and the first input of the first NAND gate, respectively. The second input of the first NOR gate is connected to the second input of the first NAND gate. The output terminal is connected to the input terminal of the fourth NOT gate. The output terminal of the second NOT gate is connected to the second input terminal of the second NOR gate and the second input terminal of the second NAND gate, respectively. The output terminal of the third NOT gate is connected to the input terminal of the sixth NOT gate. The output terminal of the first NAND gate is connected to the input terminal of the seventh NOT gate. The input terminals of the first NOT gate, the first NOR gate, the second NOR gate, and the second NOT gate serve as the input terminals of the first thermometer code encoding circuit. The output terminals of the second NOR gate, the fourth NOT gate, the fifth NOT gate, the sixth NOT gate, the second NAND gate, and the seventh NOT gate serve as the output terminals of the first thermometer code encoding circuit.

[0012] Furthermore, the first equalization generation and data serialization circuit, the second equalization generation and data serialization circuit, and the third equalization generation and data serialization circuit have the same structure. The first equalization generation and data serialization circuit includes a first latch, a second latch, a third latch, a fourth latch, a first clock delay adjustment circuit, a second clock delay adjustment circuit, a third clock delay adjustment circuit, a fourth clock delay adjustment circuit, a first 2:1 serializer, and a second 2:1 serializer. The output terminals of the first latch and the second latch are connected to the input terminals of the first 2:1 serializer, and the output terminals of the third latch and the fourth latch are connected to the input terminals of the second 2:1 serializer. The second clock delay adjustment circuit... The output terminals of the first and second latches are connected to the control terminals of the second clock delay adjustment circuit. The output terminal of the second clock delay adjustment circuit is connected to the control terminal of the first 2:1 serializer through the fourth clock delay adjustment circuit. The output terminal of the first clock delay adjustment circuit is connected to the control terminals of the third and fourth latches. The output terminal of the first clock delay adjustment circuit is connected to the control terminal of the second 2:1 serializer through the third clock delay adjustment circuit. The input terminals of the first, second, third, and fourth latches serve as the input terminals of the first equalization generation and data serialization circuit. The output terminals of the first and second 2:1 serializers serve as the output terminals of the first equalization generation and data serialization circuit.

[0013] Furthermore, the first 2:1 serializer and the second 2:1 serializer have the same structure. The first 2:1 serializer includes a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. One end of the first resistor and the second resistor, as well as the sources of the third, sixth, ninth, and twelfth transistors, are connected to the power supply terminal. The other end of the first resistor serves as the first output terminal of the first 2:1 serializer and is connected to the drains of the second and fifth transistors. The source of the second transistor is connected to the drains of the first and third transistors, and the source of the fifth transistor is connected to the drains of the fourth and sixth transistors. The gate of the first transistor is connected to the gate of the third transistor and serves as the first output terminal of the first 2:1 serializer. The first input terminal of the first 2:1 serializer is connected to the gate of the sixth transistor, and serves as the second input terminal of the first 2:1 serializer. The other end of the second resistor serves as the second output terminal of the first 2:1 serializer and is connected to the drains of the eighth and eleventh transistors. The source of the eighth transistor is connected to the drains of the seventh and ninth transistors. The source of the eleventh transistor is connected to the drains of the tenth and twelfth transistors. The gate of the seventh transistor is connected to the gate of the ninth transistor and serves as the third input terminal of the first 2:1 serializer. The gate of the tenth transistor is connected to the gate of the twelfth transistor and serves as the fourth input terminal of the first 2:1 serializer. The gates of the second, fifth, eighth, and eleventh transistors serve as clock signal input terminals. The sources of the first, fourth, seventh, and tenth transistors are connected to a common ground terminal.

[0014] Furthermore, the first clock delay adjustment circuit, the second clock delay adjustment circuit, the third clock delay adjustment circuit, and the fourth clock delay adjustment circuit have the same structure. The first clock delay adjustment circuit includes a first current source, a second current source, a third current source, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. One end of the first current source and the second current source, as well as the source of the fifteenth transistor and the sixteenth transistor, are connected to the power supply terminal. The other end of the first current source is connected to the drain of the fifteenth transistor, the drain of the thirteenth transistor, and the gate of the sixteenth transistor, and serves as the first output terminal of the first clock delay adjustment circuit. The other end of the second current source is connected to the drain of the sixteenth transistor, the drain of the fourteenth transistor, and the gate of the fifteenth transistor, and serves as the second output terminal of the first clock delay adjustment circuit. One end of the third current source is connected to the source of the thirteenth transistor and the fourteenth transistor, and the other end is grounded. The gates of the thirteenth transistor and the fourteenth transistor serve as the first input terminal and the second input terminal of the first clock delay adjustment circuit, respectively.

[0015] Furthermore, the first, second, and third output drive circuits have the same structure. The first output drive circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a third resistor, a fourth resistor, four fifth resistors, a first capacitor, a second capacitor, a fourth current source, a fifth current source, a sixth current source, and a seventh current source. The drain of the seventeenth transistor is connected to the drain of the twentieth transistor and serves as the first output terminal of the first output drive circuit. The drain of the eighteenth transistor is connected to the drain of the nineteenth transistor and serves as the second output terminal of the first output drive circuit. The gate of the seventeenth transistor is connected to the gate of the eighteenth transistor through two fifth resistors, and the gate of the nineteenth transistor is connected to the gate of the twentieth transistor through two fifth resistors. The connection line between the two fifth resistors is provided with a bias voltage terminal. The source of transistor 21 is connected to the drain of transistor 21, the source of transistor 18 is connected to the drain of transistor 22, the source of transistor 19 is connected to the drain of transistor 23, the source of transistor 20 is connected to the drain of transistor 24, the source of transistor 21 is connected to one end of the third resistor, one end of the first capacitor, and one end of the fourth current source, the source of transistor 22 is connected to the other end of the third resistor, the other end of the first capacitor, and one end of the fifth current source, the source of transistor 23 is connected to one end of the fourth resistor, one end of the second capacitor, and one end of the sixth current source, and the source of transistor 24 is connected to the other end of the fourth resistor, the other end of the second capacitor, and one end of the seventh current source. The other ends of the fourth, fifth, sixth, and seventh current sources are grounded. The gates of transistors 21, 22, 23, and 24 serve as the four input terminals of the first output drive circuit.

[0016] Furthermore, the clock duty cycle correction circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, and a twelfth inverter. The first inverter is connected in series with the second, third, and fourth inverters in sequence. The ninth inverter is connected in series with the tenth, eleventh, and twelfth inverters in sequence. The output terminal of the first inverter is connected to the input terminal of the twelfth inverter, the input terminal of the seventh inverter, and the output terminal of the eighth inverter through the fifth inverter. The output terminal of the ninth inverter is connected to the input terminal of the fourth inverter, the output terminal of the seventh inverter, and the input terminal of the eighth inverter through the sixth inverter. The input terminals of the first and ninth inverters serve as the clock signal input terminals of the clock duty cycle correction circuit, and the output terminals of the fourth and twelfth inverters serve as the control signal output terminals of the clock duty cycle correction circuit.

[0017] Beneficial effects

[0018] Compared with the prior art, the advantages of this invention are as follows:

[0019] This invention decouples the relationship between the upper, middle, and lower sub-eyes of the optical signal by converting the LSB and MSB bitstreams into three unary bitstreams. This allows for independent adjustment of the height of each sub-eye, thus solving the amplitude distortion problem caused by the static nonlinear characteristics of the laser. Furthermore, by performing independent equalization processing on each unary bitstream, the bandwidth of the laser can be made nearly uniform across the four PAM4 levels, thereby mitigating the dynamic nonlinearity problem of the laser. Attached Figure Description

[0020] Figure 1 This is a graph showing the relationship between the laser's input current and output optical power.

[0021] Figure 2 This is a graph showing the input current-bandwidth relationship of the laser.

[0022] Figure 3 This is a schematic diagram of the structure of the present invention;

[0023] Figure 4 This is a circuit diagram of the thermometer code encoding circuit in this invention;

[0024] Figure 5 This is a circuit diagram of equalization generation and data serialization in this invention;

[0025] Figure 6 This is a circuit diagram of the 2:1 serializer in this invention;

[0026] Figure 7 This is a circuit diagram of the clock delay adjustment in this invention;

[0027] Figure 8 This is a diagram of the output drive circuit in this invention;

[0028] Figure 9 This is a circuit diagram for clock duty cycle correction in this invention.

[0029] Wherein: 1-Bias current source, 2-First thermometer code encoding circuit, 3-Second thermometer code encoding circuit, 4-First equalization generation and data serialization circuit, 5-Second equalization generation and data serialization circuit, 6-Third equalization generation and data serialization circuit, 7-First output drive circuit, 8-Second output drive circuit, 9-Third output drive circuit, 10-Clock duty cycle correction circuit, 11-Laser, 12-First 2:1 serializer, 13-Second 2:1 serializer. Detailed Implementation

[0030] The present invention will be further described below with reference to specific embodiments shown in the accompanying drawings.

[0031] Figure 1 The figure shows the relationship between the input current and output optical power of the laser, where I0 is the bias current of the laser, and I... B I M and I T This is the modulation current input from the optical transmitter to the laser. Due to the static nonlinear characteristics of the laser, when the three sub-eye heights of the PAM-4 current signal output by the optical transmitter are equal, i.e., I... B I M and I T When the magnitudes are equal, the corresponding output optical power H of the three is... B H M and H T The magnitudes are inconsistent and gradually decrease, indicating that the output light signal of the laser has amplitude distortion at this time.

[0032] Figure 2 The diagram shows the input current-bandwidth relationship of a laser. The laser's bandwidth varies with the magnitude of the input current; this phenomenon is called the dynamic nonlinear characteristic of the laser. Figure 2 It can be seen that in I B I M and I T Under the corresponding common-mode current, the bandwidth of the laser is not consistent, and this bandwidth variation will further aggravate the amplitude distortion problem of the output optical signal.

[0033] See Figure 3This invention discloses a low-distortion PAM-4 optical transmitter, comprising a bias current source 1, a first thermometer code encoding circuit 2, a second thermometer code encoding circuit 3, a first equalization generation and data serialization circuit 4, a second equalization generation and data serialization circuit 5, a third equalization generation and data serialization circuit 6, a first output driving circuit 7, a second output driving circuit 8, a third output driving circuit 9, and a clock duty cycle correction circuit 10. The input terminals of the first thermometer code encoding circuit 2 and the second thermometer code encoding circuit 3 are used to input LSB and MSB code streams, respectively. The output terminal of the first thermometer code encoding circuit 2 is connected to the input terminals of the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively. The output terminal of the second thermometer code encoding circuit 3 is connected to the input terminals of the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively. The output of the clock duty cycle correction circuit 10 is connected to the control terminals of the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively. The output of the first equalization generation and data serialization circuit 4 is connected to the input of the first output drive circuit 7, the output of the second equalization generation and data serialization circuit 5 is connected to the input of the second output drive circuit 8, and the output of the third equalization generation and data serialization circuit 6 is connected to the input of the third output drive circuit 9. One end of the bias current source 1 is connected to the power supply terminal and, through the sixth resistor R6, to the output terminals of the first output drive circuit 7, the second output drive circuit 8, and the third output drive circuit 9. The other end of the bias current source 1 is connected through the seventh resistor R7 to the output terminals of the first output drive circuit 7, the second output drive circuit 8, and the third output drive circuit 9, and to one end of the laser 11. One end of the laser 11 is connected to the power supply terminal through the eighth resistor R8 and the eighth current source I8, and the other end of the laser 11 is grounded.

[0034] The first group of four half-rate non-return-to-zero (NRZ) differential signals LSB1 P LSB1 N MSB1 P MSB1 N The input to the first thermometer code encoding circuit 2 yields a first group of six half-rate unary NRZ differential signals. These six signals are then divided into three groups and input to the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively. This process generates equalization signals and converts signal rates. The circuit will produce full-rate main tap and equalization tap NRZ differential signals.

[0035] The second group of four half-rate non-return-to-zero differential signals LSB2 PLSB2 N MSB2 P MSB2 N The second thermometer code encoding circuit 3 is used to obtain the second group of six half-rate univariate NRZ differential signals. The second group of six half-rate univariate NRZ differential signals is divided into three groups and input to the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively.

[0036] The clock duty cycle correction circuit 10 outputs control signals to the first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6, respectively.

[0037] The first equalization generation and data serialization circuit 4 outputs the first set of full-rate main tap and equalization tap NRZ differential signals T. P T N TE P TE N The first output drive circuit 7 and the second equalization generation and data serialization circuit 5 output the second set of full-rate main tap and equalization tap NRZ differential signals M. P M N ME P ME N The second output drive circuit 8 and the third equalization generation and data serialization circuit 6 output the third set of full-rate main tap and equalization tap NRZ differential signals B. P B N BE P BE N Provide the third output drive circuit 9.

[0038] After conversion and summation, the first output drive circuit 7 outputs the first current signal I. T The second output drive circuit 8 outputs the second current signal I. M The third output drive circuit 9 outputs the third current signal I. B The output current I of bias current source 1 D The first current signal I T Second current signal I M and the third current signal I B After subtraction, the fourth current signal I in PAM-4 format is obtained. V The fourth current signal I V The input is fed to laser 11 to drive it to emit a PAM-4 format optical signal.

[0039] See Figure 4The first thermometer code encoding circuit 2 and the second thermometer code encoding circuit 3 have the same structure. The first thermometer code encoding circuit 2 includes a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, a first NAND gate NA1, a second NAND gate NA2, a first NOR gate NO1, and a second NOR gate NO2. The output terminal of the first NOT gate N1 is connected to the first input terminal of the second NOR gate NO2, the input terminal of the fifth NOT gate N5, and the first input terminal of the second NAND gate NA2. The first input terminal of the first NOR gate NO1 is connected to the input terminal of the third NOT gate N3 and the first input terminal of the first NAND gate NA1. The second input terminal of the first NOR gate NO1 is connected to the second input terminal of the first NAND gate NA1. The output of gate 1 is connected to the input of the fourth NOT gate N4. The output of the second NOT gate N2 is connected to the second input of the second NOR gate NO2 and the second NAND gate NA2, respectively. The output of the third NOT gate N3 is connected to the input of the sixth NOT gate N6. The output of the first NAND gate NA1 is connected to the input of the seventh NOT gate N7. The inputs of the first NOT gate N1, the first NOR gate NO1, the second NOR gate NO1, and the second NOT gate N2 serve as the inputs of the first thermometer code encoding circuit 2. The outputs of the second NOR gate NO2, the fourth NOT gate N4, the fifth NOT gate N5, the sixth NOT gate N6, the second NAND gate NA2, and the seventh NOT gate N7 serve as the outputs of the first thermometer code encoding circuit 2.

[0040] Specifically, the input signal MSB at the input terminal of the first NOT gate N1 P The first input terminal of the first NOR gate NO1 receives the input signal MSB. N The second input terminal of the first NOR gate NO1 receives the LSB signal. N The input signal LSB at the input terminal of the second NOT gate N2 P The output signal T at the output terminal of the second NOR gate NO2 P The output signal T of the fourth NOT gate N4 N The output signal M is from the output terminal of the fifth NOT gate N5. P The output signal M of the sixth NOT gate N6 N The output of the second NAND gate NA2 outputs signal B. P The output of the seventh NOT gate N7 outputs signal B. N .

[0041] The input and output relationships of the thermometer code encoding circuit are shown in Table 1. When both MSB and LSB are 0, T, M, and B are all 0; when MSB is 0 and LSB is 1, B is 1, and T and M are 0; when MSB is 1 and LSB is 0, B and M are 1, and T is 0; when both MSB and LSB are 1, T, M, and B are all 1.

[0042]

[0043] Table 1

[0044] See Figure 5 The first equalization generation and data serialization circuit 4, the second equalization generation and data serialization circuit 5, and the third equalization generation and data serialization circuit 6 have the same structure. The first equalization generation and data serialization circuit 4 includes a first latch L1, a second latch L2, a third latch L3, a fourth latch L4, a first clock delay adjustment circuit CH1, a second clock delay adjustment circuit CH2, a third clock delay adjustment circuit CH3, a fourth clock delay adjustment circuit CH4, a first 2:1 serializer 12, and a second 2:1 serializer 13. The output terminals of the first latch L1 and the second latch L2 are connected to the input terminal of the first 2:1 serializer 12, and the output terminals of the third latch L3 and the fourth latch L4 are connected to the input terminal of the second 2:1 serializer 13. The second clock delay adjustment circuit CH2... The output terminals are connected to the control terminals of the first latch L1 and the second latch L2. The output terminal of the second clock delay adjustment circuit CH2 is connected to the control terminal of the first 2:1 serializer 12 through the fourth clock delay adjustment circuit CH4. The output terminal of the first clock delay adjustment circuit CH1 is connected to the control terminals of the third latch L3 and the fourth latch L4. The output terminal of the first clock delay adjustment circuit CH1 is connected to the control terminal of the second 2:1 serializer 13 through the third clock delay adjustment circuit CH3. The input terminals of the first latch L1, the second latch L2, the third latch L3, and the fourth latch L4 serve as the input terminals of the first equalization generation and data serialization circuit 4. The output terminals of the first 2:1 serializer 12 and the second 2:1 serializer 13 serve as the output terminals of the first equalization generation and data serialization circuit 4.

[0045] Specifically, the first latch L1 and the third latch L3 are respectively input to signal D1. P D1 N The second latch L2 and the fourth latch L4 are respectively input to signal D2. P D2 N The first latch L1 outputs signal D1E P D1E N The first 2:1 serializer 12 and the second latch L2 output signal D2E. P D2E NThe first 2:1 serializer 12 and the third latch L3 output signal D1M P D1M N The second 2:1 serializer 13 and the fourth latch L3 output signal D2M. P D2M N The second 2:1 serializer 13 and the first 2:1 serializer 12 output signal DE. P DE N The second 2:1 serializer 13 outputs signal DM. P DM N The clock signal CLK is input to the input terminals of the first clock delay adjustment circuit CH1 and the second clock delay adjustment circuit CH2.

[0046] Latches L1 to L4 are used to latch the input differential signal D1 P D1 N D2 P D2 N Retiming. D1 P D1 N Equalized tap signal D1E is generated by L1 retiming. P D1E N The main tap signal D1M is generated by L3 retiming. P D1M N D1M P D1M N D1E P D1E N The delay interval is determined by clock delay adjustment circuits CH1 and CH2. Since the peak frequency of the equalizer varies with the delay interval between the equalizer taps and the main tap, the equalization characteristics of the equalizer taps can be adjusted by adjusting CH1 and CH2. (D2M) P D2M N D2E P D2E N The same logic applies above. Then, D1M P D1M N D2M P D2M N The second 2:1 serial circuit 13 is interleaved in the time domain to form the full-rate main tap signal DM. P DM N Similarly, D1E P D1E N D2E P D2E N The first 2:1 serial circuit 12 is interleaved in the time domain to form a full-rate equalized tap signal DE. P DE N .

[0047] See Figure 6 The first 2:1 serializer 12 and the second 2:1 serializer 13 have the same structure. The first 2:1 serializer 12 includes a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. One end of the first resistor R1 and the second resistor R2, as well as the sources of the third transistor M3, the sixth transistor M6, the ninth transistor M9, and the twelfth transistor M12, are connected to the power supply terminal. The other end of the first resistor R1 serves as the first output terminal of the first 2:1 serializer 12, outputting a signal D. N The source of transistor M2 is connected to the drain of transistor M1 and transistor M3, and the source of transistor M5 is connected to the drain of transistor M4 and transistor M6. The gate of transistor M1 is connected to the gate of transistor M3 and serves as the first input terminal of the first 2:1 serializer 12, with input signal D1. P The gate of the fourth transistor M4 is connected to the gate of the sixth transistor M6 and serves as the second input terminal of the first 2:1 serializer 12, with input signal D2. P The other end of the second resistor R2 serves as the second output terminal of the first 2:1 serializer 12, outputting signal D. P The source of transistor M8 is connected to the drain of transistors M7 and M9, and the source of transistor M11 is connected to the drain of transistors M10 and M12. The gate of transistor M7 is connected to the gate of transistor M9 and serves as the third input terminal of the first 2:1 serializer 12, with input signal D2. N The gate of the tenth transistor M10 is connected to the gate of the twelfth transistor M12 and serves as the fourth input terminal of the first 2:1 serializer 12, with input signal D2. P The gates of the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the eleventh transistor M11 serve as clock signal input terminals, while the gate of the second transistor M2 receives the CLK input. P The gate input CLK of the fifth transistor M5 N The gate input CLK of the eighth transistor M8 P The gate input CLK of the eleventh transistor M11 N The sources of the first transistor M1, the fourth transistor M4, the seventh transistor M7, and the tenth transistor M10 are connected to a common ground terminal.

[0048] Among them, M1~M3, M4~M6, M7~M9, and M10~M12 constitute four data selection units. Taking units M1~M3 as an example, when the clock signal CLK... P When the signal is high, the cell is selected, and transistor M2 is turned on. When data signal D1... P When it is high, the output signal D N When it is low level, similarly, when D1 P When it is low, D N It is at a high level, meaning that the output signal D of the serial circuit is at this time. N D P With input signal D1 P D1 N It changes with the change. Transistor M3 is a pre-charge transistor, when D1 P When the signal is low, M3 is turned on and charges the source of M2 to suppress output node D. N Charge sharing. The operating characteristics of the other three units are the same as above. Units M1-M3 (and M7-M9) and units M4-M6 (and M10-M12) work alternately, causing the half-rate signal D1 to... P D1 N D2 P D2 N Time-domain interleaving into full-rate signal D N D P .

[0049] See Figure 7 The first clock delay adjustment circuit CH1, the second clock delay adjustment circuit CH2, the third clock delay adjustment circuit CH3, and the fourth clock delay adjustment circuit CH4 have the same structure. The first clock delay adjustment circuit CH1 includes a first current source I1, a second current source I2, a third current source I3, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16. One end of the first current source I1 and the second current source I2, as well as the source of the fifteenth transistor M15 and the sixteenth transistor M16, are connected to the power supply terminal. The other end of the first current source I1 is connected to the drain of the fifteenth transistor M15, the drain of the thirteenth transistor M13, and the gate of the sixteenth transistor M16, and serves as the first output terminal of the first clock delay adjustment circuit CH1, outputting the signal OUT. P The other end of the second current source I2 is connected to the drain of the sixteenth transistor M16, the drain of the fourteenth transistor M14, and the gate of the fifteenth transistor M15, and serves as the second output terminal of the first clock delay adjustment circuit CH1, outputting the signal OUT. NOne end of the third current source I3 is connected to the sources of the thirteenth transistor M13 and the fourteenth transistor M14, and the other end is grounded. The gates of the thirteenth transistor M13 and the fourteenth transistor M14 serve as the first and second input terminals of the first clock delay adjustment circuit CH1, respectively. The gate input signal IN of the thirteenth transistor M13 is... N The gate input signal IN of the fourteenth transistor M14 P .

[0050] Specifically, M13 and M14 form a basic differential pair, with current source I3 providing bias current to them. M15 and M16 are connected in a cross-coupled manner, and their source-drain currents are I0 and I1, respectively. M3 and I M4 Therefore, the output node OUT PB The output current is I1+I M3 -0.5*I3, OUT NB The output current is I2+I M4 -0.5*I3, since the charging and discharging time required for the high and low level switching of the output node signal is inversely proportional to the current, the delay of the output signal relative to the input signal can be adjusted by adjusting the values ​​of I1 and I2, thus realizing the function of delay adjustment.

[0051] See Figure 8 The first output drive circuit 7, the second output drive circuit 8, and the third output drive circuit 9 have the same structure. The first output drive circuit 7 includes a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a third resistor R3, a fourth resistor R4, four fifth resistors R5, a first capacitor C1, a second capacitor C2, a fourth current source I4, a fifth current source I5, a sixth current source I6, and a seventh current source I7. The drain of the seventeenth transistor M17 is connected to the drain of the twentieth transistor M20 and serves as the first output terminal of the first output drive circuit 7, outputting the signal OUT. N The drain of the eighteenth transistor M18 is connected to the drain of the nineteenth transistor M19, and serves as the second output terminal of the first output drive circuit 7, outputting the signal OUT. PThe gate of the seventeenth transistor M17 is connected to the gate of the eighteenth transistor M18 through two fifth resistors R5. The gate of the nineteenth transistor M19 is connected to the gate of the twentieth transistor M20 through two fifth resistors R5. The connection line between the two fifth resistors R5 has a bias voltage terminal, with an input bias voltage VG. The source of the seventeenth transistor M17 is connected to the drain of the twenty-first transistor M21. The source of the eighteenth transistor M18 is connected to the drain of the twenty-second transistor M22. The source of the nineteenth transistor M19 is connected to the drain of the twenty-third transistor M23. The source of the twentieth transistor M20 is connected to the drain of the twenty-fourth transistor M24. The source of the twenty-first transistor M21 is connected to one end of the third resistor R3, one end of the first capacitor C1, and one end of the fourth current source I4. The source of the twenty-second transistor M22 is connected to the other end of the third resistor R3, the other end of the first capacitor C1, and one end of the fifth current source I5. The source of the twenty-third transistor M23 is connected to one end of the fourth resistor R4, one end of the second capacitor C2, and one end of the sixth current source I6. The source of the twenty-fourth transistor M24 is connected to the other end of the fourth resistor R4, the other end of the second capacitor C2, and one end of the seventh current source I7. The other ends of the fourth current source I4, the fifth current source I5, the sixth current source I6, and the seventh current source I7 are grounded. The gates of the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, and the twenty-fourth transistor M24 serve as the four input terminals of the first output drive circuit 7. The gate of the twenty-first transistor M21 receives the input signal D. P The gate input signal D of the twenty-second transistor M22 N The gate input signal DE of the twenty-third transistor M23 P The gate input signal DE of the twenty-fourth transistor M24 N .

[0052] Specifically, M21 and M17 form a CASCODE structure, which improves the reverse isolation of the amplifier circuit and enhances the robustness of the amplifier unit, preventing the transistor from being damaged by excessive drain-source potential difference. M22 and M18 work similarly. The resistor-capacitor combination formed by the third resistor R3 and the first capacitor C1 improves the linearity of the drive unit and expands its bandwidth. The fourth current source I4 and the fifth current source I5 provide current bias for the drive unit; the transconductance of the drive unit can be adjusted by adjusting their output currents. The equalization signal drive unit formed by M23, M19, M24, M20, R4, C2, and the sixth and seventh current sources I6 and I7 works similarly. The currents of the two drive units are superimposed at the output node of the drive circuit, forming I... P and I N .

[0053] See Figure 9The clock duty cycle correction circuit 10 includes a first inverter G1, a second inverter G2, a third inverter G3, a fourth inverter G4, a fifth inverter G5, a sixth inverter G6, a seventh inverter G7, an eighth inverter G8, a ninth inverter G9, a tenth inverter G10, an eleventh inverter G11, and a twelfth inverter G12. The first inverter G1 is connected in series with the second inverter G2, the third inverter G3, and the fourth inverter G4. The ninth inverter G9 is connected in series with the tenth inverter G10, the eleventh inverter G11, and the twelfth inverter G12. The output of the first inverter G1... The output terminal is connected to the input terminal of the twelfth inverter G12, the input terminal of the seventh inverter G7, and the output terminal of the eighth inverter G8 through the fifth inverter G5. The output terminal of the ninth inverter G9 is connected to the input terminal of the fourth inverter G4, the output terminal of the seventh inverter G7, and the input terminal of the eighth inverter G8 through the sixth inverter G6. The input terminals of the first inverter G1 and the ninth inverter G9 serve as the clock signal input terminals of the clock duty cycle correction circuit 10. The output terminals of the fourth inverter G4 and the twelfth inverter G12 serve as the control signal output terminals of the clock duty cycle correction circuit 10.

[0054] Specifically, G1~G4 and G9~G12 form two inverter chains, starting from the input port IN. N or IN P To the output port OUT N or OUT P The size of the inverters increases exponentially with each stage to enhance the driving capability of the circuit. Inverters G5 to G8 serve to correct the duty cycle of the clock signal. When the high-level and low-level times of the clock signal are not equal, since the signals of the mirror nodes of the two inverter chains are inverted, inverters G5 to G8 will shape the clock signals on the two chains until the duty cycle of the input signals of inverters G4 and G12 is 50%.

[0055] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention, and these will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A low-distortion PAM-4 optical transmitter, comprising a bias current source (1), characterized in that, It also includes a first thermometer code encoding circuit (2), a second thermometer code encoding circuit (3), a first equalization generation and data serialization circuit (4), a second equalization generation and data serialization circuit (5), a third equalization generation and data serialization circuit (6), a first output driving circuit (7), a second output driving circuit (8), a third output driving circuit (9), and a clock duty cycle correction circuit (10). The first group of four half-rate non-return-to-zero differential signals are input into the first thermometer code encoding circuit (2) to obtain the first group of six half-rate unary NRZ differential signals. The first group of six half-rate unary NRZ differential signals are divided into three groups and input into the first equalization generation and data serialization circuit (4), the second equalization generation and data serialization circuit (5), and the third equalization generation and data serialization circuit (6) respectively. The second group of four half-rate non-return-to-zero differential signals are input into the second thermometer code encoding circuit (3) to obtain the second group of six half-rate univariate NRZ differential signals. The second group of six half-rate univariate NRZ differential signals are divided into three groups and input into the first equalization generation and data serialization circuit (4), the second equalization generation and data serialization circuit (5), and the third equalization generation and data serialization circuit (6) respectively. The clock duty cycle correction circuit (10) outputs control signals to the first equalization generation and data serialization circuit (4), the second equalization generation and data serialization circuit (5), and the third equalization generation and data serialization circuit (6), respectively. The first equalization generation and data serialization circuit (4) outputs the first set of full-rate main tap and equalization tap NRZ differential signals to the first output drive circuit (7), the second equalization generation and data serialization circuit (5) outputs the second set of full-rate main tap and equalization tap NRZ differential signals to the second output drive circuit (8), and the third equalization generation and data serialization circuit (6) outputs the third set of full-rate main tap and equalization tap NRZ differential signals to the third output drive circuit (9). The first output driving circuit (7) outputs a first current signal, the second output driving circuit (8) outputs a second current signal, and the third output driving circuit (9) outputs a third current signal. The output current of the bias current source (1) subtracts the first current signal, the second current signal, and the third current signal to obtain a fourth current signal in PAM-4 format. The fourth current signal is input to the laser (11) to drive it to emit a PAM-4 format optical signal.

2. The low-distortion PAM-4 optical transmitter according to claim 1, characterized in that, The first thermometer code encoding circuit (2) and the second thermometer code encoding circuit (3) have the same structure. The first thermometer code encoding circuit (2) includes a first NOT gate (N1), a second NOT gate (N2), a third NOT gate (N3), a fourth NOT gate (N4), a fifth NOT gate (N5), a sixth NOT gate (N6), a seventh NOT gate (N7), a first NAND gate (NA1), a second NAND gate (NA2), a first NOR gate (NO1), and a second NOR gate (NO2). The output of the first NOT gate (N1) is connected to the first input of the second NOR gate (NO2), the input of the fifth NOT gate (N5), and the first input of the second NAND gate (NA2). The first input of the first NOR gate (NO1) is connected to the input of the third NOT gate (N3) and the first input of the first NAND gate (NA1). The second input of the first NOR gate (NO1) is connected to the second input of the first NAND gate (NA1). The output of NO1 is connected to the input of the fourth NOT gate (N4). The output of the second NOT gate (N2) is connected to the second input of the second NOR gate (NO2) and the second input of the second NAND gate (NA2). The output of the third NOT gate (N3) is connected to the input of the sixth NOT gate (N6). The output of the first NAND gate (NA1) is connected to the input of the seventh NOT gate (N7). The inputs of the first NOT gate (N1), the first NOR gate (NO1), the second NOR gate (NO1), and the second NOT gate (N2) serve as the inputs of the first thermometer code encoding circuit (2). The outputs of the second NOR gate (NO2), the fourth NOT gate (N4), the fifth NOT gate (N5), the sixth NOT gate (N6), the second NAND gate (NA2), and the seventh NOT gate (N7) serve as the outputs of the first thermometer code encoding circuit (2).

3. A low-distortion PAM-4 optical transmitter according to claim 1, characterized in that, The first equalization generation and data serialization circuit (4), the second equalization generation and data serialization circuit (5), and the third equalization generation and data serialization circuit (6) have the same structure. The first equalization generation and data serialization circuit (4) includes a first latch (L1), a second latch (L2), a third latch (L3), a fourth latch (L4), a first clock delay adjustment circuit (CH1), a second clock delay adjustment circuit (CH2), a third clock delay adjustment circuit (CH3), a fourth clock delay adjustment circuit (CH4), a first 2:1 serializer (12), and a second 2:1 serializer (13). The output terminals of the first latch (L1) and the second latch (L2) are connected to the input terminals of the first 2:1 serializer (12), and the output terminals of the third latch (L3) and the fourth latch (L4) are connected to the input terminals of the second 2:1 serializer (13). The second clock delay adjustment circuit (CH2)... The output terminals are connected to the control terminals of the first latch (L1) and the second latch (L2). The output terminal of the second clock delay adjustment circuit (CH2) is connected to the control terminal of the first 2:1 serializer (12) through the fourth clock delay adjustment circuit (CH4). The output terminal of the first clock delay adjustment circuit (CH1) is connected to the control terminals of the third latch (L3) and the fourth latch (L4). The output terminal of the first clock delay adjustment circuit (CH1) is connected to the control terminal of the second 2:1 serializer (13) through the third clock delay adjustment circuit (CH3). The input terminals of the first latch (L1), the second latch (L2), the third latch (L3), and the fourth latch (L4) serve as the input terminals of the first equalization generation and data serialization circuit (4). The output terminals of the first 2:1 serializer (12) and the second 2:1 serializer (13) serve as the output terminals of the first equalization generation and data serialization circuit (4).

4. A low-distortion PAM-4 optical transmitter according to claim 3, characterized in that, The first 2:1 serializer (12) and the second 2:1 serializer (13) have the same structure. The first 2:1 serializer (12) includes a first resistor (R1), a second resistor (R2), a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), an eighth transistor (M8), a ninth transistor (M9), a tenth transistor (M10), an eleventh transistor (M11), and a twelfth transistor (M12). The first resistor (R1) and the second resistor (R2) are... The source of the first transistor (M1) and the third transistor (M3), the sixth transistor (M6), the ninth transistor (M9), and the twelfth transistor (M12) are connected to the power supply terminal. The other end of the first resistor (R1) serves as the first output terminal of the first 2:1 serializer (12) and is connected to the drain of the second transistor (M2) and the fifth transistor (M5). The source of the second transistor (M2) is connected to the drain of the first transistor (M1) and the third transistor (M3). The source of the fifth transistor (M5) is connected to the drain of the fourth transistor (M4) and the sixth transistor (M6). The gate of the first transistor (M1) is connected to the third transistor (M3). The gate of the fourth transistor (M4) is connected to the gate of the sixth transistor (M6) and serves as the first input terminal of the first 2:1 serializer (12). The gate of the fourth transistor (M4) is connected to the gate of the sixth transistor (M6) and serves as the second input terminal of the first 2:1 serializer (12). The other end of the second resistor (R2) serves as the second output terminal of the first 2:1 serializer (12) and is connected to the drains of the eighth transistor (M8) and the eleventh transistor (M11). The source of the eighth transistor (M8) is connected to the drains of the seventh transistor (M7) and the ninth transistor (M9). The source of the eleventh transistor (M11) is connected to the drains of the tenth transistor (M10) and the twelfth transistor (M11). 2) The drain of the seventh transistor (M7) is connected to the gate of the ninth transistor (M9) and serves as the third input terminal of the first 2:1 serializer (12). The gate of the tenth transistor (M10) is connected to the gate of the twelfth transistor (M12) and serves as the fourth input terminal of the first 2:1 serializer (12). The gates of the second transistor (M2), the fifth transistor (M5), the eighth transistor (M8), and the eleventh transistor (M11) serve as clock signal input terminals. The sources of the first transistor (M1), the fourth transistor (M4), the seventh transistor (M7), and the tenth transistor (M10) are connected to the common ground terminal.

5. A low-distortion PAM-4 optical transmitter according to claim 3, characterized in that, The first clock delay adjustment circuit (CH1), the second clock delay adjustment circuit (CH2), the third clock delay adjustment circuit (CH3), and the fourth clock delay adjustment circuit (CH4) have the same structure. The first clock delay adjustment circuit (CH1) includes a first current source (I1), a second current source (I2), a third current source (I3), a thirteenth transistor (M13), a fourteenth transistor (M14), a fifteenth transistor (M15), and a sixteenth transistor (M16). One end of the first current source (I1) and the second current source (I2), as well as the source of the fifteenth transistor (M15) and the sixteenth transistor (M16), are connected to the power supply terminal. The other end of the first current source (I1) is connected to the fifteenth transistor (M15). The gate, drain of the thirteenth transistor (M13), and gate of the sixteenth transistor (M16) are connected to each other and serve as the first output terminal of the first clock delay adjustment circuit (CH1). The other end of the second current source (I2) is connected to the drain of the sixteenth transistor (M16), the drain of the fourteenth transistor (M14), and the gate of the fifteenth transistor (M15) and serves as the second output terminal of the first clock delay adjustment circuit (CH1). One end of the third current source (I3) is connected to the source of the thirteenth transistor (M13) and the fourteenth transistor (M14), and the other end is grounded. The gates of the thirteenth transistor (M13) and the fourteenth transistor (M14) serve as the first input terminal and the second input terminal of the first clock delay adjustment circuit (CH1), respectively.

6. A low-distortion PAM-4 optical transmitter according to claim 1, characterized in that, The first output drive circuit (7), the second output drive circuit (8), and the third output drive circuit (9) have the same structure. The first output drive circuit (7) includes the seventeenth transistor (M17), the eighteenth transistor (M18), the nineteenth transistor (M19), the twentieth transistor (M20), the twenty-first transistor (M21), the twenty-second transistor (M22), the twenty-third transistor (M23), the twenty-fourth transistor (M24), the third resistor (R3), the fourth resistor (R4), four fifth resistors (R5), the first capacitor (C1), the second capacitor (C2), the fourth current source (I4), the fifth current source (I5), and the sixth current source (I6). The seventh current source (I7) and the drain of the seventeenth transistor (M17) are connected to the drain of the twentieth transistor (M20) and serve as the first output terminal of the first output drive circuit (7). The drain of the eighteenth transistor (M18) is connected to the drain of the nineteenth transistor (M19) and serves as the second output terminal of the first output drive circuit (7). The gate of the seventeenth transistor (M17) is connected to the gate of the eighteenth transistor (M18) through two fifth resistors (R5). The gate of the nineteenth transistor (M19) is connected to the gate of the twentieth transistor (M20) through two fifth resistors (R5). The connection line between the two fifth resistors (R5) is provided with a bias voltage terminal. The seventeenth transistor... The source of transistor M17 is connected to the drain of transistor M21 (21), the source of transistor M18 is connected to the drain of transistor M22 (22), the source of transistor M19 is connected to the drain of transistor M23 (23), the source of transistor M20 is connected to the drain of transistor M24 (24), the source of transistor M21 (21) is connected to one end of resistor R3, one end of capacitor C1, and one end of current source I4 (4), and the source of transistor M22 (22) is connected to the other end of resistor R3, the other end of capacitor C1, and one end of current source I5 (5). The source of the 23rd transistor (M23) is connected to one end of the fourth resistor (R4), one end of the second capacitor (C2), and one end of the sixth current source (I6). The source of the 24th transistor (M24) is connected to the other end of the fourth resistor (R4), the other end of the second capacitor (C2), and one end of the seventh current source (I7). The other ends of the fourth current source (I4), the fifth current source (I5), the sixth current source (I6), and the seventh current source (I7) are grounded. The gates of the 21st transistor (M21), the 22nd transistor (M22), the 23rd transistor (M23), and the 24th transistor (M24) serve as the four input terminals of the first output drive circuit (7).

7. A low-distortion PAM-4 optical transmitter according to claim 1, characterized in that, The clock duty cycle correction circuit (10) includes a first inverter (G1), a second inverter (G2), a third inverter (G3), a fourth inverter (G4), a fifth inverter (G5), a sixth inverter (G6), a seventh inverter (G7), an eighth inverter (G8), a ninth inverter (G9), a tenth inverter (G10), an eleventh inverter (G11), and a twelfth inverter (G12). The first inverter (G1) is connected in series with the second inverter (G2), the third inverter (G3), and the fourth inverter (G4). The ninth inverter (G9) is connected in series with the tenth inverter (G10), the eleventh inverter (G11), and the twelfth inverter (G12). The output of inverter (G1) is connected to the input of the twelfth inverter (G12), the input of the seventh inverter (G7), and the output of the eighth inverter (G8) through the fifth inverter (G5). The output of the ninth inverter (G9) is connected to the input of the fourth inverter (G4), the output of the seventh inverter (G7), and the input of the eighth inverter (G8) through the sixth inverter (G6). The input of the first inverter (G1) and the input of the ninth inverter (G9) serve as the clock signal input of the clock duty cycle correction circuit (10). The output of the fourth inverter (G4) and the output of the twelfth inverter (G12) serve as the control signal output of the clock duty cycle correction circuit (10).

Images