Display panel and display device

Abstract

An embodiment of the present invention discloses a display panel and a display device. The display panel includes an array substrate, the array substrate includes pixel circuits, and the multiple pixel circuits are arranged in an array in the row direction and the column direction. Each pixel circuit includes a pixel driving semiconductor portion, the pixel driving semiconductor portion includes two fixed potential nodes, the row direction and the column direction intersecting; a reference signal line, the fixed potential node is electrically connected to the reference signal line; and a pixel connection semiconductor portion, two adjacent fixed potential nodes in a first direction are electrically connected through the pixel connection semiconductor portion, and the first direction is parallel to the plane of the array substrate. Adopting the above technical solution, by setting the pixel driving semiconductor portion to include two fixed potential stages, and setting the two adjacent fixed potential nodes in the first direction to be electrically connected through the pixel connection semiconductor portion, it is beneficial to improve the performance of the pixel driving semiconductor portion, thereby improving the display effect of the display panel.

Description

[0001] This application is a divisional application with the application date of June 30, 2021, application number 202110736811.8, and the name of the invention being "A display panel and display device". Technical Field

[0002] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) is one of the hot topics in the current display research field. Compared with Liquid Crystal Display (LCD), OLED display screens have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, OLED array substrates have begun to replace traditional LCD array substrates in display fields such as mobile phones, PDAs, and digital cameras.

[0004] A pixel circuit is provided in the OLED array substrate to drive the OLED light-emitting element. However, there is still room for improvement in the pixel circuit. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel and a display device. The display panel includes a pixel circuit. By improving the pixel circuit, the performance of the pixel circuit is improved, thereby improving the display performance.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including an array substrate, wherein the array substrate includes:

[0007] A pixel circuit, wherein a plurality of the pixel circuits are arranged in an array in a row direction and a column direction, each pixel circuit includes a pixel driving semiconductor portion, and the pixel driving semiconductor portion includes two fixed potential nodes, and the row direction and the column direction intersect;

[0008] a reference signal line, the fixed potential node being electrically connected to the reference signal line;

[0009] A pixel connection semiconductor portion is provided, through which two adjacent fixed potential nodes in a first direction are electrically connected, and the first direction is parallel to the plane where the array substrate is located.

[0010] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect.

[0011] The display panel provided by the present invention includes a pixel circuit, which includes a pixel driving semiconductor part. Two fixed potential nodes are set in the pixel driving semiconductor part, and the two fixed potential nodes are electrically connected to the reference signal line, which are used to reset some nodes and light-emitting elements in the pixel circuit, ensuring that the current display state of the display panel will not be affected by the previous display state, and ensuring a good display effect; furthermore, the pixel driving semiconductor part includes two fixed potential nodes, and the adjustment space for subsequent adjustment of the pixel driving semiconductor part is large, which is convenient for improving the performance of the pixel driving semiconductor part from multiple dimensions, which is beneficial to improving the performance of the pixel driving semiconductor part from multiple dimensions, and thus improving the performance of the entire pixel circuit and the display panel; at the same time, the display panel provided by an embodiment of the present invention also includes a pixel connection semiconductor part, and the two fixed potential nodes adjacent to each other in the first direction are electrically connected through the pixel connection semiconductor part, which facilitates signal transmission between the two fixed potential nodes, which is beneficial to improving the signal uniformity in the pixel driving semiconductor part and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, although the drawings described below are some specific embodiments of the present invention, for those skilled in the art, the basic concepts of the device structure, driving method and manufacturing method disclosed and suggested by the various embodiments of the present invention can be expanded and extended to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0013] Figure 1 This is a structural diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 1 is a schematic diagram of a structural layout of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 3 This is a schematic structural diagram of a pixel driving semiconductor unit provided by an embodiment of the present invention;

[0016] Figure 4 1 is a schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0017] Figure 5 yes Figure 4 A timing diagram of the scanning signal and the light-emitting control signal in the provided pixel circuit;

[0018] Figure 6This is a schematic structural diagram of a pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0019] Figure 7 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0020] Figure 8 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0021] Figure 9 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0022] Figure 10 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0023] Figure 11 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0024] Figure 12 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0025] Figure 13 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0026] Figure 14 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0027] Figure 15 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0028] Figure 16 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention;

[0029] Figure 17 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0030] Figure 18 yes Figure 17An enlarged example of area A in the middle;

[0031] Figure 19 yes Figure 17 Another enlarged example of area A in the middle;

[0032] Figure 20 yes Figure 17 Another enlarged example of area A in the middle;

[0033] Figure 21 yes Figure 17 Another enlarged example of area A in the middle;

[0034] Figure 22 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the present invention more clear, the following will refer to the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions of the present invention through implementation methods. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the basic concepts disclosed and suggested by the embodiments of the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention.

[0036] Figure 1 is a structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 1 is a schematic diagram of a structural layout of a pixel circuit provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a pixel driving semiconductor unit provided by an embodiment of the present invention, combined with Figure 1 、 Figure 2 and Figure 3 As shown, the display panel provided by the embodiment of the present invention includes an array substrate 100, the array substrate 100 includes pixel circuits 10, and the plurality of pixel circuits are arranged in an array in a row direction (the X direction shown in the figure) and a column direction (the Y direction shown in the figure). Each pixel circuit 10 includes a pixel driving semiconductor portion 11, and the pixel driving semiconductor portion 11 includes two fixed potential nodes N (N1 and N2 shown in the figure), and the row direction and the column direction intersect;

[0037] A reference signal line Vref, wherein the fixed potential node N is electrically connected to the reference signal line Vref;

[0038] The pixel is connected to the semiconductor portion, and two adjacent fixed potential nodes N in a first direction are electrically connected via the pixel connection semiconductor portion, where the first direction is parallel to the plane where the array substrate is located.

[0039] First, combine Figure 1The structural diagram of the display panel shown in FIG. 1 illustrates the basic structure of the display panel. Figure 1 As shown, the array substrate 100 provided in the embodiment of the present application includes a plurality of pixel circuits 10, which may be distributed in an array. For example, the plurality of pixel circuits 10 may be distributed in an array in the intersecting row direction X and column direction Y.

[0040] Exemplarily, the array substrate 100 may further include a driver chip IC, a first gate driver circuit VSR1, a second gate driver circuit VSR2, a power signal line PVDD, a data signal line Vdata, a reference signal line Vref, scan signal lines Scan1, Scan2, and a light emitting control signal line Emit.

[0041] The first gate drive circuit VSR1 may include a plurality of cascaded shift registers S-VSR, each of which is connected to the pixel circuit 10 via a scan signal line. The first gate drive circuit VSR1 is used to provide a scan signal to the pixel circuit 10. The driver chip IC provides a first start signal STV1 to the first gate drive circuit VSR1. Figure 1 As shown, in the plurality of cascaded shift registers S-VSR, except for the first and last shift registers S-VSR, the remaining shift registers S-VSR can provide scanning signals for two adjacent rows of pixel circuits 10. In this case, two rows of dummy pixel circuits ( Figure 1 (not shown), and are respectively connected to the scanning lines of the first and last stages of the shift register S-VSR in the shift register S-VSR, but the dummy pixel circuit is not used for display.

[0042] The second gate drive circuit VSR2 may include multiple cascaded shift registers E-VSR, each of which is connected to the pixel circuit 10 via a light-emission control signal line Emit. The second gate drive circuit VSR2 is configured to provide a light-emission control signal to the pixel circuit 10. The driver chip IC provides a second start signal STV2 to the second gate drive circuit VSR2.

[0043] In addition, a clock signal line (not shown in the figure), a high-level signal line (VGH) (not shown in the figure), and a low-level signal line (VGL) (not shown in the figure) can be connected between the first gate drive circuit VSR1 and the drive chip IC, as well as between the second gate drive circuit VSR2 and the drive chip IC. The drive chip IC provides a clock signal, a high-level signal, and a low-level signal to the first gate drive circuit VSR1 and the second gate drive circuit VSR2 to ensure that the first gate drive circuit VSR1 can output the scanning signal normally and the second gate drive circuit VSR2 can output the light-emitting control signal normally.

[0044] The first gate driving circuit VSR1 and the second gate driving circuit VSR2 may include a variety of different configurations, such as Figure 1 As shown, the array substrate 100 may include a first gate driver circuit VSR1 and a second gate driver circuit VSR2. The first gate driver circuit VSR1 and the second gate driver circuit VSR2 may be arranged on opposite sides of the array substrate 100 in the second direction Y, or may be arranged on the same side. For another example, the array substrate 100 may also include two first gate driver circuits VSR1 and two second gate driver circuits VSR2, with each end of a scan signal line electrically connected to a first gate driver circuit VSR1, and each end of a light-emission control signal line Emit electrically connected to a second gate driver circuit VSR2, to ensure good uniformity of scan signals in the scan signal lines and light-emission control signals in the light-emission control signal lines. For another example, the array substrate 100 includes two first gate driver circuits VSR1, one of which is electrically connected to pixel circuits in odd rows via scan signal lines, and the other is electrically connected to pixel circuits in even rows via scan signal lines, to ensure a simple structure of the first gate driver circuits VSR1. For another example, the array substrate 100 includes two second gate drive circuits VSR2, one of which is electrically connected to the pixel circuits of odd rows via a light-emitting control signal line, and the other is electrically connected to the pixel circuits of even rows via a light-emitting control signal line, thereby ensuring that the second gate drive circuit VSR2 has a simple structure. The embodiment of the present invention does not describe the specific configuration of the first gate drive circuit VSR1 and the second gate drive circuit VSR2. The above description of the first gate drive circuit VSR1 and the second gate drive circuit VSR2 is merely an example and is not intended to limit the present application. It is sufficient to ensure that the scan signal and the light-emitting control signal can be normally provided. For example, a gate drive circuit that can simultaneously generate the scan signal and the light-emitting control signal can also be provided.

[0045] Further, Figure 4 is a circuit structure diagram of a pixel circuit provided by an embodiment of the present invention, Figure 5 yes Figure 4 The timing diagram of the scanning signal and the light emitting control signal in the pixel circuit provided is combined with Figure 2 、 Figure 4 and Figure 5 As shown, each pixel circuit 10 may include a plurality of thin film transistors, wherein: Figure 2 and Figure 4For illustration purposes, an exemplary pixel circuit includes seven thin film transistors and one storage capacitor, i.e., a 7T1C circuit. Figure 2 、 Figure 4 and Figure 5 As shown, the working process of the pixel circuit is briefly described below. Figure 2 and Figure 4 Taking any row of pixel circuits as an example, the first scanning signal line Scan1 controls the conduction or shutoff of the first reset transistor T5 of the pixel circuit, and resets the gate potential of the driving transistor T3 when the first reset transistor T5 is turned on. The second scanning signal line Scan2 controls the conduction and shutoff of the data writing transistor T2 and the threshold compensation transistor T4 of the pixel circuit, and when the data writing transistor T2 and the threshold compensation transistor T4 are turned on, the data signal on the data signal line Vdata is written to the gate of the driving transistor T3, and the threshold voltage of the driving transistor T3 is compensated. In some optional pixel circuit designs, the scanning signal Scan n can also be multiplexed to control the conduction or shutoff of the second reset transistor T7 of the pixel circuit, and reset the anode potential of the light-emitting element when the second reset transistor T7 is turned on. In this case, there is no need to set a separate scanning signal line for the second reset transistor T7.

[0046] In other words, the first scan signal line can be understood as a scan signal line connected to the control terminal of the first reset transistor in the pixel circuit 10, and the second scan signal line can be understood as a scan signal line connected to the control terminal of the data write transistor, the control terminal of the compensation transistor, and the control terminal of the second reset transistor in the pixel circuit 10. Generally speaking, each row of pixel circuits 10 used for display is connected to at least a first scan signal line and a second scan signal line.

[0047] The power signal line PVDD is used to provide a power supply voltage to the driving transistor T3. The voltage on the power signal line PVDD can be a positive voltage. The voltage on the common power signal terminal PVEE can be a negative voltage. The reference signal line Vref is used to provide a reset voltage signal. The voltage on the reference signal line Vref can be a negative voltage.

[0048] The above embodiment is described by taking as an example that all transistors in the pixel circuit 10 are P-type transistors. In other optional embodiments, all transistors in the pixel circuit 10 may be N-type transistors, or some may be P-type transistors and some may be N-type transistors. Different enable levels may be provided for different types of transistors. The enable level is a level that can turn on the transistor. For example, for an N-type transistor, the enable level is a high level, and for a P-type transistor, the enable level is a low level.

[0049] like Figure 5As shown, the driving process of the pixel circuit 10 can include an initialization phase, a data writing phase, and a light-emitting phase. In the initialization phase, the first scanning signal line Scan1 provides a low-level signal, the first reset transistor T5 is turned on, and the gate potential of the driving transistor T3 is reset. In the data writing phase, the second scanning signal line Scan2 provides a low-level signal, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, the data signal on the data signal line Vdata is written to the gate of the driving transistor T3, and the threshold voltage of the driving transistor T3 is compensated; and the second reset transistor T7 is turned on to reset the anode potential of the light-emitting element. In the light-emitting phase, the light-emitting control signal line Emit provides a low-level signal, the light-emitting control transistors T1 and T6 are turned on, and the driving current generated by the driving transistor T3 is transmitted to the light-emitting element, causing the light-emitting element to emit light.

[0050] It should be noted that Figure 2 、 Figure 4 and Figure 5 This is only an example and is not intended to limit this application.

[0051] On the basis of the above embodiments, continue to refer to Figure 2 and Figure 3 As shown, the pixel driving semiconductor layer can be an active layer in a thin film transistor. Figure 3 The pixel driving semiconductor unit 11 in the 2-row*3-column pixel circuit 10 is shown as an example. Figure 2 and Figure 3As shown, the pixel driving semiconductor unit 11 includes two fixed potential nodes N, such as N1 and N2 shown in the figure. The two fixed potential nodes N1 and N2 can be connected to the input terminals of different thin film transistors. For example, the first node N1 is connected to the input terminal (source or drain) of the first reset transistor T5, and the second node N2 is connected to the input terminal (source or drain) of the second reset transistor T7. The two fixed potential nodes N1 and N2 are both electrically connected to the reference signal line Vref, and are used to receive the reference signal provided by the reference signal line Vref. It is used to reset the gate of the driving transistor T3 in the pixel circuit and the light-emitting element D in the display panel, ensuring that the current display state of the display panel is not affected by the previous display state, ensuring a good display effect. Furthermore, unlike the prior art where the pixel-driven semiconductor portion has only one fixed potential node, the pixel-driven semiconductor portion 11 in the embodiment of the present invention includes two fixed potential nodes N1 and N2. This allows for a larger adjustment space for adjusting the pixel-driven semiconductor portion by adjusting the two fixed potential nodes N1 and N2, facilitating multiple-dimensional performance improvements of the pixel-driven semiconductor portion, thereby improving the performance of the pixel-driven semiconductor portion and, in turn, the overall pixel circuit and display panel. Furthermore, the display panel provided by the embodiment of the present invention further includes a pixel-connecting semiconductor portion (not shown in the figure), wherein two adjacent fixed potential nodes in a first direction are electrically connected via the pixel-connecting semiconductor portion, facilitating signal transmission between the two fixed potential nodes, thereby improving signal uniformity in the pixel-driven semiconductor portion and enhancing the display effect of the display panel.

[0052] It should be noted that the embodiment of the present invention does not limit the specific direction of the first direction. The first direction can be the row direction, the column direction, or the direction with an acute angle to the row direction or the column direction. The first direction will be described in detail later based on the specific setting method of the pixel connection semiconductor part.

[0053] In summary, in the display panel provided by the embodiment of the present invention, two fixed potential nodes are set in the pixel driving semiconductor part, and the two fixed potential nodes are electrically connected to the reference signal line, which are used to reset some nodes and light-emitting elements in the pixel circuit, thereby ensuring that the current display state of the display panel will not be affected by the previous display state, and ensuring a good display effect; furthermore, the pixel driving semiconductor part includes two fixed potential nodes, and the adjustment space for subsequent adjustment of the pixel driving semiconductor part is relatively large, which is convenient for improving the performance of the pixel driving semiconductor part from multiple dimensions, and is beneficial to improving the performance of the pixel driving semiconductor part from multiple dimensions, thereby improving the performance of the entire pixel circuit and the display panel; at the same time, the display panel provided by the embodiment of the present invention also includes a pixel connection semiconductor part, and the two fixed potential nodes adjacent to each other in the first direction are electrically connected through the pixel connection semiconductor part, which facilitates signal transmission between the two fixed potential nodes, is beneficial to improving the signal uniformity in the pixel driving semiconductor part, and is beneficial to improving the display effect of the display panel.

[0054] On the basis of the above embodiments, continue to refer to Figure 2 and Figure 4 As shown, the pixel circuit 10 includes a driving transistor T3, a light-emitting element D, a first reset transistor T5 and a second reset transistor T7. The driving transistor T3 is used to control the lighting of the light-emitting element D, the first reset transistor T5 is used to control the reference signal to reset the gate potential of the driving transistor T3, and the second reset transistor T7 is used to control the reference signal to reset the anode potential of the light-emitting element D.

[0055] The array substrate 100 also includes a first scan signal line Scan1 extending along the row direction. The first scan signal line Scan1 and the pixel driving semiconductor unit 11 have two overlapping areas in the vertical direction of the plane where the array substrate 100 is located. The first scan signal line Scan1 and the pixel driving semiconductor unit 11 respectively form a first reset transistor T5 and a second reset transistor T7 through the two overlapping areas.

[0056] The two fixed potential nodes N include a first node N1 and a second node N2; one end of the first reset transistor T5 is electrically connected to the first node N1, and the other end is electrically connected to the gate of the driving transistor T3; one end of the second reset transistor T7 is electrically connected to the second node N2, and the other end is electrically connected to the anode of the light-emitting element D.

[0057] For example, Figure 2As shown, the area where the first scan signal line Scan1 overlaps with the pixel driving semiconductor unit 11 in the vertical direction of the plane where the array substrate 100 is located is the first reset transistor T5 and the second reset transistor T7. It should be noted that the first reset transistor T5 and the second reset transistor T7 are the first reset transistor T5 and the second reset transistor T7 in two adjacent pixel circuits along the column direction, that is, the first reset transistor T5 is the first reset transistor T5 in the pixel circuit of the current level, and the second reset transistor T7 is the second reset transistor T7 in the pixel circuit of the previous level. When the scan signal is transmitted on the first scan signal line Scan1, the first reset transistor T5 in the pixel circuit of the current level is used to reset the gate of the driving transistor T3 in the pixel circuit of the current level according to the received reference signal, and at the same time, the second reset transistor T7 in the pixel circuit of the previous level is used to reset the anode of the light-emitting element corresponding to the pixel circuit of the previous level according to the received reference signal.

[0058] Next, based on the above description of the pixel circuit and the pixel driving semiconductor layer, the specific configuration of the reference signal line and the pixel connection semiconductor portion will be described in detail.

[0059] As a feasible implementation method, Figure 6 This is a schematic structural diagram of a pixel driving semiconductor portion, a pixel connecting semiconductor portion and a reference signal line provided by an embodiment of the present invention, combined with Figure 2 and Figure 6 As shown, the reference signal line Vref includes a first reference signal line Vref1 and a second reference signal line Vref2 extending in the row direction and parallel to each other, and the two fixed potential nodes include a first node N1 and a second node N2; in the same pixel driving semiconductor portion 11, the first node N1 is electrically connected to the first reference signal line Vref1, and the second node N2 is electrically connected to the second reference signal line Vref2;

[0060] The pixel driving semiconductor section 11 includes a pixel connecting semiconductor section 12 , and the first node N1 and the second node N2 in the same pixel driving semiconductor section 11 are electrically connected via the pixel connecting semiconductor section 12 .

[0061] For example, as can be seen from the above description, the reference signal received by the first node N1 is used to reset the gate of the driving transistor T3, and the reference signal received by the second node N2 is used to reset the anode of the light-emitting element. Therefore, due to the different structures that need to be reset, the first node N1 and the second node N2 need to receive different reference signals. Therefore, in the embodiment of the present invention, the reference signal line Vref includes a first reference signal line Vref1 and a second reference signal line Vref2 extending in the row direction and parallel to each other, and the two fixed potential nodes include the first node N1 and the second node N2. In the same pixel driving semiconductor unit 11, the first node N1 is electrically connected to the first reference signal line Vref1, and the second node N2 is electrically connected to the second reference signal line Vref2. The first reference signal line Vref1 and the second reference signal line Vref2 can provide different reference signals to ensure independent reset of the gate of the driving transistor T3 and the anode of the light-emitting element, ensuring effective reset of the gate of the driving transistor T3 and the anode of the light-emitting element.

[0062] For further reference, Figure 2 and Figure 6 As shown, the pixel driving semiconductor portion 11 may include a pixel connecting semiconductor portion 12, that is, the pixel connecting semiconductor portion 12 is a part of the pixel driving semiconductor portion 11, specifically a part connecting the first node N1 and the second node N2 in the same pixel driving semiconductor portion 11. In this way, there is no need to add a preparation process for the pixel connecting semiconductor portion 12. The setting method of adding the pixel connecting semiconductor portion 12 is simple, and the preparation process is simple.

[0063] As another possible implementation, Figure 7 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 8 is a structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion and a reference signal line provided by an embodiment of the present invention, such as Figure 7 and Figure 8 As shown, the two fixed potential nodes N include a first node N1 and a second node N2; Figure 7 As shown, the second node N2 is electrically connected to the reference signal line Vref, and the first node N1 is electrically connected to the reference signal line Vref through the pixel connection semiconductor portion 12 and the second node N2; or Figure 8 As shown, the first node N1 is electrically connected to the reference signal line Vref, and the second node N2 is electrically connected to the reference signal line Vref via the pixel connection semiconductor portion 12 and the first node N1.

[0064] In the plurality of pixel driving semiconductor sections 11 sequentially arranged in the column direction, the second node N2 in the pixel driving semiconductor section 11 of the previous stage is electrically connected to the first node N1 in the pixel driving semiconductor section 11 of the next stage via the pixel connection semiconductor section 12 .

[0065] From the above description, it can be known that the reference signal provided by the reference signal line Vref can be a negative potential signal, which can reset both the first node N1 and the second node N2. Figure 7 and Figure 8 As shown, by setting the reference signal line Vref to include only one reference signal line Vref, the setting method of the reference signal line Vref can be kept simple.

[0066] Furthermore, the first node N1 may be directly electrically connected to the reference signal line Vref, and in this case, the second node N2 may be electrically connected to the reference signal line Vref via the pixel connection semiconductor portion 12 and the first node N1. Figure 8 The second node N2 may also be directly electrically connected to the reference signal line Vref, in which case the first node N1 may be electrically connected to the reference signal line Vref via the pixel connection semiconductor portion 12 and the second node N2, as shown. Figure 7 In this way, the first node N1 and the second node N2 are both electrically connected to the reference signal line Vref, ensuring that the gate of the driving transistor and the anode of the light-emitting element can be reset, ensuring normal display of the display panel.

[0067] For further reference, Figure 7 and Figure 8 As shown, in the multiple pixel driving semiconductor parts 11 arranged in sequence in the column direction, the second node N2 in the pixel driving semiconductor part 11 of the previous level is electrically connected to the first node N1 in the pixel driving semiconductor part 11 of the next level through the pixel connecting semiconductor part 12, so that the multiple pixel driving semiconductor parts 11 are connected in the column direction through the pixel connecting semiconductor part 12 to form a continuous semiconductor wiring. In this way, static electricity can be evenly distributed on the continuous semiconductor wiring, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor part 11 in the subsequent high-temperature process, so that the driving capability of the pixel circuit is basically consistent, achieving display uniformity, and improving the display effect.

[0068] Furthermore, the pixel connection semiconductor portion 12 and the pixel driving semiconductor portion 11 can be provided in the same layer, made of the same material, and manufactured in the same process, thereby ensuring a simple display panel structure and a simple manufacturing process.

[0069] As another possible implementation, Figure 9 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 10 is a structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion and a reference signal line provided by an embodiment of the present invention, such as Figure 9 and Figure 10 As shown, the reference signal line Vref includes a first reference signal line Vref1 and a second reference signal line Vref2 extending in the row direction and parallel to each other, and the two fixed potential nodes N include a first node N1 and a second node N2; in the same pixel driving semiconductor portion 11, the first node N1 is electrically connected to the first reference signal line Vref1, and the second node N2 is electrically connected to the second reference signal line Vref2;

[0070] Two pixel driving semiconductor sections 11 adjacent in the row direction include a first pixel driving semiconductor section 11-1 and a second pixel driving semiconductor section 11-2, and the first node N1 in the first pixel driving semiconductor section 11-1 is electrically connected to the first node N1 in the second pixel driving semiconductor section 11-2 through the pixel connecting semiconductor section 12, or the second node N2 in the first pixel driving semiconductor section 11-1 is electrically connected to the second node N2 in the second pixel driving semiconductor section 11-2 through the pixel connecting semiconductor section.

[0071] For example, as can be seen from the above description, the reference signal received by the first node N1 is used to reset the gate of the driving transistor T3, and the reference signal received by the second node N2 is used to reset the anode of the light-emitting element. Therefore, due to the different structures that need to be reset, the first node N1 and the second node N2 need to receive different reference signals. Therefore, in the embodiment of the present invention, the reference signal line Vref includes a first reference signal line Vref1 and a second reference signal line Vref2 extending in the row direction and parallel to each other, and the two fixed potential nodes include the first node N1 and the second node N2. In the same pixel driving semiconductor unit 11, the first node N1 is electrically connected to the first reference signal line Vref1, and the second node N2 is electrically connected to the second reference signal line Vref2. The first reference signal line Vref1 and the second reference signal line Vref2 can provide different reference signals to ensure independent reset of the gate of the driving transistor T3 and the anode of the light-emitting element, ensuring effective reset of the gate of the driving transistor T3 and the anode of the light-emitting element.

[0072] Further, such as Figure 9 As shown, in the two pixel driving semiconductor sections 11 arranged adjacent to each other in the row direction, the first node N1 in the first pixel driving semiconductor section 11-1 and the first node N1 in the second pixel driving semiconductor section 11-2 are electrically connected via the pixel connecting semiconductor section 12; Figure 10As shown, in the two pixel driving semiconductor parts 11 arranged adjacent to each other in the row direction, the second node N2 of the first pixel driving semiconductor part 11-1 is electrically connected to the second node N2 of the second pixel driving semiconductor part 11-2 through the pixel connecting semiconductor part, so that the multiple pixel driving semiconductor parts 11 are connected in the row direction through the pixel connecting semiconductor part 12 to form a continuous semiconductor trace, so that static electricity can be evenly distributed on the continuous semiconductor trace, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor part 11 in the subsequent high-temperature process, so that the driving capability of the pixel circuit is basically consistent, achieving display uniformity, and improving the display effect.

[0073] It should be noted that Figure 9 and Figure 10 The only difference is that the first pixel driving semiconductor unit 11-1 and the second pixel driving semiconductor unit 11-2 are determined in different ways. Figure 9 and Figure 10 It can be seen that Figure 9 and Figure 10 The only difference is Figure 9 The first pixel driving semiconductor unit 11-1 corresponds to Figure 10 The second pixel driving semiconductor unit 11-2 in Figure 9 The second pixel driving semiconductor unit 11-2 corresponds to Figure 10 The first pixel driving semiconductor unit 11-1 in FIG. Figure 9 The structure shown and Figure 10 In the structure shown, multiple pixel driving semiconductor parts 11 can be connected in the row direction through the pixel connecting semiconductor part 12 to form continuous semiconductor wiring, ensuring that the driving capabilities of the pixel circuits are basically consistent, achieving display uniformity, and improving display effects.

[0074] Furthermore, the pixel connection semiconductor portion 12 and the pixel driving semiconductor portion 11 can be provided in the same layer, made of the same material, and manufactured in the same process, thereby ensuring a simple display panel structure and a simple manufacturing process.

[0075] Based on the above embodiments, multiple pixel driving semiconductor parts 11 can be connected in the row direction through the pixel connecting semiconductor part 12 to form continuous semiconductor traces. There are many different configurations, and the following describes a concentrated and feasible configuration as an example.

[0076] As a feasible implementation method, continue to refer to Figure 9 and Figure 10As shown, the first node N1 and the second node N2 in the pixel driving semiconductor part 11 are respectively located on opposite sides of the pixel driving semiconductor part 11 in the first direction, and the first direction is parallel to the column direction or forms an acute angle with it; the patterns of the pixel driving semiconductor parts 11 in the two pixel circuits are the same.

[0077] For example, the embodiment of the present invention does not limit the first direction. The first direction may be parallel to the column direction Y or form an acute angle with the column direction Y. Figure 9 and Figure 10 The first direction is approximately parallel to the column direction Y, that is, the angle between the first direction and the column direction Y is an acute angle. Figure 9 and Figure 10 As shown, the patterns of the pixel driving semiconductor parts 11 in any two pixel circuits are the same, so that the driving capabilities of any two driving circuits are the same, ensuring good display uniformity of the display panel; at the same time, the same pattern of the pixel driving semiconductor parts 11 in any two pixel circuits can also ensure that the arrangement of the pixel driving semiconductor parts 11 is simple, and the mask structure is simple in the mask process. Therefore, in the scheme of the embodiment of the present invention, while ensuring that the gate of the driving transistor T3 and the anode of the light-emitting element are independently reset, ensuring good reset effect of the gate of the driving transistor T3 and the anode of the light-emitting element, and multiple pixel driving semiconductor parts 11 can be connected in the row direction through the pixel connecting semiconductor part 12 to form a continuous semiconductor trace, ensuring that the driving capabilities of the pixel circuits are basically consistent, and realizing display uniformity, further improving display uniformity, and ensuring that the arrangement of the pixel driving semiconductor parts 11 is simple, and the mask structure is simple in the mask process.

[0078] It should also be noted that Figure 9 and Figure 10 In the adjacent two-stage pixel driving semiconductor unit 11, the first node N1 and the second node N2 are staggered in the column direction Y. For example, the second node N2 in the previous stage pixel driving semiconductor unit 11 is located above the first node N1 in the current stage pixel driving semiconductor unit 11. This is only for Figure 9 and Figure 10The pixel connection semiconductor portion 12 is shown more simply in the figure, rather than limiting the embodiment scheme. For example, in two adjacent pixel driving semiconductor portions 11, the first node N1 and the second node N2 may also be staggered in the column direction Y. By adjusting the arrangement of the pixel connection semiconductor portion 12, it is ensured that the first node N1 in the first pixel driving semiconductor portion 11-1 and the first node N1 in the second pixel driving semiconductor portion 11-2 are electrically connected through the pixel connection semiconductor portion 12. Alternatively, in two pixel driving semiconductor portions 11 arranged adjacent to each other in the row direction, the second node N2 in the first pixel driving semiconductor portion 11-1 and the second node N2 in the second pixel driving semiconductor portion 11-2 are electrically connected through the pixel connection semiconductor portion.

[0079] As another possible implementation, Figure 11 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 12 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 13 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 14 This is a structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion and a reference signal line provided by an embodiment of the present invention, combined with Figure 11-14 As shown, the first node N1 and the second node N2 in the pixel driving semiconductor part 11 are respectively located on two opposite sides of the pixel driving semiconductor part 11 in the second direction, and the second direction is parallel to the plane where the array substrate is located, and is parallel to the column direction or forms an acute angle with the column direction; along the row direction, the patterns of the pixel driving semiconductor parts 11 in two adjacent pixel circuits arranged in sequence are different, and the patterns of the two pixel driving semiconductor parts 11 separated by one pixel driving semiconductor part 11 are the same.

[0080] For example, the embodiment of the present invention does not limit the second direction. The second direction may be parallel to the row direction X or form an acute angle with the row direction X. Figure 11-14 The angle between the second direction and the row direction X is an acute angle. Figure 11-14As shown, the first node N1 and the second node N2 in the pixel driving semiconductor portion 11 are respectively located on two opposite sides of the pixel driving semiconductor portion 11 in the second direction, so that in two adjacent levels of pixel driving semiconductor portions 11, the first node N1 in the current level of pixel driving semiconductor portion 11 and the second node N2 in the previous level of pixel driving semiconductor portion 11 will not overlap, so that the first node N1 in the current level of pixel driving semiconductor portion 11 and the second node N2 in the previous level of pixel driving semiconductor portion 11 can be arranged side by side in the row direction, so that the distance between the two adjacent levels of pixel driving semiconductor portions 11 in the column direction can be reduced, thereby ensuring that the pixel driving semiconductor portions 11 are compactly arranged, which is beneficial to increasing the number of pixel driving semiconductor portions 11 per unit area, that is, improving the resolution of the display panel and improving the display effect of the display panel. Furthermore, along the row direction, the patterns of the pixel driving semiconductor portions 11 in two adjacent pixel circuits arranged sequentially are different, while the patterns of the two pixel driving semiconductor portions 11 separated by one pixel driving semiconductor portion 11 are the same. This allows the first node N1 and / or the second node N2 in the two adjacent pixel driving semiconductor portions 11 in the row direction to be closer to each other, which helps reduce the extension length of the pixel connection semiconductor portion 12. This reduces the transmission loss of similar signals in the pixel connection semiconductor portion 12, while also helping to reduce the area of ​​multiple pixel driving semiconductor portions 11 in the display panel, thereby improving the resolution of the display panel and enhancing the display quality. Therefore, in the solution of the embodiment of the present invention, while ensuring independent reset of the gate of the driving transistor T3 and the anode of the light-emitting element, ensuring good reset effect of the gate of the driving transistor T3 and the anode of the light-emitting element, and multiple pixel driving semiconductor portions 11 can be connected in the row direction through the pixel connection semiconductor portion 12 to form a continuous semiconductor trace, ensuring that the driving capability of the pixel circuits is substantially consistent and achieving display uniformity, the resolution of the display panel and the display quality of the display panel are further improved.

[0081] Furthermore, along the row direction, the patterns of the pixel driving semiconductor portions 11 in two adjacent pixel circuits arranged in sequence are different, and the patterns of the two pixel driving semiconductor portions 11 separated by one pixel driving semiconductor portion 11 are the same, that is, in any row, the structures of the pixel driving semiconductor portions 11 at odd column positions are the same, and the structures of the pixel driving semiconductor portions 11 at even column positions are the same, such as Figure 11-14 Further, based on the above embodiment, it is also possible to Figure 11 and Figure 12 As shown, in any two rows, the structures of the pixel driving semiconductor parts 11 at odd column positions are the same, and the structures of the pixel driving semiconductor parts 11 at even column positions are the same; Figure 13 and Figure 14As shown, in two adjacent rows, the structure of the pixel-driving semiconductor portions 11 at odd-numbered columns in the first row is identical to the structure of the pixel-driving semiconductor portions 11 at even-numbered columns in the second row, and the structure of the pixel-driving semiconductor portions 11 at even-numbered columns in the first row is identical to the structure of the pixel-driving semiconductor portions 11 at odd-numbered columns in the second row. The embodiment of the present invention does not limit the specific arrangement of the pixel-driving semiconductor portions 11. It is only necessary to ensure that the patterns of the pixel-driving semiconductor portions 11 in two adjacent pixel circuits arranged sequentially along the row direction are different, and that the patterns of the two pixel-driving semiconductor portions 11 separated by one pixel-driving semiconductor portion 11 are identical. This ensures that the pixel-driving semiconductor portions 11 are arranged compactly, which is beneficial for increasing the number of pixel-driving semiconductor portions 11 per unit area, that is, improving the resolution of the display panel.

[0082] The above solution is described below by taking the first reset transistor being a single-gate transistor as an example.

[0083] On the basis of the above embodiments, continue to refer to Figure 11-14 As shown, any two adjacent pixel driving semiconductor portions 11 arranged in sequence in the row direction X include a first pixel driving semiconductor portion 11-1 and a second pixel driving semiconductor portion 111-2, the pixel driving semiconductor portion 11 located on the first side of the first pixel driving semiconductor portion 11-1 in the column direction Y is a third pixel driving semiconductor portion 11-3, and the pixel driving semiconductor portion 11 located on the first side of the second pixel driving semiconductor portion 11-2 in the column direction Y is a fourth pixel driving semiconductor portion 11-4;

[0084] The first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 and the second node in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 are arranged along the row direction X; the first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 is located between the second node in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 in the row direction X; or, the second node N2 in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 is located between the first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 in the row direction X.

[0085] For example, Figure 11-14As shown, the first node N1 and the second node N2 in the pixel driving semiconductor section 11 are respectively located on opposite sides of the pixel driving semiconductor section 11 in the second direction, and the patterns of the pixel driving semiconductor sections 11 in two adjacent pixel circuits arranged in sequence along the row direction are different, and the patterns of the two pixel driving semiconductor sections 11 separated by one pixel driving semiconductor section 11 are the same, which can ensure that the first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 and the second nodes in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 are arranged along the row direction X, that is, at the same horizontal height. In this way, the pixel driving semiconductor section 11 is compactly arranged, which is conducive to increasing the number of pixel driving semiconductor sections 11 per unit area, that is, improving the resolution of the display panel. Specifically, Figure 11 and Figure 13 The first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 is described as an example in which the first node N1 is located between the second nodes in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 in the row direction X. Figure 12 and Figure 14 The second node N2 in the third pixel driving semiconductor portion 11-3 and the fourth pixel driving semiconductor portion 11-4 is located between the first node N1 in the first pixel driving semiconductor portion 11-1 and the second pixel driving semiconductor portion 11-2 in the row direction X as an example for description.

[0086] The above embodiment uses the first reset transistor as a single-gate transistor to illustrate in detail that by reasonably setting the pixel driving semiconductor part 11, the pixel driving semiconductor part can be ensured to be compactly set, which is beneficial to increasing the number of pixel driving semiconductor parts per unit area, that is, improving the resolution of the display panel and improving the display panel.

[0087] The following description is made by taking the first reset transistor being a dual-gate transistor as an example.

[0088] Figure 15 1 is a schematic structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion, and a reference signal line provided by an embodiment of the present invention. Figure 16 This is a structural diagram of another pixel driving semiconductor portion, a pixel connecting semiconductor portion and a reference signal line provided by an embodiment of the present invention, combined with Figure 15 and Figure 16 As shown, the pixel driving semiconductor portion 11 includes a U-shaped portion, which includes a connecting portion U1 and a first branch U2 and a second branch U3 respectively connected to both ends of the connecting portion U1. The first branch U2 and the second branch U3 are arranged along the row direction X and extend along the column direction. The end of the first branch U2 away from the connecting portion U1 is a first node N1.

[0089] In the row direction X, the first branch U2 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 is located on the side of the second branch U3 away from the second node N2 in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4; or, in the row direction X, the second node N2 in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 is located on the side of the second branch U3 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 away from the first node N1 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2.

[0090] For example, Figure 15 and Figure 16 As shown, the pixel driving semiconductor portion 11 includes a U-shaped portion. In the direction perpendicular to the plane of the substrate, there are two overlapping areas between the first scanning line Scan1 and the U-shaped portion, corresponding to the channel area of ​​the dual-gate transistor, that is, the first reset transistor is a dual-gate transistor, which ensures that the leakage current of the first reset transistor is small and the gate potential of the driving transistor is stable. Furthermore, the U-shaped portion includes a connecting portion U1 and a first branch U2 and a second branch U3 respectively connected to the two ends of the connecting portion U1. The first branch U2 and the second branch U3 are arranged along the row direction X and extend along the column direction. The end of the first branch U2 away from the connecting portion U1 is the first node N1, and for the pixel driving semiconductor portion 11 at different positions, the second branch U2 and the second branch U3 are set in different ways. Specifically, as Figure 15 As shown, in the row direction X, the first branch U2 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 is located on the side of the second branch U3 away from the second node N2 in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4, that is, the N2 nodes in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 are close to each other, and the N2 nodes in the adjacent third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4 in the same row are connected through the pixel connecting semiconductor section 12, ensuring that the pixel connecting semiconductor section 12 is simply set up and the extension length of the pixel connecting semiconductor section 12 in the row direction X is short, ensuring that the signal transmission loss in the pixel connecting semiconductor section 12 is small, thereby ensuring a good display effect of the display panel. Figure 16As shown, in the row direction X, the first branch U2 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 is located on the side of the second branch U3 away from the second node N2 in the third pixel driving semiconductor section 11-3 and the fourth pixel driving semiconductor section 11-4, and the first branches U2 in the first pixel driving semiconductor section 11-1 and the second pixel driving semiconductor section 11-2 are close to each other. The first branches U2 in the adjacent first pixel driving semiconductor sections 11-1 and the second pixel driving semiconductor sections 11-2 in the same row are connected through the pixel connecting semiconductor section 12, that is, the N1 nodes in the adjacent first pixel driving semiconductor sections 11-1 and the second pixel driving semiconductor sections 11-2 in the same row are connected through the pixel connecting semiconductor section 12, so as to ensure that the pixel connecting semiconductor section 12 is set in a simple manner and the extension length of the pixel connecting semiconductor section 12 in the row direction X is short, so as to ensure that the transmission loss of the signal in the pixel connecting semiconductor section 12 is small, thereby ensuring a good display effect of the display panel.

[0091] In summary, the above embodiments illustrate various ways of setting pixel connection semiconductors. By setting the pixel connection semiconductor portion as a part of the pixel driving semiconductor portion, the pixel connection semiconductor portion is ensured to be set in a simple manner. Alternatively, by setting the pixel connection semiconductor portion, multiple pixel driving semiconductor portions are connected in the column direction or the row direction to form a continuous semiconductor trace, ensuring that static electricity can be evenly distributed on the continuous semiconductor trace, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor portion in the subsequent high-temperature process, so that the driving capability of the pixel circuit is basically consistent, achieving display uniformity, and improving the display effect. Furthermore, when multiple pixel driving semiconductor portions in the row direction form a continuous semiconductor trace through the pixel connection semiconductor portion, the pixel connection semiconductor portion is ensured to be set in a simple manner by reasonably setting the positional relationship between the first node and the second node in the pixel driving semiconductor portion; or ensuring that the multiple pixel driving semiconductor portions are compact in structure, which is conducive to increasing the number of pixel driving semiconductor portions per unit area, that is, improving the resolution of the display panel and improving the display effect of the display panel.

[0092] Based on the above embodiments, Figure 17 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 18 yes Figure 17 An enlarged example of area A is shown in the figure below. Figure 17 and Figure 18 As shown, the array substrate 100 may include a functional area FU, and pixel circuits 10 are distributed on both sides of the functional area FU along the row direction (the X direction shown in the figure) or the column direction (the Y direction shown in the figure);

[0093] The array substrate 100 further includes:

[0094] The area connection semiconductor portion 13 extends around the functional region FU; the fixed potential nodes in the pixel driving semiconductor portion 11 located on both sides of the functional region FU along the row direction or the column direction are connected to the area connection semiconductor portion 13 .

[0095] Exemplarily, the array substrate 100 has a functional area FU, and functional devices such as a camera, an earpiece, an optical fingerprint sensor, etc. can be set at the position corresponding to the functional area FU. The shape of the functional area FU can be circular, rectangular, rounded rectangular, etc., and this application does not limit this. The number of functional areas FU can be one or more, and this application does not limit this. The functional area FU can be a non-display area or a display area. When the functional area FU is a display area, it can be understood that the functional area FU also has a corresponding pixel circuit. In order to improve the transmittance of the functional area FU, the pixel circuit corresponding to the functional area FU can be set in other areas outside the functional area FU, for example, pixel circuits 10 are distributed on both sides of the functional area FU along the column direction Y.

[0096] Further, such as Figure 18 As shown, the fixed potential nodes in the pixel driving semiconductor parts 11 located on both sides of the functional area FU along the row direction or the column direction are connected to the regional connection semiconductor part 13, and the fixed potential nodes in the pixel driving semiconductor parts 11 on both sides of the functional area FU are connected to the regional connection semiconductor part 13 through the regional connection semiconductor part 13, so that the pixel driving semiconductor parts 11 located on both sides of the functional area FU in the row direction or the column direction are no longer isolated, and the pixel driving semiconductor parts 11 and the regional connection semiconductor parts 13 located on both sides of the functional area FU in the row direction or the column direction can be understood as also forming a continuous semiconductor trace, so that static electricity is evenly distributed on the continuous semiconductor trace corresponding to the functional area FU, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor parts 11 located on both sides of the functional area FU in the row direction or the column direction in the subsequent high-temperature process, so that the driving capability of the pixel circuit is basically consistent, achieving display uniformity, and improving the display effect.

[0097] It should be noted that Figure 18 The connection between the pixel-driving semiconductor portion 11 and the regional connection semiconductor portion 13 located on both sides of the functional area FU in the row direction is used as an example for description. The connection between the pixel-driving semiconductor portion 11 and the regional connection semiconductor portion 13 located on both sides of the functional area FU in the column direction is the same as the above-mentioned connection method and will not be described in detail here. Furthermore, in the subsequent embodiments, the connection between the pixel-driving semiconductor portion 11 located on both sides of the functional area FU in the row direction is also used as an example for description. The pixel-driving semiconductor portions connected in the column direction are the same as those in the row direction and will not be described in detail here.

[0098] It should also be noted that Figure 18Only one structure of the pixel driving semiconductor portion 11 is used for illustration, and the connection relationship between the remaining structures of the pixel driving semiconductor portion 11 and the region connecting semiconductor portion 13 is the same as the above connection relationship, and will not be repeated here.

[0099] Based on the above embodiments, Figure 19 yes Figure 17 Another enlarged example of area A is shown in the figure below. Figure 19 As shown, the reference signal line includes a first reference signal line and a second reference signal line extending in the row direction and parallel to each other, and the two fixed potential nodes include a first node and a second node; in the same pixel driving semiconductor portion, the first node is electrically connected to the first reference signal line, and the second node is electrically connected to the second reference signal line; the regional connection semiconductor portion 13 includes a first regional connection semiconductor portion 131 and a second regional connection semiconductor portion 132, and the pixel driving semiconductor portion 11 adjacent to the functional area FU includes a fifth pixel driving semiconductor portion 11-5 and a sixth pixel driving semiconductor portion 11-6; in the row direction X or the column direction Y, the second node N2 in the pixel driving semiconductor portion 11 located on the side of the fifth pixel driving semiconductor portion 11-5 away from the functional area FU is electrically connected to the fifth pixel driving semiconductor portion 11-5. The second node N2 in the semiconductor portion 11-5 is connected through the pixel connection semiconductor portion 12; in the row direction X or the column direction Y, the first node N1 in the pixel driving semiconductor portion 11 located on the side of the sixth pixel driving semiconductor portion 11-6 away from the functional area FU is connected to the first node N1 in the sixth pixel driving semiconductor portion 11-6 through the pixel connection semiconductor portion 12; in the row direction X or the column direction Y, the first nodes N1 in at least two fifth pixel driving semiconductor portions 11-5 located on both sides of the functional area FU are connected through the first regional connection semiconductor portion 131; in the row direction X or the column direction Y, the second nodes N2 in at least two sixth pixel driving semiconductor portions 11-6 located on both sides of the functional area FU are connected through the second regional connection semiconductor portion 132.

[0100] For example, Figure 19 The reference signal line is not shown in the figure. The reference signal line includes a first reference signal line and a second reference signal line. Figure 2 、 Figure 6 、 Figures 9-16 By setting two reference signal lines, independent reference signals are provided to the first node N1 and the second node N2, ensuring that the gate of the driving transistor and the anode of the light emitting element can be reset independently, ensuring a good reset effect.

[0101] Furthermore, in the row direction X or the column direction Y, the second node N2 in the pixel driving semiconductor portion 11 located on the side of the fifth pixel driving semiconductor portion 11-5 away from the functional area FU is connected to the second node N2 in the fifth pixel driving semiconductor portion 11-5 through the pixel connecting semiconductor portion 12, and the first node N1 in the pixel driving semiconductor portion 11 located on the side of the sixth pixel driving semiconductor portion 11-6 away from the functional area FU is connected to the first node N1 in the sixth pixel driving semiconductor portion 11-6 through the pixel connecting semiconductor portion 12, ensuring that the fifth pixel driving semiconductor portion 11-5 and the sixth pixel driving semiconductor portion 11-6, except for those located on both sides of the functional area FU, can be connected to each other to form connected semiconductor traces, so that static electricity is evenly distributed on the continuous semiconductor traces corresponding to both sides of the functional area FU, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor portions 11 located on both sides of the functional area FU in the row direction or the column direction in the subsequent high-temperature process, so that the driving capability of the pixel circuit is basically consistent, achieving display uniformity, and improving the display effect.

[0102] Furthermore, the first node N1 of at least the fifth pixel-driving semiconductor portion 11-5 located on both sides of the functional region FU is connected via the first-region connecting semiconductor portion 131. The first-region connecting semiconductor portion 131 can transmit a first reference signal Vref to ensure that a reset signal is provided to the first node N1 of the fifth pixel-driving semiconductor portion 11-5 connected to the first-region connecting semiconductor portion 131, thereby resetting the gate of the driving transistor in the fifth pixel-driving semiconductor portion 11-5. The second node N2 of at least the sixth pixel-driving semiconductor portion 11-6 located on both sides of the functional region FU is connected via the second-region connecting semiconductor portion 132. The second-region connecting semiconductor portion 132 can transmit a second reference signal Vref to ensure that a reset signal is provided to the second node N2 of the sixth pixel-driving semiconductor portion 11-6 connected to the second-region connecting semiconductor portion 132, thereby resetting the anode driver of the light-emitting element corresponding to the sixth pixel-driving semiconductor portion 11-6. To summarize, by setting the regional connection semiconductor portion 13 to include the first regional connection semiconductor portion 131 and the second regional connection semiconductor portion 132, and different reference signals can be transmitted on the first regional connection semiconductor portion 131 and the second regional connection semiconductor portion 132, it is ensured that the first node N1 and the second node N2 located on both sides of the functional area FU receive different signals respectively, and it is ensured that the pixel driving semiconductor portion 11 located on both sides of the functional area FU can provide different reset signals to the gate of its corresponding driving transistor and the anode of the light-emitting element, thereby ensuring a good reset effect.

[0103] Based on the above embodiments, Figure 20 yes Figure 17 Another enlarged example of area A is shown in the figure below. Figure 20As shown, the regional connection semiconductor portion 13 includes a third regional connection semiconductor portion 133, and the two first nodes N1 in the pixel driving semiconductor portion 11 arranged along the row direction or the column direction and respectively located on both sides of the functional region FU are connected through the third regional connection semiconductor portion 133; and / or, the regional connection semiconductor portion 13 includes a fourth regional connection semiconductor portion, and the two second nodes N2 in the pixel driving semiconductor portion 11 arranged along the row direction or the column direction and respectively located on both sides of the functional region FU are connected through the fourth regional connection semiconductor portion; and / or, the regional connection semiconductor portion 13 includes a fifth regional connection semiconductor portion 135, and the first node N1 and the second node N2 in the two pixel driving semiconductor portions 11 arranged along the row direction or the column direction and respectively located on both sides of the functional region FU are connected through the fifth regional connection semiconductor portion.

[0104] For example, Figure 20 The third region connecting the semiconductor portion 133 and the fifth region connecting the semiconductor portion 135 are shown only as an example. Figure 20 The fourth region connecting semiconductor portion is not shown in the figure. The fourth region connecting semiconductor portion is used to connect two second nodes N2 in the pixel driving semiconductor portion 11 arranged along the row direction or the column direction and respectively located on both sides of the functional area FU. The connection method of the fourth region connecting semiconductor portion and the second node N2 can refer to the connection method of the third region connecting semiconductor portion 133 and the first node N1, and will not be repeated here.

[0105] Specifically, the third-region connecting semiconductor portion 133 is used to connect the two first nodes N1 in the pixel driving semiconductor portion 11 located on both sides of the functional area FU in the row direction, the fourth-region connecting semiconductor portion is used to connect the two second nodes N2 in the pixel driving semiconductor portion 11 located on both sides of the functional area FU in the row direction, and the fifth-region connecting semiconductor portion 135 is used to connect the first node N1 and the second node N2 in the pixel driving semiconductor portion 11 located on both sides of the functional area FU in the row direction, to ensure that the two pixel driving semiconductor portions 11 located on both sides of the functional area FU along the row direction are connected to each other to form a connected semiconductor trace, so that static electricity is evenly distributed on the continuous semiconductor traces corresponding to both sides of the functional area FU, thereby improving the reliability and uniformity of the performance of the pixel driving semiconductor portions 11 located on both sides of the functional area FU in the row direction in subsequent high-temperature processes, so that the driving capability of the pixel circuit is basically consistent, thereby achieving display uniformity and improving the display effect.

[0106] Furthermore, a first reference signal Vref can be transmitted on the third-region connected semiconductor portion 133 to ensure that a reset is provided for the first node N1 in the pixel driving semiconductor portion 11 connected to the third-region connected semiconductor portion 133, thereby resetting the gate of the driving transistor in the pixel driving semiconductor portion 11; a second reference signal Vref can be transmitted on the fourth-region connected semiconductor portion to ensure that a reset signal is provided for the second node N2 in the pixel driving semiconductor portion 11 connected to the fourth-region connected semiconductor portion, thereby resetting the anode drive of the light-emitting element corresponding to the pixel driving semiconductor portion 11, thereby ensuring that the display circuit and the light-emitting element connected to the pixel circuit operate normally.

[0107] Combined with reference Figure 18 、 Figure 19 and Figure 20 As can be seen from the accompanying drawings, in the case where a functional area is set and the functional area blocks the connection relationship of the pixel driving semiconductor part, a regional connection semiconductor part can be set to realize the pixel driving semiconductor part located on both sides of the functional area along the row direction or the column direction. The regional connection semiconductor part can be further divided into a first regional connection semiconductor part, a second regional connection semiconductor part, a third regional connection semiconductor part, a fourth regional connection semiconductor part and a fifth regional connection semiconductor part according to different connection situations. See the above description for details. The regional connection semiconductor part provided in the embodiment of the present invention can be located in the same film layer as the pixel driving semiconductor part, and can be prepared using the same material and the same process, ensuring that the regional connection semiconductor part is simple to set and the display panel preparation process is simple.

[0108] Based on the above embodiments, continue to refer to Figure 20 As shown, the regional connection semiconductor portion 13 includes a fifth regional connection semiconductor portion 135, and the array substrate 100 also includes a control portion 14. The control portion 14 and the fifth regional connection semiconductor portion 135 at least partially overlap in a vertical direction of the plane where the array substrate is located, and the control portion 14 and the fifth regional connection semiconductor portion 135 constitute a switching element.

[0109] For example, since the fifth region connecting semiconductor portion 135 is used to connect the first node N1 and the second node N2 in the pixel driving semiconductor portion 11 located on both sides of the functional region FU in the row direction, but since the reference signals required by the first node N1 and the second node N2 are different, a control portion 14 can be set, and a switching element is formed by the control portion 14 and the fifth region connecting semiconductor portion 135, and then the short circuit between the first node N1 and the second node N2 is controlled to be closed by controlling the switching element, thereby avoiding the first node N1 and the second node N2 from transmitting the same reference signal through the fifth region connecting semiconductor portion 135, thereby avoiding the problem of low reset accuracy of the gate of the driving transistor or the anode of the light-emitting element.

[0110] Furthermore, the setting of the switching element can be set so that the control part 14 and the fifth region connecting semiconductor part 135 at least partially overlap in the vertical direction of the plane where the array substrate is located, so that the control part 14 and the fifth region connecting semiconductor part 135 form a thin film transistor, and the area where the control part 14 and the fifth region connecting semiconductor part 135 overlap is set as the conduction channel of the thin film transistor, and the control part 14 controls the conduction channel to be cut off to control the switching element to be closed, thereby controlling the circuit breaker between the first node N1 and the second node N2.

[0111] Based on the above embodiment, the control unit 14 can be further configured to be electrically connected to the fixed voltage terminal, so that a fixed voltage signal is transmitted on the control unit 14, and the fixed voltage signal can be used as a control signal to control the switch element to be closed, thereby controlling the switch element to remain in the off state.

[0112] For example, when the thin film transistor formed by the control unit 14 and the fifth region connecting the semiconductor portion 135 is a P-type thin film transistor, the fixed voltage terminal can be controlled to transmit a high-level signal, and the high-level signal can control the P-type thin film transistor to be in an off state. For another example, when the thin film transistor formed by the control unit 14 and the fifth region connecting the semiconductor portion 135 is an N-type thin film transistor, the fixed voltage terminal can be controlled to transmit a low-level signal, and the low-level signal can control the N-type thin film transistor to be in an off state. The embodiments of the present invention are described using the thin film transistor formed by the control unit 14 and the fifth region connecting the semiconductor portion 135 as an example of a P-type thin film transistor.

[0113] On the basis of the above embodiments, continue to refer to Figure 20 As shown, the array substrate further includes a power signal line PVDD, which extends along the PVDD column direction and is electrically connected to the pixel circuit. The power signal line PVDD includes a first branch portion 15 , which is multiplexed as a control portion 14 .

[0114] For example, combined Figure 2 and Figure 4 From the description of the pixel circuit structure and working process, we can know that the array substrate also includes a power signal line PVDD, which is used to provide a PVDD power signal to the light-emitting element to ensure that the light-emitting element can emit light normally. Generally, PVDD is a high-level signal, such as Figure 20As shown, by providing a power signal line PVDD including a first branch portion 15, the first branch portion 15 is multiplexed into the control portion 14. The high-level PVDD power signal serves as a control signal for the switching element, controlling the switching element to remain off, thereby ensuring a circuit break between the first node N1 and the second node N2 in the two pixel driver semiconductor portions located in the functional area FU. Furthermore, by utilizing the existing power signal line PVDD in the array substrate 100 as the control portion 14, the configuration of the control portion 14 is simplified.

[0115] It should be noted that Figure 20 The first branch portion 15 is only taken as a part of the power signal line PVDD as an example for explanation. It can be understood that according to the setting method of the power signal line PVDD and the setting method of the fifth region connecting the semiconductor portion 135, the first branch portion 15 can also include other settings, and the embodiment of the present invention is not limited to this.

[0116] It should also be noted that Figure 20 Only two power signal lines PVDD are shown. It is understandable that multiple power signal lines PVDD may be provided in the array substrate. For example, one power signal line PVDD is provided for each column of pixel driving semiconductor unit 11. The embodiment of the present invention does not limit the specific arrangement of the power signal line PVDD. Figure 20 The power signal line PVDD shown in FIG avoids the functional area FU and will not affect the arrangement of components in the functional area FU.

[0117] Optional, Figure 21 yes Figure 17 Another enlarged example of area A is shown in the figure below. Figure 21 As shown, the control unit 14 includes a first control unit 141 and a second control unit 142. The first control unit 141 and the second control unit 142 at least partially overlap with the same fifth region connected semiconductor unit 135 in the vertical direction of the plane where the array substrate is located, and the first control unit 141 and the second control unit 142 do not overlap in the vertical direction of the plane where the array substrate is located; the first control unit 141 and the second control unit 142 respectively constitute a first sub-switch element and a second sub-switch element with the fifth region connected semiconductor unit 135, the first control unit 141 and the second control unit 142 respectively receive different electrical signals, and at any time, at least one of the first sub-switch element and the second sub-switch element is in a cut-off state.

[0118] For example, Figure 21As shown, the control part 14 may further include a first control part 141 and a second control part 142. In the direction perpendicular to the substrate, the first control part 141 and the second control part 142 both overlap with the fifth region connected semiconductor part 135. Therefore, the first control part 141 and an area of ​​the fifth region connected semiconductor part 135 form a first sub-switch, and the first control part 141 and another area of ​​the fifth region connected semiconductor part 135 form a second sub-switch. At least one of the first sub-switch element and the second sub-switch element is in a cut-off state, which can ensure that the signal transmitted in the fifth region connected semiconductor part 135 cannot be normally transmitted at the position of the first sub-switch element and / or the position of the second sub-switch element, thereby ensuring that the first node N1 and the second node N2 in the two pixel driving semiconductor parts located in the functional area FU are disconnected.

[0119] On the basis of the above embodiments, continue to refer to Figure 21 As shown, the array substrate also includes a first scanning signal line Scan1, which extends along the row direction and is electrically connected to the pixel circuit. The first scanning signal line includes a second branch portion 16, and the second branch portion 16 is multiplexed as a first control portion 141; the second scanning signal line Scan2 extends along the row direction and is electrically connected to the pixel circuit. The second scanning signal line Scan2 includes a third branch portion 17, and the third branch portion 17 is multiplexed as a second control portion 142.

[0120] For example, combined Figure 2 and Figure 4 From the description of the pixel circuit structure and working process, we can know that the array substrate also includes a first scanning signal line Scan1 and a second scanning signal line Scan2. The first scanning signal line Scan1 and the second scanning signal line Scan2 are used to provide scanning signals to the thin film transistors in the pixel circuit to ensure the normal operation of the pixel circuit. Figure 5 As shown in the timing diagram, at any given moment, at least one of the signals in the first scan signal line Scan1 and the second scan signal line Scan2 is a high-level signal. Therefore, when the second branch 16 in the first scan line Scan1 is multiplexed into the first control unit 141 and the third branch 17 in the second scan line Scan2 is multiplexed into the second control unit 142, at least one of the signals in the second branch 16 and the third branch 17 is a high-level signal. This controls at least one of the first and second sub-switching elements to be in an off state, preventing the signal transmitted in the fifth region connecting semiconductor portion 135 from being properly transmitted at the first and / or second sub-switching elements, thereby ensuring a disconnection between the first and second nodes N1 and N2 in the two pixel driving semiconductor portions located in functional area FU. Furthermore, by utilizing the existing scan signal lines in the array substrate 100 as the control unit 14, the configuration of the control unit 14 is simplified.

[0121] It should be noted that Figure 21 The first scan signal line Scan1 and the second scan signal line Scan2 are shown only in the area corresponding to the fifth area connected to the semiconductor part 135. According to the above description, each row of pixel driving semiconductor part 11 corresponds to two scan signal lines, namely the first scan signal line Scan1 and the second scan signal line Scan2. Figure 21 In the example, for the first scan signal line Scan1 and the second scan signal line Scan2 located at the upper portion of the functional area FU, Figure 21 The third branch portion 17 is used as a portion of the second scan signal line Scan2 for illustration; for the first scan signal line Scan1 and the second scan signal line Scan2 located at the lower portion of the functional area FU, Figure 21 For the purpose of illustration, the second branch portion 16 is used as a portion of the first scanning signal line Scan1. It is understood that, depending on the configuration of the first scanning signal line Scan1 and the second scanning signal line Scan2 and the configuration of the fifth region connecting the semiconductor portion 135, the second branch portion 16 and the third branch portion 17 may also include other configurations, which are not limited in this embodiment of the present invention.

[0122] On the basis of the above embodiments, continue to refer to Figure 2 As shown, the pixel circuit provided by the embodiment of the present invention may further include a first connecting portion 18 and a second connecting portion 19, the reference signal line Vref includes a first reference signal line Vref1 and a second reference signal line Vref2 extending along the row direction and parallel to each other, and the two fixed potential nodes include a first node N1 and a second node N2; the first node N1 and the first reference signal line Vref1 are electrically connected through the first connecting portion 18; the second node N2 and the second reference signal line Vref2 are electrically connected through the second connecting portion 19.

[0123] For example, continue to refer to Figure 2 As shown, the first node N1 is electrically connected to the first reference signal line Vref1 through the first connection part 18, which is used to realize the transmission of the first reference signal, ensuring that the gate of the driving transistor can be reset; the second node N2 is electrically connected to the second reference signal line Vref2 through the second connection part 19, which is used to realize the transmission of the second reference signal, ensuring that the anode of the light-emitting element can be reset, and ensuring the normal operation of the display panel.

[0124] On the basis of the above embodiments, continue to refer to Figure 2 As shown, the array substrate includes a substrate and a driving circuit layer arranged on the substrate, and the driving circuit layer includes a semiconductor layer, a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer stacked in a direction away from the substrate;

[0125] The pixel driving semiconductor part is located in the semiconductor layer, the reference signal line is located in the first metal layer or the capacitor metal layer, and the first connecting part and the second connecting part are located in the second metal layer or the third metal layer.

[0126] According to the above, it can be known that the pixel circuit may include multiple thin film transistors and storage capacitors, the thin film transistor includes an active layer, a gate and a source-drain stage; the storage capacitor includes a first capacitor plate and a second capacitor plate; the array substrate also includes a scan signal line, a data signal line, a reference signal line and a power signal line. Among them, the active layer is the pixel driving semiconductor part, that is, the semiconductor layer located in the driving circuit layer, located on the side of the driving circuit layer close to the substrate. Further, the gate, the first capacitor plate and the scan signal line can be located in the first metal layer in the driving circuit layer; the second capacitor plate can be located in the capacitor metal layer in the driving circuit layer; the source-drain stage and the data signal line can be located in the second metal layer; the power signal line can be located in the second metal layer and / or the third metal layer. Further, the reference signal line can be located in the first metal layer or the capacitor metal layer, the first connecting part and the second connecting part can be located in the second metal layer or the third metal layer, and the first connecting part and the second connecting part are electrically connected to the reference signal line through vias, respectively, for realizing the transmission of the reference signal. In this way, the first connection portion and the second connection portion are arranged by reusing the film layer in the driving circuit layer, thereby ensuring that the arrangement of the first connection portion and the second connection portion is simple and the film layer structure of the display panel is simple.

[0127] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 22 Schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 22 As shown, the display device includes the display panel 200 in the above embodiment. The display device includes the display panel of any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be described in detail here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and an in-vehicle display device, which is not limited in the embodiment of the present invention.

[0128] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The array substrate includes: A pixel circuit, wherein a plurality of the pixel circuits are arranged in an array in a row direction and a column direction, each pixel circuit includes a pixel driving semiconductor portion, and the pixel driving semiconductor portion includes two fixed potential nodes, and the row direction and the column direction intersect; a reference signal line, the fixed potential node being electrically connected to the reference signal line; a pixel connection semiconductor portion, wherein two adjacent fixed potential nodes are electrically connected via the pixel connection semiconductor portion, the first direction being parallel to the plane of the array substrate; the reference signal line comprises a first reference signal line and a second reference signal line extending along the row direction, and the two fixed potential nodes comprise a first node and a second node; and within the same pixel driving semiconductor portion, the first node is electrically connected to the first reference signal line, and the second node is electrically connected to the second reference signal line. The two pixel driving semiconductor portions adjacent to each other in the row direction include a first pixel driving semiconductor portion and a second pixel driving semiconductor portion, the first node in the first pixel driving semiconductor portion is electrically connected to the first node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion, or the second node in the first pixel driving semiconductor portion is electrically connected to the second node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion; The plurality of pixel driving semiconductor portions include an i-th pixel driving semiconductor portion, an i+1-th pixel driving semiconductor portion, and an i+2-th pixel driving semiconductor portion sequentially arranged in the row direction, wherein i is a positive integer greater than or equal to 1; The pixel connection semiconductor portion includes a first pixel connection semiconductor portion and a second pixel connection semiconductor portion; The two second nodes in the i-th pixel driving semiconductor unit and the i+1-th pixel driving semiconductor unit are electrically connected through the second pixel connecting semiconductor unit, and the two first nodes in the i+1-th pixel driving semiconductor unit and the i+2-th pixel driving semiconductor unit are electrically connected through the first pixel connecting semiconductor unit.

2. The display panel according to claim 1, wherein: The first node and the second node in the pixel driving semiconductor portion are respectively located on two opposite sides of the pixel driving semiconductor portion in a second direction, wherein the second direction is parallel to the plane of the array substrate and is parallel to or forms an acute angle with the column direction; Along the row direction, the patterns of the pixel driving semiconductor parts in two adjacent pixel circuits arranged in sequence are different, and the patterns of the two pixel driving semiconductor parts separated by one pixel driving semiconductor part are the same.

3. The display panel according to claim 1, wherein: Two adjacent pixel driving semiconductor portions arranged in sequence in the row direction include a first pixel driving semiconductor portion and a second pixel driving semiconductor portion, a pixel driving semiconductor portion located on a first side of the first pixel driving semiconductor portion in the column direction is a third pixel driving semiconductor portion, and a pixel driving semiconductor portion located on a first side of the second pixel driving semiconductor portion in the column direction is a fourth pixel driving semiconductor portion; The first nodes in the first pixel driving semiconductor portion and the second pixel driving semiconductor portion and the second nodes in the third pixel driving semiconductor portion and the fourth pixel driving semiconductor portion are arranged along the row direction; The first node in the first pixel driving semiconductor unit and the second pixel driving semiconductor unit is located between the second node in the third pixel driving semiconductor unit and the fourth pixel driving semiconductor unit in the row direction; or, the second node in the third pixel driving semiconductor unit and the fourth pixel driving semiconductor unit is located between the first node in the first pixel driving semiconductor unit and the second pixel driving semiconductor unit in the row direction.

4. The display panel according to claim 3, wherein: The pixel driving semiconductor portion includes a U-shaped portion, which includes a connecting portion and a first branch and a second branch respectively connected to two ends of the connecting portion, the first branch and the second branch are arranged along the row direction and extend along the column direction; the end of the first branch away from the connecting portion is the first node.

5. The display panel according to claim 4, wherein: In the row direction, the first branch in the first pixel driving semiconductor unit and the second pixel driving semiconductor unit is located on the side of the second branch away from the second node in the third pixel driving semiconductor unit and the fourth pixel driving semiconductor unit; or, in the row direction, the second node in the third pixel driving semiconductor unit and the fourth pixel driving semiconductor unit is located on the side of the second branch in the first pixel driving semiconductor unit and the second pixel driving semiconductor unit away from the first node in the first pixel driving semiconductor unit and the second pixel driving semiconductor unit.

6. The display panel according to claim 1, wherein: The pixel driving semiconductor portion and the pixel connecting semiconductor portion are provided in the same layer.

7. The display panel according to claim 1, wherein: The first pixel connection semiconductor portion and the second pixel connection semiconductor portion both extend along the row direction.

8. The display panel according to claim 1, wherein: In a direction perpendicular to a plane where the display panel is located, the first pixel connection semiconductor portion and the second pixel connection semiconductor portion do not overlap with the first reference signal line and the second reference signal line.

9. The display panel according to claim 1, wherein: The first direction is the row direction.

10. The display panel according to claim 1, wherein The pixel driving semiconductor portions arranged along the column direction include pixel driving semiconductor portions in the jth row and pixel driving semiconductor portions in the j+1th row, wherein j is a positive integer greater than or equal to 1; At least two of the second nodes in the j-th row of pixel driving semiconductor portions and at least two of the first nodes in the j+1-th row of pixel connecting semiconductor portions are arranged along the row direction.

11. The display panel according to claim 1, wherein The pixel driving semiconductor portions arranged along the column direction include pixel driving semiconductor portions in the jth row and pixel driving semiconductor portions in the j+1th row, wherein j is a positive integer greater than or equal to 1; The second pixel connection semiconductor portion connected to the pixel driving semiconductor portion in the j-th row and the first pixel connection semiconductor portion connected to the pixel driving semiconductor portion in the j+1-th row are spaced apart.

12. The display panel according to claim 1, wherein The pixel circuit further includes a first connecting portion and a second connecting portion, wherein: The first node is electrically connected to the first reference signal line through the first connection portion, and the second node is electrically connected to the second reference signal line through the second connection portion.

13. The display panel according to claim 12, wherein: The array substrate includes a substrate and a driving circuit layer arranged on the substrate, wherein the driving circuit layer includes a semiconductor layer, a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer stacked in a direction away from the substrate; The first connection portion and the second connection portion are located in the second metal layer; or the first connection portion and the second connection portion are located in the third metal layer.

14. The display panel according to claim 13, wherein: The reference signal line is located in the first metal layer or the capacitor metal layer.

15. The display panel according to claim 1, wherein The pixel circuit includes a driving transistor, a light-emitting element, a first reset transistor and a second reset transistor, wherein the driving transistor is used to control the light-emitting element to light up, the first reset transistor is electrically connected to the gate of the driving transistor, and the second reset transistor is electrically connected to the anode of the light-emitting element; One end of the first reset transistor is electrically connected to the first node, and the other end is electrically connected to the gate of the driving transistor; One end of the second reset transistor is electrically connected to the second node, and the other end is electrically connected to the anode of the light emitting element.

16. The display panel according to claim 15, wherein: The first reset transistor is a dual-gate transistor.

17. The display panel according to claim 1, wherein: The first reference signal line and the second reference signal line provide different reference signals.

18. A display panel, characterized in that: The array substrate includes: A pixel circuit, wherein a plurality of the pixel circuits are arranged in an array in a row direction and a column direction, each pixel circuit includes a pixel driving semiconductor portion, and the pixel driving semiconductor portion includes two fixed potential nodes, and the row direction and the column direction intersect; a reference signal line, the fixed potential node being electrically connected to the reference signal line; a pixel connection semiconductor portion, through which two adjacent fixed potential nodes in a first direction are electrically connected, wherein the first direction is parallel to the plane where the array substrate is located; The reference signal line includes a first reference signal line and a second reference signal line extending along the row direction, and the two fixed potential nodes include a first node and a second node; in the same pixel driving semiconductor portion, the first node is electrically connected to the first reference signal line, and the second node is electrically connected to the second reference signal line; The two pixel driving semiconductor portions adjacent to each other in the row direction include a first pixel driving semiconductor portion and a second pixel driving semiconductor portion, the first node in the first pixel driving semiconductor portion is electrically connected to the first node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion, or the second node in the first pixel driving semiconductor portion is electrically connected to the second node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion; The pixel driving semiconductor portion includes a U-shaped portion, which includes a connecting portion and a first branch and a second branch respectively connected to two ends of the connecting portion, the first branch and the second branch are arranged along the row direction and extend along the column direction; the end of the first branch away from the connecting portion is the first node.

19. A display panel, characterized in that: The array substrate includes: A pixel circuit, wherein a plurality of the pixel circuits are arranged in an array in a row direction and a column direction, each pixel circuit includes a pixel driving semiconductor portion, and the pixel driving semiconductor portion includes two fixed potential nodes, and the row direction and the column direction intersect; a reference signal line, the fixed potential node being electrically connected to the reference signal line; a pixel connection semiconductor portion, through which two adjacent fixed potential nodes in a first direction are electrically connected, wherein the first direction is parallel to the plane where the array substrate is located; The reference signal line includes a first reference signal line and a second reference signal line extending along the row direction, and the two fixed potential nodes include a first node and a second node; in the same pixel driving semiconductor portion, the first node is electrically connected to the first reference signal line, and the second node is electrically connected to the second reference signal line; The two pixel driving semiconductor portions adjacent to each other in the row direction include a first pixel driving semiconductor portion and a second pixel driving semiconductor portion, the first node in the first pixel driving semiconductor portion is electrically connected to the first node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion, or the second node in the first pixel driving semiconductor portion is electrically connected to the second node in the second pixel driving semiconductor portion via the pixel connecting semiconductor portion; The first reference signal line and the second reference signal line provide different reference signals.

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