Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a display area (100) and a peripheral area, the peripheral area including a bending area (300) located on one side of the display area (100), and also includes a first crack detection line (201); the first crack detection line (201) includes a first lead segment (201a), a second lead segment (201b), a third lead segment (201c), and a fourth lead segment (201d), the first lead segment (201a) and the fourth lead segment (201d) being at least partially located in the bending area (301b). The first lead segment (201a) and the second lead segment (201b) and the third lead segment (201c) at least partially surround the display area (100). One end of the first lead segment (201a) is connected to one end of the second lead segment (201b) through a first via (K1). The other end of the second lead segment (201b) is connected to one end of the third lead segment (201c) through a second via (K2). The other end of the third lead segment (201c) is connected to one end of the fourth lead segment (201d). The display substrate includes a pixel defining layer (20) and a touch insulating layer (25). The pixel defining layer (20) has a first boundary (BL1) on the side of the first via (K1) away from the display area (100). The touch insulating layer (25) has a second boundary (BL2) on the side of the first via (K1) away from the display area (100). The second boundary (BL2) is located on the side of the first boundary (BL1) away from the display area (100).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs as the light-emitting device and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, including a display area and a peripheral area located around the display area, the peripheral area including a bending area located on one side of the display area;

[0005] A first crack detection line is located in the peripheral area and at least partially surrounds the display area. The first crack detection line includes a first lead segment, a second lead segment, a third lead segment, and a fourth lead segment. The first lead segment and the fourth lead segment are at least partially located in the bending area. The second lead segment and the third lead segment at least partially surround the display area. One end of the first lead segment is connected to one end of the second lead segment through a first via. The other end of the second lead segment is connected to one end of the third lead segment through a second via. The other end of the third lead segment is connected to one end of the fourth lead segment.

[0006] The display substrate includes a substrate, a driving circuit layer on the substrate, a pixel defining layer and a light-emitting structure layer on the side of the driving circuit layer away from the substrate, and a touch structure layer on the side of the pixel defining layer and the light-emitting structure layer away from the substrate. The pixel defining layer has a plurality of first openings in the display area, and the plurality of first openings are configured to accommodate the light-emitting structure layer.

[0007] The touch structure layer includes a touch insulating layer and a touch electrode layer located on the side of the touch insulating layer away from the pixel defining layer;

[0008] The pixel defining layer has a first boundary on the side of the first via that is away from the display area, and the touch insulating layer has a second boundary on the side of the first via that is away from the display area, with the second boundary located on the side of the first boundary that is away from the display area.

[0009] The pixel defining layer has a second opening in the peripheral region, and the first via is located in the orthographic projection of the substrate onto the second opening onto the substrate.

[0010] In an exemplary embodiment, the shortest distance between the first boundary and the second boundary is greater than 20 micrometers.

[0011] In an exemplary embodiment, the display substrate further includes a first planarization layer located between the driving circuit layer and the pixel defining layer, the first planarization layer having a third boundary on the side away from the first via, and a second boundary located on the side of the third boundary away from the display area.

[0012] In an exemplary embodiment, the shortest distance between the second boundary and the third boundary is greater than 20 micrometers.

[0013] In an exemplary embodiment, the shortest distances from the first via and the second via to the second boundary are equal.

[0014] In an exemplary embodiment, the display substrate further includes a third via, which is located on the side of the first via near the display area, and the third via is electrically connected to the second lead segment and the third lead segment.

[0015] In an exemplary embodiment, the orthographic projection of the second via onto the substrate is located in the orthographic projection of the second opening onto the substrate.

[0016] In an exemplary embodiment, the touch insulating layer covers the third via and at least a portion of the third lead segment.

[0017] In an exemplary embodiment, the second boundary is located in the bending area, and the third boundary is located on the side of the first boundary closer to the display area.

[0018] In an exemplary embodiment, the display substrate further includes a plurality of pads located on the side of the bending region away from the display region; the display substrate further includes a test circuit located between the bending region and the plurality of pads, and the other end of the first lead segment is electrically connected to the test circuit.

[0019] In an exemplary embodiment, the test circuit includes a plurality of test units, at least one of the plurality of test units including a first transistor and a second transistor, the control terminals of the first transistor and the second transistor being connected to a test control line, the first terminals of the first transistor and the second transistor being configured to be electrically connected to a data line, the second terminal of the first transistor being configured to be electrically connected to a first crack detection line, and the second terminal of the second transistor being configured to be electrically connected to a detection data line.

[0020] In an exemplary embodiment, the other end of the fourth lead segment is electrically connected to at least one of the plurality of pads.

[0021] In an exemplary embodiment, the display area includes a first edge, a second edge, a third edge, and a fourth edge connected in sequence, and the first via is located in the peripheral area near the first edge.

[0022] In an exemplary embodiment, the second lead segment is located in the peripheral area near the first edge, the second edge, the third edge, and the fourth edge; the third lead segment is located in the peripheral area near the first edge, the second edge, the third edge, and the fourth edge; the display area includes a camera hole, and the third lead segment is wound around the camera hole.

[0023] In an exemplary embodiment, the display substrate further includes a second crack detection line located in the peripheral area and at least partially surrounding the display area. The second crack detection line includes a first end and a second end, the first end and the second end being respectively connected to at least one of the plurality of pads.

[0024] In an exemplary embodiment, the second crack detection line is symmetrical about the center line of the display area.

[0025] In an exemplary embodiment, the first crack detection line includes a first sub-line and a second sub-line, and the second crack detection line includes a third sub-line and a fourth sub-line, wherein: the first sub-line is located in the peripheral region near the third edge and the fourth edge, the second sub-line is located in the peripheral region near the second edge and the third edge; the third sub-line is located in the peripheral region near the third edge and the fourth edge, and the fourth sub-line is located in the peripheral region near the second edge and the third edge.

[0026] In an exemplary embodiment, there are two first vias and two second vias. The two first vias are symmetrical about the center line of the display area, and the two second vias are symmetrical about the center line of the display area.

[0027] In an exemplary embodiment, the first via and the second via are located between the display area and the bending area.

[0028] In an exemplary embodiment, the driving circuit layer includes an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are sequentially stacked on a substrate. The first lead segment, the second lead segment, and the fourth lead segment are disposed on the same layer as any one or more of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer. The third lead segment is disposed on the same layer as the touch electrode layer.

[0029] This disclosure also provides a display device including the display substrate of any of the foregoing.

[0030] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0031] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0032] Figure 1 This is a schematic diagram of the structure of a display substrate;

[0033] Figure 2 This is a schematic diagram of the pixel arrangement structure of a display substrate;

[0034] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0035] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 5a and Figure 5b for Figure 4 Schematic diagrams of two enlarged structures in region A;

[0037] Figure 6a For display area and Figure 5a A schematic diagram of a cross-sectional structure of the BB' region;

[0038] Figure 6b For display area and Figure 5a A schematic diagram of a cross-sectional structure of the CC' region;

[0039] Figure 7a For display area and Figure 5bA schematic diagram of a cross-sectional structure of the DD' region;

[0040] Figure 7b For display area and Figure 5b A schematic diagram of a cross-sectional structure of the EE' region;

[0041] Figure 8 This is a schematic diagram of the structure of a test circuit as an exemplary embodiment of the present disclosure;

[0042] Figure 9 For display area and Figure 5a A schematic diagram showing the formation of the fifth insulating layer pattern in the BB' region;

[0043] Figure 10 For display area and Figure 5a A schematic diagram showing the formation of the fifth insulating layer pattern in the CC' region;

[0044] Figure 11 For display area and Figure 5a A schematic diagram showing the formation of the second source / drain metal layer pattern in the BB' region;

[0045] Figure 12 For display area and Figure 5a A schematic diagram showing the formation of the second source / drain metal layer pattern in the CC' region;

[0046] Figure 13 For display area and Figure 5a A schematic diagram showing the formation of the first flattening layer pattern in the BB' region;

[0047] Figure 14 For display area and Figure 5a A schematic diagram showing the formation of the first flattening layer pattern in the CC' region;

[0048] Figure 15 For display area and Figure 5a A schematic diagram showing the encapsulation layer pattern formed in the BB' region;

[0049] Figure 16 For display area and Figure 5a A schematic diagram showing the encapsulation layer pattern formed in the CC' region. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0051] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0052] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0053] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0054] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0055] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0057] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0058] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0059] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0060] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0061] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driver may sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, a scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple pixel sub-Pxij. Each pixel sub-Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and connected to the j-th data signal line.

[0062] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first light-emitting unit (sub-pixel) P1 emitting a first color light, a second light-emitting unit P2 emitting a second color light, and a third light-emitting unit P3 emitting a third color light. Each of the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of their respective light-emitting unit. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective light-emitting unit.

[0063] In an exemplary embodiment, a pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or it may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit; this disclosure does not limit the scope of the invention. In an exemplary embodiment, the shape of the light-emitting units in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three light-emitting units, the three light-emitting units may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four light-emitting units, the four light-emitting units may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the scope of the invention.

[0064] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of a sub-pixel. For example... Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 102 disposed on the substrate 10, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer 105 disposed on the encapsulation layer 104, etc., which are not limited herein.

[0065] In an exemplary embodiment, the substrate 10 can be a flexible substrate or a rigid substrate. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). The driving circuit layer 102 may include multiple transistors and storage capacitors constituting a pixel driving circuit. Figure 3The illustration uses an example where each sub-pixel includes a transistor 101 and a storage capacitor 101a. The light-emitting structure layer 103 may include an anode 19, a pixel boundary layer (PDL) 20, an organic light-emitting layer 21, and a cathode 22. The anode 19 is connected to a first connecting electrode 17a via a via, and the first connecting electrode 17a is connected to the drain electrode of the transistor 101 via a via. The organic light-emitting layer 21 is connected to the anode 19, and the cathode 22 is connected to the organic light-emitting layer 21. The organic light-emitting layer 21 emits light of the corresponding color under the drive of the anode 19 and the cathode 22. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting structure layer 103.

[0066] In an exemplary embodiment, the touch structure layer 105 may include a buffer layer, a first touch electrode layer (i.e., a bridging layer), a touch insulating layer, a second touch electrode layer, and a protective layer stacked on the encapsulation layer 104. Multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions may be disposed on the same layer of the second touch electrode layer and formed through the same patterning process. The first touch electrodes and the first connecting portions may be an integrally connected structure. Second connecting portions may be disposed on the first touch electrode layer, with adjacent second touch electrodes interconnected via vias. A touch insulating layer is disposed between the second touch electrode layer and the first touch electrode layer. In some possible implementations, multiple first touch electrodes, multiple second touch electrodes, and multiple second connecting portions may be disposed on the same layer of the second touch electrode layer. The second touch electrodes and the second connecting portions may be an integrally connected structure. First connecting portions may be disposed on the first touch electrode layer, with adjacent first touch electrodes interconnected via vias. In an exemplary embodiment, the first touch electrode may be a driving electrode (Tx) and the second touch electrode may be a sensing electrode (Rx), or the first touch electrode may be a sensing electrode (Rx) and the second touch electrode may be a driving electrode (Tx).

[0067] With the development of display devices, OLED display technology has shown tremendous potential. OLED's excellent display performance gives it a wide range of applications, but technological advancements have placed higher demands on screen integration. Flexible Multi-Layer On Cell (FMLOC) technology integrates the screen and touch control into one unit, significantly improving the integration of display devices. FMLOC technology has become a development trend in the display industry.

[0068] When using FMLOC technology, not only may the substrate have cracks, but the FMLOC itself may also have cracks. Once a crack appears, even a tiny one, moisture can easily seep into the display panel along the crack, affecting the wiring or circuitry inside the display panel, causing display defects and reduced lifespan.

[0069] This disclosure provides a display substrate in which a first crack detection line is used to detect cracks in the driving circuit layer and a second crack detection line is used to detect cracks in the touch structure layer. This enables separate detection of cracks in the driving circuit layer and the touch structure layer, thereby allowing the specific location of the crack to be detected. This facilitates accurate crack location during product manufacturing and related defect analysis, and improves product yield.

[0070] Crack detection is divided into backplane (BP) segment detection and module segment detection. BP segment detection connects the test unit pin (ET pin) and the first crack detection line for detection. Module segment detection connects the flexible circuit board pin (FPC pin) and the second crack detection line for detection. (Optionally, the second crack detection line can be connected to the input pin of the driver chip (IC) first, and then the output pin of the driver chip can be connected to the FPC pin through wiring.)

[0071] The first crack detection line has two loops, one on each side of the display panel. One end of the first crack detection line is connected to one or more green data lines through one or more first transistors in the test unit, and the other end is connected to a high voltage (VGH) signal through a pin. The VGH signal can be provided by the FPC.

[0072] Detection principle: When a crack occurs, a bright green line appears on a black screen, indicating that a crack has been formed;

[0073] Typically, when there are no cracks around the display substrate, the first crack detection line is at a high voltage (6V), which is input to the corresponding sub-pixel, resulting in a relatively small current flowing through the light-emitting device (e.g., OLED) of that sub-pixel. This light-emitting device emits almost no light, appearing black.

[0074] According to the current formula:

[0075] ID1 = K(Vgs - Vth) 2

[0076] =K[(Vdata+Vth-VDD)-Vth] 2

[0077] =K(Vdata-VDD) 2

[0078] In the above formula, Vth represents the threshold voltage of the first transistor T1, Vgs represents the voltage between the gate and source of the first transistor T1, and K is a constant value.

[0079] If the display panel has a crack, the detection voltage signal can be considered to be approximately 0V. The current flowing through the light-emitting devices of that sub-pixel column is relatively large, causing the devices to emit light. This illuminates the green pixels, resulting in a bright green line appearing on a black screen, indicating a crack in the display panel.

[0080] To simultaneously detect cracks in both the touch structure layer and the backplane (BP), vias are needed to connect the touch traces in the BP film and the FMLOC film. The first planarization layer (PLN) and pixel delimitation layer (PDL) are removed above the second source / drain metal layer (SD2) of the backplane. Simultaneously, vias are designed in the touch insulating layer (TLD) of the FMLOC process to allow the metal of the second touch electrode layer (TMB) in the FMLOC process to overlap with the metal of the second source / drain metal layer of the backplane. This enables signals from the chip (IC) to be transmitted from the IC through the BP film to the FMLOC film, thus achieving the crack detection function.

[0081] However, during the process, it was discovered that the TLD itself is an inorganic layer with a thickness of 300nm. In the first process of the FMLOC process, an inorganic layer is first deposited using CVD to form a buffer layer with a thickness of 200nm. To effectively achieve the bonding between the BP film and the FMLOC film, the TLD process needs to be etched, and it must be over-etched to ensure that the 200nm buffer layer is completely removed. However, in actual practice, the TLD over-etching goes far beyond this, continuing to etch the organic BP film layer, further etching between 200nm and 300nm. Since the etching boundary of the TLD is located above the first planarization layer, and the thickness of the first planarization layer covering the second source / drain metal layer is relatively thin, approximately between 400nm and 500nm, when the TLD over-etching process fluctuates significantly, it will cause over-etching, exposing the metal of the second source / drain metal layer and forming a groove. The TMB metal will remain at this location, causing the metal of the second source / drain metal layer on the second crack detection line to connect with the metal of the second source / drain metal layer on the first crack detection line through the TMB, resulting in a short circuit and thus preventing normal crack detection.

[0082] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 5a and Figure 5b for Figure 4 Two enlarged structural diagrams of region A in the middle. (See diagram below.) Figure 4 , Figure 5a and Figure 5b As shown, this embodiment of the present disclosure provides a display substrate, which includes a display area 100 and a peripheral area located around the display area, the peripheral area including a bending area 300 located on one side of the display area 100.

[0083] The display substrate includes: a first crack detection line 201 located in the peripheral area and at least partially surrounding the display area 100. The first crack detection line 201 includes a first lead segment 201a, a second lead segment 201b, a third lead segment 201c, and a fourth lead segment 201d. The first lead segment 201a and the fourth lead segment 201d are at least partially located in the bending area 300. The second lead segment 201b and the third lead segment 201c at least partially surround the display area 100. One end of the first lead segment 201a is connected to one end of the second lead segment 201b through a first via. The other end of the second lead segment 201b is connected to one end of the third lead segment 201c through a second via. The other end of the third lead segment 201c is connected to one end of the fourth lead segment 201d.

[0084] Figure 6a For display area and Figure 5a A schematic diagram of a cross-sectional structure of the BB' region. Figure 6b For display area and Figure 5a A schematic diagram of a cross-sectional structure of the CC' region. Figure 7a For display area and Figure 5b A schematic diagram of a cross-sectional structure of the DD' region. Figure 7b For display area and Figure 5b A schematic diagram of a cross-sectional structure of the EE' region. (Example) Figure 6a , Figure 6b , Figure 7a and Figure 7b As shown, in an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 102 disposed on the substrate 10, a pixel defining layer (PDL) 20 and a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 10, an encapsulation layer 104 disposed on the side of the pixel defining layer 20 and the light-emitting structure layer 103 away from the substrate 10, and a touch structure layer 105 disposed on the side of the encapsulation layer 104 away from the substrate 10. The pixel defining layer 20 has a plurality of first openings (not shown in the figure) in the display area 100, and the plurality of first openings are configured to accommodate the light-emitting structure layer 103.

[0085] The touch structure layer 105 includes a touch insulating layer (TLD) 25 and a second touch electrode layer (TMB) 26 located on the side of the touch insulating layer 25 away from the pixel defining layer 20; wherein, the pixel defining layer 20 has a first boundary BL1 on the side of the first via K1 away from the display area 100, and the touch insulating layer 25 has a second boundary BL2 on the side of the first via K1 away from the display area 100, and the second boundary BL2 is located on the side of the first boundary BL1 away from the display area 100.

[0086] The pixel defining layer 20 has a second opening O2 in the peripheral region, and the orthographic projection of the first via K1 on the substrate 10 lies within the orthographic projection of the second opening O2 on the substrate 10. In some other exemplary embodiments, the orthographic projection of the first via K1 on the substrate 10 may also overlap with a portion of the orthographic projection of the second opening O2 on the substrate 10.

[0087] In an exemplary implementation, such as Figure 6a , Figure 6b , Figure 7a and Figure 7b As shown, in a plane perpendicular to the substrate 10, the driving circuit layer 102 includes a first insulating layer 11, an active layer, a second insulating layer 12, a first gate metal layer, a third insulating layer 13, a second gate metal layer, a fourth insulating layer 14, a first source / drain metal layer, a fifth insulating layer 15, a second planarization layer 16, and a second source / drain metal layer, which are sequentially stacked on the substrate.

[0088] In an exemplary implementation, such as Figure 6a , Figure 6b , Figure 7a and Figure 7b As shown, in a plane perpendicular to the substrate 10, the touch structure layer 105 includes a buffer layer, a first touch electrode layer (TMA) disposed on the buffer layer, a touch insulating layer (TLD) 25 disposed on the first touch electrode layer, a second touch electrode layer (TMB) 26 disposed on the touch insulating layer 25, and a protective layer disposed on the second touch electrode layer 26.

[0089] In an exemplary embodiment, the second crack detection line 202, the first lead segment 201a, the third lead segment 201c, and the fourth lead segment 201d are disposed in the same layer as any one or more of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer, and the second lead segment 201b is disposed in the same layer as the second touch electrode layer or the first touch electrode layer.

[0090] In an exemplary implementation, such as Figure 6a , Figure 6b , Figure 7a and Figure 7bAs shown, the third lead segment 201c is disposed in the same layer as the second gate metal layer, the second crack detection line 202, the first lead segment 201a and the fourth lead segment 201d are disposed in the same layer as the second source and drain metal layer, and the second lead segment 201b is disposed in the same layer as the second touch electrode layer 26.

[0091] In an exemplary implementation, such as Figure 5a and Figure 5b As shown, the shortest distance d1 between the first boundary BL1 and the second boundary BL2 is greater than 20 micrometers.

[0092] In an exemplary implementation, such as Figure 5a , Figure 6a and Figure 6b As shown, the display substrate also includes a first planarization layer (PLN) 18 located between the driving circuit layer 102 and the pixel defining layer 20. The first planarization layer 18 has a third boundary BL3 on the side away from the first via K1, and a second boundary BL2 is located on the side of the third boundary BL3 away from the display area 100.

[0093] In an exemplary implementation, such as Figure 5a As shown, the shortest distance d2 between the second boundary BL2 and the third boundary BL3 is greater than 20 micrometers.

[0094] In an exemplary implementation, such as Figure 5a and Figure 5b As shown, the shortest distances from the first via K1 and the second via K2 to the second boundary BL2 are equal.

[0095] In an exemplary implementation, such as Figure 5a and Figure 5b As shown, the display substrate also includes a third via K3, which is located on the side of the first via K1 near the display area 100. The third via K3 is electrically connected to the second lead segment 201b and the third lead segment 201c.

[0096] In an exemplary implementation, such as Figure 5a and Figure 5b As shown, the orthographic projection of the second via K2 on the substrate 10 is located in the orthographic projection of the second opening O2 on the substrate 10.

[0097] In an exemplary implementation, such as Figure 6b and Figure 7b As shown, the touch insulating layer 25 covers the third via K3 and at least a portion of the third lead segment 201c.

[0098] In an exemplary implementation, such as Figure 5a As shown, the second boundary BL2 is located in the bending area 300, and the third boundary BL3 is located on the side of the first boundary BL1 that is close to the display area 100.

[0099] In an exemplary implementation, such as Figure 4 As shown, the display substrate also includes a plurality of pads located on the side of the bending area 300 away from the display area 100;

[0100] The display substrate also includes a test circuit CT, which is located between the bending area 300 and multiple pads. The other end of the first lead segment 201a is electrically connected to the test circuit CT.

[0101] Figure 8 This is a schematic diagram of a test circuit according to an embodiment of the present disclosure, as shown below. Figure 8 As shown, in an exemplary embodiment, the test circuit CT includes multiple test units CT1. At least one of the multiple test units CT1 includes a first transistor T1 and a second transistor T2. The control terminals of the first transistor T1 and the second transistor T2 are connected to the test control line SWD. The first terminals of the first transistor T1 and the second transistor T2 are configured to be electrically connected to the data line Data. The second terminal of the first transistor T1 is configured to be electrically connected to the first crack detection line 201. The second terminal of the second transistor T2 is configured to be electrically connected to the detection data line CTD.

[0102] In an exemplary implementation, such as Figure 4 As shown, the other end of the fourth lead segment 201d is electrically connected to at least one of the multiple pads.

[0103] In an exemplary implementation, such as Figure 4 , Figure 5a and Figure 5b As shown, the display area 100 includes a first edge 1001, a second edge 1002, a third edge 1003 and a fourth edge 1004 connected in sequence, and the first via K1 is located in the peripheral area near the first edge 1001.

[0104] In an exemplary embodiment, the second lead segment 201b is located in the peripheral area near the first edge 1001, the second edge 1002, the third edge 1003 and the fourth edge 1004.

[0105] The third lead segment 201c is located in the peripheral area near the first edge 1001, the second edge 1002, the third edge 1003 and the fourth edge 1004.

[0106] In an exemplary implementation, such as Figure 4 As shown, the display area includes a camera hole 101, and a third lead segment 201c is wound around the camera hole 101.

[0107] In an exemplary implementation, such as Figure 4As shown, the display substrate also includes a second crack detection line 202, which is located in the peripheral area and at least partially surrounds the display area 100. The second crack detection line 202 includes a first end and a second end, which are respectively connected to at least one of a plurality of pads.

[0108] In an exemplary implementation, such as Figure 4 As shown, the second crack detection line 202 is symmetrical about the center line O of the display area 100.

[0109] In an exemplary implementation, such as Figure 4 As shown, the first crack detection line 201 includes a first sub-line 2011 located on one side of the center line O and a second sub-line 2012 located on the other side of the center line O. The second crack detection line 202 includes a third sub-line 2021 located on one side of the center line O and a fourth sub-line 2022 located on the other side of the center line O, wherein:

[0110] The first sub-line 2011 is located in the peripheral area near the first edge 1001, the third edge 1003 and the fourth edge 1004, and the second sub-line 2012 is located in the peripheral area near the first edge 1001, the second edge 1002 and the third edge 1003.

[0111] The third sub-line 2021 is located in the peripheral area near the first edge 1001, the third edge 1003 and the fourth edge 1004, and the fourth sub-line 2022 is located in the peripheral area near the first edge 1001, the second edge 1002 and the third edge 1003.

[0112] In this embodiment of the present disclosure, the first crack detection line 201 detects whether a crack has appeared on the back plate by means of bright line detection; the second crack detection line 202 detects whether a crack has appeared on the back plate by means of resistance detection.

[0113] In an exemplary embodiment, there are two first vias K1 and two second vias K2. The two first vias K1 are symmetrical about the center line O of the display area 100, and the two second vias K2 are symmetrical about the center line O of the display area 100.

[0114] In an exemplary embodiment, the first via K1 and the second via K2 are located between the display area 100 and the bending area 300.

[0115] The display substrate of this embodiment has a first boundary BL1 on the side of the first via K1 away from the display area 100, and a second boundary BL2 on the side of the first via K1 away from the display area 100. The second boundary BL2 is located on the side of the first boundary BL1 away from the display area 100. This ensures that even if over-etching occurs when etching the touch insulating layer 25, the first crack detection line 201 and the second crack detection line 202 will not short-circuit, thereby improving the product quality and yield.

[0116] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0117] In an exemplary embodiment, a process for fabricating a display substrate may include the following operations.

[0118] (1) First, a driving circuit layer 102 pattern is fabricated on the substrate 10. The driving circuit layer 102 includes multiple gate lines and multiple data lines, which intersect to define multiple matrix-arranged pixel units. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor (TFT). In this embodiment, a pixel unit includes three sub-pixels, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, this embodiment is also applicable to the case where a pixel unit includes four sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W).

[0119] In an exemplary embodiment, the substrate 10 can be a flexible substrate or a rigid substrate. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking a multilayer structure as an example, the preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-Si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the preparation of the substrate 10.

[0120] In an exemplary embodiment, the fabrication process of the driving circuit layer 102 may include:

[0121] A first insulating film and an active layer film are sequentially deposited on a substrate 10. The active layer film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, and an active layer pattern disposed on the first insulating layer 11. The active layer pattern is formed in the display area 100 and includes at least the first active layer. After this patterning process, the peripheral area includes the first insulating layer 11 disposed on the substrate 10.

[0122] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer 12 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 12. The first gate metal layer pattern is formed in the display area 100 and includes at least a first gate electrode, a first capacitor electrode, multiple gate lines (not shown), and multiple gate leads (not shown). After this patterning process, the peripheral area includes a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10.

[0123] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 13 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 13. The second gate metal layer pattern is formed in the display area 100 and includes at least a second capacitor electrode and a second gate lead (not shown). The position of the second capacitor electrode corresponds to the position of the first capacitor electrode. After this patterning process, the peripheral area includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked on the substrate 10. At least one of the first gate metal layer and the second gate metal layer further includes a second crack detection line 202 and a third lead segment 201c of the first crack detection line 201.

[0124] Subsequently, a fourth insulating film is deposited, and a patterning process is used to pattern the fourth insulating film to form a pattern of a fourth insulating layer 14 covering the second gate metal layer. Multiple first openings are formed on the fourth insulating layer 14, located in the display area 100, with their positions corresponding to the two ends of the first active layer. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the multiple first openings are etched away, exposing the surface of the first active layer. After this patterning process, the peripheral region includes the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 stacked on the substrate 10.

[0125] Subsequently, a third metal thin film is deposited, and the third metal thin film is patterned using a patterning process to form a source / drain metal layer pattern on the fourth insulating layer 14. The source / drain metal layer is formed in the display area 100 and includes at least a first source electrode, a first drain electrode, a low-voltage (VSS) line (not shown), multiple data lines (not shown), and multiple data leads (not shown) patterns. The first source electrode and the first drain electrode are respectively connected to the first active layer through a first opening. In an exemplary embodiment, depending on actual needs, the source / drain metal layer may also include any one or more of a power line (VDD), a compensation line, and an auxiliary cathode. The source / drain metal layer is also referred to as the first source / drain metal layer (SD1). After this patterning process, the peripheral area includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the substrate 10.

[0126] Subsequently, a fifth insulating film is deposited to form a fifth insulating layer 15 pattern covering the source / drain metal layers. After this patterning process, the peripheral region includes a composite insulating layer disposed on the substrate 10. The composite insulating layer includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, and a fifth insulating layer 15 stacked together, as shown below. Figure 9 and Figure 10 As shown;

[0127] A second planarization film is coated on the substrate 10 with the aforementioned pattern to form a second planarization (PLN) layer 16 covering the entire substrate 10. A second opening is formed on the second planarization layer 16 through a patterning process. The second opening is formed in the display area 100. The second planarization layer 16 and the fifth insulating layer 15 within the second opening are etched away, exposing the surface of the first drain electrode of the first transistor 101. After this patterning process, the peripheral area includes a composite insulating layer disposed on the substrate 10 and a second planarization layer 16 disposed on the composite insulating layer. In an exemplary embodiment, a third via K3 may also be disposed on the second planarization layer 16 and the fifth insulating layer 15, and the third via K3 exposes a third lead segment 201c.

[0128] A fourth metal thin film is deposited on the substrate on which the aforementioned pattern is formed. The fourth metal thin film is patterned using a patterning process to form a metal conductive layer pattern on the second planarization layer 16. The metal conductive layer includes at least a first connecting electrode 17a, a second connecting electrode 17b, a first lead segment 201a, and a fourth lead segment 201d. The first connecting electrode 17a is formed in the display area 100 and is connected to the first drain electrode of the first transistor 101 through a second opening. The second connecting electrode 17b, the first lead segment 201a, and the fourth lead segment 201d are formed in the peripheral area. The second connecting electrode 17b is configured to connect to the subsequently formed second lead segment 201b and third lead segment 201c through a third via K3. The fourth lead segment 201d can be electrically connected to the third lead segment 201c through vias on multiple intermediate insulating layers. Figures 11 to 12 As shown. In an exemplary embodiment, the metal conductive layer is also referred to as the second source / drain metal layer (SD2). Depending on the actual design, the second source / drain metal layer may also include any one or more of power lines, power leads, low-voltage leads, and auxiliary cathodes.

[0129] A first planarization film is coated on the substrate 10 on which the aforementioned pattern is formed. A first planarization layer (PLN) 18 pattern is formed on the second planarization layer 16 through a masking, exposure, and development process. In the display area 100, a third opening is formed on the first planarization layer 18. The first planarization layer 18 within the third opening is developed away, exposing the surface of the first connecting electrode 17. In the peripheral area, a third opening O3 is formed on the first planarization layer 18. The first planarization layer 18 within the third opening O3 is developed away, exposing the surfaces of the first lead segment 201a and the second connecting electrode 17b, as shown below. Figures 13 to 14 As shown. In some other exemplary embodiments, the third opening O3 may not be provided on the first planarization layer 18, and in the peripheral region, the first planarization layer 18 covers the first lead segment 201a and the second connecting electrode 17b.

[0130] At this point, the driving structure layer pattern is complete on the substrate 10. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 101, the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102, and multiple gate leads and data leads constitute the driving leads for the array substrate gate driver on array (GOA). In an exemplary embodiment, the first transistor 101 may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (TFT).

[0131] (2) A pattern of light-emitting structure layer 103 and encapsulation layer 104 is prepared on the substrate 10 on which the aforementioned pattern is formed, such as... Figures 15 to 16 As shown. In an exemplary embodiment, the fabrication process of the light-emitting structure layer 103 may include:

[0132] A transparent conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed. The transparent conductive film is patterned by a patterning process to form an anode 19 pattern. The anode 19 is formed in the display area 100 and is connected to the first connecting electrode 17 through a third opening.

[0133] A pixel definition film is coated on the substrate 10 on which the aforementioned pattern is formed. A pixel definition layer (PDL) 20 pattern is formed by masking, exposure and development processes. The pixel definition layer 20 is formed in the display area 100 and the peripheral area. A first opening is formed on the pixel definition layer 20 of the display area 100. The pixel definition film in the first opening is developed away, exposing the surface of the anode 19. A second opening O2 is formed on the pixel definition layer 20 of the peripheral area. The pixel definition film in the second opening O2 is developed away, exposing the third opening O3, that is, exposing the surface of the first lead segment 201a and the second connecting electrode 17b.

[0134] An organic material thin film is coated on the substrate on which the aforementioned pattern is formed, and multiple isolation pillar (PS) patterns (not shown) are formed by masking, exposure, and development processes.

[0135] An organic light-emitting layer 21 and a cathode 22 are sequentially formed on the substrate on which the aforementioned pattern is formed. The organic light-emitting layer 21 may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, formed in the display area 100, thereby connecting the organic light-emitting layer 21 to the anode 19. Since the anode 19 is connected to the first connecting electrode 17, and the first connecting electrode 17 is connected to the drain electrode of the first transistor 101, the light emission control of the organic light-emitting layer 21 is achieved. The cathode 22 is connected to the organic light-emitting layer 21.

[0136] An encapsulation layer 104 is formed on the basis of the aforementioned pattern. The encapsulation layer 104 is formed in the display area 100 and adopts a stacked structure of inorganic material / organic material / inorganic material, with the organic material layer disposed between the two inorganic material layers.

[0137] (3) A touch structure layer 105 pattern is formed on the substrate on which the aforementioned pattern is formed. The touch structure layer 105 may include a buffer layer, a first touch electrode layer (i.e., a bridging layer), a touch insulating layer (TLD) 25, a second touch electrode layer 26, and a protective layer 27 stacked on the encapsulation layer 104. Multiple first touch electrodes, multiple second touch electrodes, and multiple first connection portions may be disposed on the second touch electrode layer 26 in the same layer and may be formed by the same patterning process. The first touch electrodes and the first connection portions may be an integral structure interconnected with each other. The second connection portions may be disposed on the first touch electrode layer, and adjacent second touch electrodes may be interconnected through vias. A touch insulating layer 25 is disposed between the second touch electrode layer 26 and the first touch electrode layer. In some possible implementations, multiple first touch electrodes, multiple second touch electrodes, and multiple second connection portions may be disposed on the second touch electrode layer 26 in the same layer. The second touch electrodes and the second connection portions may be an integral structure interconnected with each other. The first connection portions may be disposed on the first touch electrode layer, and adjacent first touch electrodes may be interconnected through vias.

[0138] In an exemplary embodiment, a first via K1 and a second via K2 are provided on the touch insulating layer (TLD) 25. The touch insulating layer 25 in the first via K1 is developed away, exposing the surface of the first lead segment 201a. The touch insulating layer 25 in the second via K2 is developed away, exposing the surface of the second connecting electrode 17b. The second touch electrode layer 26 also includes a pattern of the second lead segment 201b. The second lead segment 201b is connected to the first lead segment 201a through the first via K1 and to the second connecting electrode 17b through the second via K2. Since the second connecting electrode 17b is connected to the third lead segment 201c through the third via K3, the connection between the second lead segment 201b and the third lead segment 201c is realized.

[0139] In an exemplary embodiment, the fabrication process of the flexible display substrate may include processes such as peeling off the glass substrate, attaching the back film, and cutting, which are not limited herein.

[0140] As can be seen from the structure and fabrication process of the display substrate in the exemplary embodiments of this disclosure, the exemplary embodiments of this disclosure detect cracks in the driving circuit layer 102 through the first crack detection line 201 and the touch structure layer 105 through the second crack detection line 202. This achieves separate detection of cracks in the driving circuit layer 102 and the touch structure layer 105, thereby detecting the specific location of the cracks. This is beneficial for accurate crack location during product manufacturing and related defect analysis, thus improving product yield. In addition, by having the pixel defining layer 20 have a first boundary BL1 on the side of the first via K1 away from the display area 100, and having the touch insulating layer 25 have a second boundary BL2 on the side of the first via K1 away from the display area 100, with the second boundary BL2 located on the side of the first boundary BL1 away from the display area 100, even if over-etching occurs during the etching of the touch insulating layer 25, there is no risk of short circuit between the first crack detection line 201 and the second crack detection line 202. The exemplary embodiment of the present disclosure describes a method for preparing a display substrate that has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0141] The structures and fabrication processes shown in the exemplary embodiments of this disclosure are merely illustrative. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced according to actual needs. For example, the transistors in the driving circuit layer 102 can be top-gate structures, bottom-gate structures, single-gate structures, or dual-gate structures. Furthermore, other film structures, electrode structures, or lead structures can also be provided in the driving circuit layer 102 and the light-emitting structure layer 103. Moreover, the substrate can be a glass substrate; this disclosure does not impose specific limitations on it.

[0142] This disclosure also provides a method for fabricating a display substrate. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a bending area located on one side of the display area. The peripheral area includes a first crack detection line, and the first crack detection line at least partially surrounds the display area. The first crack detection line includes a first lead segment, a second lead segment, a third lead segment, and a fourth lead segment. The first lead segment and the fourth lead segment are at least partially located in the bending area. The second lead segment and the third lead segment at least partially surround the display area. One end of the first lead segment is connected to one end of the second lead segment through a first via. The other end of the second lead segment is connected to one end of the third lead segment through a second via. The other end of the third lead segment is connected to one end of the fourth lead segment. In an exemplary embodiment, the fabrication method may include:

[0143] A driving circuit layer is formed on the substrate.

[0144] A pixel defining layer and a light-emitting structure layer are formed on the driving circuit layer. The pixel defining layer has a plurality of first openings in the display area, and the plurality of first openings are configured to accommodate the light-emitting structure layer. The pixel defining layer has a second opening in the peripheral area. The orthographic projection of the first via on the substrate is located in the orthographic projection of the second opening on the substrate. In some other exemplary embodiments, the orthographic projection of the first via on the substrate may also overlap with the orthographic projection of the second opening on the substrate.

[0145] A touch structure layer is formed on the pixel defining layer and the light-emitting structure layer. The touch structure layer includes a touch insulating layer and a second touch electrode layer located on the side of the touch insulating layer away from the pixel defining layer. The pixel defining layer has a first boundary on the side of the first via away from the display area, and the touch insulating layer has a second boundary on the side of the first via away from the display area. The second boundary is located on the side of the first boundary away from the display area.

[0146] In an exemplary embodiment, the driving circuit layer includes an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are sequentially stacked on a substrate.

[0147] This disclosure provides a method for fabricating a display substrate. A first crack detection line is used to detect cracks in the driving circuit layer, and a second crack detection line is used to detect cracks in the touch structure layer. This allows for separate detection of cracks in both the driving circuit layer and the touch structure layer, enabling the precise location of cracks. This facilitates accurate crack localization during product manufacturing and defect analysis, improving product yield. Furthermore, by having a first boundary for the pixel defining layer on the side of the first via hole away from the display area, and a second boundary for the touch insulating layer on the same side, with the second boundary located on the side of the first boundary away from the display area, even if over-etching occurs during the etching of the touch insulating layer, there is no risk of short circuits between the first and second crack detection lines. The exemplary embodiment of this disclosure provides a display substrate fabrication method with good process compatibility, simple process implementation, ease of execution, high production efficiency, low production cost, and high yield.

[0148] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0149] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate includes a display area and a peripheral area located around the display area, the peripheral area including a bent area located on one side of the display area; A first crack detection line is located in the peripheral area and at least partially surrounds the display area. The first crack detection line includes a first lead segment, a second lead segment, a third lead segment, and a fourth lead segment. The first lead segment and the fourth lead segment are at least partially located in the bending area. The second lead segment and the third lead segment at least partially surround the display area. One end of the first lead segment is connected to one end of the second lead segment through a first via. The other end of the second lead segment is connected to one end of the third lead segment through a second via. The other end of the third lead segment is connected to one end of the fourth lead segment. The display substrate includes a driving circuit layer on the substrate, a pixel defining layer and a light-emitting structure layer on the side of the driving circuit layer away from the substrate, and a touch structure layer on the side of the pixel defining layer and the light-emitting structure layer away from the substrate. The pixel defining layer has a plurality of first openings in the display area, and the plurality of first openings are configured to accommodate the light-emitting structure layer. The touch structure layer includes a touch insulating layer and a touch electrode layer located on the side of the touch insulating layer away from the pixel defining layer; The pixel defining layer has a first boundary on the side of the first via that is away from the display area, and the touch insulating layer has a second boundary on the side of the first via that is away from the display area, with the second boundary located on the side of the first boundary that is away from the display area. The pixel defining layer has a second opening in the peripheral region, and the first via is located in the orthographic projection of the substrate onto the second opening onto the substrate.

2. The display substrate according to claim 1, wherein, The shortest distance between the first boundary and the second boundary is greater than 20 micrometers.

3. The display substrate according to claim 1, further comprising a first planarization layer located between the driving circuit layer and the pixel defining layer, the first planarization layer having a third boundary on the side away from the first via, and the second boundary located on the side of the third boundary away from the display area.

4. The display substrate according to claim 3, wherein, The shortest distance between the second boundary and the third boundary is greater than 20 micrometers.

5. The display substrate according to claim 3, wherein, The second boundary is located in the bending area, and the third boundary is located on the side of the first boundary closer to the display area.

6. The display substrate according to claim 1, wherein, The shortest distances from the first via and the second via to the second boundary are equal.

7. The display substrate according to claim 1 further includes a third via, the third via being located on the side of the first via near the display area, the third via being electrically connected to the second lead segment and the third lead segment.

8. The display substrate according to claim 7, wherein, The touch insulating layer covers the third via and at least a portion of the third lead segment.

9. The display substrate according to claim 1, wherein, The second via is located in the orthographic projection of the substrate, where the second opening is located in the orthographic projection of the substrate.

10. The display substrate according to claim 1, wherein the display substrate further comprises a plurality of pads located on the side of the bending region away from the display area; The display substrate further includes a test circuit located between the bending area and the plurality of pads, with the other end of the first lead segment electrically connected to the test circuit.

11. The display substrate according to claim 10, wherein, The test circuit includes multiple test units, at least one of which includes a first transistor and a second transistor. The control terminals of the first transistor and the second transistor are connected to a test control line. The first terminals of the first transistor and the second transistor are configured to be electrically connected to a data line. The second terminal of the first transistor is configured to be electrically connected to the first crack detection line, and the second terminal of the second transistor is configured to be electrically connected to the detection data line.

12. The display substrate according to claim 10, wherein, The other end of the fourth lead segment is electrically connected to at least one of the plurality of pads.

13. The display substrate according to claim 1, wherein, The display area includes a first edge, a second edge, a third edge, and a fourth edge connected in sequence, and the first via is located in the peripheral area near the first edge.

14. The display substrate according to claim 13, wherein, The second lead segment is located in the peripheral area close to the first edge, the second edge, the third edge, and the fourth edge; The third lead segment is located in the peripheral area close to the first edge, the second edge, the third edge and the fourth edge; The display area includes a camera hole, and the third lead segment is wound around the camera hole.

15. The display substrate of claim 13, further comprising a second crack detection line and a plurality of pads, the second crack detection line being located in the peripheral region and at least partially surrounding the display region, the plurality of pads being located on the side of the bending region away from the display region, the second crack detection line comprising a first end and a second end, the first end and the second end being respectively connected to at least one of the plurality of pads.

16. The display substrate according to claim 15, wherein, The second crack detection line is symmetrical about the center line of the display area.

17. The display substrate according to claim 15, wherein, The first crack detection line includes a first sub-line and a second sub-line, and the second crack detection line includes a third sub-line and a fourth sub-line, wherein: The first sub-line is located in the peripheral area near the third edge and the fourth edge, and the second sub-line is located in the peripheral area near the second edge and the third edge; The third sub-line is located in the peripheral area near the third and fourth edges, and the fourth sub-line is located in the peripheral area near the second and third edges.

18. The display substrate according to claim 1, wherein, The first via includes two, and the second via includes two. The two first vias are symmetrical about the center line of the display area, and the two second vias are symmetrical about the center line of the display area.

19. The display substrate according to claim 1, wherein, The first via and the second via are located between the display area and the bending area.

20. The display substrate according to claim 1, wherein, The driving circuit layer includes an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are sequentially stacked on the substrate. The first lead segment, the second lead segment, and the fourth lead segment are disposed on the same layer as any one or more of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer. The third lead segment is disposed on the same layer as the touch electrode layer.

21. A display device comprising a display substrate as described in any one of claims 1 to 20.

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