Electrostatic discharge and electrical overload detection circuits

Abstract

This application discloses a detection circuit for electrostatic discharge (ESD) and electrical overload (EDL). The detection circuit includes a protection circuit, a sensing circuit, a clamping circuit, and several stages of sequentially connected sampling logic and storage circuits. The protection circuit is coupled between the input / output pins and the internal chip and discharges to the power supply when an ESD or EDL event occurs. The sensing circuit and clamping circuit are coupled between the power supply and ground. Each stage of sampling logic is coupled to the power supply and a storage cell of the storage circuit. The first stage of sampling logic is coupled to the clamping circuit. When an ESD or EDL event occurs, the several stages of sampling logic sequentially sample the power supply voltage and change the state of the corresponding storage cell, thereby recording the ESD and EDL events sequentially in the storage cell. This application can record ESD or EDL events on the input / output pins coupled to the internal chip, and can be used to analyze the number and stage of ESD or EDL events.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor technology, and in particular to a detection circuit for electrostatic discharge and electrical overload. Background Technology

[0002] Electrostatic discharge (ESD) refers to the electrostatic discharge process accumulated on a chip. Electrical overstress (EOS) refers to the voltage or current applied to a chip exceeding its maximum specifications during operation. Both ESD and EOS can cause serious damage to chips or systems; statistics show that ESD and EOS failures account for more than 20% of all chip failures. Based on the discharge mode, ESD can be divided into human body mode (HBM), charged device mode (CDM), and machine mode (MM). ESD discharge time is typically from tens of nanoseconds to tens of microseconds, while EOS discharge time is typically longer than milliseconds. The main difference is that ESD is a high-voltage, short-duration discharge process with relatively low total energy released, while EOS is a low-voltage, long-duration discharge process with relatively high total energy released. ESD or EOS events can occur during chip manufacturing, transportation, testing, and use. However, with the reduction in device size and the thinning of the gate oxide layer, the impact of ESD and EOS on chips becomes more severe.

[0003] However, traditional designs can only prevent and protect against ESD and EOS events, but cannot detect their occurrence. Once a serious ESD or EOS event occurs in a chip, its functionality or reliability is affected, and this can only be discovered during product application.

[0004] Therefore, a circuit capable of detecting electrostatic discharge and electrical overload events is needed. Summary of the Invention

[0005] The purpose of this invention is to provide a detection circuit for electrostatic discharge and electrical overload, which can record electrostatic discharge and electrical overload events on input / output pins, and can determine the number and stage of electrostatic discharge and electrical overload events based on the records.

[0006] This application discloses a detection circuit for electrostatic discharge (ESD) and electrical overload (EOD) events on input / output pins coupled to an internal chip. The detection circuit includes a protection circuit, a sensing circuit, a clamping circuit, and several stages of sequentially connected sampling logic and storage circuits. The protection circuit is coupled between the input / output pin and the internal chip and discharges to the power supply when an ESD or EOD event occurs. The sensing circuit and the clamping circuit are coupled between the power supply and ground. Each stage of the sampling logic is coupled to the power supply and a storage cell of the storage circuit. The first stage of the sampling logic is coupled to the clamping circuit. When an ESD or EOD event occurs, the several stages of sampling logic sample the power supply voltage step by step and change the state of the corresponding storage cell, thereby the storage cell sequentially records the ESD or EOD event.

[0007] In a preferred embodiment, the clamping circuit includes a first inverter and an NMOS transistor, the input of the first inverter being coupled to the output of the sensing circuit, the output of the first inverter being coupled to the gate of the NMOS transistor, the drain of the NMOS transistor being coupled to the power supply terminal, and the source of the NMOS transistor being coupled to the ground terminal.

[0008] In a preferred embodiment, the first stage of the sampling logic in the plurality of sampling stages includes a second inverter and a PMOS transistor, and the other stages of the sampling logic in the plurality of sampling stages include NAND gates and PMOS transistors. The input terminal of the second inverter and the first input terminal of each NAND gate are coupled to the output terminal of the first inverter. The output terminal of the second inverter is coupled to the gate of the PMOS transistor in this stage. The output terminal of each NAND gate is coupled to the gate of the PMOS transistor in this stage. The source of each PMOS transistor is coupled to the power supply terminal. The drain of each PMOS transistor is coupled to the first terminal of the memory cell in this stage. The second input terminal of each NAND gate is coupled to the third terminal of the memory cell in the previous stage.

[0009] In a preferred embodiment, the storage cell is an antifuse storage cell, and the second end of the antifuse storage cell is coupled to the power supply terminal; when an electrostatic discharge or electrical overload event occurs on the input / output pin, the gate oxide layer of the antifuse storage cell is broken down, and the drain of the PMOS transistor is connected to the second input terminal of the next stage NAND gate.

[0010] In a preferred embodiment, the storage cell is an antifuse storage cell. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the gate oxide layer of the antifuse storage cell is broken down, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate.

[0011] In a preferred embodiment, the storage cell is one of a flash memory cell, a magnetic random access memory cell, or a resistive random access memory cell, and another end of the storage cell is coupled to the power supply terminal; when an electrostatic discharge or electrical overload event occurs on the input / output pin, the storage cell is erased, and the drain of the PMOS transistor is connected to the second input terminal of the next stage NAND gate.

[0012] In a preferred embodiment, the first stage of the sampling logic in the plurality of sampling stages includes a second inverter and a PMOS transistor, and the other stages of the sampling logic each include a NAND gate and a PMOS transistor. The input terminal of the second inverter and the first input terminal of each NAND gate are coupled to the output terminal of the first inverter. The output terminal of the second inverter is coupled to the gate of the PMOS transistor in this stage. The output terminal of each NAND gate is coupled to the gate of the PMOS transistor in this stage. The source of each PMOS transistor is coupled to the power supply terminal. The drain of each PMOS transistor is coupled to one end of the corresponding memory cell and the second input terminal of the NAND gate in the next stage. The other end of the memory cell is coupled to the ground terminal.

[0013] In a preferred embodiment, the memory cell is a one-time programmable memory cell. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the one-time programmable memory cell is disconnected, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate.

[0014] In a preferred embodiment, a readout circuit is further included, which is coupled to the storage circuit and reads out the state of each of the storage cells for analyzing the number and stage of the electrostatic discharge and electrical overload events.

[0015] In a preferred embodiment, when an electrostatic discharge or electrical overload event occurs on the input / output pin, a storage cell of the storage circuit transitions from a first state to a second state.

[0016] In a preferred embodiment, the protection circuit includes a first-level protection unit and a second-level protection unit. Each of the first-level and second-level protection units includes a first diode and a second diode. The anode of the first diode is coupled to the input / output pin, and the cathode of the first diode is coupled to the power supply terminal. The anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to the input / output pin. A resistor is coupled between the first-level and second-level protection units. One end of the resistor is coupled to the node between the input / output pin and the first diode and the second diode in the first-level protection unit, and the other end is coupled to the internal chip and the node between the first diode and the second diode in the second-level protection unit.

[0017] The electrostatic discharge (ESD) and electrical overload (EOD) detection circuit of this application detects and records ESD / EOS events through logic gates and memory in the circuit. By analyzing the ESD / EOS events recorded in the memory, the number and stage of ESD and EOD events can be determined, thereby enabling early detection and rapid identification of problematic chips. On the one hand, this can prevent chips subjected to ESD / EOS impacts during production and testing from flowing into customers and end-users and causing serious quality problems. On the other hand, it can provide support for optimizing design and solving problems at the source based on the recorded information.

[0018] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0019] Figure 1 A schematic diagram of an electrostatic discharge and electrical overload detection circuit according to an embodiment of this application is shown.

[0020] Figure 2A schematic diagram of the current flow in the detection circuit is shown when a first electrostatic discharge or electrical overload event occurs according to an embodiment of this application.

[0021] Figure 3 A schematic diagram of the current flow in the detection circuit when a second electrostatic discharge or electrical overload event occurs according to an embodiment of this application is shown.

[0022] Figure 4 A schematic diagram of an electrostatic discharge and electrical overload detection circuit according to an embodiment of this application is shown.

[0023] Figure 5 A schematic diagram of the current flow in the detection circuit when an electrostatic discharge or electrical overload event occurs, according to an embodiment of this application, is shown. Detailed Implementation

[0024] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0026] One embodiment of this application provides an electrostatic discharge and electrical overload detection circuit for recording electrostatic discharge and electrical overload events on input / output pins coupled to an internal chip. Figure 1 A schematic diagram of a detection circuit 100 in one embodiment of this application is shown. The detection circuit 100 includes: a protection circuit 110, a sensing circuit 120, a clamping circuit 130, several stages of sequentially connected sampling logic 140, and a storage circuit 150. The protection circuit 110 is coupled between the input / output pin 160 and the internal chip 170 and discharges to the power supply terminal VDD in the event of electrostatic discharge or electrical overload. The sensing circuit 120 is coupled between the power supply terminal VDD and the ground terminal GND, and determines whether an electrostatic discharge or electrical overload event has occurred on the input / output pin 160 based on the voltage at the power supply terminal VDD. The clamping circuit 130 is coupled between the power supply terminal VDD and the ground terminal GND, and is used to discharge the overcharge voltage on the power supply terminal VDD to the ground terminal GND, thereby clamping the power supply terminal VDD. Each stage of sampling logic 140 is coupled to the power supply terminal VDD and a storage cell of the storage circuit 150. For example, Figure 1Taking sampling logics 141, 142, and 143 as examples, the first-level sampling logic 141 is coupled to storage cell 151, the second-level sampling logic 142 is coupled to storage cell 152, the third-level sampling logic 143 is coupled to storage cell 153, and so on. Furthermore, the first-level sampling logic 141 is coupled to the clamping circuit 130. When an electrostatic discharge or electrical overload event occurs, the sampling logics 140 sequentially sample the voltage of the power supply terminal VDD and change the state of the corresponding storage cell in the storage circuit 150, thereby the storage circuit 150 sequentially records the electrostatic discharge and electrical overload events.

[0027] In one embodiment, the protection circuit 110 includes a first-level protection unit 111 and a second-level protection unit 112. Each of the first-level protection unit 111 and the second-level protection unit 112 includes a corresponding first diode D11, D21 and a corresponding second diode D12, D22. The anodes of the first diodes D11 and D21 are coupled to the input / output pin 160, and the cathodes of the first diodes D11 and D21 are coupled to the power supply terminal VDD. The anodes of the second diodes D12 and D22 are coupled to the ground terminal GND, and the cathodes of the second diodes D12 and D22 are coupled to the input / output pin 160. A resistor R is coupled between the first-level protection unit 111 and the second-level protection unit 112. One end of the resistor R is coupled to the node between the input / output pin 160 and the first diode D11 and the second diode D12 in the first-level protection unit 111, and the other end is coupled to the internal chip 170 and the node between the first diode D21 and the second diode D22 in the second-level protection unit 112.

[0028] In one embodiment, the clamping circuit 130 includes a first inverter INV1 and an NMOS transistor N1. The input terminal of the first inverter INV1 is coupled to the output terminal of the sensing circuit 120, the output terminal of the first inverter INV1 is coupled to the gate of the NMOS transistor N1, the drain of the NMOS transistor N1 is coupled to the power supply terminal VDD, and the source of the NMOS transistor N1 is coupled to the ground terminal GND.

[0029] In one embodiment, the first-stage sampling logic 141 includes a second inverter INV2 and a PMOS transistor P1, while the other stages of sampling logic include NAND gates and PMOS transistors. For example, the second-stage sampling logic 142 includes a NAND gate NAND1 and a PMOS transistor P2, the third-stage sampling logic 143 includes a NAND gate NAND2 and a PMOS transistor P3, and so on. The input of the second inverter INV2 and the first input of each NAND gate (e.g., NAND1, NAND2) are coupled to the output of the first inverter INV1. The output of the second inverter INV2 is coupled to the gate of the PMOS transistor P1 in this stage. The output of each NAND gate is coupled to the gate of the PMOS transistor in this stage; for example, the output of NAND gate NAND1 is coupled to the gate of PMOS transistor P2, the output of NAND gate NAND2 is coupled to the gate of PMOS transistor P3, and so on. The source of each PMOS transistor is coupled to the power supply terminal VDD, the drain of each PMOS transistor is coupled to the first terminal of the memory cell of the same level, and the second input of each NAND gate is coupled to the third terminal of the memory cell of the previous level. For example, the drain of PMOS transistor P1 of the first-level sampling logic 141 is coupled to the first terminal of the first-level memory cell 151, the second input of NAND gate NAND1 of the second-level sampling logic 142 is coupled to the third terminal of the first-level memory cell 151, the drain of PMOS transistor P2 of the second-level sampling logic 142 is coupled to the first terminal of the second-level memory cell 152, the second input of NAND gate NAND3 of the third-level sampling logic 143 is coupled to the third terminal of the second-level memory cell 152, and so on.

[0030] It is important to note that Figure 1 and Figure 2 In the embodiment shown, the protection circuit 110 includes two levels of protection circuits and employs logic 140, which includes at least three levels of sampling logic, but this application is not limited thereto.

[0031] In this application, the storage cell of the storage circuit 150 can be a storage cell with one or more bits. When an electrostatic discharge or electrical overload event occurs at the input / output pin 160, one of the storage cells in the storage circuit 150 transitions from a first state to a second state. For example, in one embodiment, the storage cell transitions from a low level (or "0") to a high level (or "1"). It should be understood that in other embodiments of this application, the storage cell may also transition from a high level (or "1") to a low level (or "0").

[0032] In one embodiment, the storage circuit 150 may have storage cells ranging from 8 bits to 128 bits, such as 32 bits, 64 bits, etc. Integrated circuit chips typically have multiple input / output pins, each of which is susceptible to electrostatic discharge (ESD) or electrical overload events. In one embodiment, a storage circuit may be used to record ESD and electrical overload events of multiple input / output pins; for example, a portion of the storage cells in the storage circuit (e.g., storage cells in a row of a storage array) records an ESD and electrical overload event occurring on one input / output pin.

[0033] In one embodiment, the storage cell is an anti-fuse memory cell, and the second terminal of the anti-fuse memory cell is coupled to the power supply terminal VDD. (Continue to the previous section) Figure 1 As shown, the antifuse memory cell has a first terminal (PG), a second terminal (SG), and a third terminal (S), wherein the first terminal is the gate of the programming transistor, the second terminal is the gate of the select transistor, and the third terminal is the source. The first terminal is coupled to the drain of the PMOS transistor, the second terminal is coupled to the power supply terminal, and the third terminal is coupled to the input terminal of the NAND gate of the next-stage memory cell. An insulating layer (e.g., gate oxide layer 1511) is respectively provided between the substrates of the first and second terminals (the substrates are at the same potential as the third terminal). When an electrostatic discharge or electrical overload event occurs on the input / output pin 160, the PMOS transistor of the first-stage sampling logic is turned on. The overcharge generated on the power supply terminal VDD flows to the first terminal of the memory cell and breaks down the gate oxide layer between the first terminal and the substrate. At the same time, the selected power supply VDD is turned on, and the channel below it is in the on state. This turns on the first and third terminals, causing the memory state of the memory cell to change (from unprogrammed to programmed), thereby recording the electrostatic discharge or electrical overload event. It also turns on the drain of the PMOS transistor and the second input terminal of the next stage NAND gate.

[0034] Figure 2 The diagram illustrates the current flow within the detection circuit when the first electrostatic discharge (ESD) or electrical overload event occurs on input / output pin 160. Current flows from the first diodes D11 and D21 of the protection circuit to the power supply terminal VDD. The sensing circuit 120 detects the ESD or electrical overload event and activates the clamping circuit 130 and the first-stage sampling logic 141. Part of the charge is discharged to ground GND through the clamping circuit 130, and part of the charge flows through the PMOS transistor P1 to the first terminal of the storage cell 151, breaking down the gate oxide layer between the first terminal and the substrate. The storage cell 151 transitions from a low level to a high level, thus recording the first ESD or electrical overload event. Furthermore, the PMOS transistor P2 of the sampling logic 142 is turned on. Figure 3A schematic diagram of the current flow within the detection circuit is shown when a second electrostatic discharge (ESD) or electrical overload event occurs. When another ESD or electrical overload event occurs, some charge flows through the PMOS transistor P2 to the first terminal of storage cell 152 and breaks down the gate oxide layer between the first terminal and the substrate. Storage cell 152 then transitions from a low level to a high level, thus recording the second ESD or electrical overload event. When a subsequent ESD or electrical overload event occurs, storage cell 153 transitions from a low level to a high level, thus recording that ESD or electrical overload event. This process continues, allowing the detection circuit of this embodiment to record each ESD or electrical overload event.

[0035] Table 1 shows the NAND gate delay under different processes. Parameters for electrostatic discharge (ESD) or electrical overload events are shown in Table 2. As can be seen from Tables 1 and 2, the NAND gate delay is on the order of tens of picoseconds (ps), while the rise time of the current during an ESD or electrical overload event is typically on the order of hundreds of picoseconds (ps) to nanoseconds (ns), or even milliseconds (ms), all significantly longer than the NAND gate delay. Therefore, the NAND gate's opening speed is sufficient to respond to ESD or electrical overload events.

[0036] Table 1. Delay of NAND gates under different processes.

[0037] process NAND gate delay 40nm 30-50ps 28 / 22nm 25-40ps 16nm 20-30ps

[0038] Table 2 Parameters for electrostatic discharge or electrical overload events

[0039]

[0040] It should be noted that the energy generated during an electrostatic discharge (ESD) or electrical overload event typically alters the state of a single memory cell, for example, a moderate level ESD or electrical overload event, such as below 2 kV for HBM or below 500 V for CDM. However, in some extreme cases, the energy generated may alter the state of two memory cells, for example, a high level ESD or electrical overload event, such as above 4 kV for HBM or above 800 V for CDM.

[0041] After integrated circuit chip manufacturing is completed, it may go through stages such as wafer probing (CP testing), packaging, final testing (FT testing), lab testing, user assembly line, and user application. Each stage may include different sub-stages. Electrostatic discharge (ESD) or electrical overload events may occur at any stage of the integrated circuit chip. The detection circuit of this application can record ESD or electrical overload events occurring at each stage in a storage circuit.

[0042] In one embodiment, the detection circuit 100 further includes a readout circuit (not shown) coupled to the storage circuit 150 and reads the state of each storage cell for analyzing the number and stage of the electrostatic discharge and electrical overload events. Table 3 shows the state of the storage circuit in one embodiment.

[0043] Table 3: Status Table of Storage Circuit

[0044]

[0045]

[0046] One embodiment of this application provides a detection circuit for electrostatic discharge and electrical overload. The detection circuit of this embodiment (not shown in the figure) is similar to that of the previous embodiment. Figures 1 to 3 The detection circuit 100 shown has a basically the same structure, with the main difference being: in this embodiment, the storage cell is one of a flash memory cell, a magnetic random access memory (MRAM) cell, or a resistive random access memory (RRAM) cell. The drain of each PMOS transistor is coupled to the first terminal of the storage cell in its current stage, and the second input terminal of each NAND gate is coupled to the third terminal of the storage cell in the previous stage. The second terminal of the storage cell is coupled to the power supply terminal. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the storage cell is erased, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate.

[0047] Taking a flash memory cell as an example, the first terminal of the flash memory cell is the control gate (CG), the second terminal is the drain (D), and the third terminal is the source (S). The control gate is coupled to the drain of the PMOS transistor, the drain is coupled to the power supply terminal, and the source is coupled to the input terminal of the NAND gate in the next stage of the memory cell. An insulating layer (e.g., gate oxide layer) is provided between the control gate and the drain and the source, respectively. When an electrostatic discharge or electrical overload event occurs on the input / output pin 160, the PMOS transistor of the first-stage sampling logic is turned on. The overcharge generated on the power supply terminal VDD flows to the control gate of the memory cell, generating a momentary high voltage. This high voltage generates a strong electric field between the control gate and the floating gate. Under the influence of this strong electric field, electrons in the floating gate are collected by the control gate through tunneling, causing a change in the storage state of the memory cell, thus recording the electrostatic discharge and electrical overload event. This also enables the drain of the PMOS transistor to conduct between the second input terminal of the next-stage NAND gate.

[0048] Figure 4A schematic diagram of an electrostatic discharge and electrical overload detection circuit 200 according to an embodiment of this application is shown. The protection circuit 210, sensing circuit 220, clamping circuit 230 and sampling logic 240 have the same structure as the protection circuit 110, sensing circuit 120, clamping circuit 130 and sampling logic 140 in Embodiment 1, and will not be described again here.

[0049] The first-level sampling logic 241 includes a second inverter INV2 and a PMOS transistor P1, while the other levels of sampling logic include NAND gates and PMOS transistors. For example, the second-level sampling logic 242 includes a NAND gate NAND1 and a PMOS transistor P2, the third-level sampling logic 243 includes a NAND gate NAND2 and a PMOS transistor P3, and so on. The storage circuit 250 includes several storage cells, such as storage cells 251, 252, and 253. In this embodiment, the storage cells 251, 252, and 253 are one-time programmable storage cells (eFuse memory cells). The drain of each PMOS transistor is coupled to one end of the corresponding storage cell and the second input terminal of the next-level NAND gate, and the other end of the storage cell is coupled to ground. For example, the drain of PMOS transistor P1 is coupled to one end of memory cell 251 and the second input terminal of NAND gate NAND1, and the other end of memory cell 251 is coupled to ground GND. The drain of PMOS transistor P2 is coupled to one end of memory cell 252 and the second input terminal of NAND gate NAND2, and the other end of memory cell 252 is coupled to ground GND, and so on.

[0050] In one embodiment, when an electrostatic discharge (ESD) or electrical overload event occurs on the input / output pin 260, the one-time programmable memory cell is disconnected, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate. Specifically, the overcharge generated on the power supply terminal VDD flows to the one-time programmable memory cell, causing a change in the storage state of the memory cell to record the ESD or electrical overload event, and also connecting the drain of the PMOS transistor to the second input terminal of the next-stage NAND gate. Figure 5 This diagram illustrates the current flow within the detection circuit when the first electrostatic discharge or electrical overload event occurs in this embodiment. The overcharge generated on the power supply terminal VDD flows to the storage cell 251, causing the storage cell 251 to be disconnected, and the overcharge then flows to the input terminal of the NAND gate NAND1.

[0051] It should be noted that the energy requirements per bit for different types of storage units are shown in Table 4. Combined with the energy requirements of different types of ESD / EOS in Table 2, it can be seen that the corresponding relationship between different types of storage units for electrostatic discharge and electrical overload is shown in Table 4. In this embodiment, different types of storage units can be selected as needed.

[0052] Table 4: Correspondence between storage cells and electrostatic discharge and electrical overload

[0053] Storage unit type Programming Time Programming current Energy requirements (per bit) Applicable Applications Flash <10us <10uA 10~100pJ ESD / EOS eFuse 15us 30mA 3~10nJ EOS Anti-Fuse 5us 5mA 0.1nJ ESD / EOS MRAM 100ns <5uA 0.1pJ ESD / EOS RRAM 1us 1uA 0.1pJ ESD / EOS

[0054] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0055] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0056] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0057] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A detection circuit for electrostatic discharge and electrical overload, used to record electrostatic discharge and electrical overload events on input / output pins coupled to an internal chip, characterized in that, The detection circuit includes a protection circuit, a sensing circuit, a clamping circuit, and several levels of sequentially connected sampling logic and storage circuits. The protection circuit is coupled between the input / output pin and the internal chip and discharges to the power supply terminal when an electrostatic discharge or electrical overload event occurs. The sensing circuit and the clamping circuit are coupled between the power supply terminal and the ground terminal. Each level of sampling logic is coupled to the power supply terminal and a storage cell of the storage circuit. The first level of sampling logic is coupled to the clamping circuit. When the electrostatic discharge or electrical overload event occurs, the several levels of sampling logic sample the power supply terminal voltage step by step and change the state of the corresponding storage cell, thereby recording the electrostatic discharge or electrical overload event sequentially through the storage cell.

2. The detection circuit for electrostatic discharge and electrical overload according to claim 1, characterized in that, The clamping circuit includes a first inverter and an NMOS transistor. The input terminal of the first inverter is coupled to the output terminal of the sensing circuit, the output terminal of the first inverter is coupled to the gate of the NMOS transistor, the drain of the NMOS transistor is coupled to the power supply terminal, and the source of the NMOS transistor is coupled to the ground terminal.

3. The electrostatic discharge and electrical overload detection circuit according to claim 2, characterized in that, The first level of the sampling logic in the plurality of sampling levels includes a second inverter and a PMOS transistor. The other levels of the sampling logic each include a NAND gate and a PMOS transistor. The input terminal of the second inverter and the first input terminal of each NAND gate are coupled to the output terminal of the first inverter. The output terminal of the second inverter is coupled to the gate of the PMOS transistor in this level. The output terminal of each NAND gate is coupled to the gate of the PMOS transistor in this level. The source of each PMOS transistor is coupled to the power supply terminal. The drain of each PMOS transistor is coupled to the first terminal of the memory cell in this level. The second input terminal of each NAND gate is coupled to the third terminal of the memory cell in the previous level.

4. The electrostatic discharge and electrical overload detection circuit according to claim 3, characterized in that, The second end of the storage cell is coupled to the power supply terminal; when an electrostatic discharge or electrical overload event occurs on the input / output pin, the drain of the PMOS transistor is connected to the second input terminal of the next stage NAND gate.

5. The electrostatic discharge and electrical overload detection circuit according to claim 4, characterized in that, The storage cell is an antifuse storage cell. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the gate oxide layer of the antifuse storage cell is broken down, and the drain of the PMOS transistor is connected to the second input terminal of the next stage NAND gate.

6. The electrostatic discharge and electrical overload detection circuit according to claim 4, characterized in that, The storage unit is a flash memory storage unit, a magnetic random access memory unit, or a resistive random access memory unit. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the storage unit is erased, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate.

7. The electrostatic discharge and electrical overload detection circuit according to claim 2, characterized in that, The first level of the sampling logic in the plurality of sampling levels includes a second inverter and a PMOS transistor. The other levels of the sampling logic each include a NAND gate and a PMOS transistor. The input terminal of the second inverter and the first input terminal of each NAND gate are coupled to the output terminal of the first inverter. The output terminal of the second inverter is coupled to the gate of the PMOS transistor in this level. The output terminal of each NAND gate is coupled to the gate of the PMOS transistor in this level. The source of each PMOS transistor is coupled to the power supply terminal. The drain of each PMOS transistor is coupled to one end of the corresponding memory cell and the second input terminal of the next level NAND gate. The other end of the memory cell is coupled to the ground terminal.

8. The electrostatic discharge and electrical overload detection circuit according to claim 6, characterized in that, The storage unit is a one-time programmable storage unit. When an electrostatic discharge or electrical overload event occurs on the input / output pin, the one-time programmable storage unit is disconnected, and the drain of the PMOS transistor is connected to the second input terminal of the next-stage NAND gate.

9. The detection circuit for electrostatic discharge and electrical overload according to claim 1, characterized in that, It also includes a readout circuit coupled to the storage circuit and reads out the state of each of the storage cells for analyzing the number and stage of the electrostatic discharge and electrical overload events.

10. The electrostatic discharge and electrical overload detection circuit according to claim 1, characterized in that, When an electrostatic discharge or electrical overload event occurs on the input / output pin, one of the storage cells of the storage circuit transitions from a first state to a second state.

11. The electrostatic discharge and electrical overload detection circuit according to claim 1, characterized in that, The protection circuit includes a first-level protection unit and a second-level protection unit. Each of the first-level protection unit and the second-level protection unit includes a first diode and a second diode. The anode of the first diode is coupled to the input / output pin, and the cathode of the first diode is coupled to the power supply terminal. The anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to the input / output pin. A resistor is coupled between the first-level protection unit and the second-level protection unit. One end of the resistor is coupled to the node between the input / output pin and the first diode and the second diode in the first-level protection unit, and the other end is coupled to the internal chip and the node between the first diode and the second diode in the second-level protection unit.

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