A flash memory control system and flash memory device thereof

Abstract

The application provides a flash memory control system and a flash memory device thereof, which comprises a command receiving queue, a command returning queue, a DMA controller, a processor and a command execution module, wherein the processor comprises a data memory. The flash memory control system and the flash memory device thereof provided by the application transmit flash memory operation instructions and execution state information through the DMA controller, and the hardware DMA mode can effectively improve the command interaction speed, and the hardware automatic state information reading function can effectively reduce the system consumption. The processor processes the information in the data memory to complete the analysis of the flash memory operation command, thereby avoiding the high latency caused by bus access and greatly improving the execution efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flash memory, in particular to a flash memory control system and a flash memory device thereof. BACKGROUND

[0002] With the iteration of NAND Flash technology, the Flash operation instruction is more and more complex, and the design of the Flash controller also needs to be updated synchronously, and the complexity is also higher and higher. After the Program / Read / Erase operation of the Flash particle, the command execution result information needs to be obtained through the poll status command (status information command). During this period, the Flash controller needs to continuously issue the poll status command to the Flash particle to obtain information until the valid execution result information is obtained.

[0003] In the process of conceiving and implementing the present application, the inventors found that at least the following problems exist: the complexity of the Flash operation instruction is higher and higher, and the pure hardware design cannot match the constantly updated Flash operation instruction; the repeated poll status operation in the original Flash controller consumes a lot of system resources, has high cost and low efficiency.

[0004] The foregoing description is directed to providing general background information and does not necessarily constitute prior art. SUMMARY

[0005] In order to alleviate the above problems, the present application provides a flash memory control system and a flash memory device thereof.

[0006] In one aspect, the present application provides a flash memory control system, specifically comprising a command receiving queue, a command returning queue, a DMA controller, a processor, a command execution module, the processor comprising a data storage;

[0007] The command receiving queue is used to receive a flash operation instruction;

[0008] The DMA controller is connected with the command receiving queue, and is used to copy the flash operation instruction into the data storage;

[0009] The processor is connected with the command execution module, and is used to analyze the flash operation instruction in the data storage, and send the generated flash operation information to the command execution module for corresponding operation;

[0010] The command execution module is used to execute the flash operation information, and send the command status information to the processor after the execution is completed, so that the processor writes the execution status information into the data storage;

[0011] The DMA controller is also connected with the command return queue, for copying the execution status information to the command return queue, so that the command return queue returns the execution status information of the flash operation instruction.

[0012] Optionally, when the number of instructions in the command receiving queue in the flash control system reaches a preset number or a preset time length, the DMA controller is started to copy the flash operation instruction in the command receiving queue to the data storage.

[0013] Optionally, when the command status information is received by the processor in the flash control system, the DMA controller is started and the execution status information is copied to the command return queue.

[0014] Optionally, the data storage in the flash control system includes a command information register and a command status register.

[0015] The DMA controller copies the flash operation instruction to the command information register for the processor to analyze; the processor writes the execution status information into the command status register, so that the DMA controller copies the execution status information to the command return queue.

[0016] Optionally, the data storage in the flash control system further includes a command operation register, wherein:

[0017] The processor writes the flash operation information into the command operation register, so that the command execution module reads from the command operation register; and / or,

[0018] The command execution module writes the command status information into the command operation register, so that the processor reads from the command operation register.

[0019] Optionally, the flash control system further includes an interface timing module and a driving module.

[0020] The interface timing module is connected with the command execution module, for converting the flash operation instruction generated by the command execution module according to a preset timing;

[0021] The driving module is connected between the flash memory and the interface timing module, for driving the flash memory according to the flash operation instruction.

[0022] Optionally, the flash control system further includes a data transmission module; the data transmission module is connected with the interface timing module, for transmitting read-write data.

[0023] Optionally, the command execution module in the flash memory control system executes a read status information command, and re-executes the read status information command if a preset status is not obtained.

[0024] Optionally, the command execution module in the flash memory control system includes a command parsing state machine and a read status information command queue; when idle, the command parsing state machine retrieves and executes a read status information command from the read status information command queue, and re-adds the read status information command to the read status information command queue before execution is completed; and clears the current read status information command in the read status information command queue after execution is completed.

[0025] On the other hand, this application provides a flash memory device, specifically including interconnected flash memory media and a flash memory control system as described above.

[0026] As described above, the flash memory control system and flash memory device provided in this application transmit flash memory operation instructions and execution status information through a DMA controller. The use of hardware DMA effectively improves command interaction speed, and the hardware automatic status information reading function effectively reduces system power consumption. The processor parses the flash memory operation commands by processing information in the data memory, avoiding the high latency introduced by bus access and greatly improving execution efficiency. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0028] Figure 1 This is a structural diagram of a flash memory control system according to an embodiment of this application.

[0029] Figure 2 For this application Figure 1 A structural diagram of the data storage device based on the embodiment.

[0030] Figure 3 For this application Figure 1 A structural diagram of the flash memory control system based on the embodiment.

[0031] Figure 4 This is an execution flowchart of a command execution module according to an embodiment of this application.

[0032] Figure 5 This is a schematic diagram of command receiving logic according to an embodiment of this application.

[0033] Figure 6 Command return logic diagram for an embodiment of the present application.

[0034] Figure 7 Command execution module internal logic diagram for an embodiment of the present application.

[0035] Figure 8 Command parsing state machine executing a read status information command for an embodiment of the present application.

[0036] The implementation, function features and advantages of the present application will be further described in conjunction with embodiments, with reference to the accompanying drawings. Through the above-mentioned drawings, the explicit embodiments of the present application have been shown, and more detailed description will be given hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, the same numbers are used to indicate the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] It should be noted that, in the present text, the terms "comprising", "containing" or any other variant thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device including the element, in addition, the components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meaning, and the specific meaning thereof should be determined in the explanation of the specific embodiment or further combined with the context in the specific embodiment.

[0039] It should be understood that the specific embodiments described herein are merely intended to explain the present application, and are not intended to limit the present application.

[0040] It should be noted that NAND flash is a better storage device than hard drive, especially in low-capacity applications of no more than 4GB. With the continuous pursuit of lower power consumption, lighter weight and better performance, NAND has proven to be extremely attractive. NAND flash is a non-volatile storage technology that can save data after power off. Its development goal is to reduce the cost of storing each bit and increase the storage capacity.

[0041] First embodiment

[0042] In one aspect, the application provides a flash memory control system, Figure 1 The structure diagram of the flash memory control system of an embodiment of the application is shown in the figure.

[0043] Please refer to Figure 1 In an embodiment, the flash memory control system comprises a command receiving queue 10, a command returning queue 20, a DMA controller 30, a processor 40, a command execution module 50, and the processor 40 comprises a data storage 41.

[0044] For example, DMA (Direct Memory Access) is an important feature of all modern computers, a data transfer mechanism implemented by hardware, which allows different speed hardware devices to communicate without relying on the CPU's heavy interrupt load. The processor 40 is an MCU microcontroller, and the data storage 41 is an MCU DCCM microcontroller data storage 41 that stores the data for the processor 40 code running. Optionally, the processor 40 also comprises an MCU ICCM instruction storage for storing the running instructions of the processor 40.

[0045] The command receiving queue 10 is used to receive flash operation instructions.

[0046] For example, the command receiving queue 10 is used to receive Program commands, Read commands, Erase commands, etc. sent to the NAND Flash.

[0047] The DMA controller 30 is connected with the command receiving queue 10, and is used to copy the flash operation instructions to the data storage 41.

[0048] For example, the DMA controller is used to move the flash operation instructions received by the command receiving queue 10 into the specified position in the data storage 41.

[0049] The processor 40 is connected with the command execution module 50, and is used to analyze the flash operation instructions in the data storage 41, and send the generated flash operation information to the command execution module 50 for corresponding operation.

[0050] For example, the processor 40 directly obtains flash memory operation instructions from the data memory 41, reducing the high latency introduced by bus read and write operations and effectively improving execution efficiency.

[0051] The command execution module 50 is used to execute flash memory operation information and, after execution, sends command status information (i.e., poll status command) to the processor 40 so that the processor 40 writes the execution status information into the data memory 41.

[0052] For example, the command execution module 50 receives flash memory operation instructions parsed by the processor 40 and executes flash memory operation information, such as Read operations, Program operations, and Poll status operations. Optionally, the command execution module 50 comprises a command parsing state machine and a poll status command queue.

[0053] The DMA controller 30 is also connected to the command return queue 20 and is used to copy execution status information to the command return queue 20 so that the command return queue 20 returns the execution status information of the flash memory operation instructions.

[0054] For example, the DMA controller 30 moves the execution status information in the data memory 41 into the command return queue 20, which is used to return the execution status information.

[0055] In this embodiment, the flash memory control system transmits flash memory operation commands and execution status information through the DMA controller 30. Employing hardware DMA effectively improves command interaction speed. The processor 40 processes the information in the data memory 41 to parse the flash memory operation commands, avoiding the high latency introduced by bus access and significantly improving execution efficiency.

[0056] In one embodiment, when the number of instructions in the command receiving queue 10 of the flash memory control system reaches a preset number or a preset duration, the DMA controller 30 is activated to copy the flash memory operation instructions in the command receiving queue 10 to the data storage 41.

[0057] For example, the DMA controller 30 is started after the commands in the command receiving queue 10 reach a preset trigger condition (such as quantity or time). Optionally, this application does not limit the size of the preset quantity or preset duration. For example, depending on the application scenario, the preset quantity is 10 commands and the preset duration is 1ms.

[0058] In one embodiment, when the processor 40 in the flash memory control system receives command status information, it starts the DMA controller 30 and copies the execution status information to the command return queue 20.

[0059] For example, after the processor 40 collects the command status information, it starts the DMA controller 30. The DMA controller 30 moves the execution status information in the data memory 41 into the command return queue 20. The use of hardware DMA can effectively improve the command interaction speed.

[0060] Figure 2 For this application Figure 1 A structural diagram of the data storage device based on the embodiment.

[0061] Please see Figure 2 In one embodiment, the data storage 41 in the flash memory control system includes a command information register 42 and a command status register 43.

[0062] The DMA controller 30 copies the flash memory operation instructions to the command information register 42 for the processor 40 to parse; the processor 40 writes the execution status information to the command status register 43 so that the DMA controller 30 copies the execution status information to the command return queue 20.

[0063] For example, the processor 40 parses the flash memory operation instructions in the command information register 42 of the data memory 41, and after the command is executed, stores the execution status information in the command status register 43 of the data memory 41.

[0064] Please continue reading. Figure 2 In one embodiment, the data storage 41 in the flash memory control system further includes a command operation register 44, wherein:

[0065] The processor 40 writes flash memory operation information to the command operation register 44, so that the command execution module 50 can read from the command operation register 44. The command execution module 50 writes command status information to the command operation register 44, so that the processor 40 can read from the command operation register 44.

[0066] For example, the processor 40 sends the generated flash memory operation information to the command execution module 50 through the command operation register 44, and simultaneously receives command status information through the command operation register 44. The command operation register 44 serves as the interaction space between the processor 40 and the backend command execution module 50. In this embodiment, throughout the entire command execution process, the processor 40 directly retrieves information from the space of the data memory 41, reducing the high latency introduced by bus read / write operations and effectively improving execution efficiency.

[0067] Figure 3 For this application Figure 1 A structural diagram of the flash memory control system based on the embodiment.

[0068] Please see Figure 3In one embodiment, the flash memory control system further includes an interface timing module 60 and a driver module 70.

[0069] The interface timing module 60 is connected to the command execution module 50 and is used to convert the flash memory operation instructions generated by the command execution module 50 according to a preset timing. The driver module 70 is connected between the flash memory and the interface timing module 60 and is used to drive the flash memory according to the flash memory operation instructions.

[0070] For example, after receiving a flash memory operation command, the interface timing module 60 generates the corresponding NAND operation timing and sends it to the driver module 70. The driver module 70 then uses drive signals to operate the flash memory through the NAND IO port.

[0071] Please continue reading. Figure 3 In one embodiment, the flash memory control system further includes a data transmission module 80. The data transmission module 80 is connected to the interface timing module 60 and is used to transmit read and write data.

[0072] For example, the data transmission module 80 is used to transmit read and write data from the interface timing module 60 during Read / Program operations.

[0073] In one embodiment, the command execution module 50 in the flash memory control system executes a read status information command, and re-executes the read status information command if a preset status is not obtained.

[0074] For example, the command parsing state machine in the command execution module 50 executes a pollstatus command. If the required status is not obtained, the pollstatus command is added to the pollstatus command queue. For example, pollstatus refers to obtaining the status returned by the flash memory chip after performing a certain operation. Different operations have different status results, and this status information is generally specified by the ONFI protocol, with corresponding descriptions for the flash memory chip. The automatic hardware pollstatus reading function can effectively reduce system power consumption.

[0075] Figure 4 This is an execution flowchart of a command execution module according to an embodiment of this application.

[0076] Please see Figure 4 In one embodiment, the command execution module 50 in the flash memory control system includes a command parsing state machine and a command queue for reading state information.

[0077] When idle, the command parsing state machine retrieves and executes read status information commands from the read status information command queue. If execution is incomplete, the command is re-added to the read status information command queue. After execution is complete, the current read status information command is cleared from the read status information command queue.

[0078] For example, the status information command can be a `poll status` command. When the state machine is idle and no processor 40 issues a command to be executed, a `poll status` command is retrieved from the `poll status` command queue and executed. After `poll status` is completed, the current `poll status` command is cleared; if it is not completed, it is added back to the `poll status` command queue. The command execution module 50 enables the hardware to automatically perform `poll status` during idle periods, reducing the system overhead of `poll status` operations.

[0079] Second Embodiment

[0080] On the other hand, this application provides a flash memory device, specifically including interconnected flash memory media and a flash memory control system as described above.

[0081] In one embodiment, the NAND Flash controller of the flash memory device consists of a command receive queue, a command return queue, a Command / Status DMA, an MCU (microcontroller), an MCU DCCM (microcontroller data memory), an MCU ICCM (microcontroller instruction memory), a command execution module, a data transmission module, an interface timing module, and a PHY (driver module).

[0082] The command receive queue is used to receive Program commands, Read commands, Erase commands, etc., sent to NAND Flash.

[0083] The command return queue is used to return command execution status information.

[0084] The Command / Status DMA module is used to move command information from the command receive queue into the MCU DCCM and to move command execution status information from the MCU DCCM into the command return queue. DMA (Direct Memory Access) is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on a large interrupt load on the CPU. Otherwise, the CPU would need to copy each piece of data from the source to a temporary register and then write them back to the new location. During this time, the CPU would be unavailable for other tasks.

[0085] Figure 5 This is a schematic diagram of command receiving logic according to an embodiment of this application.

[0086] Please refer to Figure 5 Optionally, the command receiving process is as follows:

[0087] Step 1: Once the number of commands in the command receiving queue reaches a preset trigger condition (such as quantity or time), the Command / Status DMA module is started. Optionally, a suitable preset trigger condition can be set according to the specific use case. For example, it can be set to start when the number of commands reaches 10, or it can be set to start again 1ms after the previous start.

[0088] Step 2: The Command / Status DMA module transfers the command information in the command receive queue to the specified location in the MCU DCCM.

[0089] Figure 6 This is a schematic diagram of the command return logic according to an embodiment of this application.

[0090] Please refer to Figure 6 Optionally, the command return process is as follows:

[0091] Step 1: After the MCU collects the command return status, it starts the Command / Status DMA module;

[0092] Step 2: The Command / Status DMA module moves the Command status information (Commandstatus) from the MCU DCCM into the command return queue.

[0093] Optionally, a Direct Memory Access (DMA) data transfer mechanism can be used for command reception and return. This hardware-implemented data transfer mechanism, using DMA to handle commands and command return information instead of relying on the MCU, effectively improves command interaction speed.

[0094] The MCU can parse command info from the DCCM, send the generated Flash operation information to the command execution module through the command operation space, and simultaneously receive command execution status information through the command operation space. After command execution is complete, the command status information is stored in the command status space of the DCCM. Throughout the entire command execution process, the MCU directly obtains information from the DCCM space, reducing the high latency introduced by bus read / write operations and effectively improving execution efficiency.

[0095] The MCU ICCM stands for MCU instruction memory, which is used to store the MCU's operating instructions.

[0096] The MCU DCCM is the MCU's data memory. The MCU DCCM contains MCU code execution data, command info, command status information (Command status), and interaction information with the command execution module (Commandoperation). For details on the internal settings of the MCU data memory, please refer to [link to documentation / reference]. Figure 2 This includes the Command info register, Command status register, and Command operation register. The Command info space stores command information, and the Command status space stores command return status information. These two spaces are the interaction space between the MCU and the front end. The Command operation space is the interaction space between the MCU and the back end command execution module. After the MCU parses the Flash operation information, it fills it into the Command operation space, and the command execution module obtains the command operation information from the corresponding address space.

[0097] Optionally, during the command execution module's execution of commands, the MCU first fills the command operation space with command operation information; then the command execution module retrieves the command operation information from the command operation space.

[0098] Optionally, during the process of the command execution module returning command execution status information, the command execution module first writes status information to the Command operation space after completing the command operation; then the MCU obtains the command execution status from the Command operation space.

[0099] Figure 7 This is a schematic diagram of the internal logic of a command execution module according to an embodiment of this application.

[0100] Please refer to Figure 7 The command execution module receives commands from the MCU, parses them, and executes Flash operations, such as Read, Program, and Poll status operations. It mainly consists of a command parsing state machine and a poll status command queue.

[0101] Figure 8 This is a schematic diagram of a command parsing state machine executing a command to read state information according to an embodiment of this application.

[0102] like Figure 8As shown, when the parsing state machine executes the poll status command, it adds the poll status command to the poll status command queue if it does not obtain the required status.

[0103] Please also refer to Figure 8 and Figure 4 When the state machine is idle and no commands are issued by the MCU, a `poll status` command is retrieved from the `poll status` command queue and executed. After a `poll status` operation is completed, the current `poll status` command is cleared; otherwise, it is added back to the `poll status` command queue. This enables the hardware to automatically perform `poll status` operations during idle periods, reducing the system overhead of `poll status` operations.

[0104] Optionally, the interface timing module is used to generate the corresponding NAND operation timing and send it to the NAND PHY after receiving the NAND Flash operation command.

[0105] Optionally, the driver module PHY is used to operate the NAND Flash via NAND IO by transmitting drive signals.

[0106] Optionally, the data transmission module is used to transmit read and write data from the interface timing module during Read / Program operations.

[0107] As described above, the flash memory control system and flash memory device provided in this application achieve command interaction between the data storage and the front-end module through DMA, thereby improving the command interaction speed. The processor and command execution module interact directly through the data storage, resulting in the fastest interaction speed. The hardware's automatic status information reading function effectively reduces system power consumption.

[0108] The embodiments of the flash memory device provided in this application may include all the technical features of any of the above embodiments. The extended and explanatory content of the specification is basically the same as that of the embodiments of the above methods, and will not be repeated here.

[0109] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0110] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0111] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0112] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0113] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0114] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0116] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A flash memory control system, characterized in that, It includes a command receiving queue, a command returning queue, a DMA controller, a processor, and a command execution module, wherein the processor includes a data storage; The command receiving queue is used to receive flash memory operation instructions; The DMA controller is connected to the command receiving queue and is used to copy the flash memory operation instructions to the data storage. The processor is connected to the command execution module and is used to parse the flash memory operation instructions in the data storage and send the generated flash memory operation information to the command execution module for corresponding operations. The command execution module is used to execute the flash memory operation information and send command status information to the processor after execution, so that the processor writes the execution status information into the data memory. The DMA controller is also connected to the command return queue and is used to copy the execution status information to the command return queue so that the command return queue returns the execution status information of the flash memory operation instruction; The data storage includes a command information register and a command status register; The DMA controller copies the flash memory operation instructions to the command information register for parsing by the processor; the processor writes the execution status information to the command status register so that the DMA controller copies the execution status information to the command return queue; The command execution module executes the command to read status information, and re-executes the command to read status information if the preset status is not obtained; The command execution module includes a command parsing state machine and a read status information command queue. When the command parsing state machine is idle, it retrieves a read status information command from the read status information command queue and executes it. If the execution is not completed, it re-adds the read status information command to the read status information command queue. After execution, the current read status information command in the read status information command queue is cleared.

2. The flash memory control system according to claim 1, characterized in that, When the number of instructions in the command receiving queue reaches a preset number or a preset duration, the DMA controller is activated to copy the flash memory operation instructions in the command receiving queue to the data storage.

3. The flash memory control system according to claim 1, characterized in that, When the processor receives the command status information, it starts the DMA controller and copies the execution status information to the command return queue.

4. The flash memory control system according to claim 1, characterized in that, The data storage also includes a command operation register, wherein: The processor writes the flash memory operation information into the command operation register, so that the command execution module reads from the command operation register; and / or, The command execution module writes the command status information into the command operation register so that the processor can read from the command operation register.

5. The flash memory control system according to claim 1, characterized in that, The flash memory control system also includes an interface timing module and a driver module; The interface timing module is connected to the command execution module and is used to convert the flash memory operation instructions generated by the command execution module according to a preset timing sequence. The driver module is connected between the flash memory and the interface timing module, and is used to drive the flash memory according to the flash operation instructions.

6. The flash memory control system according to claim 5, characterized in that, The flash memory control system also includes a data transmission module; the data transmission module is connected to the interface timing module and is used to transmit read and write data.

7. A flash memory device, characterized in that, It includes interconnected flash memory media and a flash memory control system as described in any one of claims 1-6.

Images