Method and apparatus for extending data operation bit width
By defining new control registers in the MIPS SIMD Architecture for variable vector expansion, the problem of time-consuming and laborious expansion caused by fixed data operation bit width is solved, parallelization capability and performance are improved, costs are reduced, and hardware compatibility is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 上海芯联芯智能科技有限公司
- Filing Date
- 2022-12-30
- Publication Date
- 2026-07-14
AI Technical Summary
The existing MIPS SIMD Architecture has a fixed data operation bit width of 128 bits, which makes it time-consuming, laborious and inefficient to expand the parallelization capability of data processing, requiring MSA instruction set expansion and code rewriting.
By defining new control registers, variable vector expansion can be achieved without changing the original 128-bit mode. The maximum data operation bit width after expansion is determined by the reserved control registers, and the number of arithmetic units is dynamically controlled, avoiding MSA instruction set expansion and code rewriting.
It improves the parallelization capability and performance of data processing, while reducing the cost of expansion, achieving bidirectional compatibility, eliminating the need to rewrite or recompile existing binary code on new hardware, and supporting future bit expansion.
Smart Images
Figure CN116204232B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method and apparatus for extending the data operation bit width. Background Technology
[0002] Traditional general-purpose processors are scalar processors, where each instruction execution yields only one data result. However, applications such as image and signal processing involve a large number of parallel data computations. In these cases, improving data parallelism to enhance computational performance becomes crucial. Therefore, Single Instruction Multiple Data (SIMD) technology was developed.
[0003] MIPS SIMD Architecture (MSA) is a vector instruction set module implemented by MIPS Technologies in the MIPS64 R5, first implemented in its P5600 SoC. MSA is designed to accelerate many compute-intensive applications by enabling general compiler support.
[0004] As processor applications continue to expand, the demand for parallel processing capabilities and performance is also increasing, making hardware architecture parallelism upgrades seem inevitable. However, the data operation width of MSA (Maximum Segmentation Area) is fixed at 128 bits. Therefore, each hardware expansion of parallelism means expanding the MSA instruction set and rewriting the code, which adds extra work, is time-consuming, laborious, and inefficient. Summary of the Invention
[0005] This application provides a method and apparatus for extending the bit width of data operations, which reduces the cost and time consumption of extending the parallelization capability of data processing and improves the extension efficiency.
[0006] On one hand, embodiments of this application provide a method for extending the data operation bit width, including:
[0007] Acquire the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information;
[0008] If the width of the data to be processed is greater than the original data operation bit width before expansion, and less than or equal to the maximum data operation bit width, then the target number of operation units for processing the data to be processed is determined based on the width of the data to be processed and the bit width of a single operation unit.
[0009] The target number is reduced by one and written into the arithmetic unit control register to control the start of the arithmetic unit for the target number, which then processes the data to be processed.
[0010] Optionally, the bit width of the arithmetic unit is the same as the bit width of the original data operation, and the arithmetic unit includes multiple arithmetic logic units, which are used at least for performing operations on integers and floating-point numbers.
[0011] Optionally, it also includes:
[0012] If the width of the data to be processed is less than or equal to the original data operation bit width, then a processing unit is started to process the data to be processed.
[0013] Optionally, determining the extended maximum data operation bit width based on the variable vector information includes:
[0014] Increment the variable vector information by one to obtain the total number of computing units that are in an available state;
[0015] The maximum data operation bit width is determined based on the total number and the bit width of a single arithmetic unit.
[0016] Optionally, it also includes:
[0017] If the width of the data to be processed is greater than the maximum data operation bit width, then the total number of the arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the maximum data operation bit width in the data to be processed.
[0018] For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, a corresponding number of operation units are selected to process the remaining data until the remaining data is processed.
[0019] Optionally, the value stored in the arithmetic unit control register is less than or equal to the value stored in the vector width control register.
[0020] On one hand, embodiments of this application provide an extension device for data operation bit width, including:
[0021] The acquisition module is used to acquire the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information;
[0022] The judgment module is used to determine the target number of operation units for processing the data to be processed based on the width of the data to be processed and the bit width of a single operation unit if the width of the data to be processed is greater than the original data operation bit width before expansion and less than or equal to the maximum data operation bit width.
[0023] The processing module is used to subtract one from the target number and write it into the arithmetic unit control register to control the start of the arithmetic unit for the target number to process the data to be processed.
[0024] Optionally, the bit width of the arithmetic unit is the same as the bit width of the original data operation, and the arithmetic unit includes multiple arithmetic logic units, which are used at least for performing operations on integers and floating-point numbers.
[0025] Optionally, the processing module is further configured to:
[0026] If the width of the data to be processed is less than or equal to the original data operation bit width, then a processing unit is started to process the data to be processed.
[0027] Optionally, the acquisition module is specifically used for:
[0028] Increment the variable vector information by one to obtain the total number of computing units that are in an available state;
[0029] The maximum data operation bit width is determined based on the total number and the bit width of a single arithmetic unit.
[0030] Optionally, the processing module is further configured to:
[0031] If the width of the data to be processed is greater than the maximum data operation bit width, then the total number of the arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the maximum data operation bit width in the data to be processed.
[0032] For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, a corresponding number of operation units are selected to process the remaining data until the remaining data is processed.
[0033] Optionally, the value stored in the arithmetic unit control register is less than or equal to the value stored in the vector width control register.
[0034] On one hand, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the above-described method for extending the data operation bit width.
[0035] On one hand, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described method for extending the data operation bit width.
[0036] In this embodiment, two new control registers are defined using reserved control registers to achieve variable vector expansion without changing the original 128-bit mode. This expands the data operation bit width from the original to a larger one, improving the parallelization capability and performance of data processing without requiring MSA instruction set expansion or code rewriting, thus reducing costs and increasing efficiency. Secondly, this solution supports existing binary code running directly in a new SIMD environment with uncertain bit widths. Existing source code can gain advantages on new hardware through recompilation, and future expansions (e.g., to 512-bit or 1024-bit) do not require rewriting / recompilation. The newly compiled binary code can run on hardware without expansion, achieving bidirectional compatibility. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 A schematic diagram of the software detection bits of MSA provided in the embodiments of this application;
[0039] Figure 2 A schematic diagram of the software detection bits of MSA provided in the embodiments of this application;
[0040] Figure 3 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0041] Figure 4 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0042] Figure 5 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0043] Figure 6 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0044] Figure 7 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0045] Figure 8 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0046] Figure 9 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0047] Figure 10 A schematic diagram illustrating the format of a control register provided in an embodiment of this application;
[0048] Figure 11 A schematic diagram illustrating the format of a source vector register provided in an embodiment of this application;
[0049] Figure 12 A schematic diagram illustrating the format of a source vector register provided in an embodiment of this application;
[0050] Figure 13 A schematic diagram illustrating the format of a source general-purpose register provided in an embodiment of this application;
[0051] Figure 14 A schematic diagram illustrating the format of a destination vector register provided in an embodiment of this application;
[0052] Figure 15 A schematic diagram illustrating the format of a source vector register provided in an embodiment of this application;
[0053] Figure 16 A flowchart illustrating a method for extending the bit width of data operations provided in an embodiment of this application;
[0054] Figure 17 A flowchart illustrating a method for extending the bit width of data operations provided in an embodiment of this application;
[0055] Figure 18 A schematic diagram of the structure of a data operation bit width extension device provided in an embodiment of this application;
[0056] Figure 19 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0057] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0058] For ease of understanding, the terms used in the embodiments of this invention are explained below.
[0059] MIPS architecture: A simple, optimized, and highly scalable Reduced Instruction Set Computer (RISC) architecture. Its basic characteristics include a large number of registers, instructions, and characters, and software-visible pipelined delay slots. These features enable the MIPS architecture to provide high performance per square millimeter and relatively low power consumption in today's SoC designs.
[0060] ISA: Instruction Set Architecture, is the part of computer architecture related to programming. It includes basic data types, instruction sets, registers, addressing modes, memory hierarchy, interrupts, exception handling, and external I / O. It is the interface between software and hardware, a set of standard specifications (published in document form), and does not have a physical form.
[0061] Hart: Hardware Thread, representing an independently running instruction stream. One Hart is equivalent to a virtual CPU.
[0062] Registers are computer memory within the central processing unit (CPU) used to temporarily store instructions, data, and addresses. Registers have limited storage capacity but extremely fast read / write speeds. In computer architecture, registers store intermediate results of calculations performed at a known point in time, accelerating program execution through rapid data access. Registers are located at the top of the memory hierarchy and are the fastest memory the CPU can read and write. Registers are typically measured by the number of bits they can hold; for example, an 8-bit register or a 32-bit register. In the CPU, components containing registers include the instruction register (IR), program counter, and accumulator. Registers are now often implemented as register arrays, but they can also be implemented using individual flip-flops, high-speed core memory, thin-film memory, and other methods on several machines. Types of registers include address registers, general-purpose registers (GPRs), floating-point registers (FPRs), constant registers, special-purpose registers, and vector registers. Vector registers are used to store data obtained by a vector processor executing SIMD instructions.
[0063] Arithmetic Logic Unit (ALU): A combinational logic digital circuit that performs arithmetic or bitwise operations on binary integers. The ALU differs from the floating-point unit (FPU), which operates only on floating-point numbers. The ALU is a fundamental component of many types of computing circuits, including the central processing unit (CPU), FPU, and graphics processing unit (GPU) of a computer. A single CPU, FPU, or GPU may contain multiple ALUs.
[0064] The inputs of an ALU include the data to be processed (also called operands) and an instruction code indicating the type of operation. The output of an ALU is the result of its operation. In many designs, the ALU also has status inputs or outputs to pass information about its previous or current operation between the ALU and an external status register. An ALU is a combinational logic circuit. This means that its output changes as the input changes. Under normal circumstances, the signals input to the ALU are stable, and after a sufficient amount of time (called the "propagation delay") has passed through the circuitry within the ALU, the result of the ALU operation will appear at the ALU output. The external circuitry connected to the ALU is responsible for ensuring that the ALU's input signals are stable throughout the operation and for allowing sufficient time for signal propagation before sampling the ALU's output.
[0065] For example, when performing an addition operation using the ALU, the CPU routes the operand (usually from a register) to the ALU input, while the control unit simultaneously sends a value to the ALU's opcode input to perform the addition operation. At the same time, the CPU routes the ALU's calculation result to a destination register to receive that result. While the CPU waits for the next clock cycle, the ALU input signal must remain stable to pass through the ALU and reach the destination register. When the next clock cycle arrives, the destination register will store the ALU result, and since the ALU operation is complete, the ALU input can now be set for the next ALU operation.
[0066] MSAU: A newly defined arithmetic unit in this application, which contains two 64-bit ALU units and is capable of processing integer, floating-point, and other data operations.
[0067] This application provides a method for extending the data operation bit width, which addresses the problem that the fixed data operation bit width in MSA technology leads to time-consuming, laborious, and inefficient expansion of the parallelization capability of data processing. To more clearly describe the solution in this application, MSA technology will be introduced first.
[0068] MSA (Vector Instruction Set Module) technology is a vector instruction set module implemented by MIPS Technologies in the MIPS64 R5, first implemented in its P5600 SoC. MSA aims to accelerate many compute-intensive applications by enabling general-purpose compiler support. The implementation of MSA technology strictly adheres to RISC design principles. MIPS architects designed MSA using simple instructions, thus reducing implementation complexity. The carefully selected simple SIMD instruction set is not only programmer- and compiler-friendly but also hardware-efficient in terms of speed, area, and power consumption. The MSA technology specification is scalable to accommodate future needs.
[0069] MSA technology complements the mature MIPS architecture with a set of over 150 new instructions that operate on 32 vector registers (8-bit, 16-bit, 32-bit, and 64-bit integer, 16-bit, and 32-bit fixed-point, or 32-bit and 16-bit floating-point data elements). In the current version, MSA technology implements a 128-bit wide vector register shared with the 64-bit wide floating-point unit (FPU) register. MSA version one and subsequent versions all use 128-bit vector instructions.
[0070] MSA technology includes the following features: 32 128-bit vector registers, 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64-bit vector elements; efficient vector parallel arithmetic operations for integers, fixed-point, and floating-point numbers; operations on absolute operands; available rounding and saturation options; full-precision multiplication and multiply-accumulate; conversion between integer, floating-point, and fixed-point data; a complete vector-level comparison and branch instruction set with unconditional flags; vector (1D) and array (2D) shuffling operations; byte-order-independent typed load and store instructions; compliance with the IEEE 754-2008 floating-point arithmetic standard; basic precise floating-point exception signals; predefined scalability for chips with more gates / transistors; acceleration of computationally intensive applications in conjunction with a general-purpose compiler; software-programmable solutions for functions not covered by consumer electronics applications or dedicated hardware; emerging data mining, feature extraction, image and video processing, and human-computer interaction applications; and high-performance scientific computing.
[0071] MSA is performed using the following method: the existence of the MSA implementation is indicated by the Config3MSAP bit (CP0Register 16, Select 3, bit 28), such as... Figure 1 As shown. The MSAP bit is fixed, implemented in hardware, and read-only from the software perspective. Software can determine whether MSA is implemented by checking if the MSAP bit is set. If the MSAP bit is not set, any attempt to execute an MSA instruction will result in an instruction exception. The Config5 MSAEn bit (CP0 Register 16, Select 5, bit 27) is used to determine whether MSA is enabled, such as... Figure 2 As shown. When the MSAEn bit is not set, executing the MSA command will result in an MSA disable exception.
[0072] MSA Control Registers: The control registers are used to record and manage the status and resources of the MSA. For this purpose, the MSA provides two dedicated instructions: CFCMSA (Copy from MSA Control Register) and CTCMSA (Copy to MSA Control Register). The MSA has a total of 32 control registers, of which 8 are currently in use, as follows:
[0073] MSAIR Register: MSA Implementation Register, contains information specifying the MSA identifier. The format of the MSAIR register is as follows: Figure 3 As shown.
[0074] MSACSR Register: MSA Control and Status Register, controls the operation of the MSA unit. The format of the MSACSR register is as follows: Figure 4 As shown.
[0075] MSAAccess Register: The MSA Access Register specifies which of the vector registers W0, ..., W31 defined on 32 architectures is available to software. The format of the MSAAccess register is as follows: Figure 5 As shown.
[0076] The MSASave register (MSA Save Register) specifies which of the 32 architecture-defined vector registers W0, ..., W31 was not saved after a software context switch. The format of the MSASave register is as follows: Figure 6 As shown.
[0077] The MSAModify register (MSA Modify Register) specifies which of the vector registers W0, ..., W31 defined on the 32 architectures was modified (written to). The format of MSAModify is as follows: Figure 7 As shown.
[0078] The MSARequest Register specifies which of the 32 architecture-defined vector registers W0, ..., W31 is currently requested by the MSA or FPU instruction but is not yet available. The format of the MSARequest Register is as follows: Figure 8 As shown.
[0079] MSAMap Register: Specifies the vector register to be mapped. The format of the MSAMap register is as follows: Figure 9 As shown.
[0080] MSAUnmap Register: Specifies the vector register to be unmapped. The format of the MSAUnmap register is as follows: Figure 10 As shown.
[0081] MSA instruction syntax: MSA assembly language encoding uses the following syntax elements:
[0082] func: function / instruction name, such as ADDS_S or ADDS_S indicates signed saturated addition.
[0083] df: The target data format, which can be bytes, half-word, word, double word, or vector itself.
[0084] wd, ws, wt: target, source, and target vector registers, e.g., $w0, ..., $w31.
[0085] rd, rs: General Purpose Registers (GPRs), for example, $0, ..., $31.
[0086] ws[n]: The vector register element with index n, where n is a valid index value of an element in data format df.
[0087] m: An immediate value that is valid as a bit index of the data format df.
[0088] uN, sN: n-bit unsigned or signed values, such as s10, u5.
[0089] iN: a sign-insensitive n-bit value, such as i8.
[0090] The abbreviations for data formats are shown in Table 1 and are appended to the instruction name. The data format abbreviations are the same regardless of the instruction's data type. For example, all integer, fixed-point, and floating-point instructions operating on 32-bit elements use the same word (.W) data format.
[0091] Table 1
[0092] Data format abbreviation Byte, 8-bit .B Halfword, 16-bit .H Word, 32-bit .W Doubleword, 64-bit .D Vector .V
[0093] For example, setting the value of the source vector register $w1 as follows: Figure 11 As shown, the value of the source vector register $w2 is as follows Figure 12 As shown, the value of source general-purpose register $2 is as follows Figure 13 As shown. The sum of the source vector registers $w1 and $w2 is stored in the destination vector register $w5, and the result is as follows. Figure 14 As shown. The value in $2 is expanded into the $w6 register, as follows. Figure 15 As shown.
[0094] Based on the MSA technology described above, embodiments of this application provide a flowchart of a method for extending the bit width of data operations, such as... Figure 16 As shown, the process of this method is executed by a computer device and includes the following steps:
[0095] Step S1601: Obtain the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information.
[0096] Specifically, the MSA has a total of 32 control registers, of which 8 are currently in use. This application utilizes unused reserved registers to define two new MSA control registers, namely the vector width control register (named: MSAWidth Register) and the arithmetic unit control register (named: MSA Enabled Width Register).
[0097] The vector width control register only supports read operations. It stores variable vector information, providing hardware information to the software. The total number of available arithmetic units is determined based on this variable vector information. Then, based on the total number of arithmetic units and the bit width of a single arithmetic unit, the maximum data operation bit width is determined.
[0098] In some embodiments, for older hardware, this control register is disabled and its value defaults to 0. After reading the variable vector information from the vector width control register, the variable vector information is incremented by one to obtain the total number of available arithmetic units, max_msau. Then, based on the total number max_msau and the bit width of a single arithmetic unit, the maximum data operation bit width is determined.
[0099] In practical applications, the product of the total number of available arithmetic units and the bit width of a single arithmetic unit is used as the maximum data operation bit width.
[0100] Step S1602: If the width of the data to be processed is greater than the original data operation bit width before expansion, and less than or equal to the maximum data operation bit width, then the target number of operation units for processing the data to be processed is determined based on the width of the data to be processed and the bit width of a single operation unit.
[0101] In some embodiments, the bit width of the arithmetic unit is the same as the bit width of the original data operation, and the arithmetic unit includes multiple arithmetic logic units. The arithmetic unit is used to perform operations on integers and floating-point numbers at least.
[0102] Specifically, the original data operation bit width before expansion is 128 bits, and the arithmetic unit MSAU includes two 64-bit arithmetic logic units. The target number of arithmetic units to process the data is determined by dividing the width of the data to be processed by the bit width of a single arithmetic unit.
[0103] Step S1603: Decrement the target number by one and write it into the arithmetic unit control register to control the start of the arithmetic unit for the target number to process the data to be processed.
[0104] Specifically, the arithmetic unit control register supports read and write operations. This register controls the number of arithmetic units used, thereby controlling the data operation bit width. The initial value is 0. When the written value is n, it indicates that n+1 arithmetic units (MSAUs) need to be activated, and the data width that can be processed is 128*(n+1) bits. The hardware can select an appropriate power-saving mode based on this setting. The value stored in the arithmetic unit control register is less than or equal to the value stored in the vector width control register.
[0105] In some embodiments, if the width of the data to be processed is less than or equal to the original data operation bit width, a processing unit is started to process the data to be processed.
[0106] Specifically, when the width of the data to be processed is less than or equal to the original data operation bit width, it means that the data to be processed can be operated according to the original data operation bit width. Therefore, a processing unit is started to process the data to be processed.
[0107] In some embodiments, if the width of the data to be processed is greater than the maximum data operation bit width, the total number of arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the largest data operation bit width.
[0108] For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, an appropriate number of operation units are selected to process the remaining data until the remaining data is processed.
[0109] Specifically, if the width of the data to be processed is greater than the maximum data operation bit width, it means that even if all available computing units are used, the operation on the data to be processed cannot be completed. Instead, the data to be processed needs to be divided into multiple parts and processed in multiple rounds.
[0110] In a specific embodiment, during the first round of computation, max_msau computation units are started first to process the data with the largest data operation bit width in the data to be processed, and the remaining data is processed in the second round.
[0111] During the second round of computation, if the width of the remaining data is less than or equal to the width of the original data operation bits, a computation unit is started to process the remaining data.
[0112] If the width of the remaining data is greater than the original data operation bit width but less than or equal to the maximum data operation bit width, then based on the width of the remaining data and the bit width of a single arithmetic unit, the target number of arithmetic units for processing the remaining data is determined. This target number is subtracted by one and written to the arithmetic unit control register to control the activation of the target number of arithmetic units to process the remaining data.
[0113] If the width of the remaining data is greater than the maximum data operation bit width, the total number of arithmetic units is reduced by one and written to the arithmetic unit control register to control the start of the total number of arithmetic units. The remaining data with the maximum data operation bit width is then processed, and the third round of operation is initiated. This process continues until all the remaining data is processed.
[0114] For example, such as Figure 17 As shown, this application embodiment provides a flowchart of a method for extending the bit width of data operations. The flowchart of this method is executed by a computer device and includes the following steps:
[0115] Step S1701: Obtain the data to be processed with a width of data_width.
[0116] Step S1702: Read the value mul_register_width from the vector width control register.
[0117] Step S1703: Increment the value mul_register_width by one to obtain the number of available operation units max_msau.
[0118] Step S1704: Determine the maximum data operation bit width as max_msau*128bit.
[0119] Step S1705: Determine if data_width is greater than 128 bits. If yes, proceed to step S1706; otherwise, proceed to step S1709.
[0120] Step S1706: Determine whether data_width is greater than the maximum data operation bit width. If yes, proceed to step S1707; otherwise, proceed to step S1710.
[0121] Step S1707: Start max_msau of computation units to perform operations.
[0122] Specifically, write (max_msau-1) into the arithmetic unit control register to start max_msau arithmetic units to perform operations.
[0123] Step S1708: Update data_width to (data_width-max_msau*128), then return to step S1705.
[0124] Step S1709: Start a computing unit to perform calculations.
[0125] Write 0 into the arithmetic unit control register to start an arithmetic unit to perform an operation.
[0126] Step S1710: Start the calculation of data_width / 128 operation units.
[0127] Write (data_width / 128-1) into the arithmetic unit control register to start data_width / 128 arithmetic units to perform operations.
[0128] In this embodiment, two new control registers are defined using reserved control registers to achieve variable vector expansion without changing the original 128-bit mode. This expands the data operation bit width from the original to a larger one, improving the parallelization capability and performance of data processing without requiring MSA instruction set expansion or code rewriting, thus reducing costs and increasing efficiency. Secondly, this solution supports existing binary code running directly in a new SIMD environment with uncertain bit widths. Existing source code can gain advantages on new hardware through recompilation, and future expansions (e.g., to 512-bit or 1024-bit) do not require rewriting / recompilation. The newly compiled binary code can run on hardware without expansion, achieving bidirectional compatibility.
[0129] Based on the same technical concept, this application provides a schematic diagram of the structure of a data operation bit width extension device, as shown below. Figure 18 As shown, the device 1800 includes:
[0130] The acquisition module 1801 is used to acquire the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information;
[0131] The judgment module 1802 is used to determine the target number of operation units for processing the data to be processed based on the width of the data to be processed and the bit width of a single operation unit if the width of the data to be processed is greater than the original data operation bit width before expansion and less than or equal to the maximum data operation bit width.
[0132] The processing module 1803 is used to subtract one from the target number and write it into the arithmetic unit control register to control the start of the arithmetic unit for the target number to process the data to be processed.
[0133] Optionally, the bit width of the arithmetic unit is the same as the bit width of the original data operation, and the arithmetic unit includes multiple arithmetic logic units, which are used at least for performing operations on integers and floating-point numbers.
[0134] Optionally, the processing module 1803 is further configured to:
[0135] If the width of the data to be processed is less than or equal to the original data operation bit width, then a processing unit is started to process the data to be processed.
[0136] Optionally, the acquisition module 1801 is specifically used for:
[0137] Increment the variable vector information by one to obtain the total number of computing units that are in an available state;
[0138] The maximum data operation bit width is determined based on the total number and the bit width of a single arithmetic unit.
[0139] Optionally, the processing module 1803 is further configured to:
[0140] If the width of the data to be processed is greater than the maximum data operation bit width, then the total number of the arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the maximum data operation bit width in the data to be processed.
[0141] For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, a corresponding number of operation units are selected to process the remaining data until the remaining data is processed.
[0142] Optionally, the value stored in the arithmetic unit control register is less than or equal to the value stored in the vector width control register.
[0143] In this embodiment, two new control registers are defined using reserved control registers to achieve variable vector expansion without changing the original 128-bit mode. This expands the data operation bit width from the original to a larger one, improving the parallelization capability and performance of data processing without requiring MSA instruction set expansion or code rewriting, thus reducing costs and increasing efficiency. Secondly, this solution supports existing binary code running directly in a new SIMD environment with uncertain bit widths. Existing source code can gain advantages on new hardware through recompilation, and future expansions (e.g., to 512-bit or 1024-bit) do not require rewriting / recompilation. The newly compiled binary code can run on hardware without expansion, achieving bidirectional compatibility.
[0144] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 19 As shown, it includes at least one processor 1901 and a memory 1902 connected to at least one processor. In this embodiment, the specific connection medium between the processor 1901 and the memory 1902 is not limited. Figure 19 Taking the connection between processor 1901 and memory 1902 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.
[0145] In this embodiment of the application, the memory 1902 stores instructions that can be executed by at least one processor 1901. By executing the instructions stored in the memory 1902, at least one processor 1901 can perform the steps of the above-described image processing method.
[0146] The processor 1901 is the control center of the computer device. It can connect to various parts of the computer device using various interfaces and lines, and realizes virtual chip production by running or executing instructions stored in the memory 1902 and calling data stored in the memory 1902. Optionally, the processor 1901 may include one or more processing units. The processor 1901 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 1901. In some embodiments, the processor 1901 and the memory 1902 may be implemented on the same chip; in some embodiments, they may also be implemented on separate chips.
[0147] Processor 1901 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.
[0148] Memory 1902, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 1902 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 1902 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 1902 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.
[0149] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described method for extending the data operation bit width.
[0150] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0151] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0152] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0153] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0154] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0155] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for extending the bit width of data operations, characterized in that, include: Acquire the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information; If the width of the data to be processed is greater than the original data operation bit width before expansion, and less than or equal to the maximum data operation bit width, then the target number of operation units for processing the data to be processed is determined based on the width of the data to be processed and the bit width of a single operation unit. The target number is reduced by one and written into the arithmetic unit control register to control the start of the arithmetic unit for the target number to process the data to be processed; The vector width control register and the arithmetic unit control register are unused reserved registers in the MSA, which is a vector instruction set module.
2. The method as described in claim 1, characterized in that, The bit width of the arithmetic unit is the same as the bit width of the original data operation. The arithmetic unit includes multiple arithmetic logic units and is used to perform operations on integers and floating-point numbers at least.
3. The method as described in claim 2, characterized in that, Also includes: If the width of the data to be processed is less than or equal to the original data operation bit width, then a processing unit is started to process the data to be processed.
4. The method as described in claim 1, characterized in that, The step of determining the extended maximum data operation bit width based on the variable vector information includes: Increment the variable vector information by one to obtain the total number of computing units that are in an available state; The maximum data operation bit width is determined based on the total number and the bit width of a single arithmetic unit.
5. The method as described in claim 4, characterized in that, Also includes: If the width of the data to be processed is greater than the maximum data operation bit width, then the total number of the arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the maximum data operation bit width in the data to be processed. For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, a corresponding number of operation units are selected to process the remaining data until the remaining data is processed.
6. The method as described in claim 4, characterized in that, The value stored in the arithmetic unit control register is less than or equal to the value stored in the vector width control register.
7. A device for extending the data operation bit width, characterized in that, include: The acquisition module is used to acquire the data to be processed, read the variable vector information in the vector width control register, and determine the maximum data operation bit width after expansion based on the variable vector information; The judgment module is used to determine the target number of operation units for processing the data to be processed based on the width of the data to be processed and the bit width of a single operation unit if the width of the data to be processed is greater than the original data operation bit width before expansion and less than or equal to the maximum data operation bit width. The processing module is used to subtract one from the target number and write it into the arithmetic unit control register to control the start of the arithmetic unit for the target number to process the data to be processed; The vector width control register and the arithmetic unit control register are unused reserved registers in the MSA, which is a vector instruction set module.
8. The apparatus as claimed in claim 7, characterized in that, The processing module is also used for: If the width of the data to be processed is greater than the maximum data operation bit width, then the total number of the arithmetic units is reduced by one and written into the arithmetic unit control register to control the start of the total number of arithmetic units to process the data with the maximum data operation bit width in the data to be processed. For the remaining data in the data to be processed, based on the correlation between the remaining data and the maximum data operation bit width and the original data operation bit width, a corresponding number of operation units are selected to process the remaining data until the remaining data is processed.
9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that, It stores a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the method according to any one of claims 1 to 6.