Display panel, display device, and data driver circuitry

Abstract

This application relates to a display panel, a display device, and a data driver circuit. A display device is proposed. The display panel includes a plurality of sub-pixels and a plurality of data lines electrically connected to the plurality of sub-pixels. The data driver circuit applies a data voltage for outputting an image to the plurality of data lines during a refresh frame period. The data driver circuit applies a data voltage for outputting a first image to the plurality of data lines at a first driving frequency, and applies a data voltage for outputting a second image different from the first image to the plurality of data lines at a second driving frequency higher than the first driving frequency.

Description

Technical Field

[0001] The implementation involves a display device and a data driver circuit. Background Technology

[0002] In response to the development of the information society, the demand for various types of display devices, such as liquid crystal display (LCD) devices and organic light-emitting display devices, is increasing.

[0003] For such display devices, there is a need to find ways to improve power efficiency when displaying various types of images.

[0004] As a method to improve the power efficiency of a display device, the display device can operate in a low-power mode.

[0005] When the display device operates in low-power mode, it can intermittently apply data voltages to the display panel for displaying images. However, due to the long intervals between the periods during which data voltages for displaying images are applied, the response time may be delayed before a complete frame transition. Therefore, the user of the display device may visually perceive an afterimage of the previous frame. Summary of the Invention

[0006] Various aspects provide display devices and data driver circuitry where the afterimage is invisible in low-power mode.

[0007] It also provides a display device and data driver circuit capable of operating at 1Hz in low-power mode.

[0008] One embodiment provides a display device comprising: a display panel including a plurality of sub-pixels and a plurality of data lines electrically connected to the plurality of sub-pixels; and a data driver circuit that applies a data voltage for outputting an image to the plurality of data lines during a refresh frame period. The data driver circuit may apply the data voltage for outputting a first image to the plurality of data lines at a first driving frequency, and apply a data voltage for outputting a second image different from the first image to the plurality of data lines at a second driving frequency higher than the first driving frequency.

[0009] One implementation provides a data driver circuit comprising: an image data input pin for receiving image data; a first output circuit for generating and outputting a data voltage for outputting an image based on the image data input through the image data input pin; a mode control signal input pin for inputting a mode control signal for changing the operating cycle of the first output circuit; and a sub-controller for reducing the operating cycle of the first output circuit based on the image data input through the image data input pin.

[0010] According to the implementation, the display device and data driver circuit can prevent afterimages from being visible in low-power mode.

[0011] According to the implementation, the display device and data driver circuit can operate at 1Hz in a low-power mode. Attached Figure Description

[0012] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a schematic diagram illustrating a display device according to an embodiment;

[0014] Figure 2 This is a circuit diagram illustrating an example of a sub-pixel of a display device according to an embodiment;

[0015] Figure 3 The sampling period in the display device according to the embodiment is shown;

[0016] Figure 4 An anode reset frame in a display device according to an embodiment is shown;

[0017] Figure 5 Examples of high-speed drive operation and low-speed drive operation in a display device according to an embodiment, operating at a low drive frequency, are shown.

[0018] Figure 6 The response time delay during frame switching is shown when the display device according to the embodiment operates at a low driving frequency;

[0019] Figure 7A and Figure 7B The response time delay in low-speed drive operation of a display device according to an embodiment is shown.

[0020] Figure 8 A display device according to an embodiment is shown, which displays a first image at a first driving frequency and then displays a second image at a second driving frequency higher than the first driving frequency;

[0021] Figure 9 An example of a low-power mode that the display device can operate according to an embodiment is shown;

[0022] Figures 10A to 10C This illustrates a case where the second driving frequency of the display device according to an embodiment varies according to the first driving frequency, or a case where the time period during which the display device according to an embodiment operates at the second driving frequency varies according to the first driving frequency.

[0023] Figure 11An example of a method for setting the length of each intermediate refresh frame period by a display device according to an embodiment is shown;

[0024] Figure 12 An example of a data driver circuit according to an embodiment is shown;

[0025] Figure 13 This illustrates a case where a display device according to an embodiment displays an image at a low refresh rate; and

[0026] Figure 14 This is a time-brightness curve diagram of a display device according to an embodiment, in which a first image with black grayscale is displayed in a low-power mode, and then a second image with white grayscale is displayed. Detailed Implementation

[0027] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented, and wherein the same reference numerals and symbols may be used to denote the same or similar components, even if these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein may render the subject matter of some embodiments of this disclosure considerably unclear, such descriptions will be omitted. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0028] This document may use terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0029] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be understood that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc.

[0030] When time-relative terms such as “after,” “following,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, process, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately after.”

[0031] Furthermore, when referring to any size, relative dimensions, etc., even if no specific description is specified, the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0032] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of a display device 100 according to an embodiment.

[0034] Reference Figure 1 The display device 100 according to the embodiment may include a display panel 110, a data driver circuit 120 and a gating driver circuit 130 for driving the display panel 110, and a controller 140 for controlling the data driver circuit 120 and the gating driver circuit 130.

[0035] The display panel 110 may include signal lines such as multiple data lines DL and multiple gating lines GL disposed on a substrate. The display panel 110 may also include multiple sub-pixels SP electrically connected to the multiple data lines DL and the multiple gating lines GL.

[0036] The display panel 110 may include an active area (or display area) AA for displaying images and a passive area (or non-display area) NA for not displaying images. In the display panel 110, multiple sub-pixels SP for displaying images may be disposed in the active area AA. In the passive area NA, a data driver circuit 120 and a gating driver circuit 130 may be disposed, or pads connected to the data driver circuit 120 or the gating driver circuit 130 may be disposed.

[0037] Data driver circuit 120 is configured to drive multiple data lines DL. Data driver circuit 120 can apply data voltages to the multiple data lines DL. Gating driver circuit 130 is configured to drive multiple gating lines. Gating driver circuit 130 can transmit gating signals to the multiple gating lines GL. Controller 140 can transmit a data drive timing control signal DCS to data driver circuit 120 to control the operating timing of data driver circuit 120. Controller 140 can also transmit a gating drive timing control signal GCS to gating driver circuit 130 to control the operating timing of gating driver circuit 130.

[0038] The controller 140 can start scanning at time points defined for each frame, convert image data input from an external source into image data DATA in a data signal format readable by the data driver circuit 120, provide the image data DATA to the data driver circuit 120, and control the data drive at appropriate time points in response to the scanning.

[0039] The controller 140 can receive various timing signals and input image data from an external source (e.g., a host system). For example, timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock (CLK) signal, etc.

[0040] The controller 140 can receive timing signals such as vertical synchronization signal Vsync, horizontal synchronization signal Hsync, input data enable (DE) signal and clock (CLK) signal, generate various control signals DCS and GCS, and output the control signals DCS or GCS to the data driver circuit 120 and the gating driver circuit 130 to control the data driver circuit 120 and the gating driver circuit 130.

[0041] The controller 140 outputs various gating drive timing control signals GCS, including gating start pulse (GSP), gating shift clock (GSC), gating output enable (GOE) signal, etc., to control the gating driver circuit 130.

[0042] The controller 140 outputs various data drive timing control signals DCS, including the source start pulse (SSP) and the source sampling clock (SSC), to control the data driver circuit 120.

[0043] The data driver circuit 120 drives multiple data lines DL by receiving image data DATA from the controller 140.

[0044] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs).

[0045] Each SDIC can be connected to the display panel 110 via the tape-on-brush (TAB) method, to the bonding pads of the display panel 110 via the chip-on-glass (COG) method, or via a chip-on-film (COF) structure connected to the display panel 110.

[0046] The gating driver circuit 130 can output a gating signal with an on-level voltage or a gating signal with an off-level voltage under the control of the controller 140. The gating driver circuit 130 can sequentially drive multiple gating lines GL by sequentially transmitting the gating signal with the on-level voltage to multiple gating lines GL.

[0047] The gate driver circuit 130 can be connected to the display panel 110 via the TAB method, to the bonding pads of the display panel 110 via the COG or COP method, or to the display panel 110 via the COF method.

[0048] The gate driver circuit 130 can be formed in the passive area NA of the display panel 110 using the gate-in-board (GIP) method. The gate driver circuit 130 can be disposed on the substrate of the display panel 110 or connected to the substrate. That is, when the gate driver circuit 130 is of the GIP type, it can be disposed in the passive area NA of the substrate. When the gate driver circuit 130 is of the COG or COF type, it can be connected to the substrate of the display panel 110.

[0049] When a specific gate line among the multiple gate lines GL is turned on by the gate driver circuit 130, the data driver circuit 120 can convert the image data DATA received from the controller 140 into an analog data voltage and apply the analog data voltage to the multiple data lines DL.

[0050] The data driver circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, the design of the display panel, etc., the data driver circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or to two or more of the four sides of the display panel 110.

[0051] The gating driver circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, the design of the display panel, etc., the gating driver circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or to two or more of the four sides of the display panel 110.

[0052] Controller 140 may be a timing controller used in typical display applications, a control device that includes a timing controller and is capable of performing other control functions, a control device different from a timing controller, or a circuit within a control device. Controller 140 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0053] The controller 140 can be mounted on a printed circuit board (PCB), flexible printed circuit (FPC), etc., and is electrically connected to the data driver circuit 120 and the gating driver circuit 130 via the PCB, FPC, etc.

[0054] The controller 140 can send signals to or receive signals from the data driver circuit 120 through at least one predetermined interface. Here, the interface may include, for example, a low-voltage differential signaling (LVDS) interface, an embedded point-to-point interface (EPI), a serial peripheral interface (SPI), etc.

[0055] The controller 140 may include a storage medium such as at least one register.

[0056] The display device 100 according to the embodiment can be a display such as a liquid crystal display device including a backlight unit, or it can be a self-emissive display such as an organic light-emitting display, a quantum dot display, or a micro light-emitting diode (LED) display.

[0057] When the display device 100 according to the embodiment is an organic light-emitting display, each sub-pixel SP may include a self-emissive organic light-emitting diode as a light-emitting element. When the display device 100 is a quantum dot display, each sub-pixel SP may include a light-emitting device implemented as a quantum dot as a self-emissive semiconductor crystal. When the display device 100 according to the embodiment is a micro-LED display, each sub-pixel SP may include a self-emissive micro-LED based on inorganic materials as a light-emitting device. Hereinafter, for the sake of brevity, the display device 100 according to the embodiment will be described as an organic light-emitting display, and this disclosure is not limited to organic light-emitting displays.

[0058] Figure 2 This is a circuit diagram illustrating a sub-pixel SP of a display device 100 according to an embodiment.

[0059] Reference Figure 2 The sub-pixel SP may include an organic light-emitting diode (ED) and a driving transistor D-TFT configured to drive the organic light-emitting diode ED.

[0060] In addition to the driving transistor D-TFT, the sub-pixel SP may also include at least one transistor. Each sub-pixel SP may include at least one oxide semiconductor transistor (e.g., oxide TFT).

[0061] In addition to the driving transistor D-TFT, the sub-pixel SP may also include a first transistor T1 through a sixth transistor T6. Each transistor may be a P-type transistor or an N-type transistor.

[0062] N-type transistors can be implemented as oxide transistors formed from semiconductor oxides (e.g., transistors having channels formed from semiconductor oxides such as indium oxide, gallium oxide, zinc oxide, or indium gallium zinc oxide (IGZO)). P-type transistors can be silicon transistors formed from semiconductors such as silicon (e.g., transistors having polycrystalline silicon channels known as low-temperature polycrystalline silicon (LTPS) formed using a low-temperature process).

[0063] Oxide transistors are characterized by having a lower leakage current than silicon transistors.

[0064] The sub-pixel SP may also include a storage capacitor Cstg, which is configured to apply a voltage corresponding to the data voltage Vdata to the gate node of the driving transistor D-TFT during a frame period.

[0065] The structure of a sub-pixel SP that includes 7 transistors and 1 capacitor is also called a 7T1C structure.

[0066] In the following text, for the sake of brevity, the sub-pixel SP in the display device 100 according to the embodiment will be described as having a 7T1C structure. However, the structure of the sub-pixel SP in the display device 100 according to the embodiment is not limited to a 7T1C structure, and the sub-pixel SP may also include at least one circuit device. The sub-pixel SP may have a 2T1C structure including two transistors and one capacitor. The sub-pixel SP may also include at least one transistor or at least one capacitor.

[0067] The first transistor T1 can be configured to switch the electrical connection between the first node N1 of the driving transistor D-TFT and the data line DL. The first node N1 of the driving transistor D-TFT can be either the source node or the drain node of the driving transistor D-TFT. The operating timing of the first transistor T1 can be controlled by the second scan signal Scan2[n]. When the second scan signal Scan2[n], which has an on-level voltage, is applied to the first transistor T1, the data voltage Vdata is applied to the first node N1 of the driving transistor D-TFT.

[0068] The second transistor T2 can be configured to switch the electrical connection between the first node N1 of the driving transistor D-TFT and the high-potential driving voltage (VDDEL) line. The operating timing of the second transistor T2 can be controlled by the light-emitting signal EM. When the light-emitting signal EM[n] with a conduction level voltage is applied to the second transistor T2, the high-potential driving voltage VDDEL is applied to the first node N1 of the driving transistor D-TFT.

[0069] The storage capacitor Cstg may include one end electrically connected to the second node N2 of the driving transistor D-TFT and the other end electrically connected to the high-potential drive voltage (VDDEL) line. The second node N2 of the driving transistor D-TFT may be the gate node of the driving transistor D-TFT.

[0070] The third transistor T3 is electrically connected to the second node N2 and the third node N3 of the driving transistor D-TFT. The operating timing of the third transistor T3 can be controlled by the first scan signal Scan1[n]. The third node N3 of the driving transistor D-TFT can be either the drain node or the source node of the driving transistor D-TFT.

[0071] The third transistor T3 can be an oxide transistor. Because oxide transistors have low leakage current characteristics, the voltage level of the second node N2 driving the D-TFT can remain constant. Therefore, even without applying the image display data voltage Vdata for each frame, the sub-pixel SP can display an image on the screen based on the image display data voltage Vdata input in the previous frame.

[0072] The fourth transistor T4 can be configured to switch the electrical connection between the third node N3 of the driving transistor D-TFT and the initialization voltage (Vini) line. The fourth transistor T4 can be controlled by the third scan signal Scan3[n]. When the third scan signal Scan3[n] with a conduction level voltage is applied, the initialization voltage Vini is applied to the third node N3 of the driving transistor D-TFT.

[0073] The fifth transistor T5 can be configured to switch the electrical connection between the third node N3 of the driving transistor D-TFT and the first electrode of the light-emitting device ED. The fifth transistor T5 includes a fourth node N4, and the fourth node N4 of the fifth transistor T5 is electrically connected to the first electrode of the light-emitting device ED. The fourth node N4 of the fifth transistor T5 can be either the source node or the drain node of the fifth transistor T5. The first electrode of the light-emitting device ED can be either an anode or a cathode. Hereinafter, the first electrode of the light-emitting device ED will be described as an anode.

[0074] The operating timing of the fifth transistor T5 is controlled by the light-emitting signal EM[n]. The light-emitting signal EM[n] controlling the operating timing of the fifth transistor T5 can be the same as the light-emitting signal EM[n] controlling the operating timing of the second transistor T2. The gate node of the fifth transistor T5 and the gate node of the second transistor T2 can be electrically connected to a single light-emitting signal EM[n] line.

[0075] The sixth transistor T6 can be configured to switch the electrical connection between the first electrode of the light-emitting device ED and the reset voltage (VAR) line. When the first electrode of the light-emitting device ED is the anode, the reset voltage VAR can be the anode reset voltage VAR.

[0076] The operating timing of the sixth transistor T6 can be controlled by the third scan signal Scan3[n+1]. The third scan signal Scan3[n+1] controlling the operating timing of the sixth transistor T6 can be the same signal as the third scan signal Scan3[n] controlling the operating timing of the fourth transistor T4, which controls the operating timing of another sub-pixel SP.

[0077] For example, the third scan signal Scan3[n+1] can be applied to the sixth transistor T6, which is included in the sub-pixel SP electrically connected to the nth gate line (where n is an integer equal to or greater than 1). The third scan signal Scan3[n+1] applied to this sub-pixel SP can be the same signal as the third scan signal Scan3[n+1] applied to the fourth transistor T4, which is included in the sub-pixel SP located on the (n+1)th gate line.

[0078] The first electrode of the organic light-emitting diode (OLED) is electrically connected to the fourth node N4 of the fifth transistor T5. The second electrode of the OLED is electrically connected to the low-potential drive voltage (VSSEL) line. The first electrode of the OLED can be either an anode or a cathode. The second electrode of the OLED can be either anode or cathode.

[0079] The high-potential drive voltage (VDDEL) line and the low-potential drive voltage (VSSEL) line can be common voltage lines that are connected to multiple sub-pixels SP disposed in the display panel 110.

[0080] Reference Figure 2 The third transistor T3 can be an N-type transistor, while the remaining transistors can be P-type transistors. Although the driving transistor D-TFT, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be P-type transistors, at least one of these transistors can be an N-type transistor.

[0081] Figure 3 The sampling period in the display device according to the embodiment is shown.

[0082] exist Figure 3 The diagram depicts a timing diagram of the refresh frame period during which the data voltage Vdata used to display the image is applied to the sub-pixel SP.

[0083] The refresh frame may have a first on-bias period OBS1 and a second on-bias period OBS2 configured to apply an initial voltage Vini_H of a high-level voltage to the third node N3 of the driving transistor D-TFT, and a sampling period configured to apply a voltage corresponding to the data voltage Vdata to the second node N2 of the driving transistor D-TFT.

[0084] The conduction bias periods OBS1 and OBS2 can be configured to mitigate the hysteresis effect that may occur in the driving transistor D-TFT and improve the response characteristics.

[0085] During the sampling period, a light-emitting signal EM[n] with a cutoff voltage is applied to the second transistor T2 and the fifth transistor T5. A first scan signal Scan1[n] with a turn-on voltage is applied to the third transistor T3. A second scan signal Scan2[n] with a turn-on voltage is applied to the first transistor T1. Third scan signals Scan3[n] and Scan3[n+1] with cutoff voltages are applied to the fourth transistor T4 and the sixth transistor T6, respectively.

[0086] When the sampling period begins, an initialization voltage Vini_L with a low level is applied to the third node N3 of the driving transistor D-TFT. When the third transistor T3 is turned on, the third node N3 and the second node N2 of the driving transistor D-TFT are electrically connected, and the turn-on voltage is applied to the second node N2 of the driving transistor D-TFT.

[0087] When the driving transistor D-TFT, the first transistor T1, and the third transistor T3 are turned on during the sampling period, a voltage corresponding to the data voltage Vdata is applied to the second node N2 of the transistor D-TFT. Therefore, a voltage corresponding to the data voltage Vdata is applied to one end of the storage capacitor Cstg.

[0088] Figure 4 An anode reset frame in a display device according to an embodiment is shown.

[0089] Reference Figure 4A light-emitting signal EM[n] with a cutoff level voltage is applied to the second transistor T2 and the fifth transistor T5. A first scan signal Scan1[n] with a cutoff level voltage is applied to the third transistor T3. A second scan signal Scan2[n] with a cutoff level voltage is applied to the first transistor T1. Third scan signals Scan3[n] and Scan3[n+1] are applied to the fourth transistor T4 and the sixth transistor T6, respectively. In the third scan signals Scan3[n] and Scan3[n+1], the on-level voltage and the off-level voltage can alternate with each other during the anode reset frame period.

[0090] When the third scan signal Scan3[n] is a conduction level voltage signal, the fourth transistor T4 is turned on. The high-level initialization voltage Vini_H is applied to the third node N3 of the driving transistor D-TFT.

[0091] During the anode reset frame period, a high-level initialization voltage Vini_H can be applied to the third node N3 of the driving transistor D-TFT. The corresponding periods may include a third conduction bias period OBS3 and a fourth conduction bias period OBS4.

[0092] When the third scan signal Scan3[n+1] is a conduction level voltage signal, the sixth transistor T6 is turned on. The anode reset voltage VAR is applied to the first electrode of the organic light-emitting diode ED.

[0093] The voltage level of the anode reset voltage VAR applied to the first electrode of the OLED during the anode reset frame period can be different from the voltage level of the anode reset voltage VAR applied to the first electrode of the OLED during the refresh frame period. When the voltage applied to the first electrode of the OLED during the two periods has different levels, the anode reset voltage VAR during the refresh frame period will be referred to as the VAR_A voltage, and the anode reset voltage VAR during the anode reset frame period will be referred to as the VAR_B voltage, in order to distinguish between the two voltages. This anode reset frame is also referred to as a "skip frame".

[0094] In addition, refer to Figure 4 During the anode reset frame period, a data voltage Vdata with a preset voltage level is applied to the data line DL.

[0095] A parasitic capacitance Cpara can be formed between the second node N2 of the driving transistor D-TFT and the data line DL through which the data voltage Vdata is applied to the corresponding driving transistor D-TFT. In some cases, a physical capacitor device can be provided, one end of which is electrically connected to the corresponding data line DL and the other end of which is electrically connected to the second node N2 of the driving transistor D-TFT. The following description will use the formation of the parasitic capacitance Cpara between the second node N2 of the driving transistor D-TFT and the data line DL as an example.

[0096] Because a parasitic capacitance Cpara is formed between the second node N2 of the driving transistor D-TFT and the data line DL during the anode reset frame period, it is possible to prevent the voltage level on the second node N2 of the driving transistor D-TFT from changing due to the application of a voltage with a preset level to the data line DL.

[0097] The data signal applied to the data line DL to prevent the voltage level on the second node N2 of the driving transistor D-TFT from changing during the anode reset frame period is called the "park voltage" Vpark. The voltage level of the park voltage Vpark can be the same as or similar to the voltage level of the data voltage Vdata used to display black-and-white or low-grayscale images.

[0098] During the anode reset frame period, the voltage change at the second node N2 of the driving transistor D-TFT decreases. That is, the voltage level applied to the second node N2 of the driving transistor D-TFT during the anode reset frame period can be the same as or similar to the voltage level in the previous sampling period.

[0099] Figure 5 The driving frequency of the display device 100 according to the embodiment is shown.

[0100] Reference Figure 5 The display device 100 according to the embodiment can perform a "high-speed drive operation" in which all frames are refresh frames. Furthermore, the display device according to the embodiment can perform a "medium-speed drive operation" or a "low-speed drive operation" in which at least one anode reset frame exists between different refresh frames.

[0101] Furthermore, the term "drive frequency" is defined in this document. Drive frequency is defined as the number of refresh frames output by display device 100 per second.

[0102] Reference Figure 5 According to the embodiment, the display device 100 can output 120 refresh frames per second. In this case, the driving frequency of the display device 100 is defined as 120Hz.

[0103] Reference Figure 5 According to the embodiment, the display device 100 can output 24 refresh frames per second. In this case, the driving frequency of the display device 100 is limited to 24Hz.

[0104] When the display device 100 according to the embodiment operates at a driving frequency of 120Hz in high-speed driving operation, all 120 frames displayed in the active area within 1 second are refresh frames.

[0105] When the display device operates at a drive frequency of 24Hz, 24 of the 120 frames displayed in 1 second are refresh frames, while the remaining 96 frames are anode reset frames. That is to say, after outputting one refresh frame, four anode reset frames can be output consecutively.

[0106] Therefore, the display device 100 according to the embodiment can operate at various driving frequencies (i.e., various driving modes from high-speed driving operation to low-speed driving operation).

[0107] Figure 6 The response time delay during frame switching is shown when the display device 100 according to the embodiment operates at a low driving frequency.

[0108] Reference Figure 6 The display device 100 according to the embodiment can perform low-speed drive operation.

[0109] Low-speed drive operation can be, for example, when the display device 100 operates in a low-power mode. A low-power mode can be, for example, an always-on display (AoD) mode.

[0110] As mentioned above Figure 4 During the anode reset frame period, the data driver circuit 120 applies a Parker voltage Vpark with a preset level to the data line DL. Therefore, during the anode reset frame period, the data driver circuit 120 can apply data voltages Vdata with different levels depending on the grayscale of the image data DATA.

[0111] Therefore, the data driver circuit 120 can drive only the circuit configured to output a Parker voltage Vpark with a preset level during the anode reset frame period. Thus, the power consumption of the data driver circuit 120 can be significantly reduced. Similarly, the power consumption of the display device 100 can be reduced by decreasing the driving frequency.

[0112] Reference Figure 6 According to the embodiment, the display device 100 can display an image at a driving frequency of about 1 Hz in a low-power mode such as always-on display (AoD) mode. For example, the display device 100 can output 119 anode reset frames continuously after outputting one refresh frame.

[0113] When the display device 100 is operating at low speed, the image displayed in the display area can be switched.

[0114] For example, when the display device 100 is operating at low speed, the display device 100 may display a first image with black grayscale (i.e., 0 grayscale) and then display a second image with white grayscale (i.e., 255 grayscale).

[0115] Reference Figure 6 The display device 100 may require approximately 2 to 3 refresh frames to convert from black grayscale (i.e., 0 grayscale) to white grayscale (i.e., 255 grayscale).

[0116] When the display device operates at a low speed (e.g., 1Hz), the time interval between refresh frames is 1 second.

[0117] The afterimage of the first image with black grayscale (i.e., 0 grayscale) is held for about 2 to 3 seconds so that it is visually recognizable to the user of the display device 100.

[0118] The phenomenon that the afterimage of the first image can still be visually recognized even when the image displayed on the display device 100 is switched from the first image to the second image is called "response time delay". This is also known as "response latency".

[0119] The greater the grayscale difference between the first image before image conversion and the second image after image conversion, the greater the response time delay. The lower the driving frequency, the greater the response time delay.

[0120] Figure 7A and Figure 7B The response time delay during low-speed drive operation of the display device 100 according to an embodiment is shown.

[0121] Reference Figure 7A When the display device 100 according to the embodiment operates at a low speed (e.g., at a driving frequency of 10Hz), a response delay of 0.2 to 0.3 seconds may occur.

[0122] Therefore, flickering can be visually detected between a first image with black grayscale and a second image with white grayscale.

[0123] Reference Figure 7B When the display device 100 according to the embodiment operates at a low speed (e.g., at a driving frequency of 1Hz), a response delay of 2 to 3 seconds may occur.

[0124] Therefore, the second image may not be displayed at the normal timing, and the first image may be retained as an afterimage.

[0125] Flickering and ghosting caused by response time delays may be the reason for reduced display quality.

[0126] Therefore, it is necessary to provide the display device 100 with a configuration that overcomes the response time delay problem, while also providing the display device 100 with the ability to perform low-speed drive operations.

[0127] Figure 8 A display device 100 according to an embodiment is shown, which displays a first image at a first driving frequency and then displays a second image at a second driving frequency higher than the first driving frequency.

[0128] Reference Figure 8 According to the embodiment, the display device 100 outputs a first image Image A at a first driving frequency. Furthermore, at the point in time when the image displayed by the display device 100 changes from the first image Image A to the second image Image B, the display device 100 outputs the second image Image B at a second driving frequency.

[0129] Reference Figure 8 The second driving frequency is higher than the first driving frequency. For example, when the first driving frequency is 1Hz, the second driving frequency can be approximately 30Hz or higher.

[0130] Reference Figure 8 The first drive frequency is matched to the low refresh rate (LRR). Furthermore, the second drive frequency is matched to the intermediate refresh rate (MRR). That is, in this paper, the refresh rate has the same meaning as the drive frequency.

[0131] Furthermore, the value of the second driving frequency can be a division value of the maximum driving frequency of the display device 100 according to the embodiment.

[0132] For example, when the maximum driving frequency of the display device 100 according to the embodiment is 120Hz, the value of the second driving frequency can be one of 1, 2, 3, 4, 5, 6, 8, 10, 12, 15, 20, 24, 30, 40, 60 and 120Hz.

[0133] The value of the second drive frequency can be selected from frequencies whose response time delay is not visually perceptible to the user.

[0134] As described above, the value of the second driving frequency can be set differently depending on the grayscale difference between the first image and the second image.

[0135] In some cases, the value of the second driving frequency can be selected in black-and-white situations where the response time delay is easily visible due to the maximum grayscale difference between the first and second images.

[0136] In this document, for the sake of brevity, the value of the second driving frequency will be described as being set independently of the grayscale difference between the first and second images, but this disclosure is not limited thereto.

[0137] Furthermore, the value of the second drive frequency can be selected differently based on the value of the first drive frequency. In some cases, the second drive frequency can have a fixed value that is selected independently of the value of the first drive frequency.

[0138] The value of the second driving frequency can be chosen by taking into account human cognitive characteristics. For example, it is known that the image observed by the human eye lasts as an afterimage for approximately 1 / 16 of a second.

[0139] Therefore, when the transition time from the first image Image A to the second image Image B is equal to or longer than 1 / 16 of a second, a human can perceive continuous changes in the image. Therefore, the value of the second driving frequency can, for example, be 20 Hz or higher.

[0140] In addition, referring to the above combination Figure 7A and Figure 7B The description states that when the second image Image B is a white grayscale image, it may be necessary to output two or three refresh frames until the image is converted from the first image Image A to the second image Image B.

[0141] Therefore, more specifically, the second drive frequency value can be set to 30Hz or higher so that the 2-frame period is about 1 / 16 of a second or less.

[0142] Reference Figure 8 The length (t seconds) of the intermediate refresh rate (MRR) period can vary depending on the value of the second drive frequency.

[0143] For example, when the second drive frequency is higher, the time required to transition from the first image (Image A) to the second image (Image B) may be shorter. Conversely, when the second drive frequency is lower, the time required to transition from the first image (Image A) to the second image (Image B) may be longer.

[0144] Furthermore, according to the embodiment, the display device 100 outputs the second image Image B at a first driving frequency during the time period after outputting the second image Image B at a second driving frequency.

[0145] In other words, the display device 100 according to the embodiment outputs a first image Image A at a first driving frequency, outputs a second image Image B converted from the first image Image A at a second driving frequency, and then outputs the second image Image B at the first driving frequency.

[0146] Therefore, when the image output by the display device 100 remains unchanged, the image is output at a first driving frequency, which is an extremely low driving frequency (e.g., 1 Hz), and when the image is converted, the converted image is output at a second frequency (e.g., 30 Hz). Furthermore, the display device can output the converted image again at the first driving frequency.

[0147] Therefore, the display device 100 according to the embodiment can overcome the problem of response time delay and significantly reduce power consumption.

[0148] Figure 9 An example of a low-power mode in which the display device 100 can operate according to an embodiment is shown.

[0149] Reference Figure 9 The display device 100 according to the embodiment can operate in a low-power mode. The low-power mode may be, for example, AoD mode.

[0150] When the display device 100 operates in AoD mode, it can display time information and the like in the active area AA. The time information displayed in the active area AA is continuously updated as time passes (for example, updated from 11:11 AM to 11:12 AM).

[0151] For example, refer to Figure 9 The image displayed by the display device 100 in the active area AA is changed from the first image 910 to the second image 920.

[0152] The display device 100 according to the embodiment outputs a first image 910 at a first driving frequency.

[0153] When the image displayed in the active area AA changes from the first image 910 to the second image 920, the display device 100 according to the embodiment outputs the second image 920 at a second driving frequency higher than the first driving frequency.

[0154] According to the embodiment, the display device 100 outputs a second image 920 at a second driving frequency for a preset time period, and then outputs the second image 920 at a first driving frequency.

[0155] Figures 10A to 10C The illustration shows a case where the second driving frequency of the display device 100 according to an embodiment varies according to the first driving frequency, or a case where the time period during which the display device 100 according to an embodiment operates at the second driving frequency varies according to the first driving frequency.

[0156] Reference Figure 10AAccording to the embodiment, the display device 100 displays an image at a first driving frequency during a low refresh rate (LRR) period. The display device 100 also displays an image at a second driving frequency during an intermediate refresh rate (MRR) period.

[0157] Reference Figure 10A It illustrates an embodiment in which the display device 100 displays a single refresh frame followed by five consecutive anode reset frames during the LRR period.

[0158] Reference Figure 10A This illustrates an implementation where the display device 100 displays only refresh frames during the MRR period.

[0159] Therefore, when the first drive frequency of each LRR period is 10Hz, the second drive frequency of each MRR period can be 60Hz.

[0160] Reference Figure 10B It illustrates an embodiment in which the display device 100 displays a single refresh frame followed by two consecutive anode reset frames in each LRR period.

[0161] Reference Figure 10B It illustrates an implementation in which the display device 100 displays only refresh frames in each MRR period.

[0162] Therefore, when the first drive frequency of each LRR period is 20Hz, the second drive frequency of each MRR period can be 60Hz.

[0163] Reference Figure 10A and Figure 10B When the first driving frequency increases and the second driving frequency remains constant, the difference between the first driving frequency and the second driving frequency decreases. Therefore, when the first driving frequency increases and the second driving frequency remains constant, the difference between the first driving frequency and the second driving frequency decreases. Consequently, the degree to which the afterimage of the image displayed in each LRR period is visually recognized can be relatively reduced.

[0164] Reference Figure 10A and Figure 10B When the first drive frequency increases, the length of each MRR period can be shortened. For example, refer to... Figure 10A and Figure 10B The length of each MRR period can be reduced from t1 to t2.

[0165] Reference Figure 10B Compared to the case where the length of each MRR period is constant, the length of each LRR period can be increased as the length of each MRR period decreases. Therefore, this can help reduce power consumption.

[0166] Reference Figure 10CIt illustrates an embodiment in which the display device 100 displays a single refresh frame followed by two consecutive anode reset frames in each LRR period.

[0167] Reference Figure 10C It illustrates an embodiment in which the display device 100 displays a single refresh frame followed by a single anode reset frame in each MRR period.

[0168] Therefore, when the first drive frequency of each LRR period is 20Hz, the second drive frequency of each MRR period can be 30Hz.

[0169] Reference Figure 10A and Figure 10C When the amplitude of the first driving frequency increases, the amplitude of the second driving frequency can decrease. Since the degree to which the afterimage is visually recognized decreases as the amplitude of the first driving frequency increases, the amplitude of the second driving frequency can also decrease. Here, also under these circumstances, the amplitude of the second driving frequency can be greater than the amplitude of the first driving frequency.

[0170] Figure 11 An example of a method for setting the length of each MRR period by a display device 100 according to an embodiment is shown.

[0171] Reference Figure 11 The first drive frequency of each LRR period can be used as a parameter to set the length of each MRR period.

[0172] Here, each LRR period refers to the LRR period before (or immediately before) or after (or immediately after) each MRR period.

[0173] The first driving frequency for each LRR period can be A Hz.

[0174] The first driving frequency can be the driving frequency during periods when the display device 100 operates in low-power mode. The first driving frequency can be a driving frequency that allows visual recognition of afterimages due to human cognitive characteristics (e.g., 16Hz).

[0175] The length of each MRR period, LENGTH, can be set using Equation 1 below.

[0176] [Equation 1]

[0177] LENGTH = 3 × (1 / A) (seconds)

[0178] Equation 1 reflects that the lower the value of the first driving frequency, the longer the length of each MRR period (LENGTH).

[0179] For example, when the first drive frequency is 1Hz, the value of A is 1. Here, the length of each MRR period (LENGTH) can be 3 seconds.

[0180] In Equation 1, setting the coefficient of the right-hand side to 3 is merely an example, and this disclosure is not limited thereto.

[0181] Here, the second driving frequency for each MRR period can be B Hz.

[0182] The second driving frequency of the MRR can be a value higher than the first driving frequency. The second driving frequency can be set to the same value or a smaller value than the highest driving frequency (e.g., 120Hz) that the display device 100 can achieve.

[0183] In each MRR period, the SPACE of the second drive frequency is the reciprocal of the second drive frequency, as shown in Equation 2 below.

[0184] [Equation 2]

[0185] SPACE=1 / B(seconds)

[0186] For example, when the second drive frequency in each MRR period is 30 Hz, the period SPACE of the second drive frequency is 0.033 seconds.

[0187] As mentioned above, the second driving frequency period SPACE can be selected by taking into account the characteristics of human cognition.

[0188] For example, the period SPACE of the second driving frequency can be selected to have a value less than 1 / 16, so that the afterimage cannot be visually recognized.

[0189] Reference Figure 11 The number of refresh frames (COUNT) output in each MRR period can be derived from the following Equation 3.

[0190] [Equation 3]

[0191] COUNT = LENGTH × B

[0192] The number of refresh frames output in each MRR period, COUNT, can be selected to be 2 or more.

[0193] When the length of each LRR period is 3 seconds and the value of the second drive frequency B is 30, the number of refresh frames output in each MRR period, COUNT, can be 90.

[0194] In the following text, reference will be made to Figure 9 and Figure 11 An example of a display device 100 according to an embodiment is described.

[0195] Reference Figure 9 The display device 100 according to the embodiment can display time information in a low-power mode. The time information can be expressed in minutes.

[0196] For example, the display device 100 according to the embodiment can display the first image 910 at a first driving frequency of 1Hz.

[0197] At the point in time when the image displayed on the display device 100 changes from the first image 910 to the second image 920, the display device 100 may display the second image 920 at a second driving frequency of 30Hz.

[0198] The display device 100 according to the embodiment can output the second image 920 within a time period of the value calculated in Equation 1. The display device 100 according to the embodiment can output the second image 920 according to the number of times calculated in Equation 3.

[0199] Therefore, the display device 100 can output the second image 920 up to 90 times within 3 seconds.

[0200] The display device 100 according to the embodiment outputs the second image 920 a number of times calculated according to Equation 3 during the time period calculated in Equation 1, and then outputs the second image 920 at a first driving frequency.

[0201] In this way, the display device 100 can output a second image 920 during the remaining 57-second period.

[0202] Furthermore, when the second image 920 is converted into a new image different from the second image 920, the display device 100 can output the new image through the above process.

[0203] Therefore, the display device 100 according to the embodiment can display images at extremely low driving frequencies (e.g., 1 Hz or 10 Hz). The display device 100 according to the embodiment can operate at a driving frequency that allows for continuous afterimages and is thus observable by the human eye during the LRR period.

[0204] Figure 12 A data driver circuit according to an embodiment is shown.

[0205] Reference Figure 12 According to the embodiment, the data driver circuit 120 may include an output circuit 1220.

[0206] According to the embodiment, the data driver circuit 120 may include an image data input pin through which image data DATA is received and a pin through which a timing control signal DCS is driven by the input data. The controller 140 may receive image data from an external source, convert the image data according to a data signal format readable by the data driver circuit 120, and provide the converted image data DATA to the data driver circuit 120.

[0207] Furthermore, the controller 140 can output a mode control signal MODE to drive the data driver circuit 120 in normal mode or low-power mode. The data driver circuit 120 can operate at a preset refresh frame rate in response to the mode control signal MODE. That is, the controller 140 can output the mode control signal MODE to adjust the duration during which the data driver circuit 120 applies the image display data voltage Vdata to the multiple data lines DL.

[0208] The operating period of the output circuit 1220 may change during the period when the data driver circuit 120 operates in low-power mode.

[0209] The output circuit 1220 includes a first output circuit 1222 that generates a data voltage Vdata based on grayscale values ​​of image data DATA, etc. When the data driver circuit 120 operates in low-power mode, the operating period of the first output circuit 1222 can be extended to a longer period than the operating period of the data driver circuit 120 in normal mode.

[0210] The first output circuit 1222 can be a circuit that generates a data voltage Vdata based on image data DATA and a data-driven timing control signal DCS. The first output circuit 1222 may include at least one shift register, at least one latch circuit, and at least one digital-to-analog converter.

[0211] The voltage generated by the first output circuit 1222 can be applied to multiple data lines DL during the refresh frame period.

[0212] In addition, the output circuit 1220 may also include a second output circuit 1224 that generates voltages applied to multiple data lines DL during a jump frame period that is different from the refresh frame period.

[0213] The second output circuit 1224 can output voltage during the blanking period.

[0214] Referring to the above Figure 4 The second output circuit 1224 can be a circuit that generates a Parker voltage Vpark with a preset level. The second output circuit 1224 may include a voltage regulator circuit configured to uniformly output a voltage with a constant level.

[0215] The second output circuit 1224 does not generate data voltages Vdata with different levels based on the grayscale information of the image data DATA. For the same reason, the amount of power consumed by the data driver circuit 120 during the period of driving the second output circuit 1224 is less than the amount of power consumed by the data driver circuit 120 during the period of driving the first output circuit 1222.

[0216] Therefore, the shorter the driving period of the first output circuit 1222, the greater the power consumption of the data driver circuit 120. Conversely, the longer the driving period of the first output circuit 1222, the less power the data driver circuit 120 consumes.

[0217] As described above, the controller 140 can output a mode control signal MODE, which controls the data driver circuit 120 to operate at a low refresh rate (LRR).

[0218] In addition, the data driver circuit 120 may also include a sub-controller 1210.

[0219] The sub-controller 1210 receives image data DATA input through the image data input pin and determines whether the image data DATA has been converted from the first image to the second image.

[0220] Sub-controller 1210 can control output circuit 1220. Specifically, sub-controller 1210 can control output circuit 1220 to cause data driver circuit 120, which operates at low refresh frame rate (LRR), to operate at intermediate refresh frame rate (MRR).

[0221] The sub-controller 1210 can control the output circuit 1220 to operate at an intermediate refresh frame rate during the period when the data driver circuit 120 receives the mode control signal MODE, and control the data driver circuit 120 to operate at a low refresh frame rate through the mode control signal MODE.

[0222] In other words, during the period when the data driver circuit 120 outputs data voltage Vdata for outputting the first image to multiple data lines DL at a first driving frequency, it receives image data DATA for outputting the second image from the controller 140.

[0223] Furthermore, the data driver circuit 120 can output the data voltage Vdata for outputting the second image to multiple data lines DL during the first refresh frame, in which the data voltage Vdata for outputting the second image is output at the second driving frequency.

[0224] Reference Figure 12 The following description is provided.

[0225] During the period when the output circuit 1220 operates at a low refresh rate, the first frequency can be 10Hz.

[0226] When the image data DATA input through the image data input pin is converted from the first image to the second image, the sub-controller 1210 can control the output circuit 1220 to operate at the intermediate refresh frame rate.

[0227] During the period when the output circuit 1220 operates at the intermediate refresh frame rate, the second frequency can be 60Hz.

[0228] Furthermore, during the period when the output circuit 1220 operates at a low refresh rate, the first frequency can be 1Hz.

[0229] When the image data DATA input through the image data input pin is converted from the first image to the second image, the sub-controller 1210 can control the output circuit 1220 to operate at the intermediate refresh frame rate.

[0230] During the period when the output circuit 1220 operates at the intermediate refresh frame rate, the second frequency can be 120Hz.

[0231] The sub-controller 1210 may include multiple settings SETs for controlling the output circuit 1220 to operate at a preset drive frequency.

[0232] Each of the multiple setting SETs can output a signal to operate (or drive) the output circuit 1220 at a preset drive frequency.

[0233] The sub-controller 1210 can select one setting from multiple settings SET based on the mode control signal MODE input from the controller 140.

[0234] For example, refer to Figure 12 The sub-controller 1210 can select a third setting, Set 3, based on the mode control signal MODE. In this case, the sub-controller 1210 can control the output circuit 1220 to operate at a drive frequency of 10Hz.

[0235] In addition, the sub-controller 1210 may include a memory 1215 for storing lookup tables (LUTs).

[0236] The lookup table (LUT) stores information about the refresh frame rate (also known as refresh rate) corresponding to the setting SET.

[0237] In addition, the lookup table (LUT) contains information about the driving frequency at which the data driver circuit 120 will operate when the image input to the data driver circuit 120 is converted from a first image to a second image.

[0238] For example, refer to Figure 12 The lookup table (LUT) may contain information describing the following: During the period when the output circuit 1220 operates at a low refresh rate of 10 Hz, when the image input to the data driver circuit 120 is converted from the first image to the second image, the output circuit 1220 outputs the second image at a drive frequency of 60 Hz.

[0239] Lookup table LUTs can contain join-based LUTs. Figure 11 The information calculated by equations 1 to 3 above.

[0240] Therefore, the sub-controller 1210 can drive the output circuit 1220 at a preset drive frequency by referring to the lookup table LUT and the mode control signal MODE stored in the memory 1215. When the image data DATA is converted from the first image to the second image, the sub-controller 1210 can select a setting from multiple settings SET by referring to the lookup table LUT to change the drive frequency of the output circuit 1220.

[0241] Therefore, even when the image output from the controller 140 is converted from the first image to the second image, the controller 140 can continuously output the mode control signal MODE to control the data driver circuit 120 to operate at a low refresh frame rate.

[0242] Therefore, the controller 140 can continuously drive the display device 100 in low-power mode.

[0243] Furthermore, the display device 100 according to the embodiment may be a touch display device providing touch sensing functionality. Therefore, the display device 100 may also include a touch sensing circuit to detect at least one of a touch and touch coordinates. When a touch is detected, the touch sensing circuit may output touch event information to the controller 140.

[0244] When touch event information is input during the period when the controller 140 operates the display device 100 in low power mode, the controller 140 switches the operating state of the display device 100 from low power mode to normal mode.

[0245] When touch event information is input to controller 140 during the period when data driver circuit 120 operates at intermediate refresh frame rate, mode control signal MODE is input to data driver circuit 120 to control data driver circuit 120 to operate in normal mode.

[0246] In this situation, the operation of the sub-controller 1210, which controls the output circuit 1220 to operate at the intermediate refresh frame rate, ceases. Furthermore, the sub-controller 1210 can control the output circuit 1220 to operate at a preset frequency (e.g., 120Hz) based on the mode control signal MODE.

[0247] Figure 13 The illustration shows a display device 100 according to an embodiment displaying an image at a low refresh rate.

[0248] Reference Figure 13 According to the embodiment, the display device 100 can output an image at a first driving frequency during LRR.

[0249] Reference Figure 13 According to the embodiment, the display device 100 can output a first image at a first driving frequency and output a second image at the same first driving frequency. Here, the first driving frequency can be 1Hz.

[0250] When there is a significant difference in grayscale between the first image and the second image, the user of the display device 100 can visually recognize the afterimage during the period when the first image is converted to the second image.

[0251] When the first driving frequency is 1Hz, the afterimage can be visually recognized within about 2 seconds.

[0252] The display device 100 according to the embodiment can output a first image at a first driving frequency, and output a second image at a second driving frequency during the MRR at the time point when the first image is converted into a second image.

[0253] A second driving frequency can be selected by considering human cognitive characteristics. For example, the second driving frequency could be 30Hz.

[0254] Reference Figure 13 When the second drive frequency is 30Hz, the response time may be delayed by only about 1 / 30 of a second (i.e., about 0.033 seconds).

[0255] Because the response time delay is shorter than the time it takes for a human to visually perceive the afterimage (i.e., approximately 1 / 16 of a second), the user of display device 100 perceives the first image continuously transitioning to the second image. Therefore, the user of display device 100 cannot visually perceive the afterimage.

[0256] According to the embodiment, the display device 100 outputs a second image at a second driving frequency during a preset MRR period. The MRR period can be combined as described above. Figure 11 As described, it is pre-set.

[0257] The display device 100 according to the embodiment displays a second image at a second driving frequency during the MRR period and then outputs the second image at a first driving frequency during the LRR period.

[0258] In this way, the display device 100 according to the embodiment can reduce the occurrence of visually recognizable afterimages when displaying images at a low refresh rate. Therefore, display quality can be improved, and the power efficiency of the display device 100 can be significantly improved.

[0259] Figure 14 This is a time-brightness curve diagram of the display device 100 according to the embodiment, in which a first image with black grayscale is displayed in low power mode, and then a second image with white grayscale is displayed.

[0260] Reference Figure 14 When the display device 100 according to the embodiment displays a first image with black grayscale and then displays a second image with white grayscale in a low-power mode, the display device 100 is able to prevent the afterimage of the first image from being visually recognized. That is, even when there is a significant difference in grayscale between the first image and the second image, the display device 100 according to the embodiment is able to prevent the afterimage of the first image from being visually recognized.

[0261] The embodiments of this disclosure described above will be briefly described below.

[0262] According to an embodiment, the display device 100 may include: a display panel 110 including a plurality of sub-pixels SP and a plurality of data lines DL electrically connected to the plurality of sub-pixels SP; and a data driver circuit 120 configured to apply a data voltage Vdata for outputting an image to the plurality of data lines DL during a refresh frame period. The data driver circuit 120 may apply a data voltage Vdata for outputting a first image (e.g., 910) to the plurality of data lines DL at a first driving frequency, and apply a data voltage Vdata for outputting a second image (e.g., 920) different from the first image to the plurality of data lines DL at a second driving frequency higher than the first driving frequency.

[0263] According to the embodiment, after applying a data voltage Vdata for outputting a second image to multiple data lines DL at a second driving frequency, the data driver circuit 120 can apply a data voltage Vdata for outputting a second image to the multiple data lines DL at a first driving frequency.

[0264] According to an embodiment, the data driver circuit 120 can apply a data voltage Vdata with a predetermined level to multiple data lines DL during a jump frame period that is different from the refresh frame period.

[0265] According to an embodiment, the data driver circuit 120 can apply a data voltage Vdata for outputting a first image to multiple data lines DL at a first driving frequency during a first time period (e.g., LRR time period); apply a data voltage Vdata for outputting a second image different from the first image to multiple data lines DL at a second driving frequency higher than the first driving frequency during a second time period (e.g., MRR time period) after the first time period; and apply a data voltage Vdata for outputting the second image at the first driving frequency during a third time period (e.g., LRR time period) after the second time period.

[0266] According to the embodiment, the data driver circuit 120 can apply the data voltage Vdata for outputting the second image to multiple data lines DL in a first refresh frame during which the data voltage Vdata for outputting the second image is output at a second driving frequency.

[0267] According to an embodiment, the display device 100 may further include a controller 140 configured to output image data DATA for outputting a first image and image data DATA for outputting a second image to the data driver circuit 120.

[0268] According to an embodiment, the data driver circuit 120 can receive image data DATA for outputting a second image during a period when it outputs a data voltage Vdata for outputting a first image to multiple data lines DL at a first driving frequency.

[0269] According to one embodiment, the controller 140 may output a mode control signal to adjust the period in which the data driver circuit 120 applies a data voltage Vdata for outputting an image to multiple data lines DL.

[0270] According to an embodiment, the data driver circuit 120 may include: an output circuit 1220 configured to generate and output a data voltage Vdata; and a sub-controller 1210 configured to switch the driving frequency of the output circuit 1220 from a first driving frequency to a second driving frequency by controlling the output circuit 1220.

[0271] According to the implementation, the sub-controller 1210 can determine whether the image data DATA input to the data driver circuit 120 is converted into image data DATA for outputting the second image, and convert the first driving frequency into the second driving frequency based on the determination result.

[0272] According to an embodiment, the output circuit 1220 may include: a first output circuit 1222 configured to generate and output a data voltage Vdata for outputting an image; and a second output circuit 1224 configured to generate and output a data voltage Vdata having a predetermined level. The data voltage Vdata having the predetermined level may be applied to multiple data lines DL during a skip frame period rather than a refresh frame period.

[0273] According to one embodiment, the sub-controller 1210 may include a memory 1215 storing a lookup table (LUT). The lookup table LUT contains information about a value A for a first drive frequency and a value B for a second drive frequency relative to the value of the first drive frequency.

[0274] According to an embodiment, the sub-controller 1210 may include one or more settings SET to output signals, thereby driving the output circuit 1220 at a predetermined drive frequency.

[0275] According to the implementation method, the second driving frequency can be set differently depending on the value of the first driving frequency.

[0276] According to the implementation method, the length of the time period during which the operation is performed at the second driving frequency can be set differently depending on the value of the first driving frequency.

[0277] According to the implementation, at least one of the value of the second driving frequency and the length of the time period in which the operation is performed at the second driving frequency can be set differently based on the value of the first driving frequency.

[0278] According to the implementation method, the first driving frequency can be the reciprocal of the time interval between two consecutive refresh frame periods of the first time period. The second driving frequency can be the reciprocal of the time interval between two adjacent refresh frame periods of the second time period.

[0279] According to the implementation method, the second driving frequency can be 30Hz or higher.

[0280] According to the embodiment, during the period when the display device 100 operates in low power mode, the data driver circuit 120 can apply a data voltage Vdata for outputting a first image to multiple data lines DL at a first driving frequency, and apply a data voltage Vdata for outputting a second image to multiple data lines DL at a second driving frequency.

[0281] According to an embodiment, the data driver circuit 120 may include: an image data input pin through which image data DATA is input; a first output circuit 1222 that generates and outputs a data voltage Vdata for outputting an image based on the image data DATA input through the image data input pin; a mode control signal input pin that receives a mode control signal for changing the operating cycle of the first output circuit 1222; and a sub-controller 1210 that shortens the operating cycle of the first output circuit 1222 based on the image data DATA input through the image data input pin.

[0282] According to an embodiment, the data driver circuit 120 may further include a mode control signal input pin through which a mode control signal for changing the operating period of the first output circuit 1222 is input. In response to the mode control signal, the first output circuit 1222 may operate in a low-power mode with a longer operating period, or in a normal mode with a shorter operating period.

[0283] According to the embodiment, during the period when a mode control signal for controlling the first output circuit 1222 to operate in a low-power mode is input, the sub-controller 1210 can shorten the operation period of the first output circuit 1222 when different image data DATA is input through the image data input pin.

[0284] The foregoing description has been presented to enable any person skilled in the art to implement and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The foregoing description and drawings provide examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure. Therefore, the scope of this disclosure is not limited to the illustrated embodiments, but is consistent with the widest scope consistent with the claims. The scope of protection of this disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as included within the scope of this disclosure.

[0285] Cross-references to related applications

[0286] This application claims priority to Korean Patent Application No. 10-2021-0169824, filed on December 1, 2021, which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes a plurality of sub-pixels and a plurality of data lines electrically connected to the plurality of sub-pixels; as well as A data driver circuit configured to apply data voltage to the plurality of data lines and output an image during a refresh frame period. The display device is configured to operate in at least one of a normal mode and a low-power mode configured in a display frame during at least one anode reset frame period. In the low-power mode, the data driver circuit is configured to apply a data voltage for outputting a first image to the plurality of data lines at a first driving frequency during a first time period, to apply a data voltage for outputting a second image different from the first image to the plurality of data lines at a second driving frequency higher than the first driving frequency during a second time period after the first time period, and to apply the data voltage for outputting the second image to the plurality of data lines at the first driving frequency during a third time period after the second time period. The at least one anode reset frame period, in which a predetermined data voltage is provided to the plurality of data lines, exists in each of the first period, the second period, and the third period.

2. The display device according to claim 1, wherein, The data voltage with the predetermined level provided to the plurality of data lines in each of the first time period, the second time period, and the third time period is provided by the data driver circuit.

3. The display device according to claim 1, wherein, The data driver circuit is configured to apply a data voltage for outputting the second image to the plurality of data lines in a first refresh frame that outputs a data voltage for outputting the second image at the second driving frequency.

4. The display device according to claim 1, further comprising a controller configured to output image data for outputting the first image and image data for outputting the second image to the data driver circuit.

5. The display device according to claim 4, wherein, The data driver circuit is configured to receive image data for outputting the second image during a period in which a data voltage for outputting the first image is output to the plurality of data lines at the first driving frequency.

6. The display device according to claim 4, wherein, The controller is configured to output a mode control signal to adjust the period at which the data driver circuit applies the data voltage for outputting the image to the plurality of data lines.

7. The display device according to claim 6, wherein, The data driver circuit includes: Output circuit, the output circuit being configured to generate and output data voltage; and A sub-controller configured to control the output circuit to switch the drive frequency of the output circuit from the first drive frequency to the second drive frequency.

8. The display device according to claim 7, wherein, The sub-controller is configured as follows: Determine whether the image data input to the data driver circuit is converted into image data for outputting the second image; and Based on the determined result, the first driving frequency is converted into the second driving frequency.

9. The display device according to claim 7, wherein, The output circuit includes: A first output circuit, configured to generate and output data voltage for outputting an image; and A second output circuit is configured to generate and output a data voltage with a predetermined level.

10. The display device according to claim 7, wherein, The sub-controller includes a memory for storing lookup tables, and The lookup table contains information about the value of the first drive frequency and the value of the second drive frequency relative to the value of the first drive frequency.

11. The display device according to claim 7, wherein, The sub-controller includes one or more settings to output signals, thereby driving the output circuit at a predetermined drive frequency.

12. The display device according to claim 1, wherein, Based on the value of the first drive frequency, at least one of the values ​​of the second drive frequency and the length of the period during which the operation is performed at the second drive frequency is set differently.

13. The display device according to claim 1, wherein, The first driving frequency is the reciprocal of the time interval between two consecutive refresh frame periods of the first time period, and The second driving frequency is the reciprocal of the time interval between two consecutive refresh frame periods of the second time period.

14. The display device according to claim 1, wherein, The second driving frequency is above 30Hz.

15. The display device of claim 1, further comprising a touch sensing circuit for detecting at least one of a touch and touch coordinates, and When a touch is detected, the touch sensing circuit outputs touch event information to the controller.

16. The display device according to claim 15, in, When the touch event information is input during a period when the controller is operating the display device in low power mode, the controller switches the operating state of the display device from low power mode to normal mode.

17. The display device according to claim 15, in, When the touch event information is input to the controller during the period when the data driver circuit operates at the second driving frequency, a mode control signal is input to the data driver circuit to control the data driver circuit to operate in normal mode.

18. The display device according to claim 1, in, Each of the plurality of sub-pixels includes: Light-emitting devices; A driving transistor that drives the light-emitting device; The first transistor switches the electrical connection between the first node of the driving transistor and one of the multiple data lines, and the timing of the operation of the first transistor is controlled by the second scan signal. The second transistor switches the electrical connection between the first node of the driving transistor and the high-potential driving voltage line, and the timing of the operation of the second transistor is controlled by a light-emitting signal. A third transistor is electrically connected to the second and third nodes of the driving transistor, and the timing of the operation of the third transistor is controlled by a first scan signal. The fourth transistor switches the electrical connection between the third node of the driving transistor and the initialization voltage line, and the timing of the operation of the fourth transistor is controlled by the third scan signal; A fifth transistor, which switches the electrical connection between the third node of the driving transistor and the first electrode of the light-emitting device, wherein the timing of operation of the fifth transistor is controlled by a light-emitting signal identical to the light-emitting signal of the second transistor; and A sixth transistor switches the electrical connection between the first electrode of the light-emitting device and the reset voltage line. The timing of the operation of the sixth transistor is controlled by a third scan signal. The third transistor is an oxide transistor, and The third scan signal controlling the operation timing of the sixth transistor is different from the third scan signal controlling the operation timing of the fourth transistor located in the same sub-pixel as the sixth transistor, but is the same as the third scan signal controlling the operation timing of the fourth transistor of another sub-pixel.

19. The display device according to claim 18, in, The third transistor is an N-type transistor, and the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-type transistors.

20. The display device according to claim 18, further comprising: A storage capacitor, the storage capacitor comprising one end electrically connected to the second node of the driving transistor and the other end electrically connected to the high-potential driving voltage line, The light-emitting device is connected between the fourth node of the fifth transistor and the low-potential driving voltage line, and is connected to the reset voltage line via the sixth transistor.

21. A data driver circuit, the data driver circuit comprising: An image data input pin, configured to receive image data; A first output circuit is configured to generate and output a data voltage for outputting an image based on the image data input through the image data input pin. A mode control signal input pin, the mode control signal input pin being configured to receive a mode control signal for changing the operating cycle of the first output circuit; as well as A sub-controller configured to reduce the operating cycle of the first output circuit based on the image data input through the image data input pin. The data driver circuit is configured to apply data voltages to multiple data lines during at least one refresh frame period. The first output circuit is configured to operate in normal mode or, during at least one anode reset frame period, to operate in low-power mode within a display frame. In the low-power mode, the data driver circuit is configured to apply a data voltage for outputting a first image to the plurality of data lines at a first driving frequency during a first time period, to apply a data voltage for outputting a second image different from the first image to the plurality of data lines at a second driving frequency higher than the first driving frequency during a second time period after the first time period, and to apply the data voltage for outputting the second image to the plurality of data lines at the first driving frequency during a third time period after the second time period. The at least one anode reset frame period, in which a predetermined data voltage is provided to the plurality of data lines, exists in each of the first period, the second period, and the third period.

22. The data driver circuit according to claim 21, wherein, The operating period in the low-power mode is relatively long and the operating period in the normal mode is relatively short.

23. The data driver circuit according to claim 22, wherein, When different image data is input through the image data input pin during the period when the mode control signal used to control the first output circuit to operate in the low power mode is input, the sub-controller is configured to reduce the operating period of the first output circuit.

Images