Gate driver and display device including said gate driver

Abstract

A gate driver and a display device including the gate driver are disclosed. The display driver may include multiple stages that individually drive multiple gate lines by combining multiple group signals, multiple block signals, and multiple clock signals. Each independently driven stage may include: an output buffer including a pull-up transistor that generates and outputs a scan signal with a gate on level under the control of a first node and a pull-down transistor that generates and outputs a scan signal with a gate off level under the control of a second node; a first controller that controls the first node by combining group signals provided via group lines from the multiple group signals, block signals provided via block lines from the multiple block signals, and clock signals provided via clock lines from the multiple clock signals; and a second controller that controls the second node in the opposite direction to the operation of the first node by combining the group signals, the block signals, and the clock signals.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0168716, filed in Korea on November 30, 2021, the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] The present invention relates to a gate driver that stably drives the gate lines without using a carry signal, and a display device having a gate driver. Background Technology

[0004] The display device includes a panel for displaying images via a pixel matrix and a driving circuit for driving the panel. The driving circuit has a gate driver that drives gate lines connected to the thin-film transistor (TFT) of each pixel, and a data driver that drives data lines connected to the TFT.

[0005] The gate driver comprises multiple stages that individually drive gate lines, and these stages are subordinately connected to each other. Each stage outputs a scan signal to each gate line and a carry signal to control the operation of the other stages. Each stage can operate by receiving carry signals from other stages as set signals and reset signals.

[0006] However, if a defect in any stage causes a carry signal not to be output from any of the multiple stages, the organically connected stages will not operate to output a scan signal, and thus no image will be displayed on the panel.

[0007] In order to achieve stable output of scan and carry signals, the gate driver must have multiple thin-film transistors (TFTs) in each stage for input, reset, inverter, output buffer and stabilization. This increases the size of the gate driver and thus the size of the bezel area.

[0008] The above-mentioned background information is the technical information owned by the inventor of this invention in designing this invention or in the process of designing this invention, and should not be regarded as known technology disclosed to the public before the disclosure of this invention. Summary of the Invention

[0009] In view of the above-mentioned problems and other limitations associated with related technologies, the present invention was made, and one or more aspects of the present invention provide a gate driver capable of stably driving gate lines without using a carry signal, and a display device having a gate driver.

[0010] One or more aspects of the present invention provide a gate driver capable of reducing the size of the bezel region by reducing the number of thin-film transistors in each stage, and a display device having a gate driver.

[0011] In addition to the technical advantages of the present invention described above, those skilled in the art will clearly understand the additional advantages and features of the present invention as described below.

[0012] According to one aspect of the invention, a gate driver may include multiple stages configured to individually drive multiple gate lines by combining multiple group signals, multiple block signals, and multiple clock signals, wherein each of the independently driven multiple stages includes: an output buffer including a pull-up transistor configured to generate and output a scan signal of a gate on level under the control of a first node and a pull-down transistor configured to generate and output a scan signal of a gate off level under the control of a second node; a first controller configured to control the first node by combining a group signal provided via a group line from the multiple group signals, a block signal provided via a block line from the multiple block signals, and a clock signal provided via a clock line from the multiple clock signals; and a second controller configured to control the second node in the opposite direction to the operation of the first node by combining the group signals, the block signals, and the clock signals.

[0013] According to another aspect of the invention, a display device may include the aforementioned gate driver embedded in a display panel.

[0014] According to another aspect of the present invention, a display device may include: a display panel; and a gate driver embedded in the display panel, wherein the gate driver includes a plurality of stages configured to individually drive a plurality of gate lines by combining a plurality of group signals, a plurality of block signals, and a plurality of clock signals, wherein each of the independently driven plurality of stages includes: an output buffer including a pull-up transistor configured to generate and output a scan signal with a gate on level under the control of a first node and a pull-down transistor configured to generate and output a scan signal with a gate off level under the control of a second node; a first controller configured to control the first node by combining a group signal provided via a group line from the plurality of group signals, a block signal provided via a block line from the plurality of block signals, and a clock signal provided via a clock line from the plurality of clock signals; and a second controller configured to control the second node in the opposite direction to the operation of the first node by combining the group signals, the block signals, and the clock signals.

[0015] In addition to the features of the invention described above, additional technical advantages and features of the invention will be included in this specification, falling within the scope of the invention and protected by the appended claims. Nothing in this section should be considered as a limitation of the claims. Further aspects and advantages are discussed below in conjunction with embodiments of the invention. It will be understood that the foregoing general description and the following detailed description of the invention are exemplary and explanatory, intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0016] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate various aspects of the invention and, together with the description, serve to explain the principles of the invention.

[0017] In the attached diagram:

[0018] Figure 1 This is a system configuration of a display device according to an embodiment of the present invention;

[0019] Figure 2 This is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present invention;

[0020] Figure 3 This is a schematic block diagram of a gate driver according to an embodiment of the present invention;

[0021] Figure 4 This is a block diagram illustrating the configuration of a gate driver according to an embodiment of the present invention;

[0022] Figure 5 This is a block diagram illustrating an exemplary configuration of a gate driver according to an embodiment of the present invention;

[0023] Figure 6 This is an equivalent circuit diagram illustrating the configuration of each stage of a gate driver according to an embodiment of the present invention;

[0024] Figure 7 This is a driving waveform diagram of a gate driver according to an embodiment of the present invention. Detailed Implementation

[0025] The advantages and features of the invention, as well as its implementation, will be illustrated by the following aspects described with reference to the accompanying drawings. However, the invention may be embodied in various forms and should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0026] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings to describe various aspects of the invention are merely examples, and the invention is therefore not limited to the details shown. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional parts may be added unless "only" is used.

[0027] When interpreting a factor, even if not explicitly stated, the factor is interpreted as including a range of error.

[0028] When describing positional relationships, such as when the positional relationship between two parts is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless more restrictive terms such as "exactly" or "directly" are used.

[0029] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly,” “immediately after,” or “directly” are used.

[0030] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] In describing the elements of the present invention, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to distinguish the corresponding element from other elements, and the nature, order, or number of the corresponding elements is not limited by these terms. Expressions such as “connected,” “coupled,” or “adhered” to one element or layer mean that the one element or layer may be directly connected or adhered to the other element or layer, or indirectly connected or adhered to the other element or layer with one or more intermediate elements or layers disposed therebetween, unless otherwise specified.

[0032] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed elements. For example, "at least one or more of the first element, the second element, and the third element" means a combination of all elements derived from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0033] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. Multiple aspects of the present invention can be implemented independently of each other, or can be implemented together in an interdependent relationship.

[0034] Hereinafter, aspects of the invention will be described with reference to the accompanying drawings. Since the scale of each element shown in the drawings may differ from the actual scale for ease of description, the invention is not limited to the illustrated scale. Furthermore, all components of each display device according to all embodiments of the invention are operatively engaged and configured.

[0035] Figure 1 and 3 This diagram illustrates the system configuration of a display device according to one embodiment of the present invention. Figure 2 This is an equivalent circuit diagram of the sub-pixel configuration according to an embodiment of the present invention.

[0036] The display device according to one embodiment of the present invention can be any of various display devices including liquid crystal display devices, electroluminescent display devices, micro light-emitting diode (LED) display devices, etc. The electroluminescent display device can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QD) display device, or an inorganic light-emitting diode (LED) display device.

[0037] According to one embodiment of the present invention, the display device may be a flexible display device, such as a foldable display panel, a bendable display, a rollable display panel, and a stretchable display panel.

[0038] Reference Figure 1 The display device may include a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, a level shifter 600, a gamma voltage generator 700, and a power control circuit 500. The gate driver 200 and the data driver 300 may be defined as panel drivers for driving the display panel 100. The gate driver 200, the data driver 300, the timing controller 400, the gamma voltage generator 700, and the level shifter 600 may be defined as display drivers. The level shifter 600 may be integrated into the power control circuit 500, or may be omitted.

[0039] The display panel 100 displays images through a display area AA with multiple sub-pixels SP arranged in a matrix structure. The display panel 100 may be a panel with a touch sensor screen that can be built into or attached to overlap with the pixel matrix of the display area AA. The sub-pixels SP include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light, and may also include white sub-pixels emitting white light to improve brightness. Each sub-pixel SP may be connected to a signal line disposed on the display panel 100. The signal lines disposed on the display panel 100 may include gate lines GL and data lines DL, and may further include power lines, reference lines, etc.

[0040] like Figure 2 As shown, each sub-pixel SP may include pixel circuitry comprising: a light-emitting device EL connected between a first power line PW1 for providing a high-potential driving voltage (first driving voltage) EVDD and a second power line PW2 for providing a low-potential driving voltage (second driving voltage) EVSS; a first switch TFT ST1 and a second switch TFT ST2 for independently driving the light-emitting device EL; a driving TFT DT; and a storage capacitor Cst.

[0041] The light-emitting device (EL) may include an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the second power line PW2, and an organic light-emitting layer connected between the anode and the cathode. An anode may be provided independently for each sub-pixel; however, the cathode may be a common electrode shared by all sub-pixels. When a driving current is supplied to the EL from the driving TFT DT, electrons are injected from the cathode into the organic light-emitting layer, and holes are injected from the anode into the organic light-emitting layer. The electrons and holes recombine in the organic light-emitting layer, causing the fluorescent or phosphorescent material to emit light, thereby producing light with a brightness proportional to the value of the driving current.

[0042] The first switch TFT ST1 is driven by the scan signal SCANn provided from the gate driver 200 to the gate line GLn. The first switch TFT ST1 can provide the data voltage Vdata provided from the data driver 300 to the data line DLm to the gate node N1 driving TFTDT.

[0043] The second switching TFT ST2 is driven by the scan signal SCANn provided from the gate driver 200 to the gate line GLn. The second switching TFT ST2 can provide the reference voltage Vref provided from the data driver 300 to the reference line RLm to the source node N2 of the driving TFT DT. At the same time, in sensing mode, the second switching TFT ST2 can output a current reflecting the characteristics of the driving TFT DT or the characteristics of the light-emitting device EL to the reference line RLm.

[0044] The first switch TFT ST1 and the second switch TFT ST2 can be determined by... Figure 2 The same gate line GLn is shown, or it can be controlled by different gate lines.

[0045] The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT can be charged with the voltage difference between the data voltage Vdata and the reference voltage Vref provided to the gate node N1 and the source node N2 through the first switch TFT ST1 and the second switch TFT ST2 as the driving voltage Vgs, and the charged driving voltage Vgs can be maintained during the light emission period when the first switch TFT ST1 and the second switch TFT ST2 are turned off.

[0046] The driving TFT DT controls the luminous intensity of the light-emitting device EL by controlling the current Ids flowing into the light-emitting device EL according to the driving voltage Vgs charged in the storage capacitor Cst.

[0047] The power control circuit 500 can generate and output various drive voltages required to operate all components of the display device, namely panel 100, gate driver 200, data driver 300, timing controller 400, level shifter 600, and gamma voltage generator 700, by an input voltage supplied from the outside.

[0048] The timing controller 400 can receive image data and synchronization signals from an external host system. The host system can be any of a computer, TV system, set-top box, laptop, or mobile terminal system such as a mobile phone. Synchronization signals may include a dot clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc.

[0049] The timing controller 400 can use a synchronization signal and timing setting information (start timing, pulse width, etc.) stored inside the synchronization signal to generate multiple data control signals and provide the data control signals to the data driver 300. It can also generate multiple control signals and provide the multiple control signals to the level shifter 600.

[0050] The timing controller 400 performs various image processing operations, such as brightness correction and image quality correction to reduce power consumption, and provides the processed image data to the data driver 300.

[0051] For additional correction, the timing controller 400 can apply compensation values ​​for the characteristic deviations of each sub-pixel stored in memory before providing the processed data to the data driver 300. In sensing mode, the timing controller 400 senses the characteristics of each sub-pixel SP of the display panel 100 (threshold voltage of the driving TFT, mobility of the driving TFT, threshold voltage of the light-emitting device, etc.) via the data driver 300, and updates the compensation values ​​of each sub-pixel stored in memory using the sensing results. The sensing mode of the display device can be executed according to instructions from the host system, or by a user request sent via the host system, or according to the driving sequence of the timing controller 400.

[0052] The gamma voltage generator 700 generates a set of reference gamma voltages, including multiple reference gamma voltages with different voltage levels, and provides the set of reference gamma voltages to the data driver 300. Under the control of the timing controller 400, the gamma voltage generator 700 generates multiple reference gamma voltages corresponding to the gamma characteristics of the display device and provides these reference gamma voltages to the data driver 300. The gamma voltage generator 700 can be formed in a programmable gamma IC, wherein the gamma voltage generator 700 can receive gamma data from the timing controller 400, generate or adjust the reference gamma voltage level according to the gamma data, and output the reference gamma voltage level to the data driver 300.

[0053] The data driver 300 is controlled according to data control signals provided from the timing controller 400. The data driver 300 converts digital data received from the timing controller 400 into analog data signals and provides each data signal to each data line DLm of the display panel 100. The data driver 300 can convert digital data into analog data signals using grayscale voltages subdivided from multiple reference gamma voltages provided by the gamma voltage generator 700.

[0054] The data driver 300 can provide a reference voltage Vref to the reference line RLm. In sensing mode, the data driver 300 can sense the electrical characteristics of each sub-pixel SP through the reference line RLm and output the sensing results to the timing controller 400.

[0055] The level shifter 600 generates multiple gate control signals based on multiple control signals provided from the timing controller 400 and provides the gate control signals to the gate driver 200. The level shifter 600 can provide multiple group signals, multiple block signals, and multiple clock signals by level shifting or logic processing the multiple control signals provided from the timing controller 400, and can provide the generated group signals, block signals, and clock signals to the gate driver 200.

[0056] Meanwhile, if the level shifter 600 is omitted, the timing controller 400 can generate multiple gate control signals including multiple group signals, multiple block signals and multiple clock signals, and can provide multiple gate control signals to the gate driver 200.

[0057] The gate driver 200 is controlled according to a plurality of gate control signals provided from the timing controller 400 or the level shifter 600, and drives the gate lines of the display panel 100 individually. The gate driver 200 provides a gate-on level scan signal to the corresponding gate line during the driving period of each gate line, and provides a gate-off level scan signal to the corresponding gate line during the non-driving period of each gate line.

[0058] The gate driver 200 can be formed together with the TFTs of the pixel matrix of the display area AA, and can be built into the display panel 100 in an in-panel gate (GIP) type configuration. The gate driver 200 can be disposed on one side of the bezel area adjacent to the display area AA, and can provide a scan signal to one end of each gate line. Simultaneously, the gate driver 200 can be disposed on both sides of the bezel area adjacent to the display area AA, and can provide scan signals to both ends of each gate line.

[0059] The TFTs disposed in the display area AA and the bezel area including the gate driver 200 of the display panel 100 may be at least one of the following: amorphous TFT using an amorphous silicon semiconductor layer, polycrystalline TFT using a polycrystalline silicon semiconductor layer, and oxide TFT using a metal oxide semiconductor layer.

[0060] In particular, the gate driver 200 can generate multiple scan signals by combining multiple group signals, multiple block signals, and multiple clock signals provided from the timing controller 400 or the level shifter 600, and can output each scan signal to each of the multiple gate lines. The gate driver 200 can generate n scan signals (=x×y×z) by combining x clock signals (x is an integer of 2 or greater), y block signals (y is an integer of 2 or greater), and z group signals (z is an integer of 2 or greater), and can drive n gate lines individually.

[0061] Therefore, each stage of the gate driver 200 does not need to output a carry signal to control the operation of other stages, thereby reducing the number of TFTs constituting each stage. A detailed explanation will follow later.

[0062] Reference Figure 3According to one embodiment of the present invention, a display device may include a display panel 100, which includes GIP-type gate drivers 200L and 200R, a data driver 300, a control PCB 410 on which a timing controller 400 is mounted, and source PCBs 800L and 800R on which shift registers 600L and 600R are mounted.

[0063] The timing controller 400, mounted on the control PCB 410, can be connected to the source PCBs 800L and 800R via flat flexible cables FFC420L and 420R. Figure 1 The gamma voltage generator 700 and power control circuit 500 shown can be mounted on the control PCB 410.

[0064] The data driver 300 includes a plurality of data integrated circuits (ICs) 310 arranged in the X-axis direction to divide and drive data lines disposed in the display area AA of the display panel 100, and each data IC 310 can be individually mounted on each circuit film 320 to form a chip-on-film (COF) 330. The plurality of COFs 330 on which the data ICs 310 are mounted can be bonded and connected to the display panel 100 and the source PCBs 800L and 800R via an anisotropic conductive film (ACF) according to the tape autobonding (TAB) method, and can be located between the display panel 100 and the source PCBs 800L and 800R.

[0065] Level shifters 600L and 600R can be mounted on source PCBs 800L and 800R, respectively. Level shifters 600L and 600R can provide gate control signals to the first gate driver 200L and the second gate driver 200R via the outermost COF 330.

[0066] GIP-type gate drivers 200L and 200R can be located on both sides of the bezel area adjacent to the display area AA of the display panel 100. Gate drivers 200L and 200R can receive multiple gate control signals from each of level shifters 600L and 600R, thereby individually driving the gate lines located in the display area AA.

[0067] Gate drivers 200L and 200R can generate multiple scan signals by combining multiple group signals, multiple block signals and multiple clock signals received from level shifters 600L and 600R, and can output multiple scan signals to multiple gate lines respectively.

[0068] Therefore, each stage of gate drivers 200L and 200R does not require an output carry signal to control the operation of other stages, thereby reducing the number of TFTs constituting each stage. A detailed description will follow later.

[0069] As described above, the gate drivers 200, 200L, and 200R according to one embodiment of the present invention do not require a carry signal, thereby preventing display defects caused by the failure to output a carry signal. Furthermore, by reducing the number of TFTs constituting the gate drivers 200, 200L, and 200R, the circuit structure and the size of the gate drivers 200, 200L, and 200R can be reduced, and the size of the bezel area in the display panel 100 for placing the gate drivers 200, 200L, and 200R can also be reduced.

[0070] Figure 4 and 5 This is a block diagram schematically illustrating the configuration of a gate driver according to an embodiment of the present invention.

[0071] Reference Figure 4 The gate driver 200 includes multiple stages GIP#1 to GIP#n for individually outputting multiple scan signals SCAN1 to SCAN(n) to multiple gate lines, each stage being driven independently. Here, n represents the total number of gate lines disposed on the display panel 100.

[0072] The gate driver 200 may receive multiple gate control signals from the timing controller 400 and the level shifter 600. The multiple gate control signals may include z group signals GROUP1 to GROUPz, y block signals BLOCK1 to BLOCKy, and x clock signals SCCLK1 to SCCLKx.

[0073] The n stages GIP#1 to GIP#n constituting the gate driver 200 can be jointly provided with multiple power supply voltages GVDD0, GVDD1, GVDD2, GVSS0 and GVSS1 output from the power supply control circuit 500.

[0074] Each of the n stages GIP#1 to GIP#n constituting the gate driver 200 can directly receive any one of z group signals GROUP1 to GROUPz, any one of y block signals BLOCK1 to BLOCKy, and any one of x clock signals SCCLK1 to SCCLKx, can generate each scan signal SCANk (k = 1 to n), and can output the generated scan signal.

[0075] The n levels GIP#1 to GIP#n can be divided into z groups, where the z group signals GROUP1 to GROUPz are provided separately to the z groups. Each of the z groups can be divided into y blocks, where the y block signals BLOCK1 to BLOCKy are provided separately to the y blocks. Each of the y blocks can include x levels, where x clock signals SCCLK1 to SCCLKx are provided separately to the x levels.

[0076] n levels GIP#1 to GIP#n can generate n (=x×y×z) scan signals by combining z group signals, y block signals and x clock signals, and can drive n gate lines individually.

[0077] For example, the gate driver 200 for driving 2160 gate lines of a UHD may include 2160 stages and may generate and output 2160 (=12×12×15) scan signals individually by combining 12 clock signals, 12 block signals and 15 group signals.

[0078] For ease of explanation, Figure 5 An exemplary case is shown where the gate driver includes 18 (n=18) levels GIP#1 to GIP#18.

[0079] The gate driver 200, including the first to eighteenth levels GIP#1 to GIP#18, can receive two group signals GROUP1 and GROUP2, three block signals BLOCK1 to BLOCK3, and three clock signals SCCLK1 to SCCLK3 from the timing controller 400 or the level shifter 600. It can generate 18 scan signals SCAN1 to SCAN18 individually and output scan signals to 18 gate lines respectively.

[0080] Levels 1 through 18, GIP#1 through GIP#18, can be divided into a first group (G1) providing the first group signal (GROUP1) and a second group (G2) providing the second group signal (GROUP2). The first group (G1) can be further divided into blocks B11 (1-1) providing the first block signal (BLOCK1), blocks B12 (1-2) providing the second block signal (BLOCK2), and blocks B13 (1-3) providing the third block signal (BLOCK3). The second group (G2) can be divided into blocks B21 (2-1) providing the first block signal (BLOCK1), blocks B22 (2-2) providing the second block signal (BLOCK2), and blocks B23 (2-3) providing the third block signal (BLOCK3). Each of the 1-1 B11, 1-2 B12, and 1-3 B13 included in the first group G1 and each of the 2-1 B21, 2-2 B22, and 2-3 B23 included in the second group G may include three levels GIP#3k-2 to GIP#3k (k = 1 to 6) that are individually provided with first to third clock signals SCCLK1 to SCCLK3.

[0081] Therefore, according to one embodiment of the present invention, the gate driver 200 can generate n (=x×y×z) scan signals by combining z group signals GROUP1 to GROUPz, y block signals BLOCK1 to BLOCKy, and x clock signals SCCLK1 to SCCLKx directly provided from the timing controller 400 or the level shifter 600, and can output the generated scan signals. Thus, each of the n stages GIP#1 to GIP#n does not need to be used to control the carry signals of other stages, thereby preventing problems caused by carry signal failure.

[0082] Figure 6 This is an equivalent circuit diagram illustrating the basic configuration of each GIP stage in a gate driver according to an embodiment of the present invention.

[0083] Reference Figure 6 Each level GIP#k (k = 1 to n) may include a clock line 232 of any one of the clock signals SCCLKx provided with x clock signals SCCLK1 to SCCLKx, a block line 234 of any one of the block signals BLOCK1 to BLOCKy provided with y block signals, and a group line 236 of any one of the group signals GROUP1 to GROUPz provided with z group signals.

[0084] Each level GIP#k may include multiple power lines 242, 244, 246, 252 and 254 that are supplied with multiple power supply voltages GVDD0, GVDD1, GVDD2, GVSS0 and GVSS1.

[0085] For example, each stage GIP#k may include a first power line 242 provided with a first gate on voltage GVDD0, a second power line 244 provided with a second gate on voltage GVDD1, a third power line 246 provided with a third gate on voltage GVDD2, a fourth power line 252 provided with a first gate off voltage GVSS0, and a fifth power line 254 provided with a second gate off voltage GVSS1.

[0086] Here, the first to third gate conduction voltages GVDD0, GVDD1, GVDD2 represent the activation voltage levels for turning on the TFTs, and can be defined as the first to third gate high voltages, or the first to third high-potential power supply voltages. The first to third gate conduction voltages GVDD0, GVDD1, GVDD2 can have the same voltage level, or different voltage levels satisfying GVDD0 < GVDD1 < GVDD2. The first and second gate cutoff voltages GVSS0 and GVSS1 can be defined as the first and second gate low voltages or the first and second low-potential power supply voltages. The first and second gate cutoff voltages GVSS0 and GVSS1 can have the same voltage level, or different voltage levels satisfying GVSS1 < GVSS0.

[0087] Each stage GIP#k may include an output buffer 220 that generates a scan signal SCANk having a first gate conduction voltage GVDD0 and a first gate cutoff voltage GVSS0 in response to the control of the first node Q and the second node QB and outputs the scan signal SCANk through an output node OUT. Each stage GIP#k may include a controller 210 that controls the output buffer 220 via the first node Q and the second node QB by combining a clock signal SCCLKx, a block signal BLOCKy, and a group signal GROUPz. The controller of each stage GIP#k may include a first controller 212 that controls the first node Q by combining the clock signal SCCLKx provided via a clock line, the block signal BLOCKy provided via a block line, and the group signal GROUPz provided via a group line, and a second controller 214 that controls the second node QB contrary to the operation of the first node Q by combining the clock signal SCCLKx, the block signal BLOCKy, and the group signal GROUPz.

[0088] The output buffer 220 may include: a pull-up transistor T8, controlled by the voltage of the first node Q and configured to output the first gate conduction voltage GVDD0 to the output node OUT; and a pull-down transistor T9, controlled by the voltage of the second node QB and configured to output the first gate cutoff voltage GVSS0 to the output node OUT.

[0089] The pull-up TFT T8 may conduct when the voltage of the first node Q, which is the output of the first controller 212, is at the gate conduction level, and may output a scan signal SCANk at the gate conduction level using the first gate conduction voltage GVDD0 provided via the first power line 242.

[0090] The pull-down TFT T9 can be turned on when the voltage of the second node QB, which is the output of the second controller 214, is at the gate on level, and can output a scan signal SCANk with the gate off level using the first gate off voltage GVSS0 provided via the fourth power line 252.

[0091] The first controller 212 can output a clock signal SCCLKx with a gate-on level to the first node Q, and can activate the first node Q when all of the clock signal SCCLKx, the block signal BLOCKy, and the group signal GROUPz are at the gate-on level (e.g., high level), thereby turning on the pull-up TFT T8. The first controller 212 can output a clock signal SCCLKx with a gate-off level or a second gate-off voltage GVSS1 to the first node Q, and can deactivate the first node Q when at least any one of the clock signal SCCLKx, the block signal BLOCKy, and the group signal GROUPz is at the gate-off level (e.g., low level), thereby turning off the pull-up TFT T8.

[0092] For example, the first controller 212 may include: a first TFT T1 and a second TFT T2 connected in series between the clock line 232 and the first node Q and controlled by the block signal BLOCKy and the group signal GROUPz; and a third TFT T3 connected between the first node Q and the fifth power line 254 and controlled by the third gate on-state voltage GVDD2.

[0093] The first TFT T1 can be controlled and turned on by the block signal BLOCKy provided to the gate from the block line 234, and can output the clock signal SCCLKx provided to the drain from the clock line 232 to the drain of the second TFT T2.

[0094] The second TFT T2 can be controlled and turned on by the group signal GROUPz provided to the gate from the group line 236, and can output the clock signal SCCLKx provided via the first TFT T1 to the first node Q.

[0095] The third TFT T3 can be turned on by the third gate turn-on voltage GVDD2 supplied to the gate from the third power line 246, and the first node Q can be connected to the second gate cut-off voltage GVSS1 of the fifth power line 254.

[0096] When the clock signal SCCLKx, the block signal BLOCKy, and the group signal GROUPz are all at the gate-on level (high level), the first TFT T1 and the second TFT T2 output the gate-on level clock signal SCCLKx to the first node Q, and then activate the first node Q, thereby turning on the pull-up TFT T8.

[0097] When the first TFT T1 and the second TFT T2 are at the gate-on level and the clock signal SCCLKx is at the gate-off level, they output the clock signal SCCLKx at the gate-off level, and then deactivate the first node Q, thereby turning off the pull-up TFT T8.

[0098] When at least one of the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz is at the gate cutoff level, the third TFT T3 outputs the second gate cutoff voltage GVSS1 to the first node Q, deactivating the first node Q and thus turning off the pull-up TFT T8.

[0099] When all of the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz are at the gate on level, the second controller 214 outputs a second gate off voltage GVSS1 to the second node QB and deactivates the second node QB, thereby turning off the pull-down TFT T9. When at least one of the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz is at the gate off level, the second controller 214 outputs a second gate on voltage GVDD1 to the second node QB and activates the second node QB, thereby turning on the pull-down TFT T9.

[0100] For example, the second controller 214 may include: a fourth TFT T4 connected between the second power line 244 and the second node QB and controlled by the third gate on-state voltage GVDD2 of the third power line 246; and a fifth TFT T5, a sixth TFT T6, and a seventh TFT T7 connected in series between the second node QB and the fifth power line 254 and controlled by the clock signal SCCLKx, the block signal BLOCKy, and the group signal GROUPz, respectively. When the block signal and the group signal are at the gate on-state, the second controller 214 may output a second gate off-state voltage to the second node QB via the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and when at least one of the clock signal, the block signal, and the group signal is at the gate off-state, the second controller 214 may output a second gate on-state voltage to the second node QB via the fourth transistor T4.

[0101] The fourth TFT T4 is turned on by the third gate on-state voltage GVDD2 supplied to the gate from the third power supply line 246, and can output the second gate on-state voltage GVDD1 supplied to the drain from the second power supply line 244 to the second node QB. When the fourth TFT T4 is turned on by the third gate on-state voltage GVDD2, the third gate on-state voltage GVDD2 is higher than the second gate on-state voltage GVDD1, thereby the third TFT T4 is determined to remain in the on-state.

[0102] The fifth TFT T5 can be controlled by the clock signal SCCLKx provided to the gate from the clock line 232, and the second node QB can be connected to the drain of the sixth TFT T6, for example, the sixth TFT T6.

[0103] The sixth TFT T6 can be controlled by the block signal BLOCKy provided to the gate from the block line 234, and the fifth TFT T5 can be connected to the seventh TFT T7, for example, the source of the fifth TFT T5 can be connected to the drain of the seventh TFT T7.

[0104] The seventh TFT T7 is controlled by the group signal GROUPz provided to the gate by the group line 236, and the source of the sixth TFT T6, for example, can be connected to the second gate cutoff voltage GVSS1 of the fifth power supply line 254.

[0105] When the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz are all at the gate on level, the fifth to seventh TFTs can connect the second node QB to the second gate off voltage GVSS1 of the fifth power line 254, thereby deactivating the second node QB and turning off the pull-down TFT T9.

[0106] When the pull-up TFT T8 and pull-down TFT T9 are turned off by the second gate cutoff voltage GVSS1 of their respective gates, the second gate cutoff voltage GVSS1 of the respective gates is lower than the first gate cutoff voltage GVSS0 of the respective source. Therefore, the pull-up TFT T8 and pull-down TFT T9 are reliably kept in the off state even under negative threshold voltage conditions, thereby preventing leakage current.

[0107] Since the clock signal SCCLKx is connected to the drain of the first TFT T1 through the first controller 212, the number of TFTs T1 to T3 constituting the first controller 212 can be reduced to less than the number of TFTs T4 to T7 constituting the second controller 214.

[0108] Therefore, when the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz are all at the gate on level, each stage GIP#k can turn on the pull-up TFT T8 and turn off the pull-down TFT T9, thereby outputting the first gate on voltage GVDD0 as the gate on level scan signal SCANk. Simultaneously, when at least one of the clock signal SCCLKx, block signal BLOCKy, and group signal GROUPz is at the gate off level, each stage GIP#k can turn off the pull-up TFT T8 and turn on the pull-down TFT T9, thereby outputting the first gate off voltage GVSS0 as the gate off level scan signal SCANk.

[0109] Therefore, in the case of the gate driver 200 according to one embodiment of the present invention, each stage GIP#k (k = 1 to 9) is formed by 9 TFTs. Thus, compared with the configuration of each stage of the gate driver of a comparative example that includes an input section, a reset section, an inverter, an output buffer, and a stabilizing section as needed for the carry signal, the number of TFTs in each stage according to the embodiment of the present invention is reduced, thereby reducing the circuit structure and the size of the gate driver 200, thereby reducing the size of the bezel area.

[0110] Figure 7 This is according to one embodiment of the present invention. Figure 5 and 6 The diagram shows the driving waveform of the gate driver.

[0111] Reference Figures 5 to 7 The gate driver 200, with 18 levels GIP#1 to GIP#18, can receive x = 3 clock signals SCCLK1, SCCLK2, and SCCLK3; y = 3 block signals BLOCK1, BLOCK2, and BLOCK3; and z = 2 group signals GROUP1 and GROUP2. It can sequentially generate and output 18 scan signals SCAN1 to SCAN18 without using a carry signal. The 18 scan signals SCAN1 to SCAN18 can sequentially output gate-on level scan signals SCAN1 to SCAN18 in the corresponding first to eighteenth time periods T1 to T18.

[0112] Three-phase clock signals SCCLK1, SCCLK2, and SCCLK3 with different phases may have a first section including a gate on-level (high level) portion of a first time period and a gate off-level (low level) portion of a second time period, and the gate on-level portion of the first time period may be provided by being sequentially phase-delayed.

[0113] The first time period for each clock signal SCCLK1, SCCLK2, and SCCLK3 may include at least one horizontal time period H corresponding to the time period during which a scan signal providing the gate turn-on level is provided to each gate line. The second time period may be configured to be longer than the first time period.

[0114] The three-phase block signals BLOCK1, BLOCK2 and BLOCK3 with different phases may have a second segment including a gate on level (high level) portion of the third time period and a gate off level (low level) portion of the fourth time period, wherein the gate on level portion of the third time period may be provided by sequential phase delay.

[0115] The third time period of each block signal BLOCK1, BLOCK2, and BLOCK3 can be set to be longer than the time overlapping with the first time period of clock signals SCCLK1, SCCLK2, and SCCLK3, and the fourth time period can be set to be longer than the third time period. In other words, the third time period of the gate on-level in each of the y block signals BLOCK1 to BLOCKy can be set to be longer than the time overlapping with the first time period of the x clock signals SCCLK1 to SCCLKx.

[0116] The two-phase group signals GROUP1 and GROUP2 with different phases may have a third segment including a gate on level (high level) portion of the fifth period and a gate off level (low level) portion of the sixth period, and the gate on level portion of the fifth period may be provided by sequential phase delay.

[0117] The fifth time period of each group signal GROUP1 and GROUP2 can be set to be longer than the time overlapping with the third time period of block signals BLOCK1, BLOCK2, and BLOCK3, and the sixth time period can be set to be longer than the fifth time period. In other words, the fifth time period of the gate on-level in each of the z group signals GROUP1 to GROUP2z can be set to be longer than the time overlapping with the third time period of the y block signals BLOCK1 to BLOCK3y.

[0118] Reference Figure 5 and 7 In the first group G1 of the first group of signals GROUP1, which includes the first to ninth levels GIP#1 to GIP#9, the first to third levels GIP#1, GIP#2, and GIP#3 of the 1-1 block B11 of the first block signal BLOCK1 can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The first to third levels GIP#1, GIP#2, and GIP#3 can sequentially output the first to third scan signals SCAN1, SCAN2, and SCAN3 of the gate-on level, which overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3 of the gate-on level in the overlapping portion between the first group of signals GROUP1 and the first block signal BLOCK1 of the gate-on level, respectively, and can output the gate-off level in the remaining portion.

[0119] In the first group G1, among the first to ninth levels GIP#1 to GIP#9, the fourth to sixth levels GIP#4, GIP#5, and GIP#6 of the 1-2 B12 blocks that are provided with the second signal BLOCK2 can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The fourth to sixth levels GIP#4, GIP#5, and GIP#6 can sequentially output the fourth to sixth scan signals SCAN4, SCAN5, and SCAN6, which overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively, in the overlapping portion between the first group signal GROUP1 and the second signal BLOCK2, which are at the gate-on level. They can also output the gate-off level in the remaining portion.

[0120] In the first group G1, among the first to ninth levels GIP#1 to GIP#9, the seventh to ninth levels GIP#7, GIP#8, and GIP#9 of the 1st to 3rd blocks B13, which are provided with the third block signal BLOCK3, can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The seventh to ninth levels GIP#7, GIP#8, and GIP#9 can sequentially output the seventh to ninth scan signals SCAN7, SCAN8, and SCAN9, which overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively, in the overlapping portion between the first group signal GROUP1 (gate-on level) and the third block signal BLOCK3 (gate-on level), and can output the gate-off level in the remaining portion.

[0121] In the second group G2, which provides the second group signal GROUP2, among the tenth to eighteenth levels GIP#10 to GIP#18, the tenth to eleventh level GIP#10, GIP#11, and GIP#12 of the 2-1 block B21 which provides the first block signal BLOCK1 can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The tenth to eleventh level GIP#10, GIP#11, and GIP#12 can sequentially output the tenth to twelfth level scan signals SCAN10, SCAN11, and SCAN12, which overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively, in the overlapping portion between the second group signal GROUP2 with the gate-on level and the first block signal BLOCK1 with the gate-on level, and can output the gate-off level in the remaining portion.

[0122] In the second group G2, among the tenth to eighteenth levels GIP#10 to GIP#18, the thirteenth to fifteenth levels GIP#13, GIP#14, and GIP#15 of the 2-2 blocks B22 that provide the second signal BLOCK2 can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The thirteenth to fifteenth levels GIP#13, GIP#14, and GIP#15 can sequentially output the thirteenth to fifteenth scan signals SCAN13, SCAN14, and SCAN15 that overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively, in the overlapping portion between the second group signal GROUP2 with the gate-on level and the second block signal BLOCK2 with the gate-on level, and can output the gate-off level in the remaining portion.

[0123] In the second group G2, among the tenth to eighteenth levels GIP#10 to GIP#18, the sixteenth to eighteenth levels GIP#16, GIP#17, and GIP#18 of the 2-3 B23 blocks provided with the third signal BLOCK3 can be provided with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively. The sixteenth to eighteenth levels GIP#16, GIP#17, and GIP#18 can sequentially output the sixteenth to eighteenth scan signals SCAN16, SCAN17, and SCAN18 that overlap with the first to third clock signals SCCLK1, SCCLK2, and SCCLK3, respectively, in the overlapping portion between the second group signal GROUP2 with the gate-on level and the third signal BLOCK3 with the gate-on level, and can output the gate-off level in the remaining portion.

[0124] As described above, the gate drivers 200, 200L, and 200R of the display device according to one embodiment of the present invention generate and output n (=x×y×z) scan signals by combining z group signals GROUP1 to GROUPz, y block signals BLOCK1 to BLOCKy, and x clock signals SCCLK1 to SCCLKx directly provided from the timing controller 400 or level shifters 600, 600L, and 600R. Thus, each of the n levels GIP#1 to GIP#n does not need to be used to control carry signals of other levels, thereby preventing problems caused by carry signal failures.

[0125] Furthermore, in the case of the gate drivers 200, 200L, and 200R of the display device according to one embodiment of the present invention, each stage GIP#k is formed by nine TFTs. Thus, compared to the configuration of each stage of the gate driver in a comparative example where a carry signal is required, the number of TFTs in each stage according to the embodiment of the present invention is reduced, thereby reducing the circuit structure and the size of the gate drivers 200, 200L, and 200R, thereby reducing the size of the bezel area in the display panel 100.

[0126] According to one embodiment of the present invention, the gate driver and the display device generate and output a scan signal by combining group signals, block signals and clock signals directly provided from level shifters or timing controllers in each stage of the gate driver, thereby preventing display failures due to the failure to output carry signals.

[0127] In a gate driver and display device according to an embodiment of the present invention, the number of TFTs in each stage can be reduced to nine, thereby reducing the circuit structure and the size of the gate driver, thereby reducing the size of the bezel area in the display panel.

[0128] The gate driver and display device according to one or more embodiments of the present invention can be applied to a variety of electronic devices. For example, the gate driver and display device including the gate driver according to one embodiment of the present invention can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic diaries, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigators, vehicle navigation systems, vehicle display devices, televisions, wallpaper display devices, signal marking devices, gaming devices, laptops, monitors, cameras, portable cameras, and home appliances.

[0129] A gate driver according to some embodiments may include multiple stages configured to individually drive multiple gate lines by combining multiple group signals, multiple block signals, and multiple clock signals, wherein each of the independently driven multiple stages includes: an output buffer including a pull-up transistor configured to generate and output a scan signal of a gate on level under the control of a first node and a pull-down transistor configured to generate and output a scan signal of a gate off level under the control of a second node; a first controller configured to control the first node by combining group signals provided via group lines from the multiple group signals, block signals provided via block lines from the multiple block signals, and clock signals provided via clock lines from the multiple clock signals; and a second controller configured to control the second node in the opposite direction to the operation of the first node by combining the group signals, the block signals, and the clock signals.

[0130] According to some embodiments, a display device may include the aforementioned gate driver integrated into a display panel.

[0131] According to some embodiments, the first controller can turn on the pull-up transistor by activating the first node when all of the clock signal, the block signal, and the group signal are at a gate-on level. According to some embodiments, the first controller can turn off the pull-up transistor by deactivating the first node when at least one of the clock signal, the block signal, and the group signal is at a gate-off level.

[0132] According to some embodiments, the second controller can turn off the pull-down transistor by deactivating the second node when all of the clock signal, the block signal, and the group signal are at a gate-on level. According to some embodiments, the second controller can turn on the pull-down transistor by activating the second node when at least one of the clock signal, the block signal, and the group signal is at a gate-off level.

[0133] When the pull-up transistor is turned on by the first controller, according to some embodiments, the pull-up transistor can output a scan signal of a first gate on-state voltage provided via a first power line as the gate on-state level. When the pull-down transistor is turned on by the second controller, according to some embodiments, the pull-down transistor can output a scan signal of a first gate off-state voltage provided via a fourth power line as the gate off-state level.

[0134] According to some embodiments, the first controller may include: a first transistor controlled by the block signal and configured to output the clock signal; a second transistor controlled by the group signal and configured to connect the first transistor to the first node; and a third transistor controlled by a third gate on-state voltage provided via a third power line and configured to connect a fifth power line provided with a second gate off-state voltage to the first node.

[0135] When the block signal and the group signal are at the gate on level, the first controller, according to some embodiments, can output the clock signal to the first node via the first transistor and the second transistor. When at least one of the clock signal, the block signal, and the group signal is at the gate off level, the first controller, according to some embodiments, can output the second gate off voltage to the first node via the third transistor.

[0136] According to some embodiments, the second controller may include: a fourth transistor controlled by a third gate-on voltage provided via the third power line and configured to connect a second power line provided with a second gate-on voltage to the second node; and a fifth, sixth, and seventh transistor connected in series between the second node and the fifth power line provided with the second gate-off voltage and controlled by the clock signal, the block signal, and the group signal.

[0137] When the block signal and the group signal are at the gate on level, according to some embodiments, the second controller may output the second gate off voltage to the second node via the fifth transistor, the sixth transistor, and the seventh transistor. When at least one of the clock signal, the block signal, and the group signal is at the gate off level, according to some embodiments, the second controller may output the second gate on voltage to the second node via the fourth transistor. The second gate off voltage is lower than the first gate off voltage, and the second gate on voltage is higher than the first gate on voltage and lower than the third gate on voltage.

[0138] According to some embodiments, the plurality of levels may comprise n levels by including z groups of signals individually provided with z groups of signals, where z is an integer of 2 or greater, and n = x × y × z, each of the z groups may include y blocks of signals individually provided with y blocks of signals, where y is an integer of 2 or greater, and each of the y blocks includes x levels of signals individually provided with x clock signals, where x is an integer of 2 or greater.

[0139] Each of the x clock signals according to some embodiments may have a first segment including a gate-on level portion of a first time period and a gate-off level portion of a second time period, wherein the gate-on level portion of the first time period is provided with a sequential phase delay. Each of the y block signals according to some embodiments may have a second segment including a gate-on level portion of a third time period and a gate-off level portion of a fourth time period, wherein the gate-on level portion of the third time period is provided with a sequential phase delay, and the third time period is set to be longer than the time overlapping with the first time period of the x clock signals. Each of the z group signals according to some embodiments may have a third segment including a gate-on level portion of a fifth time period and a gate-off level portion of a sixth time period, wherein the gate-on level portion of the fifth time period is provided with a sequential phase delay, and the fifth time period is set to be longer than the time overlapping with the third time period of the y block signals.

[0140] In addition to the beneficial effects of the present invention described above, other features and advantages will be clearly understood by those skilled in the art based on the foregoing description or explanation. Furthermore, those skilled in the art can achieve the features, structures, effects, etc., described in at least one example of the present invention by combining or modifying other examples. Therefore, the content related to these combinations and modifications should be interpreted as being included within the scope of this application.

[0141] The present invention described above is not limited to the embodiments and drawings described above, and various substitutions, modifications, and variations can be made in the present invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, the scope of the present invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present invention.

Claims

1. A gate driver comprising multiple stages configured to individually drive multiple gate lines by combining multiple group signals, multiple block signals, and multiple clock signals. Each of the plurality of independently driven levels includes: An output buffer, the output buffer including a pull-up transistor configured to generate and output a scan signal with a gate on level under the control of a first node and a pull-down transistor configured to generate and output a scan signal with a gate off level under the control of a second node; A first controller is configured to control the first node by combining a group signal provided via a group line from the plurality of group signals, a block signal provided via a block line from the plurality of block signals, and a clock signal provided via a clock line from the plurality of clock signals. as well as A second controller is configured to control the second node in the opposite direction to the operation of the first node by combining the group signal, the block signal, and the clock signal. The plurality of levels are comprised of n levels by including z groups of signals, each group being individually provided with z groups of signals, where z is an integer of 2 or greater, and n = x × y × z. Each of the z groups comprises y blocks, each provided with y block signals individually, where y is an integer of 2 or greater. Each of the y blocks comprises x stages that are individually provided with x clock signals, where x is an integer of 2 or greater.

2. The gate driver according to claim 1, wherein: The first controller activates the pull-up transistor by turning on the first node when all of the clock signal, the block signal, and the group signal are at the gate-on level. The first controller turns off the pull-up transistor by deactivating the first node when at least one of the clock signal, the block signal, and the group signal is at a gate cutoff level.

3. The gate driver according to claim 1, wherein: The second controller turns off the pull-down transistor by deactivating the second node when all of the clock signal, the block signal, and the group signal are at the gate-on level. The second controller turns on the pull-down transistor by activating the second node when at least one of the clock signal, the block signal, and the group signal is at the gate cutoff level.

4. The gate driver according to claim 1, wherein: When the pull-up transistor is turned on by the first controller, the pull-up transistor outputs a scan signal as the gate on-state level, which is a first gate on-state voltage provided via the first power line. When the pull-down transistor is turned on by the second controller, the pull-down transistor outputs a first gate cutoff voltage provided via the fourth power line as a scan signal for the gate cutoff level.

5. The gate driver of claim 1, wherein the first controller comprises: A first transistor, which is controlled by the block signal and configured to output the clock signal; A second transistor, controlled by the group of signals and configured to connect the first transistor to the first node; as well as The third transistor is controlled by a third gate on-voltage provided via a third power line and is configured to be connected to the first node by a fifth power line provided with a second gate off-voltage.

6. The gate driver according to claim 5, wherein: When the block signal and the group signal are at the gate on level, the first controller outputs the clock signal to the first node via the first transistor and the second transistor. When at least one of the clock signal, the block signal, and the group signal is at a gate cutoff level, the first controller outputs the second gate cutoff voltage to the first node via the third transistor.

7. The gate driver of claim 1, wherein the second controller comprises: A fourth transistor, controlled by a third gate-on voltage provided via a third power line and configured to be connected to the second node by a second power line provided with a second gate-on voltage; as well as The fifth, sixth, and seventh transistors are connected in series between the second node and the fifth power line provided with a second gate cutoff voltage and are controlled by the clock signal, the block signal, and the group signal.

8. The gate driver according to claim 7, wherein: When the block signal and the group signal are at the gate on level, the second controller outputs the second gate off voltage to the second node via the fifth transistor, the sixth transistor, and the seventh transistor. When at least one of the clock signal, the block signal, and the group signal is at the gate off level, the second controller outputs the second gate on voltage to the second node via the fourth transistor.

9. The gate driver according to claim 8, wherein: The second gate cutoff voltage is lower than the first gate cutoff voltage provided via the fourth power line. The second gate on-state voltage is higher than the first gate on-state voltage provided via the first power line and lower than the third gate on-state voltage.

10. The gate driver according to claim 1, wherein: Each of the x clock signals has a first segment comprising a gate-on level portion of a first time period and a gate-off level portion of a second time period, and the gate-on level portion of the first time period is provided with a phase delay. Each of the y block signals has a second segment comprising a gate-on level portion of a third time period and a gate-off level portion of a fourth time period. The gate-on level portion of the third time period is provided with a sequential phase delay, and the third time period is set to be longer than the time overlapping with the first time period of the x clock signals. Each of the z groups of signals has a third segment including a fifth time period with a gate on level and a sixth time period with a gate off level. The fifth time period with a gate on level is provided with a phase delay, and the fifth time period is set to be longer than the time that overlaps with the third time period of the y block signals.

11. The gate driver according to claim 7, wherein: The fifth transistor is controlled by the clock signal and is configured to connect the second node to the sixth transistor. The sixth transistor is controlled by the block signal and is configured to connect the fifth transistor to the seventh transistor. The seventh transistor is controlled by the group of signals and is configured to connect the sixth transistor to the second gate cutoff voltage of the fifth power line.

12. The gate driver of claim 10, wherein the second time period is configured to be longer than the first time period.

13. The gate driver of claim 10, wherein the fourth time period is configured to be longer than the third time period.

14. The gate driver of claim 10, wherein the sixth time period is configured to be longer than the fifth time period.

15. A display device, comprising: Display panel; as well as The gate driver built into the display panel, The gate driver includes multiple stages configured to individually drive multiple gate lines by combining multiple group signals, multiple block signals, and multiple clock signals. Each of the plurality of independently driven levels includes: An output buffer, the output buffer including a pull-up transistor configured to generate and output a scan signal with a gate on level under the control of a first node and a pull-down transistor configured to generate and output a scan signal with a gate off level under the control of a second node; A first controller, configured to control the first node by combining group signals provided via group lines from the plurality of group signals, block signals provided via block lines from the plurality of block signals, and clock signals provided via clock lines from the plurality of clock signals; and A second controller is configured to control the second node in the opposite direction to the operation of the first node by combining the group signal, the block signal, and the clock signal. The plurality of levels are comprised of n levels by including z groups of signals, each group being individually provided with z groups of signals, where z is an integer of 2 or greater, and n = x × y × z. Each of the z groups comprises y blocks, each provided with y block signals individually, where y is an integer of 2 or greater. Each of the y blocks comprises x stages that are individually provided with x clock signals, where x is an integer of 2 or greater.

16. The display device according to claim 15, wherein: The first controller activates the pull-up transistor by turning on the first node when all of the clock signal, the block signal, and the group signal are at the gate-on level. The first controller disables the pull-up transistor by deactivating the first node when at least one of the clock signal, the block signal, and the group signal is at a gate-off level. The second controller turns off the pull-down transistor by deactivating the second node when all of the clock signal, the block signal, and the group signal are at the gate-on level. The second controller turns on the pull-down transistor by activating the second node when at least one of the clock signal, the block signal, and the group signal is at the gate cutoff level.

17. The display device according to claim 15, wherein: When the pull-up transistor is turned on by the first controller, the pull-up transistor outputs a scan signal as the gate on-state level, which is a first gate on-state voltage provided via the first power line. When the pull-down transistor is turned on by the second controller, the pull-down transistor outputs a first gate cutoff voltage provided via the fourth power line as a scan signal for the gate cutoff level.

18. The display device according to claim 15, wherein the first controller comprises: A first transistor, which is controlled by the block signal and configured to output the clock signal; A second transistor, controlled by the group of signals and configured to connect the first transistor to the first node; as well as The third transistor is controlled by a third gate on-voltage provided via a third power line and is configured to be connected to the first node by a fifth power line provided with a second gate off-voltage.

19. The display device according to claim 18, wherein: When the block signal and the group signal are at the gate on level, the first controller outputs the clock signal to the first node via the first transistor and the second transistor. When at least one of the clock signal, the block signal, and the group signal is at a gate cutoff level, the first controller outputs the second gate cutoff voltage to the first node via the third transistor.

20. The display device according to claim 15, wherein the second controller comprises: A fourth transistor, controlled by a third gate-on voltage provided via a third power line and configured to be connected to the second node by a second power line provided with a second gate-on voltage; as well as The fifth, sixth, and seventh transistors are connected in series between the second node and the fifth power line provided with a second gate cutoff voltage and are controlled by the clock signal, the block signal, and the group signal.

21. The display device according to claim 20, wherein: When the block signal and the group signal are at the gate on level, the second controller outputs the second gate off voltage to the second node via the fifth transistor, the sixth transistor, and the seventh transistor. When at least one of the clock signal, the block signal, and the group signal is at a gate off level, the second controller outputs the second gate on voltage to the second node via the fourth transistor. The second gate cutoff voltage is lower than the first gate cutoff voltage provided via the fourth power line. The second gate on-state voltage is higher than the first gate on-state voltage provided via the first power line and lower than the third gate on-state voltage.

22. The display device according to claim 15, wherein: Each of the x clock signals has a first segment comprising a gate-on level portion of a first time period and a gate-off level portion of a second time period, and the gate-on level portion of the first time period is provided with a phase delay. Each of the y block signals has a second segment comprising a gate-on level portion of a third time period and a gate-off level portion of a fourth time period. The gate-on level portion of the third time period is provided with a sequential phase delay, and the third time period is set to be longer than the time overlapping with the first time period of the x clock signals. Each of the z groups of signals has a third segment including a fifth time period with a gate on level and a sixth time period with a gate off level. The fifth time period with a gate on level is provided with a phase delay, and the fifth time period is set to be longer than the time that overlaps with the third time period of the y block signals.

23. The display device according to claim 20, wherein: The fifth transistor is controlled by the clock signal and is configured to connect the second node to the sixth transistor. The sixth transistor is controlled by the block signal and is configured to connect the fifth transistor to the seventh transistor. The seventh transistor is controlled by the group of signals and is configured to connect the sixth transistor to the second gate cutoff voltage of the fifth power line.

24. The display device according to claim 22, wherein: The second time period is set to be longer than the first time period. The fourth time period is set to be longer than the third time period. The sixth time period is set to be longer than the fifth time period.

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