Pixel driving circuit and display device

Abstract

The application discloses a pixel driving circuit and a display device. A first voltage line provides a power supply voltage Vdd; a second voltage line provides a preset voltage, and the preset voltage is less than the power supply voltage; a first driving transistor comprises a first gate, a first electrode and a second electrode, the first electrode is electrically connected with the first voltage line in a first stage; a first end of a first storage capacitor is electrically connected with the first voltage line in the first stage, and a second end of the first storage capacitor is electrically connected with the first gate and the second electrode in the first stage; a first end of a second storage capacitor is electrically connected with the second electrode and the second end of the first storage capacitor in the first stage, and a second end of the second storage capacitor is electrically connected with the second voltage line in the first stage; a storage voltage in the first storage capacitor is Vth, and a storage voltage in the second storage capacitor is Vth+Vdd. The application effectively improves the impedance voltage drop of the power supply line, thereby avoiding the influence of the uneven image brightness of the display panel.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a pixel driving circuit and a display device. Background Technology

[0002] With the development of optoelectronic display technology and semiconductor manufacturing technology, thin-film transistor (TFT) display panels have become increasingly mature. OLED (Organic Light Emitting Diode) display panels have significant advantages in terms of thickness, color saturation, contrast ratio, and flexible display capabilities, and their development has broad prospects. Active-matrix organic light-emitting diodes (AMOLEDs) feature high density, wide viewing angle, fast response speed, and low power consumption, and are currently widely used in high-performance display fields.

[0003] Since the power lines are distributed from near to far from the power chip, the power lines at the far end have impedance, and there will be a certain voltage drop when they pass through each OLED unit. Therefore, there is a difference in the current provided by the Vdd voltage at the near end and the far end, and this effect is more obvious for larger screens. That is, the impedance voltage drop of the power lines causes uneven brightness of the display panel image.

[0004] Therefore, it is necessary to provide a pixel driving circuit and display device to effectively improve the effect of uneven brightness of the display panel caused by the impedance voltage drop of the power line. Summary of the Invention

[0005] This application provides a pixel driving circuit and display device that effectively improves the effect of uneven image brightness on the display panel caused by the impedance voltage drop of the power line.

[0006] This application provides a pixel driving circuit, the operation of which includes a first stage, the pixel driving circuit comprising:

[0007] A first voltage line, which is used to provide the power supply voltage Vdd;

[0008] A second voltage line is used to provide a preset voltage, which is less than the power supply voltage.

[0009] A first driving transistor, the first driving transistor including a first gate, a first electrode, and a second electrode, wherein the first electrode is electrically connected to the first voltage line in the first stage;

[0010] A first storage capacitor, wherein a first terminal of the first storage capacitor is electrically connected to the first voltage line in the first stage, and a second terminal of the first storage capacitor is electrically connected to the first gate and the second electrode in the first stage; and

[0011] The second storage capacitor has its first terminal electrically connected to the second electrode and the second terminal of the first storage capacitor in the first stage, and its second terminal electrically connected to the second voltage line in the first stage; both the first storage capacitor and the second storage capacitor are in a charging state in the first stage, the storage voltage in the first storage capacitor is Vth, and the storage voltage in the second storage capacitor is Vth+Vdd.

[0012] This application designs a pixel driving circuit where the first terminal of the first driving transistor is electrically connected to the first voltage line in the first stage to load the power supply voltage. The first terminal of the first storage capacitor is electrically connected to the first voltage line in the first stage, and the second terminal of the first storage capacitor is electrically connected to the first gate and the second terminal in the first stage. Similarly, the first terminal of the second storage capacitor is electrically connected to the second terminal and the second terminal of the first storage capacitor in the first stage, and the second terminal of the second storage capacitor is electrically connected to the second voltage line in the first stage. At this time, since the power supply voltage is greater than a preset voltage, the power supply voltage charges the first and second storage capacitors until the first driving transistor is turned off. At this time, the stored voltage in the first storage capacitor is Vth, and the stored voltage in the second storage capacitor is Vth + Vdd. That is, the voltage of the first gate of the first driving transistor is Vth + Vdd, the voltage of the first terminal of the first driving transistor is Vdd, and the voltage difference between the first gate and the first terminal of the first driving transistor is Vth, independent of Vdd. This effectively improves the uniformity of the display panel image brightness caused by the impedance voltage drop of the power supply line, thereby enhancing the uniformity of the display brightness of the display device.

[0013] Optionally, the operation phase of the pixel driving circuit further includes a second phase, and the pixel driving circuit further includes:

[0014] Data line, the data line being used to provide data voltage Vdata;

[0015] In the second stage, the second terminal of the second storage capacitor is disconnected from the second voltage line and electrically connected to the data line. In the second stage, the second storage capacitor is in a charging state, and the storage voltage in the second storage capacitor is Vth+Vdd+Vdata.

[0016] Optionally, the operation phase of the pixel driving circuit further includes a third phase, and the pixel driving circuit further includes:

[0017] The second driving transistor is in the off state in both the first stage and the second stage. The second driving transistor includes a second gate, a third terminal and a fourth terminal. The second gate is electrically connected to the first gate and the second terminal of the first storage capacitor. The third terminal is electrically connected to the first terminal of the first storage capacitor.

[0018] In the third stage, the second terminal of the second storage capacitor is electrically connected to the second voltage line and disconnected from the data line; in the third stage, the first terminal of the second storage capacitor is disconnected from the first gate.

[0019] The light-emitting unit has its first end electrically connected to the fourth electrode in the third stage; the first storage capacitor and the second storage capacitor discharge the light-emitting unit through the second driving transistor.

[0020] Optionally, the pixel driving circuit further includes a first switching unit, a first end of the first switching unit being electrically connected to a first end of the light-emitting unit, a second end of the first switching unit being electrically connected to a second end of the light-emitting unit, and the first end of the first switching unit and the second end of the first switching unit being electrically connected in the first stage and / or the second stage.

[0021] Optionally, the pixel driving circuit further includes a first switching unit and a reset voltage line. The reset voltage line is used to provide a reset voltage, which is less than the first voltage. The first end of the first switching unit is electrically connected to the first end of the light-emitting unit, and the second end of the first switching unit is electrically connected to the reset voltage line. The first end of the first switching unit and the second end of the first switching unit are electrically connected in the first stage and / or the second stage.

[0022] Optionally, the pixel driving circuit further includes a second switching unit and the third switching unit. The first end of the second switching unit is electrically connected to the data line, and the second switching unit is electrically connected to the first end of the first storage capacitor. The second switching unit is in an off state during the first stage.

[0023] The first terminal of the third switching unit is electrically connected to the fourth terminal of the second driving transistor, and the second terminal of the third switching unit is electrically connected to the first terminal of the light-emitting unit. The third switching unit is in an off state during the first stage.

[0024] Optionally, the pixel driving circuit further includes a fourth switching unit, the first terminal of which is electrically connected to the first terminal of the first storage capacitor, and the second terminal of which is electrically connected to the second voltage line. The fourth switching unit is in a conducting state in the first stage; the fourth switching unit is in a disconnected state in the second stage; the second switching unit is in a conducting state in the second stage; and the third switching unit is in a disconnected state in the second stage.

[0025] Optionally, the pixel driving circuit further includes a fifth switching unit and a sixth switching unit. The first terminal of the fifth switching unit is electrically connected to the first voltage line, and the second terminal of the fifth switching unit is electrically connected to the first terminal of the first storage capacitor and the third terminal of the second driving transistor. The fifth switching unit is in the conducting state in both the first and second stages, and the fifth switching unit is in the disconnected state in the third stage.

[0026] The first terminal of the sixth switching unit is electrically connected to the first gate and the second gate, and the second terminal of the sixth switching unit is electrically connected to the first terminal of the second storage capacitor and the second terminal of the first driving transistor. The sixth switching unit is in the conducting state in both the first stage and the second stage, and the sixth switching unit is in the disconnected state in the third stage.

[0027] The second switching unit is in the off state in the third stage, and the third and fourth switching units are in the on state in the third stage.

[0028] Optionally, the first driving transistor and the second driving transistor are N-type transistors;

[0029] The pixel driving circuit further includes a first scan line, a second scan line, a third scan line, and a control line. The control terminals of the fifth and sixth switching units are both electrically connected to the first scan line. The control terminal of the second switching unit is electrically connected to the second scan line. The control terminal of the fourth switching unit is electrically connected to the third scan line. The control terminal of the third switching unit is electrically connected to the control line. The second, third, fourth, fifth, and sixth switching units are N-type transistors or P-type transistors.

[0030] Secondly, embodiments of this application provide a display device including the pixel driving circuit described above. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below.

[0032] Figure 1 This is a schematic diagram of a first type of pixel driving circuit in the first stage provided in the embodiments of this application;

[0033] Figure 2 This is a schematic diagram of a second type of pixel driving circuit in the first stage provided in the embodiments of this application;

[0034] Figure 3 This is a circuit diagram of the pixel driving circuit provided in the embodiment of this application in the second stage;

[0035] Figure 4 This is a circuit diagram of the pixel driving circuit in the third stage provided in the embodiments of this application;

[0036] Figure 5 This is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of this application;

[0037] Figure 6 This is a circuit diagram of a first connection method of the first switching unit, the second driving transistor, and the third switching unit in the first stage pixel driving circuit provided in this application embodiment.

[0038] Figure 7 This is a circuit diagram illustrating a second connection method of the first switching unit in the first-stage pixel driving circuit provided in an embodiment of this application.

[0039] Figure 8 This is a schematic diagram of the pixel driving circuit provided in the embodiment of this application, in which the first switching unit, the third switching unit, and the fifth switching unit are in the off state in the second stage.

[0040] Figure 9 This is a circuit diagram of the pixel driving circuit provided in the embodiment of this application, in the third stage where the first switching unit, the second switching unit, the fifth switching unit, and the sixth switching unit are in the off state;

[0041] Figure 10 This is a timing diagram of a pixel driving circuit provided in an embodiment of this application.

[0042] Icon labels:

[0043] Pixel driving circuit 100; first voltage line 10; second voltage line 20; first storage capacitor C1; second storage capacitor C2; light-emitting unit 30; first driving transistor TA2; first gate G1; first electrode S1; second electrode D1; second driving transistor T1; second gate G2; third electrode S2; fourth electrode D2; data line 40; first switching unit TA4; second switching unit TB1; third switching unit T2; fourth switching unit T3; fifth switching unit TA1; sixth switching unit TA3; first scan voltage SCANA; second scan voltage SCANB; third scan voltage SCANC; control voltage Emit. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. In addition, the reference to "embodiment" or "implementation method" in this application means that a specific feature, structure or characteristic described in connection with the embodiment or implementation method can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0045] In describing some embodiments, the term "electrical connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. As another example, the term "electrical connection" may be used in describing some embodiments to indicate that two or more components have physical contact or an electrical signal path, such as two components being connected by a signal line, or other electrical components or circuits existing between the two components, but a signal path exists between them through these other electrical components. However, the term "electrical connection" may also refer to two or more components that do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] In OLED display devices, since the power lines are distributed from near to far from the power chip, the power lines at the far end have impedance, and there will be a certain voltage drop when they pass through each OLED cell. Therefore, there is a difference in the current provided by the Vdd voltage at the near end and the far end, and this effect is more obvious for larger screens. That is, the impedance voltage drop of the power lines leads to uneven brightness of the display panel image.

[0047] This application provides a pixel driving circuit and display device that effectively improves the effect of uneven image brightness on the display panel caused by the impedance voltage drop of the power line.

[0048] Please see Figure 1 , Figure 1 This is a partial structural diagram of the pixel driving circuit. The pixel driving circuit 100 includes at least a first voltage line 10, a second voltage line 20, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting unit 30.

[0049] The operation stages of the pixel driving circuit 100 include a first stage t1, a second stage t2, and a third stage t3. Among them, the first stage t1 and the second stage t2 are the stages before the light-emitting unit 30 emits light, and the third stage t3 is the light-emitting stage of the light-emitting unit 30.

[0050] The first voltage line 10 is used to provide the power supply voltage Vdd. In other words, the first voltage line 10 is a power supply line.

[0051] The second voltage line 20 is used to provide a preset voltage V1. The preset voltage V1 is less than the power supply voltage. The preset voltage V1 can be an external voltage, denoted as V1. The preset voltage V1 is a low voltage.

[0052] Please see Figure 2 Optionally, the preset voltage V1 can be the reference ground of the display panel or the common electrode voltage of the display panel.

[0053] Please see Figure 2 The pixel driving circuit 100 further includes a first driving transistor TA2.

[0054] Please see Figure 2 The first driving transistor TA2 includes a first gate G1, a first electrode S1, and a second electrode D1. The first electrode S1 can be the source, and the second electrode D1 can be the drain; alternatively, the first electrode S1 can be the drain, and the second electrode D1 can be the source. In this embodiment, the first electrode S1 can be the source, and the second electrode D1 can be the drain.

[0055] The first electrode S1 is electrically connected to the first voltage line 10 in the first stage t1, that is, the first electrode S1 is electrically connected to the first voltage line 10 in the first stage t1, so that the first electrode S1 is loaded with the power supply voltage Vdd.

[0056] The first terminal of the first storage capacitor C1 is electrically connected to the first voltage line 10 during the first stage t1, and the second terminal of the first storage capacitor C1 is electrically connected to the first gate G1 and the second terminal D1 during the first stage t1. It can be understood that the first storage capacitor C1 is used to store the voltage difference, Vsg, between the first terminal S1 and the first gate G1 of the first driving transistor TA2. Furthermore, during the first stage t1, the drain of the first driving transistor TA2 is electrically connected to the first gate G1.

[0057] During the first stage t1, the first terminal of the second storage capacitor C2 is electrically connected to the second terminal D1 and the second terminal of the first storage capacitor C1, and the second terminal of the second storage capacitor C2 is electrically connected to the second voltage line 20 during the first stage t1. Optionally, the second voltage line 20 can be the reference ground of the display panel or the common terminal of the display panel.

[0058] Since the first terminal S1 of the first driving transistor TA2 is at a high potential and the first gate G1 of the first driving transistor TA2 is at a relatively low potential, the first driving transistor TA2 is operating in the amplification region. At this time, the first terminal S1 of the first driving transistor TA2 is connected to the second terminal D1.

[0059] Furthermore, since the first terminal of the first storage capacitor C1 is at a high potential, but the second terminal of the second storage capacitor C2 is essentially grounded, both the first storage capacitor C1 and the second storage capacitor C2 are in a charging state during the first stage t1.

[0060] Once the first storage capacitor C1 is charged to the point where the first driving transistor TA2 is cut off, it can no longer be charged. At this time, the stored voltage in the first storage capacitor C1 is Vth, where Vth is the threshold voltage of the first driving transistor TA2.

[0061] Since the potential at the first terminal of the first storage capacitor C1 is Vdd, and the voltage stored in the first storage capacitor C1 is Vth, the voltage stored in the second storage capacitor C2 is Vth + Vdd.

[0062] Please see Figure 2 The pixel driving circuit 100 further includes a second driving transistor T1, which includes a second gate G2, a third terminal S2, and a fourth terminal D2. The third terminal S2 can be the source, and the fourth terminal D2 can be the drain; alternatively, the fourth terminal D2 can be the drain, and the third terminal S2 can be the source. In this embodiment, the third terminal S2 can be the source, and the fourth terminal D2 can be the drain.

[0063] The third electrode S2 is electrically connected to the first electrode S1, and the third electrode S2 and the first electrode S1 have the same potential.

[0064] The second gate G2 is electrically connected to the first gate G1. The second gate G2 has the same potential as the first gate G1.

[0065] The fourth electrode D2 is electrically connected to the light-emitting unit 30. The first terminal of the second storage capacitor C2 is electrically connected to the first gate G1 and the second gate G2. The second terminal of the second storage capacitor C2 is equivalent to ground. Therefore, the voltage stored in the second storage capacitor C2 is the potential of the first gate G1 of the first driving transistor TA2, and also the potential of the second gate G2 of the second driving transistor T1. Since the potential of the first gate G1 of the first driving transistor TA2 and the potential of the second gate G2 of the second driving transistor T1 are both Vth + Vdd, the voltage of the first terminal S1 of the first driving transistor TA2 and the third terminal S2 of the second driving transistor T1 is Vdd. The voltage difference between the first gate G1 and the first terminal S1 of the first driving transistor TA2, and the voltage difference between the second gate G2 and the third terminal S2 of the second driving transistor T1 are independent of Vdd. This effectively improves the effect of the impedance voltage drop of the power line on the uneven brightness of the display panel image, and improves the uniformity of the display brightness of the display device.

[0066] Of course, in other embodiments, the preset voltage V1 of the display panel can also be an external small voltage to initialize the TFT element, thereby reducing the parasitic capacitance generated by the TFT device and affecting the display brightness.

[0067] This application designs a pixel driving circuit 100 such that the first terminal S1 of the first driving transistor TA2 is electrically connected to the first voltage line 10 in the first stage t1 to apply the power supply voltage. This also electrically connects the first terminal of the first storage capacitor C1 to the first voltage line 10 in the first stage t1, and the second terminal of the first storage capacitor C1 to the first gate G1 and the second terminal D1 in the first stage t1. Furthermore, it electrically connects the first terminal of the second storage capacitor C2 to the second terminal D1 and the second terminal of the first storage capacitor C1 in the first stage t1, and the second terminal of the second storage capacitor C2 to the second voltage line 20 in the first stage t1. At this time, because... When the power supply voltage is greater than the preset voltage V1, the power supply voltage charges the first storage capacitor C1 and the second storage capacitor C2 until the first driving transistor TA2 is turned off. At this time, the storage voltage in the first storage capacitor C1 is Vth, and the storage voltage in the second storage capacitor C2 is Vth+Vdd. That is, the voltage of the first gate G1 of the first driving transistor TA2 is Vth+Vdd, the voltage of the first terminal S1 of the first driving transistor TA2 is Vdd, and the voltage difference between the first gate G1 and the first terminal S1 of the first driving transistor TA2 is Vth, which is independent of Vdd. This effectively improves the effect of the impedance voltage drop of the power line on the uneven brightness of the display panel image and improves the uniformity of the display brightness of the display device.

[0068] Please see Figure 3 The pixel driving circuit 100 also includes a data line 40.

[0069] The data line 40 is used to provide the data voltage Vdata.

[0070] In the second stage t2, the second terminal of the second storage capacitor C2 is disconnected from the second voltage line 20 and electrically connected to the data line 40. The electrical connection methods of the first terminal of the second storage capacitor C2, the first driving transistor TA2, and the first storage capacitor C1 are the same as in the first stage t1.

[0071] The data line 40 provides the data voltage. When the second terminal of the second storage capacitor C2 is electrically connected to the data line 40, the data line 40 acts as a charge pump, applying the data voltage to the first terminal of the second storage capacitor C2. The second storage capacitor C2 is in a charging state during the second stage t2. The stored voltage in the second storage capacitor C2 is Vth + Vdd + Vdata. At this time, the potentials of the first gate G1 and the second gate G2 are Vth + Vdd + Vdata. The potential of the first terminal S1 of the first driving transistor TA2 and the third terminal S2 of the second driving transistor T1 is Vdd. At this time, the voltage difference between the third terminal S2 of the second driving transistor T1 and the second gate G2 is Vth + Vdata.

[0072] Optionally, the second driving transistor T1 is in the off state in both the first stage t1 and the second stage t2. That is, the third terminal S2 and the fourth terminal D2 of the second driving transistor T1 are not conducting. Specifically, the fourth terminal D2 of the second driving transistor T1 and the light-emitting unit 30 are both in the off state in both the first stage t1 and the second stage t2. Thus, the fourth terminal D2 of the second driving transistor T1 is essentially in a floating state, and consequently, the third terminal S2 and the fourth terminal D2 of the second driving transistor T1 are not conducting.

[0073] Please see Figure 4 In the third stage t3, the second gate G2 is electrically connected to the first gate G1 and the second terminal of the first storage capacitor C1. The third terminal S2 is electrically connected to the first terminal of the first storage capacitor C1 in the third stage t3.

[0074] The first terminal of the light-emitting unit 30 is electrically connected to the fourth electrode D2 in the third stage t3. In this stage, the second driving transistor T1 operates in the amplification region, that is, the third electrode S2 is connected to the fourth electrode D2.

[0075] In the third stage t3, the second terminal of the second storage capacitor C2 is electrically connected to the second voltage line 20 and disconnected from the data line 40.

[0076] The first terminal of the second storage capacitor C2 is disconnected from the first gate G1 and the second gate G2 in the third stage t3.

[0077] Due to the voltage stabilizing effect of the first storage capacitor C1 and the second storage capacitor C2, the first storage capacitor C1 and the second storage capacitor C2 discharge to the light-emitting unit 30 through the second driving transistor T1. At this time, the potential of the second gate G2 is Vth+Vdata. After passing through the second driving transistor T1, the current of the fourth electrode D2 is positively correlated with Vdata and is unrelated to Vth and Vdd.

[0078] The first driving transistor TA2 and the second driving transistor T1 form a mirror-symmetric current source. At this time, the potential of the second terminal D1 of the first driving transistor TA2 is the same as the potential of the fourth terminal D2 of the second driving transistor T1.

[0079] The threshold voltage of the driving transistor in each pixel unit of an OLED display panel varies, causing inconsistent current to the light-emitting diodes in each pixel unit, resulting in uneven brightness of the OLED display panel. Furthermore, as the driving transistors operate for longer periods, the materials age and deteriorate, leading to problems such as threshold voltage drift, which also contributes to uneven display performance. This unevenness worsens with increasing driving time and the aging of the driving transistor materials.

[0080] The pixel driving circuit 100 provided in this application, through the circuit design of the first stage t1, the second stage t2, and the third stage t3, ensures that the voltage difference between the gate and source of the driving transistor is V during the light-emitting stage. sg =V th +V data .

[0081] The expression for the drive current generated by the driving transistor can be simplified to:

[0082]

[0083] As can be derived from the formula, the driving current generated by the driving transistor in this application is ultimately determined only by μ, W, L, and C. GI The current passing through the light-emitting unit 30 is determined by the data voltage Vdata. That is, the current passing through the light-emitting unit 30 is unrelated to Vth and Vdd, which can effectively avoid the problem of the threshold voltage of the driving transistor drifting due to the aging and variation of the driving transistor material, thus affecting the driving current. It also avoids the problem of uneven brightness of the display panel image caused by the impedance voltage drop of the first voltage line 10 (power line), which can effectively improve the display brightness accuracy of the display panel.

[0084] In this embodiment, the light-emitting unit 30 is a current-driven light-emitting diode, including but not limited to an organic light-emitting diode (OLED). For example, the first and second ends of the light-emitting unit 30 are the anode and cathode of the light-emitting diode, respectively.

[0085] This application does not limit the specific structure of the pixel driving circuit 100. The following description, in conjunction with the accompanying drawings, illustrates one example of the pixel driving circuit 100. Of course, the pixel driving circuit 100 provided in this application includes, but is not limited to, the following embodiments.

[0086] Please see Figure 5 and Figure 6 The pixel driving circuit 100 further includes a first switching unit TA4. Figure 6 The "×" indicates that the device is in the off or open state.

[0087] The first switching unit TA4 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the on / off state of the first and second terminals. The first terminal of the first switching unit TA4 is electrically connected to the first terminal of the light-emitting unit 30, and the second terminal of the first switching unit TA4 is electrically connected to the second terminal of the light-emitting unit 30.

[0088] In one alternative implementation, please refer to Figure 6 The first terminal of the first switching unit TA4 and the second terminal of the first switching unit TA4 are electrically connected in the first stage t1 and / or the second stage t2. Optionally, the first terminal of the first switching unit TA4 and the second terminal of the first switching unit TA4 are electrically connected in the first stage t1. Optionally, the first terminal of the first switching unit TA4 and the second terminal of the second switching unit are electrically connected in both the first stage t1 and the second stage t2.

[0089] When the light-emitting unit 30 operates for a long time, the anode is under a high voltage for an extended period, which can easily generate parasitic capacitance. This results in residual charge on the anode, which, through repeated charging and discharging, forms a built-in electric field, affecting the light emission accuracy and lifespan of the OLED.

[0090] Before the light-emitting unit 30 emits light, the anode and cathode of the light-emitting unit 30 are short-circuited by electrically connecting the first terminal and the second terminal of the first switching unit TA4, so as to eliminate the built-in electric field of the light-emitting unit 30 and avoid the built-in electric field of the light-emitting unit 30 from affecting the light emission accuracy and lifespan.

[0091] During the first stage t1 and the second stage t2, the fourth terminal D2 of the second driving transistor T1 is disconnected from the light-emitting unit 30. During this process, the first switching unit TA4 is turned on, short-circuiting the anode and cathode of the light-emitting unit 30 to eliminate the built-in electric field of the light-emitting unit 30 and to prevent it from being affected by the second driving transistor T1.

[0092] In another alternative implementation, please refer to Figure 7 The pixel driving circuit 100 further includes a first switching unit TA4 and a reset voltage line. The reset voltage line provides a reset voltage. The reset voltage is less than the power supply voltage. A first terminal of the first switching unit TA4 is electrically connected to a first terminal of the light-emitting unit 30, and a second terminal of the first switching unit TA4 is electrically connected to the reset voltage line. The first terminal and the second terminal of the first switching unit TA4 are electrically connected in the first stage t1 and / or the second stage t2.

[0093] This application does not limit the magnitude of the reset voltage. The reset voltage is applied to the first terminal of the light-emitting unit 30, which initializes the light-emitting unit 30, eliminates the built-in electric field, and will not burn out the light-emitting unit 30. When the potential of the second terminal of the light-emitting unit 30 is Vss, the potential of the reset voltage is near Vss, slightly less than or slightly greater than Vss. For example, if Vss is -5V, the reset voltage V2 can be -3V, -2V, etc.

[0094] Optionally, the first terminal of the first switching unit TA4 and the second terminal of the first switching unit TA4 are electrically connected in the first stage t1. Optionally, the first terminal of the first switching unit TA4 and the second terminal of the first switching unit TA4 are electrically connected in the second stage t2. Optionally, the first terminal of the first switching unit TA4 and the second terminal of the first switching unit TA4 are electrically connected in both the first stage t1 and the second stage t2.

[0095] If VSS is 0V or a negative voltage, then when the first switching unit TA4 is turned on, the anode of the OLED is written with a voltage Vss-Vref that is more negative than Vss, where Vref is a positive voltage. Vss-Vref ensures that the light-emitting unit 30 will not be burned out, nor will the OLED emit light.

[0096] Compared to the first implementation method, this implementation method controls and removes the built-in electric field of the OLED more quickly and thoroughly, thus effectively improving the OLED lifespan.

[0097] Before the light-emitting unit 30 emits light, the anode and cathode of the light-emitting unit 30 are short-circuited by electrically connecting the first terminal and the second terminal of the first switching unit TA4, so as to eliminate the built-in electric field of the light-emitting unit 30 and avoid the built-in electric field of the light-emitting unit 30 from affecting the light emission accuracy and lifespan.

[0098] Of course, the first switching unit TA4 is in the conducting state in the third stage t3, so as to realize the electrical conduction between the second driving transistor T1 and the light-emitting unit 30, and then discharge the light-emitting unit 30.

[0099] Please see Figure 5 and Figure 8 The pixel driving circuit 100 further includes a second switching unit TB1 and a third switching unit T2. Figure 8 The "×" indicates that the device is in the off or open state.

[0100] The third switching unit T2 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the conduction or disconnection of the first and second terminals.

[0101] The first terminal of the third switching unit T2 is electrically connected to the fourth terminal D2 of the second driving transistor T1, and the second terminal of the third switching unit T2 is electrically connected to the first terminal of the light-emitting unit 30. The third switching unit T2 is in an off state during the first stage t1 and the second stage t2. At this time, the first storage capacitor C1 and the second storage capacitor C2 can be charged to configure the potential of the second gate G2 of the second driving transistor T1 and the potential of the first terminal S1 of the second driving transistor T1. Furthermore, the built-in electric field of the light-emitting unit 30 can be eliminated by controlling the conduction of the first switching unit TA4.

[0102] The third switching unit T2 is turned on in the third stage t3, i.e. the light-emitting stage, so that the second driving transistor T1 is turned on with the light-emitting unit 30, and the first storage capacitor C1 and the second storage capacitor C2 discharge to the light-emitting unit 30 through the second driving transistor T1.

[0103] The second switching unit TB1 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the on / off state of the first and second terminals. The first terminal of the second switching unit TB1 is electrically connected to the data line 40, and the second terminal of the second switching unit TB1 is electrically connected to the second terminal of the second storage capacitor C2.

[0104] The second switching unit TB1 is in the off state during the first stage t1, thereby disconnecting the second storage capacitor C2 from the data line 40.

[0105] The second switching unit TB1 is in the conducting state in the second stage t2, realizing the electrical connection between the second storage capacitor C2 and the data line 40.

[0106] The second switching unit TB1 is in the off state in the third stage t3, thereby disconnecting the second storage capacitor C2 from the data line 40.

[0107] Please see Figure 8 The pixel driving circuit 100 further includes a fourth switching unit T3.

[0108] The fourth switching unit T3 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the on / off state of the first and second terminals. The first terminal of the fourth switching unit T3 is electrically connected to the second terminal of the second storage capacitor C2. The second terminal of the fourth switching unit T3 is electrically connected to the second voltage line 20.

[0109] The fourth switching unit T3 is in the conducting state in the first stage t1, so that the second terminal of the second storage capacitor C2 is loaded with a preset voltage V1. For example, the second terminal of the second storage capacitor C2 is grounded and the first terminal of the first storage capacitor C1 is at a high potential, thereby charging the first storage capacitor C1 and the second storage capacitor C2, thereby realizing that the potential of the second gate G2 of the second driving transistor T1 is Vth+Vdd.

[0110] The fourth switching unit T3 is in the off state in the second stage t2, so that the second storage capacitor C2 can be electrically connected to the data line 40, so that the data voltage is loaded to the second gate G2 of the second driving transistor T1 through the second storage capacitor C2, thereby realizing that the potential of the second gate G2 of the second driving transistor T1 is Vth+Vdd+Vdata.

[0111] The fourth switching unit T3 is in the conducting state in the third stage t3, so that the second terminal of the second storage capacitor C2 is loaded with a preset voltage V1. For example, the second terminal of the second storage capacitor C2 is grounded, so that the second storage capacitor C2 can discharge to the light-emitting unit 30 through the first driving transistor TA2 and the second driving transistor T1.

[0112] Please see Figure 5 and Figure 9 The pixel driving circuit 100 further includes a fifth switching unit TA1 and a sixth switching unit TA3.

[0113] The fifth switching unit TA1 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the conduction or disconnection of the first and second terminals.

[0114] The first terminal of the fifth switching unit TA1 is electrically connected to the first voltage line 10.

[0115] The second terminal of the fifth switching unit TA1 is electrically connected to the first terminal of the first storage capacitor C1 and the third terminal S2 of the second driving transistor T1.

[0116] The fifth switching unit TA1 is in the conducting state in both the first stage t1 and the second stage t2, so that the first terminal S1 of the first driving transistor TA2 and the first terminal of the first storage capacitor C1 are loaded with the power supply voltage Vdd.

[0117] The fifth switching unit TA1 is in the off state during the third stage t3, so that the first storage capacitor C1 and the second storage capacitor C2 can discharge to the light-emitting unit 30 without being affected by the power supply voltage.

[0118] The sixth switching unit TA3 includes a control terminal, a first terminal, and a second terminal. The control terminal controls the conduction or disconnection of the first and second terminals.

[0119] The first terminal of the sixth switching unit TA3 is electrically connected to the first gate G1 and the second gate G2, and the second terminal of the sixth switching unit TA3 is electrically connected to the first terminal of the second storage capacitor C2 and the second terminal D1 of the first driving transistor TA2.

[0120] The sixth switching unit TA3 is in the conducting state in both the first stage t1 and the second stage t2, so as to charge the second storage capacitor C2 and change the potential of the second gate G2 of the second driving transistor T1, that is, to charge the second gate G2 of the second driving transistor T1.

[0121] The sixth switching unit TA3 is in the off state in the third stage t3, so that the second storage capacitor C2 is discharged through the first driving transistor TA2 and the second driving transistor T1, and the first storage capacitor C1 is discharged through the second driving transistor T1.

[0122] The first switch unit TA4 and the second switch unit TB1 are in the off state in the third stage t3, and the third switch unit T2 and the fourth switch unit T3 are in the on state in the third stage t3.

[0123] Optionally, the first driving transistor TA2 and the second driving transistor T1 are P-type transistors. The first terminal S1 is the source, the second terminal D1 is the drain, the third terminal S2 is the source, and the fourth terminal D2 is the drain. Of course, in other embodiments, the first driving transistor TA2 and the second driving transistor T1 can be N-type transistors.

[0124] The first switching unit TA4, the second switching unit TB1, the third switching unit T2, the fourth switching unit T3, the fifth switching unit TA1, and the sixth switching unit TA3 are N-type transistors or P-type transistors.

[0125] The pixel driving circuit 100 also includes a first scan line, a second scan line, a third scan line, and a control line.

[0126] The control terminals of the first switching unit TA4, the fifth switching unit TA1, and the sixth switching unit TA3 are all electrically connected to the first scan line. By setting multiple switching units electrically connected to the same scan line, the number of scan lines can be reduced, simplifying the pixel driving circuit 100.

[0127] The first scan line provides a first scan voltage SCANA, which is applied to the control terminals of the first switching unit TA4, the fifth switching unit TA1, and the sixth switching unit TA3 to control the connection or disconnection between the first and second terminals of the first switching unit TA4. The first switching unit TA4 is either an N-type or a P-type transistor. When the first switching unit TA4 is a P-type transistor and the first scan voltage SCANA is high, the first and second terminals of the first switching unit TA4 are disconnected, and the first switching unit TA4 is in an off state. When the first scan voltage SCANA is low, the first and second terminals of the first switching unit TA4 are connected, and the first switching unit TA4 is in a connected state. The implementation of the first switching unit TA4 being an N-type transistor can be referenced to the implementation of the second switching unit TB1 being a P-type transistor, and will not be repeated here.

[0128] Please see Figure 10 , Figure 10 for Figure 5 The signal timing diagram of the pixel driving circuit 100 is shown. Taking N-type transistors as an example, the operation of the pixel driving circuit 100 at different stages within an image frame is illustrated. The different stages of the pixel driving circuit 100 within an image frame include the first stage t1, the second stage t2, and the third stage t3.

[0129] The first scanning voltage SCANA is low, low, and high in the first stage t1, the second stage t2, and the third stage t3, respectively. The first switching unit TA4 is on, on, and off in the first stage t1, the second stage t2, and the third stage t3, respectively. The states of the fifth switching unit TA1 and the sixth switching unit TA3 are the same as those of the second switching unit TB1, and will not be described again here.

[0130] The control terminal of the second switching unit TB1 is electrically connected to the second scan line. The second scan line provides a second scan voltage SCANB, which is applied to the control terminal of the second switching unit TB1 to control the connection or disconnection between the first and second terminals of the second switching unit TB1. The second switching unit TB1 is either an N-type transistor or a P-type transistor. Taking a P-type transistor as an example: When the second scan voltage SCANB is high, the first and second terminals of the second switching unit TB1 are disconnected, and the second switching unit TB1 is in an off state; when the second scan voltage SCANB is low, the first and second terminals of the second switching unit TB1 are connected, and the second switching unit TB1 is in a connected state. The levels of the second scan voltage SCANB in ​​the first stage t1, the second stage t2, and the third stage t3 are, respectively, high, low, and high. The states of the second switching unit TB1 in the first stage t1, the second stage t2, and the third stage t3 are, respectively, off, connected, and off. The implementation of the second switching unit TB1 as an N-type transistor can refer to the implementation of the second switching unit TB1 as a P-type transistor, and will not be repeated here.

[0131] The control terminal of the fourth switching unit T3 is electrically connected to the third scan line. The third scan line provides a third scan voltage SCANC, which is applied to the control terminal of the fourth switching unit T3 to control the conduction or disconnection between the first and second terminals of the fourth switching unit T3. The fourth switching unit T3 is either an N-type transistor or a P-type transistor. Taking a P-type transistor as an example: When the third scan voltage SCANC is high, the first and second terminals of the fourth switching unit T3 are disconnected, and the fourth switching unit T3 is in an off state; when the third scan voltage SCANC is low, the first and second terminals of the fourth switching unit T3 are connected, and the fourth switching unit T3 is in a conducting state. The levels of the third scan voltage SCANC in the first stage t1, the second stage t2, and the third stage t3 are, respectively, low, high, and low. The states of the fourth switching unit T3 in the first stage t1, the second stage t2, and the third stage t3 are, respectively, on, off, and on. The implementation of the fourth switching unit T3 as an N-type transistor can refer to the implementation of the fourth switching unit T3 as a P-type transistor, and will not be repeated here.

[0132] The control terminal of the third switching unit T2 is electrically connected to the control line. The control line provides a control voltage Emit, which is applied to the control terminal of the third switching unit T2 to control the connection or disconnection between the first and second terminals of the third switching unit T2. The third switching unit T2 is either an N-type transistor or a P-type transistor. Taking a P-type transistor as an example: When the control voltage Emit is high, the first and second terminals of the third switching unit T2 are disconnected, and the third switching unit T2 is in an off state; when the control voltage Emit is low, the first and second terminals of the third switching unit T2 are connected, and the third switching unit T2 is in a conducting state. The control voltage Emit levels in the first stage t1, the second stage t2, and the third stage t3 are high, high, and low, respectively. The state of the third switching unit T2 in the first stage t1, the second stage t2, and the third stage t3 is disconnected, disconnected, and connected, respectively. The implementation of the third switching unit T2 as an N-type transistor can refer to the implementation of the third switching unit T2 as a P-type transistor, and will not be repeated here.

[0133] Furthermore, as can be seen from the timing diagram, the timing of the first scan line is completely opposite to that of the control line. Therefore, the control terminal of the third switching unit T2 can also be electrically connected to the first scan line. Also, the type of the third switching unit T2 is opposite to that of the first switching unit TA4, the fifth switching unit TA1, and the sixth switching unit TA3. For example, the first switching unit TA4, the fifth switching unit TA1, and the sixth switching unit TA3 are P-type transistors, while the third switching unit T2 is an N-type transistor.

[0134] As can be seen from the timing diagram, the timing of the second scan line is completely opposite to that of the third scan line. Therefore, the control terminal of the second switching unit TB1 and the fourth switching unit T3 can be electrically connected to the same scan line. Furthermore, the type of the second switching unit TB1 is opposite to that of the fourth switching unit T3. For example, the second switching unit TB1 is a P-type transistor, and the fourth switching unit T3 is an N-type transistor.

[0135] This application does not specifically limit the type of switching unit. Optionally, the switching unit may include, but is not limited to, thin-film transistors, field-effect transistors, etc.

[0136] The following explanation will be based on the example where the first driving transistor, the second driving transistor, the first switching unit, the first switching unit, the first switching unit, the first switching unit, the first switching unit, and the first switching unit are all P-type transistors.

[0137] In the first stage: the first scan voltage SCANA and the third scan voltage SCANC are low, while the second scan voltage SCANB and the control voltage Emit are high. The first driving transistor TA2 operates in the amplification region, and the second driving transistor T1 is off. The fifth switching unit TA1, the sixth switching unit TA3, the fourth switching unit T3, and the first switching unit TA4 are turned on, while the third switching unit T2 and the second switching unit TB1 are turned off. The power supply voltage Vdd charges the voltage at point G1 (G2) through the fifth switching unit TA1, the first driving transistor TA2, and the sixth switching unit TA3 until Vsg = Vth. At this point, the voltage Vg is Vdd + Vth, and the first driving transistor TA2 is off. The first storage capacitor C1 provides voltage regulation, so the voltage at point G1 (G2) is Vdd + Vth. Simultaneously, the first switching unit TA4 is turned on, thus neutralizing the charge at both ends of the light-emitting unit 30, weakening the built-in electric field, and improving the OLED lifespan.

[0138] In the second stage: the second scan voltage SCANB and the first scan voltage SCANA are low, while the third scan voltage SCANC and the control voltage Emit are high. The first driving transistor TA2 operates in the amplification region, and the second driving transistor T1 operates in the cutoff region. The fifth switching unit TA1, the sixth switching unit TA3, the second switching unit TB1, and the first switching unit TA4 are turned on, while the third switching unit T2 and the fourth switching unit T3 are turned off. The first storage capacitor C1 and the second storage capacitor C2 are regulated, and the voltage at point G1 (point G2) is charged to Vdd + Vth + Vdata.

[0139] In the third stage: the control voltage EMI T and the third scanning voltage SCANC are at low level, the first scanning voltage SCANA and the second scanning voltage SCANB are at high level, the second driving transistor T1 and the first driving transistor TA2 are working in the amplification region, the fifth switching unit TA1, the sixth switching unit TA3, the fourth switching unit T3 and the first switching unit TA4 are turned on, the third switching unit T2 and the second switching unit TB1 are turned off, the first storage capacitor C1 and the second storage capacitor C2 discharge to the light-emitting unit 30 through the second driving transistor T1 and the third switching unit T2, so that the light-emitting unit 30 emits light.

[0140] The display device provided in this application includes the pixel driving circuit 100 described in any of the above embodiments.

[0141] The display device can be any device that displays either moving (e.g., video) or stationary (e.g., still image) text or images. More specifically, the display device can be one of a variety of electronic devices, including but not limited to mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, etc. The embodiments of this disclosure do not impose any particular limitation on the specific form of the above-described display device.

[0142] It should be understood that in the pixel driving circuit 100 provided in the embodiments of this disclosure, nodes do not necessarily represent actual components. In some examples, these nodes represent the junctions of related couplings (i.e. electrical connections) in the equivalent circuit diagram of the pixel driving circuit 100. In other words, these nodes are nodes equivalent to the junctions of related electrical connections in the circuit diagram.

[0143] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application, and such improvements and refinements are also considered to be within the protection scope of this application.

Claims

1. A pixel driving circuit, characterized by comprising: The working stage of the pixel driving circuit comprises a first stage, and the pixel driving circuit comprises: a first voltage line for providing a power voltage Vdd; a second voltage line for providing a preset voltage, the preset voltage being less than the power voltage; a first driving transistor comprising a first gate, a first electrode, and a second electrode, the first electrode being electrically connected to the first voltage line in the first stage; a first storage capacitor having a first end electrically connected to the first voltage line in the first stage, and a second end electrically connected to the first gate and the second electrode in the first stage; and a second storage capacitor having a first end electrically connected to the second electrode and the second end of the first storage capacitor in the first stage, and a second end electrically connected to the second voltage line in the first stage; the first storage capacitor and the second storage capacitor are both in a charging state in the first stage, the storage voltage in the first storage capacitor is Vth, and the storage voltage in the second storage capacitor is Vth+Vdd.

2. The pixel driving circuit according to claim 1, wherein The working stage of the pixel driving circuit further comprises a second stage, and the pixel driving circuit further comprises: a data line for providing a data voltage Vdata; the second end of the second storage capacitor is disconnected from the second voltage line and electrically connected to the data line in the second stage, and the second storage capacitor is in a charging state in the second stage, the storage voltage in the second storage capacitor being Vth+Vdd+Vdata.

3. The pixel driving circuit of claim 2, wherein, The working stage of the pixel driving circuit further comprises a third stage, and the pixel driving circuit further comprises: a second driving transistor in an off state in the first stage and the second stage, the second driving transistor comprising a second gate, a third electrode, and a fourth electrode, the second gate being electrically connected to the first gate and the second end of the first storage capacitor, and the third electrode being electrically connected to the first end of the first storage capacitor; the second end of the second storage capacitor is electrically connected to the second voltage line and disconnected from the data line in the third stage; the first end of the second storage capacitor is disconnected from the first gate in the third stage; a light emitting unit having a first end electrically connected to the fourth electrode in the third stage; the first storage capacitor and the second storage capacitor discharge the light emitting unit through the second driving transistor.

4. The pixel driving circuit of claim 3, wherein, The pixel driving circuit further comprises a first switch unit having a first end electrically connected to the first end of the light emitting unit, a second end electrically connected to the second end of the light emitting unit, and the first end and the second end being electrically connected in the first stage and / or the second stage.

5. The pixel driving circuit of claim 3, wherein, The pixel driving circuit further comprises a first switch unit and a reset voltage line, the reset voltage line is used for providing a reset voltage, the reset voltage is less than the power voltage, a first end of the first switch unit is electrically connected to a first end of the light emitting unit, a second end of the first switch unit is electrically connected to the reset voltage line, and the first end of the first switch unit and the second end of the first switch unit are electrically conducted in the first stage and / or the second stage.

6. The pixel driving circuit of claim 3, wherein, The pixel driving circuit further comprises a second switch unit and a third switch unit, a first end of the second switch unit is electrically connected to the data line, the second switch unit is electrically connected to a second end of the second storage capacitor, and the second switch unit is in a disconnected state in the first stage. A first end of the third switch unit is electrically connected to a fourth pole of the second driving transistor, a second end of the third switch unit is electrically connected to the first end of the light emitting unit, and the third switch unit is in a disconnected state in the first stage.

7. The pixel driving circuit of claim 6, wherein, The pixel driving circuit further comprises a fourth switch unit, a first end of the fourth switch unit is electrically connected to the second end of the second storage capacitor, a second end of the fourth switch unit is electrically connected to the second voltage line, the fourth switch unit is in a conducted state in the first stage, the fourth switch unit is in a disconnected state in the second stage, the second switch unit is in a conducted state in the second stage, and the third switch unit is in a disconnected state in the second stage.

8. The pixel driving circuit of claim 7, wherein, The pixel driving circuit further comprises a fifth switch unit and a sixth switch unit, a first end of the fifth switch unit is electrically connected to the first voltage line, a second end of the fifth switch unit is electrically connected to a first end of the first storage capacitor and a third pole of the second driving transistor, the fifth switch unit is in a conducted state in the first stage and the second stage, and the fifth switch unit is in a disconnected state in the third stage. A first end of the sixth switch unit is electrically connected to the first gate and the second gate, a second end of the sixth switch unit is electrically connected to a first end of the second storage capacitor and a second pole of the first driving transistor, the sixth switch unit is in a conducted state in the first stage and the second stage, and the sixth switch unit is in a disconnected state in the third stage. The second switch unit is in a disconnected state in the third stage, and the third switch unit and the fourth switch unit are in a conducted state in the third stage.

9. The pixel driving circuit of claim 8, wherein, The first driving transistor and the second driving transistor are N-type transistors. The pixel driving circuit further comprises a first scan line, a second scan line, a third scan line and a control line, the control end of the fifth switch unit and the control end of the sixth switch unit are electrically connected with the first scan line, the control end of the second switch unit is electrically connected with the second scan line, the control end of the fourth switch unit is electrically connected with the third scan line, and the control end of the third switch unit is electrically connected with the control line; the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit are N-type transistors or P-type transistors.

10. A display device, characterized by comprising: The pixel driving circuit comprises any one of claims 1 to 9.

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