Method of operating a memory

Abstract

A method of operating a memory includes: applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector to an on state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein the selector has a first voltage threshold before applying the second voltage pulse, wherein the selector has a second voltage threshold less than the first voltage threshold after applying the second voltage pulse; and after applying the second voltage pulse, applying a third voltage pulse to the memory cell, wherein the third voltage pulse switches the selector to the on state; wherein the selector remains in an off state continuously between the first voltage pulse and the third voltage pulse.

Description

Technical Field

[0001] This disclosure relates to a method for manipulating memory. Background Technology

[0002] Semiconductor memory is used in integrated circuits for electronic applications, including, for example, radios, televisions, mobile phones, and personal computing devices. One type of semiconductor memory is phase-change random access memory (PCRAM), which involves storing values ​​in a phase-change material, such as a chalcogenide material. The phase-change material can switch between an amorphous phase (where the phase-change material has high resistivity) and a crystalline phase (where the phase-change material has low resistivity) to indicate bit codes. A PCRAM cell typically includes a phase-change material (PCM) element between two electrodes. Summary of the Invention

[0003] Some embodiments of this disclosure include a method of operating memory comprising applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, wherein the first voltage pulse switches the selector to an ON state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein the selector has a first voltage threshold before applying the second voltage pulse, wherein the selector has a second voltage threshold less than the first voltage threshold after applying the second voltage pulse; and after applying the second voltage pulse, applying a third voltage pulse to the memory cell, wherein the third voltage pulse switches the selector to an ON state; wherein the selector remains in an OFF state between the first voltage pulse and the third voltage pulse.

[0004] Some embodiments of this disclosure include a method of operating memory comprising performing a subcritical stress process on a memory array, wherein each memory cell of the memory array includes a chalcogenide selector, wherein performing the subcritical stress process includes applying a first voltage between a first word line and a first bit line of the memory array, wherein the first memory cell of the memory array is connected to the first word line and the first bit line, wherein at the start of the subcritical stress process, the chalcogenide selector of the first memory cell has a first critical voltage, wherein the amplitude of the first voltage is less than the first critical voltage, and wherein at the end of the subcritical stress process, the chalcogenide selector of the first memory cell has a second critical voltage less than the first critical voltage.

[0005] Some embodiments of this disclosure include a method for operating memory comprising: determining a target threshold voltage of a chalcogenide selector; applying a first voltage pulse to the chalcogenide selector, wherein the amplitude of the first voltage pulse is less than the amplitude of the target threshold voltage; after applying the first voltage pulse, applying a test voltage pulse to the chalcogenide selector, wherein the amplitude of the test voltage pulse is at least the amplitude of the target threshold voltage; determining whether the test voltage pulse successfully switched the chalcogenide selector to an on state; and based on determining that the chalcogenide selector was switched to an on state, applying a second voltage pulse to the chalcogenide selector, wherein the duration of the second voltage pulse is longer than the duration of the first voltage pulse and / or the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. Attached Figure Description

[0006] Some embodiments of this disclosure are best understood from the following description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not necessarily drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1 The illustration shows a perspective view of a memory array according to some embodiments;

[0008] Figure 2A and Figure 2B The figure shows a cross-sectional view of a memory cell according to some embodiments;

[0009] Figure 3 The figure shows a diagram illustrating the current-voltage characteristics of a selector according to some embodiments;

[0010] Figure 4 The diagram illustrates the voltage and current across the selector according to some embodiments;

[0011] Figure 5A The figure illustrates the threshold voltage versus delay time of a selector according to some embodiments;

[0012] Figure 5B The diagram illustrates the voltage and current across the selector according to some embodiments;

[0013] Figure 6 The figure shows a diagram of the voltage across a selector including subcritical stress according to some embodiments;

[0014] Figure 7 The figure illustrates the threshold voltage versus delay time of a selector according to some embodiments;

[0015] Figure 8A , Figure 8B , Figure 8CThe figure shows a diagram of the voltage across a selector including subcritical stress according to some embodiments;

[0016] Figure 9A The diagram illustrates the voltage across a selector with successive subcritical stresses according to some embodiments.

[0017] Figure 9B The figure illustrates the threshold voltage versus delay time of a selector according to some embodiments;

[0018] Figure 10A , Figure 10B The diagram illustrates the voltage across a selector including a subcritical stress, which has multiple subcritical voltage pulses, according to some embodiments.

[0019] Figure 11 The illustration shows a flowchart of an adaptive subcritical stress process for memory cells according to some embodiments.

[0020] [Symbol Explanation]

[0021] 100: Phase-Change Random Access Memory (PCRAM) Array

[0022] 102: Word Line

[0023] 104: Bitline

[0024] 106: Insulation layer

[0025] 108: Insulating materials

[0026] 110: PCRAM cell

[0027] 112: Top electrode

[0028] 114: Bottom Electrode

[0029] 116: Bidirectional Critical Switching (OTS) Layer, OTS Selector

[0030] 117: Intermediate electrode

[0031] 118: Phase Change Material (PCM) Layer

[0032] 200A: Pulse

[0033] 200B: Pulse

[0034] 300: Subcritical stress

[0035] 300A: Subcritical stress

[0036] 300B: Subcritical stress

[0037] 300C: Subcritical stress

[0038] 300D: Subcritical stress

[0039] 300E: Subcritical stress

[0040] 300F: Subcritical stress

[0041] 310: Subcritical voltage pulse

[0042] 401: Data Point

[0043] 402: Data Point

[0044] 403: Data Point

[0045] 410: Data Points

[0046] 501: Data Point

[0047] 502: Data Point

[0048] 511: Data Points

[0049] 512: Data Points

[0050] 600: Process

[0051] 602: Operation

[0052] 604: Operation

[0053] 606: Operation

[0054] 608: Operation

[0055] 610: Operation

[0056] 612: Operation Detailed Implementation

[0057] The following disclosure provides numerous different embodiments, or examples, of various features for implementing some embodiments of this disclosure. Specific examples of elements and arrangements are described below to simplify some embodiments of this disclosure. Of course, these examples are merely illustrative and are not intended to be limiting. For example, the form of a first feature above or over a second feature in the following description may include embodiments in which the first feature and the second feature are in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Furthermore, some embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, specify a relationship between the various embodiments and / or configurations discussed.

[0058] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0059] According to some embodiments, a subcritical voltage stress is applied to a critical memory selector to counteract time-delay critical voltage drift. For example, the selector's critical voltage may increase during the time delay between switching pulses, and applying a subcritical voltage stress as described herein can reduce the increased critical voltage back to a no-delay value. The subcritical stress comprises a voltage less than the selector's critical voltage, which reduces stress on the selector, lowers power consumption, and reduces the chance of the selector turning on. The subcritical voltage stress may also be a voltage with the opposite polarity to the selector's switching voltage. By using a subcritical voltage stress as described herein to reduce the critical voltage, device uniformity, repeatability, or efficiency can be improved.

[0060] Figure 1 The illustration shows a perspective view of a phase-change random access memory (PCRAM) array 100 according to some embodiments. The PCRAM array 100 includes word lines 102, bit lines 104, and PCRAM cells 110 connected in a "crossover" configuration. Other configurations of the word lines 102, bit lines 104, or PCRAM cells 110 are also possible. In some embodiments, multiple PCRAM arrays 100 may be stacked to form a three-dimensional (3D) memory array (not shown). The PCRAM array 100 may be formed on a substrate (not shown), which may be a semiconductor substrate or other type of substrate. In some embodiments, the substrate may include active and / or passive devices (e.g., transistors, diodes, capacitors, resistors, etc.). These devices may be formed according to applicable manufacturing processes. In some embodiments, no devices are formed in the substrate. In some embodiments, the PCRAM array 100 is formed in a metallization layer of an interconnect structure (not shown) above the substrate. The PCRAM array may be electrically connected to one or more metallization layers. For example, in some embodiments, word lines 102 and / or bit lines 104 may be conductors of a metallization layer.

[0061] exist Figure 1In the embodiment shown, each PCRAM cell 110 includes a top electrode 112, a bottom electrode 114, a bidirectional threshold switching (OTS) layer 116, and a phase change material (PCM) layer 118, as described below. Figures 2A to 2B A more detailed description follows. Bit lines 104 are electrically connected to the bottom electrodes 114 of each column of PCRAM cells 110 in the PCRAM array 100. Each column of the PCRAM array 100 has an associated bit line 104, and the PCRAM cells 110 in a column are connected to the bit line 104 of that column. Word lines 102 are electrically connected to the top electrodes 112 of each row of PCRAM cells 110 in the PCRAM array 100. Each row of the PCRAM array 100 has an associated word line 102, and the PCRAM cells 110 in a row are connected to the word line 102 of that row. In this way, each PCRAM cell 110 of the PCRAM array 100 can be selected via an appropriate combination of word lines 102 and bit lines 104. For example, a particular PCRAM cell 110 can be selected by accessing a single word line 102 connected to the PCRAM cell 110 and also by accessing a single bit line 104 connected to the PCRAM cell 110 (e.g., for read or write operations).

[0062] In some embodiments, the resistance of the PCM layer 118 of each PCRAM cell 110 is programmable and can be changed between a high-resistance state and a low-resistance state, thus corresponding to two states of binary code. In some embodiments, the resistance state of the PCM layer 118 of the PCRAM cell 110 can be programmed (e.g., "written") by applying an appropriate voltage pulse to the PCRAM cell 110, which generates a corresponding current pulse on the PCM layer 118. In some embodiments, the amplitude of the programmed current pulse is in the range of about 50 μA to about 800 μA, although other currents are also possible. In some cases, the amplitude of the programmed voltage pulse can be in the range of about 1V to about 2V, although other voltages are also possible. In some embodiments, the state of the PCRAM cell 110 can be read by applying a relatively small current to the PCRAM cell 110, which allows the resistance of the PCRAM cell 110 to be measured without interfering with the resistance state of the PCM layer 118. Other types of memory or memory architectures may use different read schemes or amplitudes than in this example.

[0063] The OTS layer 116 of each PCRAM cell 110 is used as a selector to allow individual access (e.g., write or read) to each PCRAM cell 110. In this way, the OTS layer 116 of the PCRAM cell 110 may also be referred to herein as "OTS selector 116". The OTS selector 116 has a threshold voltage (V). TH The characteristics of ). Below V TH Under the applied voltage (e.g., at the subcritical voltage), the OTS selector 116 is in a high-resistance state, limiting the current through the PCRAM cell 110. When the voltage is greater than V... TH Under the applied voltage, the OTS selector 116 is in a low-resistance state, creating a current path through the PCRAM cell 110 for write or read operations. In this way, only when the voltage across the OTS selector 116 is greater than V... TH A write operation can only be performed on PCRAM cell 110 when a certain threshold voltage is reached. In some cases, PCRAM cell 110 can be read using a sub-threshold voltage. In some embodiments, the threshold voltage V... TH The amplitude ranges from approximately 1V to approximately 2V, although other voltages are also possible. In some cases, the critical voltage V... TH Tuning can be achieved, for example, by adjusting the material or thickness of each layer.

[0064] Reference Figure 3 The diagram illustrates an example of the current on the OTS selector 116 as a function of the voltage applied to the selector. Figure 3 This is a representative diagram for illustrative purposes, and the OTS selector 116 may have different current-voltage characteristics than those shown. Figure 3 As shown, the OTS selector 116 is in a low conductivity state (e.g., "off") unless a voltage higher than the on-state threshold V is applied. TH When the applied voltage is removed or reduced below the cutoff threshold voltage (sometimes also called the "holding voltage"), the OTS selector 116 enters a high conductivity state (e.g., the "on" state). When the applied voltage is removed or reduced below the cutoff threshold voltage (sometimes also called the "holding voltage"), the OTS selector 116 returns to a low conductivity state. The cutoff threshold voltage can be the same as the on threshold voltage V. TH Same or different. The threshold voltage V of the OTS selector 116 of PCRAM cell 110. TH This can also be referred to as the critical voltage V of PCRAM cell 110 in this article. TH .

[0065] Reference Figure 2A and Figure 2B The figure shows a cross-sectional view of a PCRAM cell 110 according to some embodiments. Figure 2A and Figure 2BPCRAM cell 110 in the middle can be used for, for example Figure 1 In the PCRAM array shown, such as the PCRAM array, each PCRAM cell 110 includes a top electrode 112, a bottom electrode 114, an OTS layer 116, a PCM layer 118, and an intermediate electrode 117. One or more insulating materials 108 may surround and protect the PCRAM cell 110, and may include one or more inter-metal dielectric (IMD) layers and / or one or more oxide, nitride, etc. Figure 2A The illustration shows a PCRAM cell 110 with a "symmetrical" or "cylinder" shape, and Figure 2B The illustration shows a PCRAM cell 110 with an “asymmetrical” or “mushroom” shape and a narrow bottom electrode 114. Figure 2A and Figure 2B The PCRAM cell 110 shown is a non-limiting example, and the PCRAM cell 110 may have other layers, widths, configurations, sizes, shapes, or configurations in other embodiments.

[0066] In some embodiments, bit lines 104 may be formed in an insulating layer 106, which may be an intermetallic dielectric (IMD) layer, etc. Bit lines 104 may be formed of one or more conductive materials, such as tungsten, titanium, tantalum, ruthenium, cobalt, nickel, or combinations thereof, and may be deposited by suitable processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, etc. Bit lines 104 may be formed using suitable processes, such as damascene, dual damascene, or other processes.

[0067] In some embodiments, the bottom electrode 114, PCM layer 118, intermediate electrode 117, OTS layer 116, and top electrode 112 are deposited via blanket deposition and then patterned together to form individual PCRAM cells 110. An insulating material 108 may subsequently be deposited around the PCRAM cells 110. For example, this process can form structures such as… Figure 2A The cylindrical PCRAM cell 110 is shown. In other embodiments, one or more layers of the PCRAM cell 110 may be formed or patterned separately. This process can form PCRAM cells 110 with layers of different widths, such as... Figure 2BThe mushroom-shaped PCRAM cell 110 shown includes a bottom electrode 114 formed therein, followed by patterning of other layers of the PCRAM cell 110 in a separate operation. For example, the bottom electrode 114 may be formed first by etching trenches in an insulating material 108 and filling the trenches with a conductive material. Other techniques are also possible.

[0068] A bottom electrode 114 is formed on bit line 104. The bottom electrode 114 may be formed of one or more conductive materials similar to those described for bit line 104, and may be formed using similar processes. In some embodiments, the bottom electrode 114 may include a barrier layer (not shown). A PCM layer 118 is formed on the bottom electrode 114. In some embodiments, the PCM layer 118 is formed of a chalcogenide material. Chalcogenide materials include at least chalcogenide anions (e.g., selenium (Se), tellurium (Te), etc.) and positively charged elements (e.g., germanium (Ge), silicon (Si), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), zinc (Zn), nitrogen (N), boron (B), carbon (C), etc.). Acceptable chalcogenide materials include, but are not limited to, GeSbTe (GST) or GeSbTeX, where X is a material such as Ag, Sn, In, Si, N, etc. Other materials are also possible. The PCM layer 118 can be formed using appropriate deposition processes, such as PVD, CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, etc.

[0069] In some embodiments, an intermediate electrode 117 is formed on the PCM layer 118. The intermediate electrode 117 can be formed using materials or techniques similar to those described for the bottom electrode 114. An OTS layer 116 is formed on the intermediate electrode 117. The OTS layer 116 can be formed from one or more of the materials described above for the PCM layer 118. For example, the OTS layer 116 can be formed from a chalcogenide material, which can be a material similar to or different from that of the PCM layer 118. The OTS layer 116 can be formed using suitable deposition processes such as PVD, CVD, PECVD, ALD, etc.

[0070] A top electrode 112 is formed on the OTS layer 116. The top electrode 112 can be formed using materials or techniques similar to those described for the bottom electrode 114. Word lines 102 can then be formed on the top electrode 112. In some embodiments, word lines 102 can be formed using materials or techniques similar to those used for bit lines 104. Other materials or techniques are also possible.

[0071] Reference Figure 4 The diagram illustrates representative voltage and current of the OTS selector 116 (e.g., OTS layer 116) of a PCRAM cell 110 according to some embodiments. Figure 4 The diagram illustrates the voltage applied to the OTS selector 116 and the corresponding current flowing through the OTS selector 116 as a function of time. Figure 4 This is a representative diagram for illustrative purposes, and the OTS selector 116 may have different current-voltage characteristics than those shown. Figure 4 The diagram illustrates a first voltage pulse 200A, followed by a second voltage pulse 200B. Both pulses 200A and 200B can be voltage pulses used to program the PCRAM cell 110; therefore, both pulses 200A and 200B include a voltage greater than the threshold voltage V of the OTS selector 116 of the PCRAM cell 110. TH The voltage. For example... Figure 4 As shown, after a delay time t from the completion of the first pulse 200A D A second pulse 200B is then applied. The delay time t between the two subsequent voltage pulses applied to the PCRAM cell 110 depends on the specific application or operation of the PCRAM array 100. D It can cover a wide range, such as t as short as a fraction of a second. D (e.g., microseconds or less) or thousands of seconds D (For example, several weeks or longer).

[0072] However, in some cases, the threshold voltage V of the OTS selector 116... TH With time delay t D Increases and increases. In Figure 5A and Figure 5B The text explains the "time delay critical voltage drift," and its diagrams are shown below. TH For t D Representative diagrams and representative diagrams of voltage and current across OTS selector 116. Figures 5A to 5B This is a representative illustration for illustrative purposes, and the OTS selector 116 may have different characteristics than those shown. Figure 5A The threshold voltage V of the OTS selector 116 is shown in the figure. TH With the previous voltage pulse (e.g.) Figure 5A The time delay t since the pulse 200A) D Exemplary relationships between them. For example... Figure 5A As shown, the critical voltage V TH With time delay t D Increases logarithmically. Critical voltage V TH The increase over time can be attributed to factors such as atomic relaxation of materials like the OTS layer 116.

[0073] Figure 5B A diagram illustrating the voltage and current of the OTS selector 116 is shown, illustrating the voltage and current during time delay t.D The critical voltage then increases. Figure 5B The illustration is similar to Figure 4 The diagram shows that, except for the first pulse 200A which has a critical voltage V THA In addition, and at a time delay t D Subsequently, the second pulse 200B has an increased threshold voltage V. THB Critical voltage V THB Corresponding to Figure 5A The critical voltage V in TH In some cases, due to the time delay t D The resulting critical voltage V TH Increasing the pulse voltage may reduce efficiency or require applying a higher voltage, thus increasing the risk of leakage, damage, or interference with unselected PCRAM cells 110. In some cases, the critical voltage V of PCRAM cell 110... TH The voltage can be increased to a sufficiently large level that write and / or read operations performed on the PCRAM cell 110 fail. In some cases, a "dummy" voltage pulse similar to pulses 200A and 200B can be applied between the first pulse 200A and the second pulse 200B to reduce the increased threshold voltage (e.g., V). THB Reset to a lower voltage (e.g., V) THA And effectively delay the time t D Reset to zero. However, applying a dummy voltage pulse in this manner would unnecessarily stress the PCRAM cell 110, causing unwanted heating and consuming additional power.

[0074] Figure 6 The illustration is a representative diagram of the voltage applied to an OTS selector 116 across a PCRAM cell 110 according to some embodiments. The OTS selector 116 includes a subcritical stress 300 between two voltage pulses 200A and 200B. Applying the subcritical stress 300, as described herein, can reduce the effect of time delay critical voltage drift, as described in more detail below. Figure 6 The illustration is similar to Figure 5B The diagram shows the applied voltage, except that subcritical stress 300 is applied to OTS selector 116 during the time between the first pulse 200A and the second pulse 200B. In some embodiments, subcritical stress 300 includes application to OTS selector 116 for a duration t. S Voltage V during ("stress time") S (Stress voltage) pulse, where stress voltage V S The amplitude is less than the critical voltage V of the first pulse of 200A. THA In some embodiments, the stress voltage V of the subcritical stress 300 SIt can have a polarity opposite to that of pulses 200A and 200B. For example, pulses 200A and 200B can be positive voltages and stress voltage V. S It can be a negative voltage, such as Figure 6 As shown in the diagram. In this way, in some cases, the subcritical stress 300 can be considered as a "negative stress" or "reverse polarity stress". In other embodiments, pulses 200A and 200B are related to the stress voltage V. S They can have the same polarity. In some cases, it includes a V with a polarity opposite to that of pulses 200A and 200B. S The subcritical stress 300 can improve the critical voltage recovery effect of the subcritical stress 300, as described in more detail below.

[0075] In some embodiments, the subcritical stress 300 includes a stress time t ranging from approximately 1 millisecond to approximately 10 seconds. S A voltage pulse is applied to the PCRAM cell 110, although other stress durations are also possible. In some embodiments, the subcritical stress 300 may comprise a stress voltage V having an amplitude in the range of approximately 0.6V to approximately 1.2V. S Other stress voltages are also possible, and in other embodiments, the subcritical stress 300 may comprise multiple different stress voltages V. S In some embodiments, the stress voltage V S The amplitude can be based on or determined by the voltage threshold V of the OTS selector 116. TH (For example, V) THA or V THB The amplitude of the stress voltage VS is determined. For example, the amplitude of the stress voltage VS may be less than the voltage threshold V of the OTS selector 116 (e.g., V). THA or V THB The magnitude of V. In some embodiments, V S The amplitude can be V TH Between approximately 50% and approximately 80% of the amplitude. In some embodiments, V S The amplitude can be less than V TH The amplitude is between approximately 200mV and approximately 900mV. S and V TH Other relative magnitudes are possible, and for example, can be based on V. TH The amplitude is determined. In some embodiments, the use of a subcritical voltage pulse can reduce electrical stress on PCRAM cells 110, reduce power consumption, and prevent unwanted switching of other PCRAM cells 110. The subcritical stress 300 may include, for example, Figure 6The voltage waveform shown is generally square or rectangular, or the subcritical stress 300 may have other waveform shapes, such as triangular, trapezoidal, circular, stepped, or other shapes. In some embodiments, the subcritical stress 300 is delayed by a first time t after the first pulse 200A. DA The second pulse 200B is applied at the subcritical stress 300 with a second time delay t. DB Apply at the location. Time delay t DA and t DB Each can be approximately zero microseconds or longer.

[0076] In some cases, the application of subcritical stress 300, as described in this paper, can reduce the effect of time-delayed critical voltage drift. This measure... Figure 7 The diagram illustrates the delay time t. D Critical voltage V of the function TH The measurement data. Delay time t D Logarithmic scale 10 (t D / t0) represents, where t0 is the reference unit for the delay time. Figure 7 The data points shown are intended as illustrative examples, and such or other critical voltages may appear with such or other time delays in other embodiments. The square data points extending from data point 401 to data point 403 represent the OTS selector 116 at various time delays t. D V after the past TH Measured value. For example, data point 403 represents the value measured at a delay time t. D1 The critical voltage V obtained afterward was measured. TH1 At time delay t D1 During this period, the critical voltage has increased from approximately V. TH0 The baseline critical voltage is increased to V. TH1 The "increased critical voltage". In this way, Figure 7 The square data points indicate V TH With t D The increase is similar to the previous increase. Figure 5A The relationship shown.

[0077] Circular data point 410 represents the same delay time t as data point 403. D1 The critical voltage measurement was performed under these conditions, except that the measurement at data point 410 was performed after the first application of subcritical stress 300. The applied subcritical stress 300 is similar to that applied to... Figure 6 The described subcritical stress is 300. (Example) Figure 7 As shown, applying subcritical stress 300 has reduced the critical voltage from the increased critical voltage V. TH1Reduced to the "reduced critical voltage" V TH2 The magnitude of the decrease in critical voltage caused by the subcritical stress of 300 is... Figure 7 The middle is represented as V diff In some embodiments, during the time delay, the threshold voltage of the OTS selector 116 has been increased to the increased connection voltage (e.g., V). TH1 Afterwards, the increased critical voltage can be reduced to a lower critical voltage (e.g., V) by applying a subcritical stress of 300. TH2 In other words, the use of subcritical stress 300 as described herein can reduce the critical voltage of OTS selector 116 that increases due to time delay. In this way, applying subcritical stress 300 can at least partially restore the increased critical voltage to the normal (e.g., zero-second time delay) critical voltage, and thus reduce the effect of time-delayed critical voltage drift. Figure 7 The data points shown are examples, and the use of subcritical stress 300 to reduce the critical voltage, as described herein, can be used for other time delays or critical voltages besides those shown. The critical voltage recovery benefits of subcritical stress 300 as described herein are reproducible and repeatable, and can be implemented such that PCRAM cell 110 undergoes little or no permanent change to its operation or characteristics.

[0078] In some embodiments, the critical voltage V diff The reduction ranges from approximately 50 mV to approximately 500 mV. In some embodiments, V diff The magnitude of the reduction can be between approximately 2% and approximately 40% of the increased critical voltage magnitude. In some embodiments, the reduced critical voltage can be between approximately 60% and approximately 98% of the increased critical voltage magnitude. Other magnitudes or relative magnitudes are also possible. The achieved critical voltage reduction V diff The actual magnitude can depend on parameters of the subcritical stress 300, such as the first time delay t. DA Second time delay t DB Stress voltage V S Stress time t S Or other factors. For example, a second time delay t greater than approximately zero seconds. DB The allowable reduction in the voltage threshold increases due to the time-delayed critical voltage drift. As another example, a larger V... S or a larger t S This can lead to a larger V diff Besides these examples, the critical voltage decreases by V. diff It may be affected by other factors or conditions.

[0079] Still referencing Figure 7Data point 402 shows that the measured value of the increased critical voltage is approximately equal to V. TH2 It corresponds to the time delay t D2 In this way, from V TH1 To V TH2 The critical voltage decreases by V diff Roughly equivalent to delaying the actual time from t D1 Reduce to effective time delay t D2 Actual time delay t D1 With effective time delay t D2 The logarithmic difference between them Figure 7 The value shown in the image is the effective delay reduction t. diff For data point 410, the effective delay is reduced by t. diff This corresponds to a reduction of approximately five orders of magnitude (e.g., t). D2 Approximately 10 -5 ×t D1 In other embodiments, the effective time delay is reduced by t. diff It can range from about one order of magnitude to about 12 orders of magnitude or more, although other values ​​are possible.

[0080] The subcritical stress 300 can be controlled to have various properties. For example, specific properties of the subcritical stress 300 can be configured for a particular application or desired result. Figures 8A to 8C , Figure 9A and Figures 10A to 10B The diagram illustrates the voltage applied across an OTS selector 116 according to some embodiments, the OTS selector 116 including subcritical stresses of 300A to 300F. Figures 8A to 10B The voltage diagram shown is similar to Figure 6 The voltage diagrams shown are different from those of the subcritical stresses 300A to 300F. Subcritical stresses 300A to 300F are intended as non-limiting examples, and subcritical stress 300 may have different characteristics than those shown or described, while still remaining within the scope of some embodiments disclosed herein.

[0081] The stress voltage or stress time of the subcritical stress 300 can be controlled to provide an appropriate reduction in the critical voltage. For example, Figure 8A The figure illustrates a relatively small stress voltage V. SA and a relatively long stress time t SA The subcritical stress is 300A. In some cases, applying a smaller stress voltage over a longer stress period can reduce the electrical stress or heat generation of the PCRAM cell 110. Figure 8B The figure illustrates a relatively large stress voltage V. SB and relatively short stress time t SBThe subcritical stress is 300B. In some embodiments, a larger stress voltage or a longer stress time can achieve a greater reduction in the critical voltage V. diff In some embodiments, the stress voltage or stress time can be controlled to depend on a first time delay t. DA For example, in a longer first time delay t DA Subsequently, the subcritical stress 300 can be controlled to achieve a larger stress voltage or a longer stress time to achieve a greater reduction in the critical voltage V. diff In some embodiments, a similar threshold voltage reduction V diff This can be achieved by applying a relatively small stress voltage V. S and relatively long stress time t S The subcritical stress 300 (e.g., similar to subcritical stress 300A) or by applying a relatively large stress voltage V S and relatively short stress time t S The subcritical stress 300 (e.g., similar to subcritical stress 300B) is used to achieve this.

[0082] In some embodiments, the subcritical stress 300 includes a plurality of stress voltages, each of which may have a corresponding stress time. Figure 8C The diagram illustrates a series of subcritical stresses 300°C, including a first stress voltage V. SC1 Then came something different from V. SC1 The second stress voltage V SC2 First stress voltage V SC1 After stress is applied for a time t C1 Second stress voltage V SC2 After being applied differently than t C1 Stress time t C2 In other embodiments, the subcritical stress 300 may comprise more than two distinct stress voltages. These stress voltages can be arranged in any suitable order. For example, in some embodiments, the second stress voltage V... SC2 It can be in the first stress voltage V SC1 Previously applied. Multiple stress voltages within the subcritical stress 300 can be arranged in any suitable order. The various stress voltages may have the same stress time or may have different stress times. For example, in some embodiments, a first stress voltage V may be applied. SC1 Time t C2 And a second stress voltage V can be applied. SC2 Time t C1 Any appropriate stress time can be used for various stress voltages within the subcritical stress range of 300.

[0083] Figure 9AThe figure illustrates a subcritical stress 300D applied continuously between a first voltage pulse 200A and a second voltage pulse 200B, according to some embodiments. In other words, the stress time t of the subcritical stress 300D... S Equal to the delay time t between pulses 200A and 200B D .like Figure 9A As shown, in some embodiments, the subcritical stress 300D may have a stress voltage polarity opposite to that of the voltage pulses 200A and 200B. Figure 9A The subcritical stress 300D shown has a constant V S However, in other embodiments, the stress voltage V S It can vary during the application of continuous subcritical stress 300D. In some cases, applying continuous subcritical stress 300D can allow for a reduction in the effect of time-delay critical voltage drift, while allowing for little or no monitoring or measurement of the delay time t. D Additionally, the stress voltage V is used as the subcritical voltage. S This can reduce heat generation or power consumption.

[0084] Figure 9B The delay time t is shown as the time under conditions of both applied and unapplied successive subcritical stresses of 300D. D Critical voltage V of the function TH The measurement data. Delay time t D Logarithmic scale 10 (t D / t0) represents the time delay, where t0 is the reference unit for the delay time. The circular data points represent the critical voltage V of the OTS selector 116. TH The measured values, which are measured over various time delays t D After the past, with a time delay t D Data was obtained under conditions of continuous application of a subcritical stress of 300D. The square data points represent the critical voltage V of the OTS selector 116. TH The measured value, which is measured over various time delays t D It was obtained after the fact, but without any subcritical stress being applied. Figure 9B The illustration shows that the application of successive subcritical stresses 300D reduces the effect of time delay critical voltage drift. For example, the application of successive subcritical stresses 300D reduces the increasing critical voltage at data point 501 to the reduced critical voltage at data point 511, and the application of successive subcritical stresses 300D reduces the increasing critical voltage at data point 502 to the reduced critical voltage at data point 512. In some cases, the application of successive subcritical stresses 300D may result in an increased critical voltage for longer delay times t. D The reduction is even greater. Figure 9BThe measurement data shown are non-limiting examples for illustrative purposes.

[0085] In some embodiments, a single subcritical stress 300 may comprise two or more subcritical voltage pulses 310. This situation occurs in... Figure 10A As shown in the figure, the subcritical stress 300E is determined by the stress voltage V. S A plurality of subcritical voltage pulses 310 are formed. Each subcritical voltage pulse 310 with a subcritical stress 300E has a pulse stress time t. PS Furthermore, the subcritical voltage pulse 310 is separated by a pulse delay time t. PD .and Figure 10A Compared to the one shown, the subcritical stress 300E may have fewer or more subcritical voltage pulses 310. In some cases, using a subcritical stress 300E containing multiple subcritical voltage pulses 310 can avoid effects caused by thermal accumulation or electric field stress, specifically for high stress voltages V. S Various characteristics of the subcritical stress 300E can be controlled, such as the period of the subcritical voltage pulse 310 (e.g., t). PS +t PD The duty cycle of the subcritical voltage pulse 310 (e.g., t) PS :t PD ), stress voltage V S The number of subcritical voltage pulses 310 or other characteristics.

[0086] In other embodiments, a single subcritical stress 300 may comprise different stress voltages V S Different pulse stress times t PS Or different pulse delay times t PD Multiple subcritical voltage pulses. Figure 10B The illustration shows a non-limiting example in which a single subcritical stress 300F comprises multiple subcritical voltage pulses having various characteristics, such as pulse stress time, pulse delay time, stress voltage, waveform, etc. All variations and combinations of subcritical voltage pulses are considered to be within the scope of some embodiments disclosed herein.

[0087] The subcritical stress 300 described herein can be applied to a single PCRAM cell 110 or applied in parallel to multiple PCRAM cells 110. For example, the subcritical stress 300 can be applied simultaneously to PCRAM cells 110 sharing the same word line 102 or the same bit line 104. In some cases, when the subcritical stress 300 is applied to multiple PCRAM cells 110, a subcritical stress voltage V as described herein is used. SThis can reduce power consumption. The subcritical stress 300, as described herein, can be applied in various ways, depending on, for example, the specific application, device, or device operation. For example, in some embodiments, the subcritical stress 300 can be applied after the device (or part of the device) is powered on or activated. In some embodiments, if a delay time t is determined... D When the time delay is at or above a certain critical delay time (e.g., a certain number of seconds), a subcritical stress 300 may be present. In some embodiments, the subcritical stress 300 may be applied periodically. In some embodiments, if the delay time t D If the time delay is less than a certain critical delay time, then the subcritical stress 300 may not be applied. In some embodiments, the delay time t may be used as the basis for determining the subcritical stress. D To control the characteristics of the subcritical stress 300. For example, a smaller t D It can correspond to a smaller V S Or a smaller number of subcritical voltage pulses. Other examples are also possible. In some embodiments, if a critical voltage V is determined... TH Subcritical stress 300 can be applied once a certain amount of voltage has been increased or the voltage has been increased to or above a certain critical voltage. Other conditions or techniques for applying or controlling subcritical stress 300 are possible.

[0088] In some embodiments, the subcritical stress 300 may be adaptively applied to reduce the increased critical voltage of the PCRAM cell 110 to near or below the target critical voltage V. TH0 The critical voltage. This reduces variation and places the PCRAM cell 110 in a more defined or ideal state. In some embodiments, the critical voltage variation among the plurality of PCRAM cells 110 can be reduced by applying an adaptive subcritical stress 300 to each of the PCRAM cells 110 respectively. In this way, the plurality of PCRAM cells 110 can simultaneously have a critical voltage V close to or below a single target critical voltage. TH0 The critical voltage. For example, this can improve the uniformity of PCRAM cells 110 in PCRAM array 100. In some cases, using an adaptive subcritical stress process can increase the effectiveness of applying subcritical stress 300, optimize the stress applied to the OTS selector, or avoid applying excessive stress to the OTS selector (e.g., applying more stress than necessary). In some embodiments, subcritical stress 300 can be adaptively applied by repeatedly first measuring the critical voltage of PCRAM cells 110 and then applying subcritical stress 300, wherein the characteristics of each applied subcritical stress 300 are based on the target critical voltage V. TH0 The difference between the measured critical voltage and the previously measured critical voltage. For example, when the previously measured critical voltage is relatively close to the target critical voltage V. TH0 At that time, the stress voltage V after applying a subcritical stress of 300 is...S or stress time t S It can be relatively small. Other technologies are also possible.

[0089] Figure 11 The illustration shows a flowchart of an adaptive subcritical stress process 600 for a PCRAM cell according to some embodiments. At operation 602, the target critical voltage V of the PCRAM cell is determined. TH0 For example, the adaptive subcritical stress process 600 can be executed to reduce the critical voltage of a PCRAM cell to below the target critical voltage V. TH0 Alternatively, the threshold voltage of the PCRAM cell can be adjusted to be approximately equal to the target threshold voltage V. TH0 In some cases, a time-delayed critical voltage drift can increase the critical voltage of a PCRAM cell to above the target critical voltage V. TH0 Under the assumption of [presumably a specific condition or requirement], an adaptive subcritical stress process 600 is performed. At operation 602, an initial subcritical stress is applied to the PCRAM cell. The initial subcritical stress may be similar to any of the subcritical stresses described herein. For example, the initial subcritical stress may comprise one or more subcritical voltage pulses and may have a stress voltage V. S and stress time t S Etc. The initial subcritical stress can reduce the critical voltage of a PCRAM cell to the target critical voltage V. TH0 .

[0090] At operation 606, the voltage will be equal to or higher than the target critical voltage V. TH0 A test voltage is applied to the PCRAM cell. The goal is to reduce the threshold voltage below the target threshold voltage V. TH0 Then an application approximately equal to the target critical voltage V can be applied. TH0 The test voltage. If it is desired that the critical voltage be adjusted to approximately equal to the target critical voltage V... TH0 Then an application approximately equal to the target critical voltage V can be applied. TH0 Or slightly greater than the target critical voltage V TH0 The test voltage. If the initial subcritical stress has sufficiently reduced the critical voltage of the PCRAM cell, the test voltage applied at operation 606 turns on the OTS selector of the PCRAM cell, causing the OTS selector to temporarily enter a high conductivity state (e.g., "on" state).

[0091] At operation 608, it is measured or detected whether the OTS selector is turned on by the test voltage applied at operation 606. If the OTS selector is successfully turned on at operation 606, the critical voltage of the PCRAM cell has been reduced to approximately the target critical voltage V. TH0 Or below the target critical voltage V TH0If the switch is successful, process 600 ends at operation 612.

[0092] If the critical voltage of the PCRAM cell is still too high, the voltage applied at operation 606 is insufficient to enable the OTS selector, and process 600 continues from operation 608 to operation 610. At operation 610, a new subcritical stress characteristic that provides a greater critical voltage reduction effect than the initial subcritical stress is determined. For example, in some embodiments, a new stress voltage greater than the initial subcritical stress may be determined, and / or a new stress time longer than the initial subcritical stress may be determined. In some embodiments, the number of subcritical voltage pulses may be increased from the number used in the initial subcritical stress. Other characteristic variations that determine the new subcritical stress characteristic are possible.

[0093] After determining the new subcritical stress characteristic in operation 610, process 600 returns to operation 604 and applies a subcritical stress with the new subcritical stress characteristic. In some cases, a new subcritical stress characteristic is not determined at operation 610, and the subcritical stress at operation 604 reuses the previously determined subcritical stress characteristic. In other embodiments, the same subcritical stress characteristic is always reused for the subcritical stress at operation 604. Then, process 600 applies a test voltage at operation 606 and determines whether the OTS selector is turned on in operation 608 as before. If the OTS selector is turned on, process 600 ends at operation 612. If the OTS selector is not turned on, a new subcritical stress characteristic is determined in operation 610, which may again include increasing the stress voltage, stress time, and / or the number of subcritical voltage pulses. In operation 604, a subcritical stress with new subcritical stress characteristics is applied, and in this way, process 600 can continue to determine new subcritical stress characteristics until the OTS selector is successfully activated in operation 608 and process 600 ends in operation 612.

[0094] As described herein, using subcritical stress to reduce the effect of time-delay critical voltage drift in memory cell selectors offers several advantages. The techniques described herein allow for the restoration of at least partially increased critical voltages of memory cell selectors to baseline critical voltages while keeping the selectors in the off state. For example, the techniques described herein can be applied in parallel to a single selector or multiple selectors by applying subcritical stress to selectors sharing the same word line or bit line. Subcritical stress uses a voltage below the voltage critical, rather than equal to or higher than the voltage critical. This avoids the need for a large voltage restoration critical voltage after long delay times. The use of subcritical voltage can reduce power consumption, reduce electric or thermal stress on the selector, or reduce the risk of turning on adjacent selectors. Subcritical stress can have a voltage with opposite polarity to the selector switching voltage. For example, the characteristics of subcritical stress can be configured to optimize critical voltage restoration, improve efficiency, or minimize power consumption. In some cases, the characteristics of subcritical stress can be adaptively configured to provide the desired critical voltage restoration. The techniques described in this paper are specifically for PCRAM, but can also be applied to other types of non-volatile memory, such as resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), spin orbit torque magnetoresistive random access memory (SOT-MRAM), and so on. The techniques described in this paper can be applied to various memory architectures, such as 1-selector-1-resistor (1S1R) configurations, cross-point or cross-switch configurations, multi-layer stacked configurations, 3D vertical configurations, etc. Furthermore, the techniques described in this paper can be applied to memories containing OTS selectors, chalcogenide selectors, or other critical selector types, or selector materials exhibiting time-delay critical memory drift.

[0095] According to some embodiments of this disclosure, a method of operating memory includes applying a first voltage pulse across a memory cell, wherein the memory cell includes a selector, and the first voltage pulse switches the selector to an ON state; after applying the first voltage pulse, applying a second voltage pulse across the memory cell, wherein before applying the second voltage pulse, the selector has a first voltage threshold, and wherein after applying the second voltage pulse, the selector has a second voltage threshold less than the first voltage threshold; and after applying the second voltage pulse, applying a third voltage pulse to the memory cell, wherein the third voltage pulse switches the selector to an ON state; wherein the selector remains in an OFF state continuously between the first voltage pulse and the third voltage pulse. In one embodiment, the first voltage pulse and the third voltage pulse have a first voltage polarity, and the second voltage pulse has a second voltage polarity opposite to the first voltage polarity. In one embodiment, the amplitude of the second voltage pulse is less than the amplitude of both the first voltage threshold and the second voltage threshold. In one embodiment, the method includes applying a fourth voltage pulse after applying the first voltage pulse and before applying the second voltage pulse. In one embodiment, the selector includes a layer of GeCTe. In one embodiment, the duration between the first voltage pulse and the second voltage pulse is greater than one second. In one embodiment, a third voltage pulse is applied immediately after the second voltage pulse. In one embodiment, the first voltage threshold is a voltage difference in the range of 50mV to 500mV greater than the second voltage threshold. In one embodiment, the second voltage pulse is applied continuously from the first voltage pulse to the third voltage pulse.

[0096] According to some embodiments of this disclosure, a method of operating memory includes performing a subcritical stress process on a memory array, wherein each memory cell of the memory array includes a chalcogenide selector, wherein performing the subcritical stress process includes applying a first voltage between a first word line and a first bit line of the memory array, wherein the first memory cell of the memory array is connected to the first word line and the first bit line, wherein at the start of the subcritical stress process, the chalcogenide selector of the first memory cell has a first critical voltage, wherein the amplitude of the first voltage is less than the first critical voltage, and wherein at the end of the subcritical stress process, the chalcogenide selector of the first memory cell has a second critical voltage less than the first critical voltage. In one embodiment, performing the subcritical stress process includes simultaneously applying the first voltage between the first word line and the second bit line of the memory array, wherein a second memory cell of the memory array is connected to the first word line and the second bit line. In one embodiment, applying the first voltage includes applying a series of pulses of the first voltage. In one embodiment, the method includes applying a second voltage between a first word line and a first bit line of a memory array prior to performing a subcritical stress process, wherein the second voltage is greater than a first critical voltage, wherein the polarity of the second voltage is opposite to the polarity of the first voltage, and wherein no voltage is applied between the first word line and the first bit line during the time between applying the second voltage and applying the first voltage. In one embodiment, the method includes determining an elapsed time since the application of the second voltage, wherein the application of the first voltage is based on the elapsed time. In one embodiment, the memory array is a phase-change random access memory (PCRAM) array.

[0097] According to some embodiments of this disclosure, a method of operating memory includes determining a target threshold voltage for a chalcogenide selector; applying a first voltage pulse to the chalcogenide selector, wherein the amplitude of the first voltage pulse is less than the amplitude of the target threshold voltage; after applying the first voltage pulse, applying a test voltage pulse to the chalcogenide selector, wherein the amplitude of the test voltage pulse is at least the amplitude of the target threshold voltage; determining whether the test voltage pulse successfully switched the chalcogenide selector to an on state; and based on determining that the chalcogenide selector was switched to an on state, applying a second voltage pulse to the chalcogenide selector, wherein the duration of the second voltage pulse is longer than the duration of the first voltage pulse and / or the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In one embodiment, the method includes applying a third voltage pulse to the chalcogenide selector before applying the second voltage pulse, based on determining that the chalcogenide selector was switched to an on state. In one embodiment, the amplitude of the second voltage pulse is less than the target threshold voltage. In one embodiment, the chalcogenide selector is a selector for memory cells of a PCRAM memory array. In one embodiment, no second voltage pulse is applied after it is determined that the chalcogenide selector has been successfully switched to the ON state.

[0098] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the appearance of some embodiments disclosed herein. Those skilled in the art should understand that they can readily use some embodiments disclosed herein as a basis for designing or modifying other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of some embodiments disclosed herein, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of some embodiments disclosed herein.

Claims

1. A method for operating memory, characterized in that, Include: A first voltage pulse is applied across a memory cell, wherein the memory cell includes a selector, and the first voltage pulse switches the selector to an on state; After the first voltage pulse is applied, a second voltage pulse is applied across the memory cell, wherein before the second voltage pulse is applied, the selector has a first voltage threshold, wherein after the second voltage pulse is applied, the selector has a second voltage threshold that is less than the first voltage threshold, wherein the amplitude of the second voltage pulse is less than the amplitude of the first voltage threshold and less than the amplitude of the second voltage threshold. as well as After the second voltage pulse is applied, a third voltage pulse is applied to the memory cell, wherein the third voltage pulse switches the selector to the on state. The selector remains in a closed state between the first voltage pulse and the third voltage pulse.

2. The method as described in claim 1, characterized in that, The first voltage pulse and the third voltage pulse have a first voltage polarity, and the second voltage pulse has a second voltage polarity opposite to the first voltage polarity.

3. The method as described in claim 1, characterized in that, This memory unit is a phase-change random access memory unit.

4. The method as described in claim 1, characterized in that, It further includes applying a fourth voltage pulse after the first voltage pulse is applied and before the second voltage pulse is applied.

5. The method as described in claim 1, characterized in that, This selector contains a layer of GeCTe.

6. The method as described in claim 1, characterized in that, The duration between the first voltage pulse and the second voltage pulse is greater than one second.

7. The method as described in claim 1, characterized in that, The third voltage pulse is applied immediately after the second voltage pulse.

8. The method as described in claim 1, characterized in that, The first voltage threshold is a voltage difference within the range of 50 mV to 500 mV greater than the second voltage threshold.

9. The method as described in claim 1, characterized in that, The second voltage pulse is applied continuously from the first voltage pulse to the third voltage pulse.

10. A method for operating memory, characterized in that, Include: Performing a critical stress process on a memory array, wherein each memory cell of the memory array includes a chalcogenide selector, wherein performing the critical stress process includes: A first voltage is applied between a first word line and a first bit line of the memory array, wherein a first memory cell of the memory array is connected to the first word line and the first bit line, wherein at the beginning of the critical stress process, the chalcogenide selector of the first memory cell has a first critical voltage, wherein an amplitude of the first voltage is less than the first critical voltage, and wherein at the end of the critical stress process, the chalcogenide selector of the first memory cell has a second critical voltage less than the first critical voltage; as well as Before performing the critical stress process, a second voltage is applied between the first word line and the first bit line of the memory array, wherein the second voltage is greater than the first critical voltage, wherein one polarity of the second voltage is opposite to one polarity of the first voltage, and wherein no voltage is applied between the first word line and the first bit line during a period between the application of the second voltage and the application of the first voltage.

11. The method as described in claim 10, characterized in that, The critical stress process further includes: simultaneously applying the first voltage between the first word line and the second bit line of the memory array, wherein a second memory cell of the memory array is connected to the first word line and the second bit line.

12. The method as described in claim 10, characterized in that, Applying the first voltage involves a series of pulses that apply the first voltage.

13. The method as described in claim 10, characterized in that, The time between the first voltage and the second voltage is greater than one second.

14. The method as described in claim 13, characterized in that, It further includes: determining an elapsed time since the second voltage was applied, wherein the application of the first voltage is based on the elapsed time.

15. The method as described in claim 10, characterized in that, This memory array is a phase-change random access memory array.

16. A method for operating memory, characterized in that, Include: Determine a target critical voltage for a chalcogenide selector; A first voltage pulse is applied to the chalcogenide selector, wherein the amplitude of the first voltage pulse is less than the amplitude of the target threshold voltage; After the first voltage pulse is applied, a test voltage pulse is applied to the chalcogenide selector, wherein the amplitude of the test voltage pulse is at least the amplitude of the target threshold voltage; Determine whether the test voltage pulse successfully switched the chalcogenide selector to a conducting state; as well as Based on the determination to switch the chalcogenide selector to the on state, a second voltage pulse is applied to the chalcogenide selector, wherein the duration of the second voltage pulse is longer than the duration of the first voltage pulse and / or the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse.

17. The method as described in claim 16, characterized in that, It further includes: based on determining that the chalcogenide selector has switched to the on state, applying a third voltage pulse to the chalcogenide selector before applying the second voltage pulse.

18. The method as described in claim 16, characterized in that, The amplitude of the second voltage pulse is less than the target critical voltage.

19. The method as described in claim 16, characterized in that, The chalcogenide selector is a selector for a memory cell in a phase-change random access memory array.

20. The method as described in claim 16, characterized in that, Once it is confirmed that the chalcogenide selector has been successfully switched to the on state, the second voltage pulse is not applied.

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