A charge pump circuit for on-chip clock generation circuit

Abstract

This invention claims protection for a charge pump circuit for an on-chip clock generation circuit, including a bias circuit, a compensation circuit, and a charge pump core circuit. The invention employs MOSFETs M11-M36 and operational amplifier OP2 to form a dynamic current compensation structure. It dynamically compensates the charge / discharge current of the charge pump by controlling the currents of PMOS transistors M12, M18, M28, and M30, thereby increasing the matching range of the charge pump's charge / discharge current. Furthermore, it utilizes PMOS transistor M50 to suppress the channel modulation effect on the current of PMOS transistor M51 and NMOS transistor M57 to suppress the channel modulation effect on the current of NMOS transistor M58, improving the matching performance of the charge pump's charge / discharge current. This results in a high-performance charge pump circuit for an on-chip clock generation circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a charge pump circuit for an on-chip clock generation circuit. Background Technology

[0002] High-speed analog-to-digital converters (ADCs), high-speed serial link transceivers, and clock and data recovery (CDR) circuits all require precise clocks. Phase-locked loops (PLLs) are widely used in system clock signal generation circuits due to their high stability, lack of jitter accumulation, and low phase noise. The charge pump circuit, as a crucial component of the PLL, directly impacts the performance of the entire PLL system, and consequently, the system's overall performance characteristics.

[0003] Figure 1 This is a traditional charge pump circuit where MOSFETs M1 and M4 are the charging and discharging current sources, respectively, and MOSFETs M2 and M3 act as the charging and discharging switches, respectively. When MOSFET M2 is closed and MOSFET M3 is open, MOSFET M1, acting as the charging current source, operates, and the charging current of the charge pump is injected into the load capacitor CL, causing the voltage at the output terminal Vctrl to rise. When MOSFET M2 is open and MOSFET M3 is closed, MOSFET M4, acting as the discharging current source, operates, and the charge pump draws discharging current from the capacitor, causing the voltage at the output terminal Vctrl to drop. When both MOSFETs M2 and M3 are open, neither current source operates, the net current flowing out of the current source branch is zero, and the voltage at the output terminal Vctrl remains unchanged. Traditional charge pumps suffer from problems such as matching range and current mismatch, thus limiting their application in high-performance systems. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above. A charge pump circuit for on-chip clock generation is proposed. The technical solution of this invention is as follows:

[0005] A charge pump circuit for an on-chip clock generation circuit includes: a bias circuit (1), a compensation circuit (2), and a charge pump core circuit (3). The signal output terminal of the bias circuit (1) is connected to the signal input terminals of the compensation circuit (2) and the charge pump core circuit (3), and the signal output terminal of the compensation circuit (2) is connected to the signal input terminal of the charge pump core circuit (3). The bias circuit (1) provides a bias signal to the compensation circuit (2) and the charge pump core circuit (3). The compensation circuit (2) provides dynamic compensation current to the charge pump core circuit (3) through PMOS transistor M12, PMOS transistor M18, NMOS transistor M28, and NMOS transistor M30. The charge pump core circuit (3) provides charging / discharging current to the filter capacitor of the subsequent circuit through the output terminal Vctrl of the charge pump circuit.

[0006] Furthermore, the bias circuit (1) includes: a current source Iref, PMOS transistors M1, M6, M37, M38, M43, and M44, resistors R1 and R2. One end of the current source Iref is connected to the source of PMOS transistor M1 and the external power supply VDD, respectively. The other end of the current source Iref is connected to one end of resistor R1, the gate of NMOS transistors M37, M38, M39, M40, M41, and M42, respectively. The other end of resistor R1 is connected to the drain of NMOS transistor M37, the gate of NMOS transistor M43, the gate of NMOS transistor M44, the gate of NMOS transistor M45, the gate of NMOS transistor M46, and the NMOS transistor M44. The gate of S-channel transistor M47 is connected to the gate of NMOS transistor M48. The source of NMOS transistor M37 is connected to the drain of NMOS transistor M43. The source of NMOS transistor M43 is connected to the source of NMOS transistor M44 and external ground GND. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M6. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M6, one end of resistor R2, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M4, and the gate of PMOS transistor M5. The other end of resistor R2 is connected to the drain of NMOS transistor M38, the gate of PMOS transistor M6, the gate of PMOS transistor M7, the gate of PMOS transistor M8, the gate of PMOS transistor M9, and the gate of PMOS transistor M10. The source of NMOS transistor M38 is connected to the drain of NMOS transistor M44.

[0007] Furthermore, in the bias circuit (1), NMOS transistors M37 and M38 have the same channel width-to-length ratio, and NMOS transistors M44 and M43 have the same channel width-to-length ratio, so that PMOS transistors M1, M6, M37, M38, M43, M44 and current source Iref have the same current.

[0008] Furthermore, the compensation circuit (2) includes: PMOS transistors M2, M3, M4, M7, M8, M9, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, NMOS transistors M23, M24, M25, M26, M27, M28, M29, M30, and NMOS transistors M28, M29, and M29. The transistors are M31, M32, M33, M34, M35, M36, M39, M40, M41, M45, M46, and M47, along with resistors R3 and R4. The source of PMOS transistor M13 is connected to the sources of PMOS transistors M2, M3, M11, M12, M16, M19, M17, M20, M21, and M4, as well as an external resistor. The power supply VDD is connected. The gate of PMOS transistor M13 is connected to the drain of PMOS transistor M13, the source of PMOS transistor M14, and the bias terminal Vcmn2. The gate of PMOS transistor M14 is connected to the bias terminal DN. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the gate of NMOS transistor M25, the source of NMOS transistor M23, the source of PMOS transistor M24, the output terminal of amplifier OP2, and the inverting input terminal of amplifier OP2. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M29, the gate of NMOS transistor M29, and the gate of NMOS transistor M28. The source of NMOS transistor M29 is connected to N... The sources of MOSFETs M28, M32, M31, M33, M35, M27, M36, M45, M46, and M47, as well as external ground GND, are connected. The drain of PMOS transistor M2 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 is connected to one end of resistor R3. The other end of resistor R3 is connected to the gate of NMOS transistor M30, the drain of NMOS transistor M31, and the gate of NMOS transistor M32. The source of NMOS transistor M30 is connected to the drain of NMOS transistor M32.The drain of PMOS transistor M3 is connected to the source of PMOS transistor M8. The drain of PMOS transistor M8 is connected to the gate of NMOS transistors M32, M33, and M34, respectively. The gate of NMOS transistor M34 is connected to the bias terminal DN. The source of NMOS transistor M34 is connected to the drain of NMOS transistor M35. The gate of NMOS transistor M35 is connected to the gate of NMOS transistor M36, the drain of NMOS transistor M36, and PMOS transistor M9, respectively. The drain of PMOS transistor M11 is connected to the drain of NMOS transistor M23. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12, the drain of PMOS transistor M11, and the drain of NMOS transistor M25. The source of NMOS transistor M25 is connected to the drain of NMOS transistor M26. The gate of NMOS transistor M26 is connected to the bias terminal UP. The source of NMOS transistor M26 is connected to the drain of NMOS transistor M27, the gate of NMOS transistor M27, and the bias terminal Vcmp2. The drain of PMOS transistor M16 is connected to PM... The source of PMOS transistor M18 is connected to the gate of PMOS transistor M19, the drain of PMOS transistor M19, and one end of resistor R4. The other end of resistor R4 is connected to the drain of NMOS transistor M39. The source of NMOS transistor M39 is connected to the drain of NMOS transistor M45. The drain of PMOS transistor M20 is connected to the source of PMOS transistor M22. The gate of PMOS transistor M22 is connected to the bias terminal UP. The drain of PMOS transistor M22 is connected to the gate of PMOS transistor M16. The source of PMOS transistor M40 is connected to the gate and drain of PMOS transistor M17, and the drain of NMOS transistor M40. The source of NMOS transistor M40 is connected to the drain of NMOS transistor M46. The drain of PMOS transistor M21 is connected to the gate of PMOS transistor M21, the gate of PMOS transistor M20, the drain of PMOS transistor M24, and the drain of NMOS transistor M41. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M9. The source of NMOS transistor M41 is connected to the drain of NMOS transistor M47.

[0009] Furthermore, in the compensation circuit (2), PMOS transistors M2 and M1 have the same channel width-to-length ratio, PMOS transistors M7 and M6 have the same channel width-to-length ratio, PMOS transistors M3 and M4 have the same channel width-to-length ratio and are α times that of PMOS transistor M1, PMOS transistors M8 and M9 have the same channel width-to-length ratio and are α times that of PMOS transistor M6, and NMOS transistors M45 and M43 have the same channel width-to-length ratio. In comparison, NMOS transistors M39 and M37 have the same channel width-to-length ratio; NMOS transistors M46 and M47 have the same channel width-to-length ratio, which is α times that of NMOS transistor M43; NMOS transistors M40 and M41 have the same channel width-to-length ratio, which is α times that of NMOS transistor M37; the bias terminals UP and DN have opposite signals; and amplifier OP2 forces the source voltage V of PMOS transistor M24. CP The voltage V at the output terminal Vctrl of the charge pump circuit ctrl equal.

[0010] Furthermore, in the compensation circuit (2), when the bias terminal UP is low and the bias terminal DN is high, NMOS transistor M34 and PMOS transistor M14 are turned on simultaneously, while NMOS transistor M26 and PMOS transistor M22 begin to turn off, and the charge pump circuit discharges. When the voltage Vctrl at the output terminal V of the charge pump circuit... ctrl When the current drops to a certain value, PMOS transistor M24 turns off, and the current of NMOS transistor M23 flows into amplifier OP2. NMOS transistors M35 and M36 have the same channel width-to-length ratio, and NMOS transistors M32 and M33 have the same channel width-to-length ratio. The current I of NMOS transistor M30... 30 Current of NMOS transistor M23 Where μ n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 23 V is the channel width-to-length ratio of NMOS transistor M23. cmn1 The voltage at the bias terminal Vcmn1, V CP V is the source voltage of PMOS transistor M24. THn This is the threshold voltage of the NMOS transistor; the PMOS transistor M14, with a large channel width-to-length ratio, operates in the deep transistor region and its source voltage is approximately equal to the voltage V at the bias terminal Vcmn2. cmn2 NMOS transistors M29 and M28 have the same channel width-to-length ratio. The current I of NMOS transistor M28 is... 28 ≈ Where μ p Hole mobility, (W / L)15 V is the channel width-to-length ratio of PMOS transistor M15. THp This is the threshold voltage of the PMOS transistor.

[0011] Furthermore, in the compensation circuit (2), when the bias terminal UP is high and the bias terminal DN is low, NMOS transistor M34 and PMOS transistor M14 are simultaneously turned off, and NMOS transistor M26 and PMOS transistor M22 are turned on, charging the charge pump circuit. When the voltage Vctrl at the output terminal V of the charge pump circuit... ctrl When the current rises to a certain value, NMOS transistor M23 turns off, and the current of PMOS transistor M24 flows into amplifier OP2. PMOS transistors M20 and M21 have the same channel width-to-length ratio, and PMOS transistors M16 and M17 have the same channel width-to-length ratio. The current I of PMOS transistor M18... 18 Current of PMOS transistor M24 Where μ p C represents hole mobility. ox The capacitance of the gate oxide layer per unit area (W / L) 24 V is the channel width-to-length ratio of PMOS transistor M24. CP V is the source voltage of PMOS transistor M24. cmp1 The voltage at the bias terminal Vcmp1, V THp This is the threshold voltage of the PMOS transistor; the NMOS transistor M26, with a large channel width-to-length ratio, operates in the deep transistor region and its source voltage is approximately equal to the voltage V at the bias terminal Vcmp2. cmp2 PMOS transistors M11 and M12 have the same channel width-to-length ratio. The current I of PMOS transistor M12 is... 12 ≈ Where, μ n Electron mobility, (W / L) 25 V is the channel width-to-length ratio of PMOS transistor M25. THn This is the threshold voltage of the NMOS transistor.

[0012] Furthermore, the charge pump core circuit (3) includes: PMOS transistors M5, M10, M42, M48, M49, M50, M51, M52, M53, M54, M55, M56, M57, M58, amplifiers OP1 and OP2, resistors R5 and R6, wherein the source of PMOS transistor M5 is connected to the source of PMOS transistor M49, the source of PMOS transistor M50, and the source of PMOS transistor M58. The source of transistor M51 is connected to the external power supply VDD. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M10. The drain of PMOS transistor M10 is connected to one end of resistor R5. The other end of resistor R5 is connected to the drain of NMOS transistor M56, the gate of NMOS transistor M56, the drain of NMOS transistor M57, and the gate of NMOS transistor M58. The source of NMOS transistor M56 is connected to the source of NMOS transistor M48, the source of NMOS transistor M57, the source of NMOS transistor M58, and the external ground GND. The gate of PMOS transistor M49 is connected to the drain of PMOS transistor M50, the PMOS transistor M57, the gate of PMOS transistor M58, and the gate of PMOS transistor M59. The gate of transistor M51, the drain of PMOS transistor M49, and one end of resistor R6 are connected. The other end of resistor R6 is connected to the drain of NMOS transistor M42. The source of NMOS transistor M42 is connected to the drain of NMOS transistor M48. The drain of PMOS transistor M51 is connected to the drains of PMOS transistors M12 and M18, the source of PMOS transistor M52, and the source of PMOS transistor M53. The gate of PMOS transistor M52 is connected to the bias terminal UP. The drain of PMOS transistor M52 is connected to the output terminal of amplifier OP1, the inverting input terminal of amplifier OP1, and the drain of NMOS transistor M54. The gate of NMOS transistor M54 is connected to the bias terminal DN, the gate of PMOS transistor M53 is connected to the bias terminal UP, the drain of PMOS transistor M53 is connected to the non-inverting input terminal of amplifier OP1, the non-inverting input terminal of amplifier OP2, the drain of NMOS transistor M55, the gate of PMOS transistor M50, the gate of NMOS transistor M57, and the circuit output terminal Vctrl. The gate of NMOS transistor M55 is connected to the bias terminal DN, and the source of NMOS transistor M55 is connected to the source of NMOS transistor M54, the drain of NMOS transistor M28, the drain of NMOS transistor M30, and the drain of NMOS transistor M58.

[0013] Furthermore, in the charge pump core circuit (3), PMOS transistors M5 and M11 have the same channel width-to-length ratio, PMOS transistors M10 and M6 have the same channel width-to-length ratio, NMOS transistors M42 and M37 have the same channel width-to-length ratio, NMOS transistors M48 and M43 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS transistor M51 is α times that of PMOS transistor M49, and the channel width-to-length ratio of NMOS transistor M58 is α times that of NMOS transistor M56. When the bias terminal UP is low and the bias terminal DN is high, the charge pump circuit discharges, and the voltage V at the circuit output terminal Vctrl is... ctrl To reduce the current reduction in NMOS transistor M58 caused by the channel modulation effect, a technique is employed to replicate a portion of the current flowing through NMOS transistor M56. This technique aims to mitigate the current reduction in NMOS transistor M58 due to the channel modulation effect. The discharge current I of the charge pump circuit is also affected. DN That is, the current flowing through the NMOS transistor M55 is I DN = Among them I ref μ is the current of the current source Iref. n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 57 V is the channel width-to-length ratio of the NMOS transistor M57. THn ΔI is the threshold voltage of the NMOS transistor. 58 The current deviation of the NMOS transistor M58 caused by the channel modulation effect, I 30 I is the current of NMOS transistor M30. 28 The current I is the current of the NMOS transistor M28. 30 and current I 28 Dynamic compensation is applied to the discharge current of the charge pump; when the bias terminal UP is high and the bias terminal DN is low, the charge pump circuit charges, and the voltage V... ctrl The current rises because the channel modulation effect reduces the saturation current of PMOS transistor M51. To suppress this current drop caused by the channel modulation effect, a technique is used to replicate a portion of the current flowing through PMOS transistor M49. The charging current I of the charge pump circuit... UP That is, the current flowing through PMOS transistor M50 is I UP = Where μ p Hole mobility, (W / L) 50 V is the channel width-to-length ratio of the PMOS transistor M50. DD The voltage ΔI is the external power supply VDD. 51 The current deviation of PMOS transistor M51 caused by channel modulation effect, I 12 I is the current of PMOS transistor M12.18 V is the current of PMOS transistor M18. THp The threshold voltage of the PMOS transistor is given by I. 12 and current I 18 Dynamic compensation is applied to the charging current of the charge pump to improve the matching range of the charging current.

[0014] The advantages and beneficial effects of this invention are as follows:

[0015] This invention provides a charge pump circuit for an on-chip clock generation circuit. It employs MOSFETs M11-M36 and operational amplifier OP2 to form a dynamic current compensation structure. The compensation current dynamically adjusts based on the voltage at the charge pump output terminal Vctrl and the charge pump charging / discharging current, and is controlled by the current I of NMOS transistor M30. 30 and the current I of NMOS transistor M28 28 Dynamic compensation is performed on the discharge current of the charge pump, and the current I through the PMOS transistor M12 is... 12 and the current I of PMOS transistor M18 18 The charging current of the charge pump is dynamically compensated to increase the matching range of the charge pump's charging / discharging current. The technology of using PMOS transistor M50 to suppress the channel modulation effect on the current of PMOS transistor M51 and NMOS transistor M57 to suppress the channel modulation effect on the current of NMOS transistor M58 is adopted to improve the matching of the charge pump's charging and discharging current, thereby realizing a high-performance charge pump circuit for on-chip clock generation circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a conventional charge pump circuit according to a preferred embodiment of the present invention;

[0017] Figure 2 A schematic diagram of a charge pump circuit for an on-chip clock generation circuit, according to a preferred embodiment of the present invention;

[0018] Figure 3 A simulation diagram of charge pump circuit for on-chip clock generation circuit, which is provided as a preferred embodiment of the present invention, shows the charge and discharge current matching. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0020] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0021] In this embodiment, MOS transistors M11 to M36 and operational amplifier OP2 are used to form a dynamic current compensation structure. The charge / discharge current of the charge pump is dynamically compensated by the current of PMOS transistors M12, M18, M28, and M30, thereby increasing the matching range of the charge / discharge current of the charge pump. The technology of using PMOS transistor M50 to suppress the channel modulation effect on the current of PMOS transistor M51 and NMOS transistor M57 to suppress the channel modulation effect on the current of NMOS transistor M58 is used to improve the matching of the charge pump charge / discharge current, thereby realizing a high-performance charge pump circuit for on-chip clock generation circuit.

[0022] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0023] Example

[0024] A charge pump circuit for on-chip clock generation circuits, such as Figure 2 As shown, it includes bias circuit 1, compensation circuit 2 and charge pump core circuit 3;

[0025] The signal output terminal of the bias circuit 1 is connected to the signal input terminal of the compensation circuit 2 and the charge pump core circuit 3, and the signal output terminal of the compensation circuit 2 is connected to the signal input terminal of the charge pump core circuit 3. The bias circuit 1 provides a bias signal to the compensation circuit 2 and the charge pump core circuit 3. The compensation circuit 2 provides dynamic compensation current to the charge pump core circuit 3 through PMOS transistors M12, M18, M28, and M30. The charge pump core circuit 3 provides charging / discharging current to the filter capacitor of the subsequent circuit through the circuit output terminal Vctrl.

[0026] As a preferred technical solution, such as Figure 2As shown, the bias circuit 1 includes: a current source Iref, PMOS transistors M1, M6, M37, M38, M43, and M44, resistors R1 and R2. One end of the current source Iref is connected to the source of PMOS transistor M1 and the external power supply VDD. The other end of the current source Iref is connected to one end of resistor R1, the gates of NMOS transistors M37, M38, M39, M40, M41, and M42. The other end of resistor R1 is connected to the drain of NMOS transistor M37, the gate of NMOS transistor M43, the gate of NMOS transistor M44, the gate of NMOS transistor M45, the gate of NMOS transistor M46, and the gate of NMOS transistor M44. The gate of M47 is connected to the gate of NMOS transistor M48. The source of NMOS transistor M37 is connected to the drain of NMOS transistor M43. The source of NMOS transistor M43 is connected to the source of NMOS transistor M44 and external ground GND. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M6. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M6, one end of resistor R2, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M4, and the gate of PMOS transistor M5. The other end of resistor R2 is connected to the drain of NMOS transistor M38, the gate of PMOS transistor M6, the gate of PMOS transistor M7, the gate of PMOS transistor M8, the gate of PMOS transistor M9, and the gate of PMOS transistor M10. The source of NMOS transistor M38 is connected to the drain of NMOS transistor M44.

[0027] The compensation circuit 2 includes: PMOS transistors M2, M3, M4, M7, M8, M9, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, NMOS transistors M23, M24, M25, M26, M27, M28, M29, M30, M31, and N... MOSFETs M32, M33, M34, M35, M36, M39, M40, M41, M45, M46, and M47, resistors R3 and R4, and the source of PMOS transistor M13 is connected to the sources of PMOS transistors M2, M3, M11, M12, M16, M19, M17, M20, M21, and M4, as well as the external power supply V. The gate of PMOS transistor M13 is connected to the drain of PMOS transistor M13, the source of PMOS transistor M14, and the bias terminal Vcmn2. The gate of PMOS transistor M14 is connected to the bias terminal DN. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the gate of NMOS transistor M25, the source of NMOS transistor M23, the source of PMOS transistor M24, the output terminal of amplifier OP2, and the inverting input terminal of amplifier OP2. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M29, the gate of NMOS transistor M29, and the gate of NMOS transistor M28. The source of NMOS transistor M29 is connected to the NMOS transistor M28. The sources of S-MOSFET M28, NMOS transistors M32, M31, M33, M35, M27, M36, M45, M46, and M47 are connected to external ground (GND). The drain of PMOS transistor M2 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 is connected to one end of resistor R3. The other end of resistor R3 is connected to the gate of NMOS transistor M30, the drain of NMOS transistor M31, and the gate of NMOS transistor M32. The source of NMOS transistor M30 is connected to the drain of NMOS transistor M32.The drain of PMOS transistor M3 is connected to the source of PMOS transistor M8. The drain of PMOS transistor M8 is connected to the gate of NMOS transistors M32, M33, and M34, respectively. The gate of NMOS transistor M34 is connected to the bias terminal DN. The source of NMOS transistor M34 is connected to the drain of NMOS transistor M35. The gate of NMOS transistor M35 is connected to the gate of NMOS transistor M36, the drain of NMOS transistor M36, and PMOS transistor M9, respectively. The drain of PMOS transistor M11 is connected to the drain of NMOS transistor M23. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12, the drain of PMOS transistor M11, and the drain of NMOS transistor M25. The source of NMOS transistor M25 is connected to the drain of NMOS transistor M26. The gate of NMOS transistor M26 is connected to the bias terminal UP. The source of NMOS transistor M26 is connected to the drain of NMOS transistor M27, the gate of NMOS transistor M27, and the bias terminal Vcmp2. The drain of PMOS transistor M16 is connected to PM... The source of PMOS transistor M18 is connected to the gate of PMOS transistor M19, the drain of PMOS transistor M19, and one end of resistor R4. The other end of resistor R4 is connected to the drain of NMOS transistor M39. The source of NMOS transistor M39 is connected to the drain of NMOS transistor M45. The drain of PMOS transistor M20 is connected to the source of PMOS transistor M22. The gate of PMOS transistor M22 is connected to the bias terminal UP. The drain of PMOS transistor M22 is connected to the gate of PMOS transistor M16. The source of PMOS transistor M40 is connected to the gate and drain of PMOS transistor M17, and the drain of NMOS transistor M40. The source of NMOS transistor M40 is connected to the drain of NMOS transistor M46. The drain of PMOS transistor M21 is connected to the gate of PMOS transistor M21, the gate of PMOS transistor M20, the drain of PMOS transistor M24, and the drain of NMOS transistor M41. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M9. The source of NMOS transistor M41 is connected to the drain of NMOS transistor M47.

[0028] The charge pump core circuit 3 includes: PMOS transistors M5, M10, M42, M48, M49, M50, M51, M52, M53, M54, M55, M56, M57, and M58; amplifiers OP1 and OP2; resistors R5 and R6; wherein the source of PMOS transistor M5 is connected to the source of PMOS transistors M49, M50, and M51, respectively. The PMOS transistor M5 is connected to the external power supply VDD. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M10. The drain of PMOS transistor M10 is connected to one end of resistor R5. The other end of resistor R5 is connected to the drain of NMOS transistor M56, the gate of NMOS transistor M56, the drain of NMOS transistor M57, and the gate of NMOS transistor M58. The source of NMOS transistor M56 is connected to the source of NMOS transistor M48, the source of NMOS transistor M57, the source of NMOS transistor M58, and the external ground GND. The gate of PMOS transistor M49 is connected to the drain of PMOS transistor M50 and the external ground GND. The gate of transistor OP1, the drain of PMOS transistor M49, and one end of resistor R6 are connected. The other end of resistor R6 is connected to the drain of NMOS transistor M42. The source of NMOS transistor M42 is connected to the drain of NMOS transistor M48. The drain of PMOS transistor M51 is connected to the drains of PMOS transistors M12, M18, M52, and M53. The gate of PMOS transistor M52 is connected to the bias terminal UP. The drain of PMOS transistor M52 is connected to the output of amplifier OP1, the inverting input of amplifier OP1, and the drain of NMOS transistor M54. The gate of NMOS transistor M54 is connected to the bias terminal DN, the gate of PMOS transistor M53 is connected to the bias terminal UP, the drain of PMOS transistor M53 is connected to the non-inverting input terminal of amplifier OP1, the non-inverting input terminal of amplifier OP2, the drain of NMOS transistor M55, the gate of PMOS transistor M50, the gate of NMOS transistor M57, and the circuit output terminal Vctrl, the gate of NMOS transistor M55 is connected to the bias terminal DN, and the source of NMOS transistor M55 is connected to the source of NMOS transistor M54, the drain of NMOS transistor M28, the drain of NMOS transistor M30, and the drain of NMOS transistor M58.

[0029] In the bias circuit 1, NMOS transistors M37 and M38 have the same channel width-to-length ratio, and NMOS transistors M44 and M43 have the same channel width-to-length ratio, such that the drain current I1 of PMOS transistor M1, the drain current I6 of PMOS transistor M6, and the drain current I of NMOS transistor M37 are...37 The drain current I of NMOS transistor M38 38 The drain current I of NMOS transistor M43 43 The drain current I of NMOS transistor M44 44 and the current I of the current source Iref ref There are I1 = I6 = I 37 =I 38 =I 44 =I ref .

[0030] In the compensation circuit 2, PMOS transistors M2 and M1 have the same channel width-to-length ratio, PMOS transistors M7 and M6 have the same channel width-to-length ratio, PMOS transistors M3 and M4 have the same channel width-to-length ratio and are α times that of PMOS transistor M1, PMOS transistors M8 and M9 have the same channel width-to-length ratio and are α times that of PMOS transistor M6, NMOS transistors M45 and M43 have the same channel width-to-length ratio, NMOS transistors M39 and M37 have the same channel width-to-length ratio, NMOS transistors M46 and M47 have the same channel width-to-length ratio and are α times that of NMOS transistor M43, NMOS transistors M40 and M41 have the same channel width-to-length ratio and are α times that of NMOS transistor M37, the bias terminal UP has opposite signals to the bias terminal DN, and the bias terminal DN has opposite signals to the bias terminal DN. When the bias terminal UP is low and the bias terminal DN is high, NMOS transistor M34 and PMOS transistor M14 are simultaneously turned on, while NMOS transistor M26 and PMOS transistor M22 begin to turn off. The charge pump circuit discharges, and the voltage V at the circuit output terminal Vctrl increases. ctrl The source voltage V of the PMOS transistor M24 is reduced by amplifier OP2. CP The voltage V at the circuit output terminal Vctrl ctrl Equal, when voltage V ctrl When the current drops to a certain value, PMOS transistor M24 turns off, and the current of NMOS transistor M23 flows into amplifier OP2. At this time, the current I of NMOS transistor M23 is... 23 for

[0031]

[0032] In the formula, μ n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 23 V is the channel width-to-length ratio of NMOS transistor M23. THnLet I be the threshold voltage of the NMOS transistor. NMOS transistors M35 and M36 have the same channel width-to-length ratio, and NMOS transistors M32 and M33 have the same channel width-to-length ratio. Then, the current I of NMOS transistor M30 is... 30 There is I 30 =I 23 The PMOS transistor M14 has a large channel width-to-length ratio and its gate is at a low level, causing it to operate in the deep transistor region. Therefore, the source voltage of the PMOS transistor M15 is approximately equal to the voltage V at the bias terminal Vcmn2. cmn2 NMOS transistors M29 and M28 have the same channel width-to-length ratio. Therefore, the current I of NMOS transistor M28 is... 28 Approximately

[0033]

[0034] In the formula, μ p Hole mobility, (W / L) 15 V is the channel width-to-length ratio of PMOS transistor M15. THp This is the threshold voltage of the PMOS transistor.

[0035] When the bias terminal UP is high and the bias terminal DN is low, NMOS transistor M34 and PMOS transistor M14 are simultaneously turned off, while NMOS transistor M26 and PMOS transistor M22 are turned on. The charge pump circuit charges, and the voltage V at the circuit output terminal Vctrl increases. ctrl As the voltage rises, amplifier OP2 forces the source voltage V of PMOS transistor M24 to rise. CP The voltage V at the circuit output terminal Vctrl ctrl Equal, when voltage V ctrl When the current rises to a certain value, NMOS transistor M23 turns off, and the current of PMOS transistor M24 flows into amplifier OP2. At this time, the current I of PMOS transistor M24 is... 24 for

[0036]

[0037] In the formula, (W / L) 24 V is the channel width-to-length ratio of PMOS transistor M24. cmp1 Given the voltage at the bias terminal Vcmp1, PMOS transistors M20 and M21 have the same channel width-to-length ratio, and PMOS transistors M16 and M17 have the same channel width-to-length ratio. Then, the current I of PMOS transistor M18... 18 There is I 18 =I 24The NMOS transistor M26 has a large channel width-to-length ratio and its gate is at a high level, causing it to operate in the deep transistor region. Therefore, the source voltage of the PMOS transistor M25 is approximately equal to the voltage V at its bias terminal Vcmp2. cmp2 If PMOS transistors M11 and M12 have the same channel width-to-length ratio, then the current I of PMOS transistor M12 is... 12 Approximately

[0038]

[0039] In the formula, (W / L) 25 This is the channel width-to-length ratio of the PMOS transistor M25.

[0040] In the core circuit 3 of the charge pump, PMOS transistors M5 and M11 have the same channel width-to-length ratio, PMOS transistors M10 and M6 have the same channel width-to-length ratio, NMOS transistors M42 and M37 have the same channel width-to-length ratio, NMOS transistors M48 and M43 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS transistor M51 is α times that of PMOS transistor M49, and the channel width-to-length ratio of NMOS transistor M58 is α times that of NMOS transistor M56. When the bias terminal UP is low and the bias terminal DN is high, the charge pump circuit discharges, and the voltage V at the circuit output terminal Vctrl... ctrl To reduce the saturation current of NMOS transistor M58 due to the channel modulation effect, a technique is employed to replicate a portion of the current flowing through NMOS transistor M56 to overcome the channel modulation effect, thereby improving the matching of the discharge current. Furthermore, the current I of NMOS transistor M58... 58 for

[0041]

[0042] In the formula, ΔI 58 The current deviation of the NMOS transistor M58 caused by the channel modulation effect, I 57 The current of NMOS transistor M57 is...

[0043]

[0044] In the formula, (W / L) 57 Given the channel width-to-length ratio of NMOS transistor M57, the discharge current I of the charge pump circuit is... DN That is, the current flowing through the NMOS transistor M55 is

[0045]

[0046] When the bias terminal UP is high and the bias terminal DN is low, the charge pump circuit charges, and the voltage V at the circuit output terminal Vctrl increases.ctrl The current rises because the channel modulation effect reduces the saturation current of PMOS transistor M51. A technique is used to replicate a portion of the current flowing through PMOS transistor M49 to overcome the channel modulation effect, thereby improving the charging current matching. Furthermore, the current I of PMOS transistor M51... 51 , it is

[0047] I 51 =α(I ref -I 50 )-ΔI 51 (8)

[0048] In the formula, ΔI 51 The current deviation of PMOS transistor M51 caused by channel modulation effect, I 50 The current of PMOS transistor M50 is...

[0049]

[0050] In the formula, (W / L) 50 Given the channel width-to-length ratio of PMOS transistor M50, the discharge current I of the charge pump circuit is... UP That is, the current flowing through PMOS transistor M50 is

[0051]

[0052] Figure 3 This is a simulation curve of the charge pump circuit for an on-chip clock generation circuit according to the present invention, showing the charge and discharge current matching. The horizontal axis represents voltage, and the vertical axis represents charge and discharge current. The simulation results show that the current mismatch is 2% when the output voltage ranges from 0.21V to 0.94V.

[0053] In the above embodiments of this application, a charge pump circuit for an on-chip clock generation circuit includes a bias circuit, a compensation circuit, and a charge pump core circuit. This application embodiment uses MOS transistors M11-M36 and operational amplifier OP2 to form a dynamic current compensation structure. The charge pump charging / discharging current is dynamically compensated by the currents of PMOS transistors M12, M18, M28, and M30, increasing the matching range of the charge pump charging / discharging current. The technology of using PMOS transistor M50 to suppress the channel modulation effect on the current of PMOS transistor M51 and NMOS transistor M57 to suppress the channel modulation effect on the current of NMOS transistor M58 improves the matching of the charge pump charging / discharging current, thereby realizing a high-performance charge pump circuit for an on-chip clock generation circuit.

[0054] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0055] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0056] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0057] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A charge pump circuit for an on-chip clock generation circuit, characterized by, include: The circuit comprises a bias circuit (1), a compensation circuit (2), and a charge pump core circuit (3). The signal output terminal of the bias circuit (1) is connected to the signal input terminals of the compensation circuit (2) and the charge pump core circuit (3), and the signal output terminal of the compensation circuit (2) is connected to the signal input terminal of the charge pump core circuit (3). The bias circuit (1) provides a bias signal to the compensation circuit (2) and the charge pump core circuit (3). The compensation circuit (2) provides dynamic compensation current to the charge pump core circuit (3) through PMOS transistor M12, PMOS transistor M18, NMOS transistor M28, and NMOS transistor M30. The charge pump core circuit (3) provides charging / discharging current to the filter capacitor of the subsequent circuit through the output terminal Vctrl of the charge pump circuit. The compensation circuit (2) includes: PMOS transistors M2, M3, M4, M7, M8, M9, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, NMOS transistors M23, M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, and M35. The system includes NMOS transistors M36, M39, M40, M41, M45, M46, and M47, resistors R3 and R4. The source of PMOS transistor M13 is connected to the sources of PMOS transistors M2, M3, M11, M12, M16, M19, M17, M20, M21, and M4, as well as the external power supply VDD. The gate of PMOS transistor M13 is connected to its drain, the source of PMOS transistor M14, and the bias terminal Vcmn2. The gate of PMOS transistor M14 is connected to its bias terminal. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the gate of NMOS transistor M25, the source of NMOS transistor M23, the source of PMOS transistor M24, the output of amplifier OP2, and the inverting input of amplifier OP2. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M29, the gate of NMOS transistor M29, and the gate of NMOS transistor M28. The source of NMOS transistor M29 is connected to the source of NMOS transistor M28, the source of NMOS transistor M32, the source of NMOS transistor M31, the source of NMOS transistor M33, the source of NMOS transistor M35, and the inverting input of amplifier OP2. The sources of MOSFET M27, NMOS transistors M36, M45, M46, and M47, as well as external ground (GND), are connected. The drain of PMOS transistor M2 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 is connected to one end of resistor R3. The other end of resistor R3 is connected to the gate of NMOS transistor M30, the drain of NMOS transistor M31, and the gate of NMOS transistor M31. The source of NMOS transistor M30 is connected to the drain of NMOS transistor M32. The drain of PMOS transistor M3 is connected to the source of PMOS transistor M8. The drain of PMOS transistor M8 is connected to the source of NMOS transistor M32. The gate of transistor M2, the gate and drain of NMOS transistor M33, and the drain of NMOS transistor M34 are connected. The gate of NMOS transistor M34 is connected to the bias terminal DN. The source of NMOS transistor M34 is connected to the drain of NMOS transistor M35. The gate of NMOS transistor M35 is connected to the gate and drain of NMOS transistor M36, the drain of PMOS transistor M9, and the drain of NMOS transistor M23. The gate of PMOS transistor M11 is connected to the gate and drain of PMOS transistor M12, the drain of PMOS transistor M11, and the drain of NMOS transistor M25. The source of NMOS transistor M25 is connected to the drain of NMOS transistor M26. The gate of MOSFET M26 is connected to the bias terminal UP. The source of NMOS transistor M26 is connected to the drain of NMOS transistor M27, the gate of NMOS transistor M27, and the bias terminal Vcmp2. The drain of PMOS transistor M16 is connected to the source of PMOS transistor M18. The gate of PMOS transistor M18 is connected to the gate of PMOS transistor M19, the drain of PMOS transistor M19, and one end of resistor R4. The other end of resistor R4 is connected to the drain of NMOS transistor M39. The source of NMOS transistor M39 is connected to the drain of NMOS transistor M45. The drain of PMOS transistor M20 is connected to the source of PMOS transistor M22. The gate of PMOS transistor M22 is connected to the bias terminal UP. The drain of PMOS transistor M22 is connected to the gate of PMOS transistor M16, the gate of PMOS transistor M17, the drain of PMOS transistor M17, and the drain of NMOS transistor M40. The source of NMOS transistor M40 is connected to the drain of NMOS transistor M46. The drain of PMOS transistor M21 is connected to the gate of PMOS transistor M21, the gate of PMOS transistor M20, the drain of PMOS transistor M24, and the drain of NMOS transistor M41. The drain of PMOS transistor M4 is connected to the source of PMOS transistor M9. The source of NMOS transistor M41 is connected to the drain of NMOS transistor M47.

2. The charge pump circuit for an on-chip clock generation circuit according to claim 1, characterized in that, The bias circuit (1) includes: a current source Iref, PMOS transistors M1, M6, M37, M38, M43, and M44, resistors R1 and R2. One end of the current source Iref is connected to the source of PMOS transistor M1 and the external power supply VDD. The other end of the current source Iref is connected to one end of resistor R1, the gate of NMOS transistors M37, M38, M39, M40, M41, and M42. The other end of resistor R1 is connected to the drain of NMOS transistor M37, the gate of NMOS transistor M43, the gate of NMOS transistor M44, the gate of NMOS transistor M45, the gate of NMOS transistor M46, and the gate of NMOS transistor M44. The gate of transistor M47 is connected to the gate of NMOS transistor M48. The source of NMOS transistor M37 is connected to the drain of NMOS transistor M43. The source of NMOS transistor M43 is connected to the source of NMOS transistor M44 and external ground GND. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M6. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M6, one end of resistor R2, the gate of PMOS transistor M2, the gate of PMOS transistor M3, the gate of PMOS transistor M4, and the gate of PMOS transistor M5. The other end of resistor R2 is connected to the drain of NMOS transistor M38, the gate of PMOS transistor M6, the gate of PMOS transistor M7, the gate of PMOS transistor M8, the gate of PMOS transistor M9, and the gate of PMOS transistor M10. The source of NMOS transistor M38 is connected to the drain of NMOS transistor M44.

3. A charge pump circuit for an on-chip clock generation circuit according to claim 2, characterized in that, In the bias circuit (1), NMOS transistors M37 and M38 have the same channel width-to-length ratio, and NMOS transistors M44 and M43 have the same channel width-to-length ratio, so that PMOS transistors M1, M6, M37, M38, M43, M44 and current source Iref have the same current.

4. A charge pump circuit for an on-chip clock generation circuit according to claim 1, characterized in that, In the compensation circuit (2), PMOS transistors M2 and M1 have the same channel width-to-length ratio, PMOS transistors M7 and M6 have the same channel width-to-length ratio, PMOS transistors M3 and M4 have the same channel width-to-length ratio and are α times that of PMOS transistor M1, PMOS transistors M8 and M9 have the same channel width-to-length ratio and are α times that of PMOS transistor M6, NMOS transistors M45 and M43 have the same channel width-to-length ratio, NMOS transistors M39 and M37 have the same channel width-to-length ratio, NMOS transistors M46 and M47 have the same channel width-to-length ratio and are α times that of NMOS transistor M43, NMOS transistors M40 and M41 have the same channel width-to-length ratio and are α times that of NMOS transistor M37, and the bias terminal UP and bias terminal... With opposite signals, the bias terminal DN and the bias terminal With the opposite signal, amplifier OP2 forces the source voltage V of PMOS transistor M24. CP The voltage V at the output terminal Vctrl of the charge pump circuit ctrl equal.

5. A charge pump circuit for an on-chip clock generation circuit according to claim 1, characterized in that, In the compensation circuit (2), when the bias terminal UP is low and the bias terminal DN is high, NMOS transistor M34 and PMOS transistor M14 are turned on simultaneously, while NMOS transistor M26 and PMOS transistor M22 begin to turn off, and the charge pump circuit discharges. When the voltage Vctrl at the output terminal V of the charge pump circuit... ctrl When the current drops to a certain value, PMOS transistor M24 turns off, and the current of NMOS transistor M23 flows into amplifier OP2. NMOS transistors M35 and M36 have the same channel width-to-length ratio, and NMOS transistors M32 and M33 have the same channel width-to-length ratio. The current I of NMOS transistor M30... 30 The current I of NMOS transistor M23 23 There is I 30 =I 23 = , where μ n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 23 V is the channel width-to-length ratio of NMOS transistor M23. cmn1 The voltage at the bias terminal Vcmn1, V CP V is the source voltage of PMOS transistor M24. THn This is the threshold voltage of the NMOS transistor; the PMOS transistor M14, with a large channel width-to-length ratio, operates in the deep transistor region and its source voltage is approximately equal to the voltage V at the bias terminal Vcmn2. cmn2 NMOS transistors M29 and M28 have the same channel width-to-length ratio. The current I of NMOS transistor M28 is... 28 ≈ , where μ p Hole mobility, (W / L) 15 V is the channel width-to-length ratio of PMOS transistor M15. THp This is the threshold voltage of the PMOS transistor.

6. A charge pump circuit for an on-chip clock generation circuit according to claim 4, characterized in that, In the compensation circuit (2), when the bias terminal UP is high and the bias terminal DN is low, NMOS transistor M34 and PMOS transistor M14 are simultaneously turned off, and NMOS transistor M26 and PMOS transistor M22 are turned on, charging the charge pump circuit. When the voltage Vctrl at the output terminal V of the charge pump circuit... ctrl When the current rises to a certain value, NMOS transistor M23 turns off, and the current of PMOS transistor M24 flows into amplifier OP2. PMOS transistors M20 and M21 have the same channel width-to-length ratio, and PMOS transistors M16 and M17 have the same channel width-to-length ratio. The current I of PMOS transistor M18... 18 The current I of PMOS transistor M24 24 There is I 18 =I 24 = , where μ p C represents hole mobility. ox The capacitance of the gate oxide layer per unit area (W / L) 24 V is the channel width-to-length ratio of PMOS transistor M24. CP V is the source voltage of PMOS transistor M24. cmp1 The voltage at the bias terminal Vcmp1, V THp This is the threshold voltage of the PMOS transistor; the NMOS transistor M26, with a large channel width-to-length ratio, operates in the deep transistor region and its source voltage is approximately equal to the voltage V at the bias terminal Vcmp2. cmp2 PMOS transistors M11 and M12 have the same channel width-to-length ratio. The current I of PMOS transistor M12 is... 12 ≈ , where μ n Electron mobility, (W / L) 25 V is the channel width-to-length ratio of PMOS transistor M25. THn This is the threshold voltage of the NMOS transistor.

7. A charge pump circuit for an on-chip clock generation circuit according to claim 1, characterized in that, The charge pump core circuit (3) includes: PMOS transistors M5, M10, M42, M48, M49, M50, M51, M52, M53, M54, M55, M56, M57, and M58; amplifiers OP1 and OP2; resistors R5 and R6. The source of PMOS transistor M5 is connected to the sources of PMOS transistors M49, M50, and M51, as well as the external power supply VDD. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M10. The drain of PMOS transistor M10 is connected to one end of resistor R5. The other end of resistor R5 is connected to the drain of NMOS transistor M56, the gate of NMOS transistor M56, the drain of NMOS transistor M57, and NMOS transistor M51. The gate of NMOS transistor M8 is connected to the source of NMOS transistor M56, which is connected to the source of NMOS transistor M48, the source of NMOS transistor M57, the source of NMOS transistor M58, and external ground GND. The gate of PMOS transistor M49 is connected to the drain of PMOS transistor M50, the gate of PMOS transistor M51, the drain of PMOS transistor M49, and one end of resistor R6. The other end of resistor R6 is connected to the drain of NMOS transistor M42. The source of NMOS transistor M42 is connected to the gate of NMOS transistor M48. The drain of OS transistor M48 is connected to the drain of PMOS transistor M51, which is connected to the drain of PMOS transistor M12, the drain of PMOS transistor M18, the source of PMOS transistor M52, and the source of PMOS transistor M53. The gate of PMOS transistor M52 is connected to the bias terminal UP. The drain of PMOS transistor M52 is connected to the output terminal of amplifier OP1, the inverting input terminal of amplifier OP1, and the drain of NMOS transistor M54. The gate of NMOS transistor M54 is connected to the bias terminal UP. Connected, the gate and bias terminal of PMOS transistor M53 The drain of PMOS transistor M53 is connected to the non-inverting input of amplifier OP1, the non-inverting input of amplifier OP2, the drain of NMOS transistor M55, the gate of PMOS transistor M50, the gate of NMOS transistor M57, and the output terminal Vctrl. The gate of NMOS transistor M55 is connected to the bias terminal DN. The source of NMOS transistor M55 is connected to the source of NMOS transistor M54, the drain of NMOS transistor M28, the drain of NMOS transistor M30, and the drain of NMOS transistor M58.

8. A charge pump circuit for an on-chip clock generation circuit according to claim 7, characterized in that, In the core circuit (3) of the charge pump, PMOS transistors M5 and M11 have the same channel width-to-length ratio, PMOS transistors M10 and M6 have the same channel width-to-length ratio, NMOS transistors M42 and M37 have the same channel width-to-length ratio, NMOS transistors M48 and M43 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS transistor M51 is α times that of PMOS transistor M49, and the channel width-to-length ratio of NMOS transistor M58 is α times that of NMOS transistor M56. When the bias terminal UP is low and the bias terminal DN is high, the charge pump circuit discharges, and the voltage V at the circuit output terminal Vctrl is... ctrl To reduce the current reduction in NMOS transistor M58 caused by the channel modulation effect, a technique is employed to replicate a portion of the current flowing through NMOS transistor M56. This technique aims to mitigate the current reduction in NMOS transistor M58 due to the channel modulation effect. The discharge current I of the charge pump circuit is also affected. DN That is, the current flowing through the NMOS transistor M55 is I DN = , where I ref μ is the current of the current source Iref. n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 57 V is the channel width-to-length ratio of the NMOS transistor M57. THn ΔI is the threshold voltage of the NMOS transistor. 58 The current deviation of the NMOS transistor M58 caused by the channel modulation effect, I 30 I is the current of NMOS transistor M30. 28 The current I is the current of the NMOS transistor M28. 30 and current I 28 Dynamic compensation is applied to the discharge current of the charge pump; when the bias terminal UP is high and the bias terminal DN is low, the charge pump circuit charges, and the voltage V... ctrl The current rises because the channel modulation effect reduces the saturation current of PMOS transistor M51. To suppress this current drop caused by the channel modulation effect, a technique is used to replicate a portion of the current flowing through PMOS transistor M49. The charging current I of the charge pump circuit... UP That is, the current flowing through PMOS transistor M50 is I UP = , where μ p Hole mobility, (W / L) 50 V is the channel width-to-length ratio of the PMOS transistor M50. DD The voltage ΔI is the external power supply VDD. 51 The current deviation of PMOS transistor M51 caused by channel modulation effect, I 12 I is the current of PMOS transistor M12. 18 V is the current of PMOS transistor M18. THp The threshold voltage of the PMOS transistor is given by I. 12 and current I 18 Dynamic compensation is applied to the charging current of the charge pump to improve the matching range of the charging current.

Images