MOSFET device and method of making the same
By configuring the SiGe source region in the MOSFET device and controlling the gradient distribution of Ge content, the problem of easy breakdown in SiC MOSFET devices when improving channel mobility is solved, achieving a balance between high mobility and breakdown resistance, and improving the stability and performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2024-12-13
- Publication Date
- 2026-06-23
AI Technical Summary
While improving channel mobility, existing SiC MOSFET devices are prone to breakdown, leading to device failure.
By configuring SiGe material as the source region in a MOSFET device and gradually increasing its Ge content along the direction from the substrate to the epitaxial layer, the relaxation of SiGe is released during the annealing process, which is greater than that of SiC. This generates compressive strain in the channel region, reduces the effective mass and scattering probability of charge carriers, improves the channel mobility, and reduces the on-resistance.
While improving channel mobility, it effectively prevents device breakdown, ensures device lattice compatibility and epitaxial performance, and simplifies the process flow.
Smart Images
Figure CN122269772A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a MOSFET device and a method for fabricating the same. Background Technology
[0002] With the development of high-power SiC MOSFET devices, increasing attention has been paid to energy loss during device operation. Currently, many methods have been adopted, such as reducing channel width and drift layer thickness, to improve channel mobility. However, this also results in devices being more prone to breakdown and failure. Therefore, how to improve channel mobility while ensuring the device is less susceptible to breakdown has become a pressing technical problem. Summary of the Invention
[0003] To address some or all of the aforementioned problems, this disclosure provides a MOSFET device and its fabrication method, which can improve channel mobility while ensuring that the device is not easily broken down.
[0004] According to a first aspect of this disclosure, a MOSFET device is provided, comprising: at least one cell unit, the cell unit comprising: a substrate; an epitaxial layer disposed on the substrate, the substrate and the epitaxial layer having a first conductivity type; two spaced-apart body regions disposed within the epitaxial layer and extending from the side of the epitaxial layer away from the substrate toward the substrate side, the body regions having a second conductivity type, and the substrate, the epitaxial layer and the body regions being made of SiC; and two source regions respectively disposed within the two body regions and extending from the side of the epitaxial layer away from the substrate toward the substrate side, the source regions having a first conductivity type, and the source regions being made of SiC. (1-x) Ge x And Si in at least a portion of the source region (1-x) Ge x In the figure, x increases along the direction from the substrate to the epitaxial layer; the gate electrode is disposed on the epitaxial layer and extends from the two adjacent body regions to the two source regions respectively; the source electrode is disposed on the epitaxial layer and the gate electrode.
[0005] According to a second aspect of this disclosure, a MOSFET device is provided, comprising: a substrate; an epitaxial layer disposed on the substrate, the substrate and the epitaxial layer having a first conductivity type; a plurality of body regions disposed at intervals within the epitaxial layer and extending from the side of the epitaxial layer away from the substrate toward the substrate side, the body regions having a second conductivity type, the substrate, the epitaxial layer and the body regions being made of SiC; each body region further comprising two source regions disposed at intervals, the source regions extending from the side of the epitaxial layer away from the substrate toward the substrate side, the source regions having a first conductivity type, and the source regions being made of SiC. (1-x) Ge x And the park, and at least a portion of the source region contains Si(1-x) Ge x The value of x increases along the direction from the substrate to the epitaxial layer.
[0006] A gate electrode is disposed on the epitaxial layer and covers the epitaxial layer between two adjacent body regions and extends to cover a portion of two adjacent source regions that are close to each other.
[0007] The source electrode is disposed on the epitaxial layer and the gate electrode.
[0008] According to a third aspect of this disclosure, a method for fabricating a MOSFET device is provided, comprising: providing a substrate; fabricating an epitaxial layer on the substrate, the epitaxial layer and the substrate having a first conductivity type; implanting to form a plurality of body regions on a side of the epitaxial layer away from the substrate, the body regions having a second conductivity type, and the substrate, the epitaxial layer and the body regions being made of SiC; etching each body region to form two spaced-apart source region trenches; epitaxially growing a source region inside and outside the source region trenches to form a SiGe material layer of the first conductivity type to form a first device, wherein at least a portion of the Ge content in the SiGe material layer increases along the direction from the substrate to the epitaxial layer; annealing the first device to form the source region from the SiGe material layer; fabricating a gate electrode on the epitaxial layer, the gate electrode covering the epitaxial layer and extending to cover a portion of the body region and extending to cover the nearest portion of the source region; the body region below the gate electrode being configured as a channel region, the crystal compressive stress in the channel region being greater than the crystal compressive stress in the epitaxial layer; and fabricating a source electrode on the epitaxial layer and the gate electrode.
[0009] In the MOSFET device and fabrication method provided in the embodiments of this disclosure, the source region is configured as SiGe material, and the Ge in at least a portion of the source region increases along the direction from the substrate to the epitaxial layer. Since the lattice constant of SiGe is larger than that of SiC, and the gradient SiGe is located next to the channel region, relaxation will occur in the SiGe source region. After retreating, the relaxation will be released, thereby causing compressive strain in the channel region. The channel region with compressive strain can reduce the effective mass of carriers and the scattering probability at the same time, thereby improving the mobility of inverted laminar carriers and reducing the on-resistance at the same time. This achieves the technical effect of improving the channel mobility of the device while ensuring that the device is not easily broken down. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:
[0011] Figure 1 This is a schematic diagram of the structure of a MOSFET device provided in some embodiments of this disclosure;
[0012] Figure 2 This is a schematic diagram illustrating a scenario of a MOSFET device provided in some embodiments of this disclosure;
[0013] Figure 3 This is a schematic diagram illustrating the changing trend of the Ge content percentage in the source region of a MOSFET device provided in some embodiments of this disclosure;
[0014] Figure 4 This is a schematic diagram illustrating another trend in the percentage of Ge content in the source region of a MOSFET device provided in some embodiments of this disclosure;
[0015] Figure 5 This is a schematic diagram of the internal structure of the source region of a MOSFET device provided in some embodiments of this disclosure;
[0016] Figure 6 This is a schematic diagram of another internal structure of the source region of a MOSFET device provided in some embodiments of this disclosure;
[0017] Figure 7 This is another schematic diagram of the structure of a MOSFET device provided in some embodiments of the present disclosure;
[0018] Figure 8 This is yet another structural schematic diagram of a MOSFET device provided in some embodiments of this disclosure;
[0019] Figure 9 A flowchart illustrating a method for fabricating a MOSFET device according to some embodiments of this disclosure;
[0020] Figures 10a-10j This is a schematic diagram illustrating structural changes in the process flow of a MOSFET device provided in some embodiments of this disclosure. Detailed Implementation
[0021] The present disclosure will now be further explained in conjunction with the accompanying drawings.
[0022] In the description of this application, "growth" refers to "epitaxygrowth," that is, growing a layer structure with certain requirements on a material to be treated. Techniques involving "growth" may include metal-organic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc. Those skilled in the art can select an appropriate epitaxial growth technique based on the specific circumstances.
[0023] In the description of this application, "etching" should be understood in a broad sense, that is, growing a layer of photoresist on the surface of the material to be processed, selectively exposing and developing the photoresist through a mask to leave a photoresist layer on the surface of the material to be processed that is the same as the mask pattern, then selectively etching the material to be processed by chemical or physical methods, and finally peeling off the photoresist layer to form a structure on the material to be processed that corresponds to the mask pattern.
[0024] In the description of this application, the orientation or positional relationship indicated by terms such as "upper" or "lower" is based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this disclosure and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0025] In the description of this application, except for Embodiment 1, the other embodiments are written in a manner that avoids repetition as much as possible, that is, focusing on the differences between each embodiment and other embodiments. In these embodiments, any technical features that are not explicitly described can be referred to the corresponding description in Embodiment 1.
[0026] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0027] This disclosure provides an embodiment of a MOSFET device. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the structure of a MOSFET device provided in some embodiments of this disclosure, such as... Figure 1 As shown, the MOSFET device 10 includes:
[0028] Substrate 101;
[0029] An epitaxial layer 102 is disposed on a substrate 101, and the substrate 101 and the epitaxial layer 102 have a first conductivity type.
[0030] Two spaced-apart body regions 103 are disposed within the epitaxial layer 102 and extend from the side of the epitaxial layer 102 away from the substrate 101 toward the substrate 101. The body regions 103 have a second conductivity type, and the materials of the substrate 101, the epitaxial layer 102 and the body regions 103 are all SiC.
[0031] Two source regions 104 are respectively disposed within two body regions 103 and extend along the side of the epitaxial layer 102 away from the substrate 101 toward the substrate 101. The source regions 104 have a first conductivity type, and the material of the source regions 104 is Si. (1-x) Ge x And Si in at least a portion of the source region 104 (1-x) Ge x The value of x increases along the direction from substrate 101 to epitaxial layer 102.
[0032] A gate electrode 105 is disposed on the epitaxial layer 102 and extends from two adjacent body regions 103 to two source regions 104 respectively; the body region 103 below the gate electrode 105 is configured as a channel region 1031, and the crystal compressive stress in the channel region 1031 is greater than the crystal compressive stress in the epitaxial layer 102.
[0033] The source electrode 105 is disposed on the epitaxial layer 102 and the gate electrode 105.
[0034] Here, the substrate 101, epitaxial layer 102, and body region 103 are all made of SiC. Exemplarily, the substrate 101, epitaxial layer 102, and body region 103 can be made of 4H-SiC. It is known that 4H-SiC has advantages such as wide bandgap, high breakdown electric field strength, high thermal conductivity, and high electron mobility, making it an ideal semiconductor material for high-power metal-oxide-semiconductor field-effect transistors (MOSFETs). However, due to the high interface state density between 4H-SiC and SiO2, the 4H-SiC MOSFET has low channel mobility and high on-resistance.
[0035] Of course, the materials of substrate 101, epitaxial layer 102 and body region 103 can all be 4H-SiC, or one of them can be 4H-SiC. In other embodiments, the materials of substrate 101, epitaxial layer 102 and body region 103 can also be other crystal forms of SiC, and no limitation is made here.
[0036] Here, source region 104 is formed by epitaxial growth, and the epitaxial growth material is SiGe, not SiC.
[0037] Here, the gate electrode 105 can be a planar gate electrode or a trench gate electrode. The gate electrode 105 includes: a gate oxide layer disposed on the epitaxial layer, polysilicon disposed on the gate oxide layer, and an interlayer dielectric layer disposed between the polysilicon and the source electrode. It should be noted that the gate electrode here is a conventional gate electrode, which will not be described in detail here.
[0038] Here, the first conductivity type can be N-type and the second conductivity type can be P-type; of course, in other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.
[0039] It should be noted that P-type SiC material usually refers to SiC material layer doped with P-type ions, which can be Al or B ions. N-type SiC material usually refers to SiC material doped with N-type ions; generally, an excess of Si atoms in SiC will form N-type SiC.
[0040] It should be noted that if N-type conductivity is required in SiGe materials, the process is similar to that in SiC materials, and will not be elaborated further here.
[0041] It is understandable that, taking 4H-SiC as the material for substrate 101, epitaxial layer 102, and body region 103, the electrical performance of the 4H-SiC MOSFET will change under mechanical strain. Since SiGe has a large lattice constant, placing SiGe material next to the channel region 1031, i.e., as the source region 104, will cause relaxation within the SiGe material. This relaxation can be released during annealing, resulting in uniaxial compressive strain in the channel region 1031. This uniaxial compressive strain will simultaneously reduce the effective mass and scattering probability of the carriers in the channel region 1031, thereby improving the carrier mobility of the inversion layer and reducing the on-resistance of the channel region 1031. In this way, the embodiments of this disclosure improve the on-resistance of the device without causing a decrease in breakdown voltage.
[0042] For example, please refer to Figure 2 ,like Figure 2As shown, the left figure shows the structure of SiGe and SiC crystals under stress relaxation, and the right figure shows the structure of SiGe and SiC crystals under stress release. It can be seen from the figures that after stress release, the SiC crystal compressive stress in the SiC material region connected to the SiGe material region is relatively large, and the distance between atoms becomes smaller. In other words, by configuring the source region as SiGe material, the compressive stress of the SiC crystal in the channel region near the source region can be increased after stress release, thus reducing the distance between SiC atoms in the channel region near the source region. This reduces both the effective mass of charge carriers and the scattering probability in the channel region, improving the carrier mobility in the inversion layer and reducing the on-resistance. Therefore, it can improve the channel mobility of the MOSFET device while ensuring that the device is not easily broken down.
[0043] In some embodiments, the material of the source region 104 may be Si. (1-x) Ge x And Si in at least a portion of the source region (1-x) Ge x The value of x increases along the direction from the substrate to the epitaxial layer, including the fact that the material of the source region 104 can be Si. (1-x) Ge x , where x increases along the direction away from body region 103.
[0044] It should be noted that the lower the Ge content, the smaller the SiGe lattice fit and thermal expansion fit at the SiC interface, which can prevent film peeling during annealing. Therefore, the Ge content in SiGe materials that are closer to SiC should be designed to be lower, thereby ensuring higher lattice fit of the device.
[0045] Therefore, in this embodiment, by designing x to increase along the direction away from the body region 103, it is possible to ensure that the channel mobility of the MOSFET device is improved while ensuring that the device is not easily broken down. At the same time, it is also possible to ensure the lattice compatibility of the MOSFET device, thereby ensuring the epitaxial performance of the MOSFET device.
[0046] In other embodiments, the material of the source region 104 may be Si. (1-x) Ge x And Si in at least a portion of the source region (1-x) Ge x The value of x increases along the direction from the substrate to the epitaxial layer, including: the material of the source region 104 can be Si. (1-x) Ge x , where x increases along the direction from substrate 101 to epitaxial layer 102.
[0047] It should be noted that since epitaxial growth is usually done in whole layers, in order to simplify the process while ensuring a certain degree of lattice compatibility, x is designed to increase along the direction from the substrate 101 to the epitaxial layer 102. This can ensure that the channel mobility of the MOSFET device is improved while ensuring that the device is not easily broken down, and at the same time, the lattice compatibility of the MOSFET device is ensured, thereby ensuring the epitaxial performance of the MOSFET device and further simplifying the process.
[0048] In some embodiments, x gradually increases along the direction from the substrate to the epitaxial layer. For example, see [link to example]. Figure 3 , Figure 3 This is a schematic diagram illustrating the changing trend of the Ge content percentage in the source region of a MOSFET device provided in some embodiments of this disclosure, such as... Figure 3 As shown, the Ge content percentage changes with the growth of the source region. It can be seen that the Ge content percentage increases with the growth of the source region. This indicates that the growth direction of the source region is from the substrate to the epitaxial layer. Through this embodiment, the channel mobility of the MOSFET device can be improved while ensuring that the device is not easily broken down. At the same time, the lattice compatibility of the MOSFET device can be ensured, thereby guaranteeing the epitaxial performance of the MOSFET device.
[0049] It should be noted that the curvature of the curve showing the change in Ge content as a percentage of the source region is not limited, as long as it gradually increases.
[0050] In other embodiments, x increases in steps along the direction of the epitaxial layer of the substrate. For example, see [link to example]. Figure 4 , Figure 4 This is a schematic diagram illustrating another trend in the percentage of Ge content in the source region of a MOSFET device provided in some embodiments of this disclosure, as shown below. Figure 4 As shown, the Ge content percentage changes with the growth of the source region. It can be seen that the Ge content percentage increases stepwise with the growth of the source region. This indicates that the growth direction of the source region is from the substrate to the epitaxial layer. This embodiment ensures improved channel mobility of the MOSFET device while preventing breakdown, and also guarantees the lattice compatibility of the MOSFET device, thereby ensuring its epitaxial performance.
[0051] It should be noted that there is no limit to the number of steps in the Ge content percentage, nor is there a limit to the step period.
[0052] In some embodiments, the MOSFET device further includes a drain electrode disposed on the side of the substrate 101 away from the epitaxial layer 102.
[0053] In some embodiments, the Ge content percentage increases by 0.2% for every 50 nm increase in thickness.
[0054] In some embodiments, x takes the value [0.2-0.8].
[0055] In some embodiments, the source region is configured as a multilayer substructure, wherein each substructure is stacked along the direction from the substrate to the epitaxial layer; the proportion of Ge content in the multiple substructures increases sequentially along the direction from the substrate to the epitaxial layer.
[0056] It should be noted that the Ge content in each substructure can be uniformly distributed along the direction from the substrate to the epitaxial layer, or it can gradually increase along the direction from the substrate to the epitaxial layer. The Ge content percentage of a single substructure refers to the average Ge content percentage of the entire substructure.
[0057] It should be noted that the Ge content in each substructure gradually increases along the direction from the substrate to the epitaxial layer, which can further ensure lattice matching, reduce epitaxial lattice adaptation problems, and improve device stability.
[0058] For example, please refer to Figure 5 , Figure 5 This is a schematic diagram of the internal structure of the source region of a MOSFET device provided in some embodiments of this disclosure, such as... Figure 5 As shown, the source region 104 may include a first substructure 1041, a second substructure 1042 disposed on the first substructure 104, a third substructure 1043 disposed on the second substructure 1042, and a fourth substructure 1044 disposed on the third substructure 1043. In some embodiments, the Ge content percentage of the first substructure 1041 may be 0.2, the Ge content percentage of the second substructure 1042 may be 0.4, the Ge content percentage of the third substructure 1043 may be 0.6, and the Ge content percentage of the fourth substructure 1044 may be 0.8.
[0059] To further ensure lattice matching between SiC and SiGe materials, reduce lattice compatibility issues between epitaxial layers, and improve device stability, in some embodiments, the source region is configured as multiple sub-regions, each sub-region being symmetrically arranged about the central axis of the source region, and adjacent sub-regions having a nested and nested relationship; the Ge content in the multiple sub-regions increases sequentially from outside the source region to inside the source region.
[0060] It should be noted that the Ge content in each sub-region can be uniformly distributed along the direction from outside the source region to inside the source region, or it can gradually increase along the direction from outside the source region to inside the source region. The Ge content percentage of a single sub-region refers to the average Ge content percentage of the entire sub-region.
[0061] It should be noted that the Ge content in each sub-region gradually increases from outside the source region to inside the source region, which can further ensure lattice matching, reduce epitaxial lattice adaptation problems, and improve device stability.
[0062] For example, please refer to Figure 6 , Figure 6 This is a schematic diagram of another internal structure of the source region of a MOSFET device provided in some embodiments of this disclosure, such as... Figure 6 As shown, the source region 104 may include a first sub-region 1045, a second sub-region 1046 nested within the first sub-region 1045, a third sub-region 1047 nested within the second sub-region 1046, and a fourth sub-region 1408 nested within the third sub-region 1047.
[0063] In some embodiments, the Ge content ratio of the first sub-region 1041 can be 0.2, the Ge content ratio of the second sub-region 1042 can be 0.4, the Ge content ratio of the third sub-region 1403 can be 0.6, and the Ge content ratio of the fourth sub-region 1044 can be 0.8.
[0064] This disclosure also provides a MOSFET device; please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is another schematic diagram of the structure of a MOSFET device provided in some embodiments of this disclosure, such as... Figure 7 As shown, the MOSFET device includes:
[0065] Substrate 101;
[0066] Epitaxial layer 102. Disposed on substrate 101, wherein substrate 101 and epitaxial layer 103 have a first conductivity type;
[0067] Multiple body regions 103 are spaced apart within the epitaxial layer 102 and extend from the side of the epitaxial layer 102 away from the substrate 101 toward the substrate 101. The body regions 103 have a second conductivity type. The substrate 101, the epitaxial layer 102 and the body regions 103 are all made of SiC.
[0068] Each body region 103 is further provided with two source regions 104 at intervals. The source regions 104 extend from the side of the epitaxial layer 102 away from the substrate 101 toward the substrate side. The source regions 102 have a first conductivity type, and the material of the source regions 102 is Si. (1-x) Ge x And Si in at least a portion of the source region 102 (1-x) Ge x The value of x increases along the direction from substrate 101 to epitaxial layer 102.
[0069] A gate electrode 105 is disposed on the epitaxial layer 101 and covers the epitaxial layer 102 between two adjacent body regions 103 and extends to cover a portion of two source regions 104 that are close to each other within the two adjacent body regions 103; the body region 103 below the gate electrode 105 is configured as a channel region 1031, and the crystal compressive stress in the channel region 1031 is greater than the crystal compressive stress in the epitaxial layer 102.
[0070] The source electrode 106 is disposed on the epitaxial layer 102 and the gate electrode 105.
[0071] It is understood that a MOSFET device is composed of multiple cell structures, with the cells spaced apart to form a fully functional MOSFET device. In this embodiment, the integration of multiple cell structures is described.
[0072] In some embodiments, x increases gradually along the direction from the substrate to the epitaxial layer, or x increases stepwise along the direction from the substrate to the epitaxial layer.
[0073] In other embodiments, the source region is configured as a multilayer substructure, with each substructure stacked along the direction from the substrate to the epitaxial layer.
[0074] The Ge content in the multiple substructures increases sequentially from the substrate to the epitaxial layer.
[0075] In other embodiments, the source region is configured as multiple sub-regions, each sub-region being symmetrical about the central axis of the source region, and adjacent sub-regions having a nested and nested relationship.
[0076] The Ge content in multiple sub-regions increases sequentially from outside the source region to inside the source region.
[0077] It should be noted that the MOSFET device in this embodiment has the same technical effects as the MOSFET device with the single cell structure described above, and will not be repeated here.
[0078] It should be noted that, in some embodiments, please refer to Figure 8 , Figure 8 This is yet another schematic diagram of a MOSFET device provided in some embodiments of the present disclosure, such as... Figure 8 As shown, the MOSFET device also includes a body region contact region 107 disposed within the body region 103 and between the two source regions 104 of the same body region 103, the body region contact region 107 having a second conductivity type. The provision of the body region contact region improves the breakdown voltage of the device's body diode and enhances the device's reliability.
[0079] Another aspect of this application provides a method for fabricating a MOSFET, please refer to... Figure 9As shown in Figure 10, the fabrication method of this MOSFET device includes:
[0080] Step 91: Provide a substrate 101.
[0081] For example, such as Figure 10a The substrate 101 can be a silicon substrate or a silicon carbide substrate; in this embodiment, the substrate 101 is a SiC substrate. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application.
[0082] Step 92: An epitaxial layer 102 is prepared on the substrate 101, the epitaxial layer 102 having a first conductivity type with the substrate 101.
[0083] It should be noted that the first conductivity type can be either N-type or P-type.
[0084] For example, such as Figure 10a After cleaning and polishing the N-type SiC substrate, an N-type SiC epitaxial layer 2 with a thickness of 1-100 μm and a concentration of 1E14–5E16 cm⁻¹ is grown on substrate 101 using MOCVD (Metal-organic Chemical Vapor Deposition). -3 And then polish and grind.
[0085] Step 93: A body region 103 is formed by implantation on the side of the epitaxial layer 102 away from the substrate 101. The body region 103 has a second conductivity type, and the materials of the substrate 101, the epitaxial layer 102 and the body region 103 are all SiC.
[0086] It should be noted that when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type. Here, we take an example where the first conductivity type is N-type and the second conductivity type is P-type.
[0087] For example, such as Figure 10b Step 93, implanting a body region 103 on the side of the epitaxial layer 102 away from the substrate 101, may include: depositing a first thin film barrier layer 901 on the SiC epitaxial layer, spin-coating a first photoresist 902 on the device region and performing a photolithography process to form an opening of 10-100 μm, and then performing P-type ion implantation to obtain a P-type doped region, which is the body region 103. Here, the P-type ions can be Al or B ions.
[0088] Step 94: Etch each volume region to form two source region trenches arranged at intervals.
[0089] For example, such as Figure 10cThe first photoresist 902 is removed using a dry or wet method, and a second thin film barrier layer 903 is deposited on the epitaxial layer with the P-type doped region already prepared. A second photoresist 904 is spin-coated on the P-type doped region and photolithography is performed to form an opening of 4-40 μm. Then, the SiGe growth region, i.e. the source region trench 900, is etched out using a dry or wet method.
[0090] Step 95: An epitaxial growth of a SiGe material layer of a first conductivity type is formed in the source region trench 900 to form a first device, wherein at least a portion of the Ge content in the SiGe material layer increases along the direction from the substrate 101 to the epitaxial layer 102.
[0091] For example, such as Figure 10d After the SiGe growth region is prepared, i.e., after the source trench 900 is prepared, the second photoresist 904 is removed, and Si with a compositional gradient is formed at the opening, i.e., within the source trench 900. (1-x) Ge x Material growth yields a SiGe material layer 905. Here, at least a portion of the Ge content in the SiGe material layer extends from the substrate 101 to the epitaxial layer 102.
[0092] In some embodiments, Si (1-x) Ge x In the material layer, x tends to increase along the direction away from the body region 103.
[0093] It should be noted that the lower the Ge content, the smaller the SiGe lattice fit and thermal expansion fit at the SiC interface, which can prevent film peeling during annealing. Therefore, the Ge content in SiGe materials that are closer to SiC should be designed to be lower, thereby ensuring higher lattice fit of the device.
[0094] Therefore, in this embodiment, by designing x to increase along the direction away from the body region 103, it is possible to ensure that the channel mobility of the MOSFET device is improved while ensuring that the device is not easily broken down. At the same time, it is also possible to ensure the lattice compatibility of the MOSFET device, thereby ensuring the epitaxial performance of the MOSFET device.
[0095] In other embodiments, Si (1-x) Ge x In the material layer, x tends to increase along the direction from substrate 101 to epitaxial layer 102.
[0096] It should be noted that since epitaxial growth is usually done in whole layers, in order to simplify the process while ensuring a certain degree of lattice compatibility, x is designed to increase along the direction from the substrate 101 to the epitaxial layer 102. This can ensure that the channel mobility of the MOSFET device is improved while ensuring that the device is not easily broken down, and at the same time, the lattice compatibility of the MOSFET device is ensured, thereby ensuring the epitaxial performance of the MOSFET device and further simplifying the process.
[0097] In one specific embodiment, please refer to Figure 905 again. The SiGe material layer 905 includes four film layers with different Ge contents, and the Ge contents are respectively x = 0.2, x = 0.4, x = 0.6 and x = 0.8.
[0098] For example, with Figure 5 For example, the Ge content of the first substructure 1041 is 0.2%, the Ge content of the second substructure 1042 is 0.4%, the Ge content of the third substructure 1043 is 0.6%, and the Ge content of the fourth substructure 1044 is 0.8%. Figure 6 For example, the Ge content in the first sub-region 1045 is 0.2%, the Ge content in the second sub-region 1046 is 0.4%, the Ge content in the third sub-region 1047 is 0.6%, and the Ge content in the fourth sub-region 1048 is 0.8%.
[0099] Step 96: As Figure 10e The first device is annealed to form the source region 103 of the SiGe material layer.
[0100] Step 97, as follows Figure 10h and Figure 10i A gate electrode 105 is fabricated on the epitaxial layer 102. The gate electrode 105 covers the epitaxial layer 102 and extends to cover a portion of the body region 103 and extends to cover the nearest portion of the source region 104. The body region 103 below the gate electrode 105 is configured as a channel region 1031, and the crystal compressive stress in the channel region 1031 is greater than the crystal compressive stress in the epitaxial layer 102.
[0101] For example, such as Figure 10f After the SiGe material layer is prepared by N-type heavy doping, the first thin film layer 901 and the second thin film layer 903 are removed, and the first device is annealed. At this time, the relaxed SiGe material layer 905 will release internal stress, expand the lattice, and become the source region 104 with lattice expansion, and generate compressive stress on the channel region 1031. Compressive strain will be generated inside the channel region 1031. At this time, the SiC channel region with strain is completed.
[0102] For example, the preparation of an N-type heavily doped SiGe material layer includes: implanting N-type ions into the SiGe material layer. N-type ions may include N ions or P ions, etc.
[0103] In some embodiments, annealing the first device includes annealing the first device at an annealing temperature of 500-900°C for 30-60 minutes. This releases the internal stress of the SiGe material layer, causing lattice expansion, which in turn leads to lattice compression in the channel region, increasing stress and thus improving the channel mobility and reducing the channel resistance.
[0104] Step 98: As Figure 10j A source electrode 106 is fabricated on the epitaxial layer 102 and the gate electrode 105.
[0105] It should be added that, in some embodiments, please further combine Figure 10g The method further includes:
[0106] In step 96, after annealing the first device, ion implantation of a second conductivity type is performed between the two source regions 104, for example, p-type heavily doped ion implantation, thereby forming a bulk contact region 107. Then, step 97 is performed, in which a gate electrode 105 is fabricated on the epitaxial layer 102, and step 98 is performed, in which a source electrode 106 is fabricated on the epitaxial layer 102 and the gate electrode 105.
[0107] The above description is merely a preferred embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily make changes or variations within the technical scope disclosed in this disclosure, and such changes or variations should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. As long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. This disclosure is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A MOSFET device, comprising: At least one cellular structure, the cellular structure comprising: Substrate; An epitaxial layer is disposed on the substrate, wherein the substrate and the epitaxial layer have a first conductivity type; Two spaced-apart body regions are disposed within the epitaxial layer and extend from the side of the epitaxial layer away from the substrate toward the substrate side. The body regions have a second conductivity type, and the substrate, the epitaxial layer, and the body regions are all made of SiC. Two source regions are respectively disposed within the two body regions and extend along the side of the epitaxial layer away from the substrate toward the substrate side. The source regions have a first conductivity type, and the material of the source regions is Si. (1-x) Ge x And Si in at least a portion of the source region (1-x) Ge x The value of x increases along the direction from the substrate to the epitaxial layer. A gate electrode is disposed on the epitaxial layer and extends from between two adjacent body regions toward the two source regions respectively; the body region below the gate electrode is configured as a channel region, and the crystal compressive stress in the channel region is greater than the crystal compressive stress in the epitaxial layer; The source electrode is disposed on the epitaxial layer and the gate electrode.
2. The device according to claim 1, characterized in that, The x increases gradually along the direction from the substrate to the epitaxial layer, or the x increases in a stepwise manner along the direction from the substrate to the epitaxial layer.
3. The device according to claim 1, characterized in that, The source region is configured as a multilayer substructure, with each substructure stacked along the direction from the substrate to the epitaxial layer. The proportion of Ge content in the plurality of substructures increases sequentially along the direction from the substrate to the epitaxial layer.
4. The device according to claim 1, characterized in that, The source region is configured into multiple sub-regions, each sub-region being symmetrically arranged about the central axis of the source region, and adjacent sub-regions having a nested and nested relationship. The Ge content in the plurality of sub-regions increases sequentially from outside the source region to inside the source region.
5. A MOSFET device, comprising: Substrate; An epitaxial layer is disposed on the substrate, wherein the substrate and the epitaxial layer have a first conductivity type; Multiple body regions are spaced apart within the epitaxial layer and extend from the side of the epitaxial layer away from the substrate toward the substrate side. The body regions have a second conductivity type. The substrate, the epitaxial layer, and the body regions are all made of SiC. Each of the body regions is further provided with two source regions spaced apart. The source regions extend from the side of the epitaxial layer away from the substrate toward the substrate side. The source regions have a first conductivity type, and the material of the source regions is Si. (1-x) Ge x And Si in at least a portion of the source region (1-x) Ge x The value of x increases along the direction from the substrate to the epitaxial layer. A gate electrode is disposed on the epitaxial layer and covers the epitaxial layer between two adjacent body regions and extends to cover a portion of two source regions that are close to each other within the two adjacent body regions; the body region below the gate electrode is configured as a channel region, and the crystal compressive stress in the channel region is greater than the crystal compressive stress in the epitaxial layer. The source electrode is disposed on the epitaxial layer and the gate electrode.
6. The device according to claim 5, characterized in that, The x increases gradually along the direction from the substrate to the epitaxial layer, or the x increases in a stepwise manner along the direction from the substrate to the epitaxial layer.
7. The device according to claim 5, characterized in that, The source region is configured as a multilayer substructure, with each substructure stacked along the direction from the substrate to the epitaxial layer. The Ge content in the plurality of substructures increases sequentially along the direction from the substrate to the epitaxial layer.
8. The device according to claim 5, characterized in that, The source region is configured into multiple sub-regions, each sub-region being symmetrically arranged about the central axis of the source region, and adjacent sub-regions having a nested and nested relationship. The Ge content in the plurality of sub-regions increases sequentially from outside the source region to inside the source region.
9. A method for fabricating a MOSFET device, comprising: Provide a substrate; An epitaxial layer is prepared on the substrate, wherein the epitaxial layer and the substrate have a first conductivity type; A body region is formed by implantation on the side of the epitaxial layer away from the substrate. The body region has a second conductivity type, and the materials of the substrate, the epitaxial layer, and the body region are all SiC. Each volume region is etched to form two source region trenches arranged at intervals; A SiGe material layer of a first conductivity type is epitaxially grown inside and outside the source region trench to form a first device, and at least a portion of the SiGe material layer has a Ge content that increases along the direction from the substrate to the epitaxial layer. The first device is annealed to form a source region from the SiGe material layer; A gate electrode is fabricated on the epitaxial layer, the gate electrode covering the epitaxial layer and extending to cover a portion of the body region and extending to cover the nearest portion of the source region; the body region below the gate electrode is configured as a channel region, the crystal compressive stress in the channel region being greater than the crystal compressive stress in the epitaxial layer; A source electrode is fabricated on the epitaxial layer and the gate electrode.
10. The method according to claim 9, characterized in that, The annealing of the first device includes: The first device was annealed at an annealing temperature of 500-900℃ for 30-60 minutes.